exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  22 #define DEBUG_DISAS
  23
  24 #ifndef glue
  25 #define xglue(x, y) x ## y
  26 #define glue(x, y) xglue(x, y)
  27 #define stringify(s)    tostring(s)
  28 #define tostring(s)     #s
  29 #endif
  30
  31 #ifndef THUNK_H
  32 /* horrible */
  33 typedef uint32_t target_ulong;
  34 #endif
  35
  36 #if GCC_MAJOR < 3
  37 #define __builtin_expect(x, n) (x)
  38 #endif
  39
  40 #ifdef __i386__
  41 #define REGPARM(n) __attribute((regparm(n)))
  42 #else
  43 #define REGPARM(n)
  44 #endif
  45
  46 /* is_jmp field values */
  47 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  48 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  49 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  50 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  51
  52 struct TranslationBlock;
  53
  54 /* XXX: make safe guess about sizes */
  55 #define MAX_OP_PER_INSTR 32
  56 #define OPC_BUF_SIZE 512
  57 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  58
  59 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
  60
  61 extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
  62 extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
  63 extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
  64 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  65 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  66
  67 typedef void (GenOpFunc)(void);
  68 typedef void (GenOpFunc1)(long);
  69 typedef void (GenOpFunc2)(long, long);
  70 typedef void (GenOpFunc3)(long, long, long);
  71
  72 #if defined(TARGET_I386)
  73
  74 void optimize_flags_init(void);
  75
  76 #endif
  77
  78 extern FILE *logfile;
  79 extern int loglevel;
  80
  81 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  82 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  83 void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
  84 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  85                  int max_code_size, int *gen_code_size_ptr);
  86 int cpu_restore_state(struct TranslationBlock *tb,
  87                       CPUState *env, unsigned long searched_pc);
  88 void cpu_exec_init(void);
  89 int page_unprotect(unsigned long address);
  90 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  91 void tlb_flush_page(CPUState *env, uint32_t addr);
  92 void tlb_flush_page_write(CPUState *env, uint32_t addr);
  93 void tlb_flush(CPUState *env);
  94 int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot,
  95                  int is_user, int is_softmmu);
  96
  97 #define CODE_GEN_MAX_SIZE        65536
  98 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
  99
 100 #define CODE_GEN_HASH_BITS     15
 101 #define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)
 102
 103 #define CODE_GEN_PHYS_HASH_BITS     15
 104 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 105
 106 /* maximum total translate dcode allocated */
 107
 108 /* NOTE: the translated code area cannot be too big because on some
 109    archs the range of "fast" function calls is limited. Here is a
 110    summary of the ranges:
 111
 112    i386  : signed 32 bits
 113    arm   : signed 26 bits
 114    ppc   : signed 24 bits
 115    sparc : signed 32 bits
 116    alpha : signed 23 bits
 117 */
 118
 119 #if defined(__alpha__)
 120 #define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
 121 #elif defined(__powerpc__)
 122 #define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
 123 #else
 124 #define CODE_GEN_BUFFER_SIZE     (8 * 1024 * 1024)
 125 #endif
 126
 127 //#define CODE_GEN_BUFFER_SIZE     (128 * 1024)
 128
 129 /* estimated block size for TB allocation */
 130 /* XXX: use a per code average code fragment size and modulate it
 131    according to the host CPU */
 132 #if defined(CONFIG_SOFTMMU)
 133 #define CODE_GEN_AVG_BLOCK_SIZE 128
 134 #else
 135 #define CODE_GEN_AVG_BLOCK_SIZE 64
 136 #endif
 137
 138 #define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
 139
 140 #if defined(__powerpc__)
 141 #define USE_DIRECT_JUMP
 142 #endif
 143 #if defined(__i386__)
 144 #define USE_DIRECT_JUMP
 145 #endif
 146
 147 typedef struct TranslationBlock {
 148     unsigned long pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 149     unsigned long cs_base; /* CS base for this block */
 150     unsigned int flags; /* flags defining in which context the code was generated */
 151     uint16_t size;      /* size of target code for this block (1 <=
 152                            size <= TARGET_PAGE_SIZE) */
 153     uint8_t *tc_ptr;    /* pointer to the translated code */
 154     struct TranslationBlock *hash_next; /* next matching tb for virtual address */
 155     /* next matching tb for physical address. */
 156     struct TranslationBlock *phys_hash_next;
 157     /* first and second physical page containing code. The lower bit
 158        of the pointer tells the index in page_next[] */
 159     struct TranslationBlock *page_next[2];
 160     target_ulong page_addr[2];
 161
 162     /* the following data are used to directly call another TB from
 163        the code of this one. */
 164     uint16_t tb_next_offset[2]; /* offset of original jump target */
 165 #ifdef USE_DIRECT_JUMP
 166     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 167 #else
 168     uint32_t tb_next[2]; /* address of jump generated code */
 169 #endif
 170     /* list of TBs jumping to this one. This is a circular list using
 171        the two least significant bits of the pointers to tell what is
 172        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 173        jmp_first */
 174     struct TranslationBlock *jmp_next[2];
 175     struct TranslationBlock *jmp_first;
 176 } TranslationBlock;
 177
 178 static inline unsigned int tb_hash_func(unsigned long pc)
 179 {
 180     return pc & (CODE_GEN_HASH_SIZE - 1);
 181 }
 182
 183 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 184 {
 185     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 186 }
 187
 188 TranslationBlock *tb_alloc(unsigned long pc);
 189 void tb_flush(CPUState *env);
 190 void tb_link(TranslationBlock *tb);
 191 void tb_link_phys(TranslationBlock *tb,
 192                   target_ulong phys_pc, target_ulong phys_page2);
 193
 194 extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
 195 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 196
 197 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
 198 extern uint8_t *code_gen_ptr;
 199
 200 /* find a translation block in the translation cache. If not found,
 201    return NULL and the pointer to the last element of the list in pptb */
 202 static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
 203                                         unsigned long pc,
 204                                         unsigned long cs_base,
 205                                         unsigned int flags)
 206 {
 207     TranslationBlock **ptb, *tb;
 208     unsigned int h;
 209
 210     h = tb_hash_func(pc);
 211     ptb = &tb_hash[h];
 212     for(;;) {
 213         tb = *ptb;
 214         if (!tb)
 215             break;
 216         if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
 217             return tb;
 218         ptb = &tb->hash_next;
 219     }
 220     *pptb = ptb;
 221     return NULL;
 222 }
 223
 224
 225 #if defined(USE_DIRECT_JUMP)
 226
 227 #if defined(__powerpc__)
 228 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 229 {
 230     uint32_t val, *ptr;
 231
 232     /* patch the branch destination */
 233     ptr = (uint32_t *)jmp_addr;
 234     val = *ptr;
 235     val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
 236     *ptr = val;
 237     /* flush icache */
 238     asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
 239     asm volatile ("sync" : : : "memory");
 240     asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
 241     asm volatile ("sync" : : : "memory");
 242     asm volatile ("isync" : : : "memory");
 243 }
 244 #elif defined(__i386__)
 245 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 246 {
 247     /* patch the branch destination */
 248     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 249     /* no need to flush icache explicitely */
 250 }
 251 #endif
 252
 253 static inline void tb_set_jmp_target(TranslationBlock *tb,
 254                                      int n, unsigned long addr)
 255 {
 256     unsigned long offset;
 257
 258     offset = tb->tb_jmp_offset[n];
 259     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 260     offset = tb->tb_jmp_offset[n + 2];
 261     if (offset != 0xffff)
 262         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 263 }
 264
 265 #else
 266
 267 /* set the jump target */
 268 static inline void tb_set_jmp_target(TranslationBlock *tb,
 269                                      int n, unsigned long addr)
 270 {
 271     tb->tb_next[n] = addr;
 272 }
 273
 274 #endif
 275
 276 static inline void tb_add_jump(TranslationBlock *tb, int n,
 277                                TranslationBlock *tb_next)
 278 {
 279     /* NOTE: this test is only needed for thread safety */
 280     if (!tb->jmp_next[n]) {
 281         /* patch the native jump address */
 282         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 283
 284         /* add in TB jmp circular list */
 285         tb->jmp_next[n] = tb_next->jmp_first;
 286         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 287     }
 288 }
 289
 290 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 291
 292 #ifndef offsetof
 293 #define offsetof(type, field) ((size_t) &((type *)0)->field)
 294 #endif
 295
 296 #if defined(__powerpc__)
 297
 298 /* we patch the jump instruction directly */
 299 #define JUMP_TB(opname, tbparam, n, eip)\
 300 do {\
 301     asm volatile (".section \".data\"\n"\
 302                   "__op_label" #n "." stringify(opname) ":\n"\
 303                   ".long 1f\n"\
 304                   ".previous\n"\
 305                   "b __op_jmp" #n "\n"\
 306                   "1:\n");\
 307     T0 = (long)(tbparam) + (n);\
 308     EIP = eip;\
 309     EXIT_TB();\
 310 } while (0)
 311
 312 #define JUMP_TB2(opname, tbparam, n)\
 313 do {\
 314     asm volatile ("b __op_jmp" #n "\n");\
 315 } while (0)
 316
 317 #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
 318
 319 /* we patch the jump instruction directly */
 320 #define JUMP_TB(opname, tbparam, n, eip)\
 321 do {\
 322     asm volatile (".section \".data\"\n"\
 323                   "__op_label" #n "." stringify(opname) ":\n"\
 324                   ".long 1f\n"\
 325                   ".previous\n"\
 326                   "jmp __op_jmp" #n "\n"\
 327                   "1:\n");\
 328     T0 = (long)(tbparam) + (n);\
 329     EIP = eip;\
 330     EXIT_TB();\
 331 } while (0)
 332
 333 #define JUMP_TB2(opname, tbparam, n)\
 334 do {\
 335     asm volatile ("jmp __op_jmp" #n "\n");\
 336 } while (0)
 337
 338 #else
 339
 340 /* jump to next block operations (more portable code, does not need
 341    cache flushing, but slower because of indirect jump) */
 342 #define JUMP_TB(opname, tbparam, n, eip)\
 343 do {\
 344     static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
 345     static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
 346     goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
 347 label ## n:\
 348     T0 = (long)(tbparam) + (n);\
 349     EIP = eip;\
 350 dummy_label ## n:\
 351     EXIT_TB();\
 352 } while (0)
 353
 354 /* second jump to same destination 'n' */
 355 #define JUMP_TB2(opname, tbparam, n)\
 356 do {\
 357     goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n - 2]);\
 358 } while (0)
 359
 360 #endif
 361
 362 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 363 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 364
 365 #ifdef __powerpc__
 366 static inline int testandset (int *p)
 367 {
 368     int ret;
 369     __asm__ __volatile__ (
 370                           "0:    lwarx %0,0,%1 ;"
 371                           "      xor. %0,%3,%0;"
 372                           "      bne 1f;"
 373                           "      stwcx. %2,0,%1;"
 374                           "      bne- 0b;"
 375                           "1:    "
 376                           : "=&r" (ret)
 377                           : "r" (p), "r" (1), "r" (0)
 378                           : "cr0", "memory");
 379     return ret;
 380 }
 381 #endif
 382
 383 #ifdef __i386__
 384 static inline int testandset (int *p)
 385 {
 386     char ret;
 387     long int readval;
 388
 389     __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
 390                           : "=q" (ret), "=m" (*p), "=a" (readval)
 391                           : "r" (1), "m" (*p), "a" (0)
 392                           : "memory");
 393     return ret;
 394 }
 395 #endif
 396
 397 #ifdef __s390__
 398 static inline int testandset (int *p)
 399 {
 400     int ret;
 401
 402     __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
 403                           "   jl    0b"
 404                           : "=&d" (ret)
 405                           : "r" (1), "a" (p), "0" (*p)
 406                           : "cc", "memory" );
 407     return ret;
 408 }
 409 #endif
 410
 411 #ifdef __alpha__
 412 static inline int testandset (int *p)
 413 {
 414     int ret;
 415     unsigned long one;
 416
 417     __asm__ __volatile__ ("0:   mov 1,%2\n"
 418                           "     ldl_l %0,%1\n"
 419                           "     stl_c %2,%1\n"
 420                           "     beq %2,1f\n"
 421                           ".subsection 2\n"
 422                           "1:   br 0b\n"
 423                           ".previous"
 424                           : "=r" (ret), "=m" (*p), "=r" (one)
 425                           : "m" (*p));
 426     return ret;
 427 }
 428 #endif
 429
 430 #ifdef __sparc__
 431 static inline int testandset (int *p)
 432 {
 433         int ret;
 434
 435         __asm__ __volatile__("ldstub    [%1], %0"
 436                              : "=r" (ret)
 437                              : "r" (p)
 438                              : "memory");
 439
 440         return (ret ? 1 : 0);
 441 }
 442 #endif
 443
 444 #ifdef __arm__
 445 static inline int testandset (int *spinlock)
 446 {
 447     register unsigned int ret;
 448     __asm__ __volatile__("swp %0, %1, [%2]"
 449                          : "=r"(ret)
 450                          : "0"(1), "r"(spinlock));
 451
 452     return ret;
 453 }
 454 #endif
 455
 456 #ifdef __mc68000
 457 static inline int testandset (int *p)
 458 {
 459     char ret;
 460     __asm__ __volatile__("tas %1; sne %0"
 461                          : "=r" (ret)
 462                          : "m" (p)
 463                          : "cc","memory");
 464     return ret == 0;
 465 }
 466 #endif
 467
 468 typedef int spinlock_t;
 469
 470 #define SPIN_LOCK_UNLOCKED 0
 471
 472 #if defined(CONFIG_USER_ONLY)
 473 static inline void spin_lock(spinlock_t *lock)
 474 {
 475     while (testandset(lock));
 476 }
 477
 478 static inline void spin_unlock(spinlock_t *lock)
 479 {
 480     *lock = 0;
 481 }
 482
 483 static inline int spin_trylock(spinlock_t *lock)
 484 {
 485     return !testandset(lock);
 486 }
 487 #else
 488 static inline void spin_lock(spinlock_t *lock)
 489 {
 490 }
 491
 492 static inline void spin_unlock(spinlock_t *lock)
 493 {
 494 }
 495
 496 static inline int spin_trylock(spinlock_t *lock)
 497 {
 498     return 1;
 499 }
 500 #endif
 501
 502 extern spinlock_t tb_lock;
 503
 504 extern int tb_invalidated_flag;
 505
 506 #if (defined(TARGET_I386) || defined(TARGET_PPC)) && \
 507     !defined(CONFIG_USER_ONLY)
 508
 509 void tlb_fill(unsigned long addr, int is_write, int is_user,
 510               void *retaddr);
 511
 512 #define ACCESS_TYPE 3
 513 #define MEMSUFFIX _code
 514 #define env cpu_single_env
 515
 516 #define DATA_SIZE 1
 517 #include "softmmu_header.h"
 518
 519 #define DATA_SIZE 2
 520 #include "softmmu_header.h"
 521
 522 #define DATA_SIZE 4
 523 #include "softmmu_header.h"
 524
 525 #undef ACCESS_TYPE
 526 #undef MEMSUFFIX
 527 #undef env
 528
 529 #endif
 530
 531 #if defined(CONFIG_USER_ONLY)
 532 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 533 {
 534     return addr;
 535 }
 536 #else
 537 /* NOTE: this function can trigger an exception */
 538 /* XXX: i386 target specific */
 539 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 540 {
 541     int is_user, index;
 542
 543     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 544 #if defined(TARGET_I386)
 545     is_user = ((env->hflags & HF_CPL_MASK) == 3);
 546 #elif defined (TARGET_PPC)
 547     is_user = msr_pr;
 548 #else
 549 #error "Unimplemented !"
 550 #endif
 551     if (__builtin_expect(env->tlb_read[is_user][index].address !=
 552                          (addr & TARGET_PAGE_MASK), 0)) {
 553         ldub_code((void *)addr);
 554     }
 555     return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
 556 }
 557 #endif
 558