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[qemu.git] / exec-all.h
1 /*
2 * internal execution defines for qemu
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
22 #define DEBUG_DISAS
23
24 #ifndef glue
25 #define xglue(x, y) x ## y
26 #define glue(x, y) xglue(x, y)
27 #define stringify(s) tostring(s)
28 #define tostring(s) #s
29 #endif
30
31 #if __GNUC__ < 3
32 #define __builtin_expect(x, n) (x)
33 #endif
34
35 #ifdef __i386__
36 #define REGPARM(n) __attribute((regparm(n)))
37 #else
38 #define REGPARM(n)
39 #endif
40
41 /* is_jmp field values */
42 #define DISAS_NEXT 0 /* next instruction can be analyzed */
43 #define DISAS_JUMP 1 /* only pc was modified dynamically */
44 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
45 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
46
47 struct TranslationBlock;
48
49 /* XXX: make safe guess about sizes */
50 #define MAX_OP_PER_INSTR 32
51 #define OPC_BUF_SIZE 512
52 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
53
54 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
55
56 extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
57 extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
58 extern long gen_labels[OPC_BUF_SIZE];
59 extern int nb_gen_labels;
60 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
61 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
62 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
63 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
64 extern target_ulong gen_opc_jump_pc[2];
65
66 typedef void (GenOpFunc)(void);
67 typedef void (GenOpFunc1)(long);
68 typedef void (GenOpFunc2)(long, long);
69 typedef void (GenOpFunc3)(long, long, long);
70
71 #if defined(TARGET_I386)
72
73 void optimize_flags_init(void);
74
75 #endif
76
77 extern FILE *logfile;
78 extern int loglevel;
79
80 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
81 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
82 void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
83 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
84 int max_code_size, int *gen_code_size_ptr);
85 int cpu_restore_state(struct TranslationBlock *tb,
86 CPUState *env, unsigned long searched_pc,
87 void *puc);
88 int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
89 int max_code_size, int *gen_code_size_ptr);
90 int cpu_restore_state_copy(struct TranslationBlock *tb,
91 CPUState *env, unsigned long searched_pc,
92 void *puc);
93 void cpu_resume_from_signal(CPUState *env1, void *puc);
94 void cpu_exec_init(CPUState *env);
95 int page_unprotect(unsigned long address, unsigned long pc, void *puc);
96 void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
97 int is_cpu_write_access);
98 void tb_invalidate_page_range(target_ulong start, target_ulong end);
99 void tlb_flush_page(CPUState *env, target_ulong addr);
100 void tlb_flush(CPUState *env, int flush_global);
101 int tlb_set_page(CPUState *env, target_ulong vaddr,
102 target_phys_addr_t paddr, int prot,
103 int is_user, int is_softmmu);
104
105 #define CODE_GEN_MAX_SIZE 65536
106 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
107
108 #define CODE_GEN_PHYS_HASH_BITS 15
109 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
110
111 /* maximum total translate dcode allocated */
112
113 /* NOTE: the translated code area cannot be too big because on some
114 archs the range of "fast" function calls is limited. Here is a
115 summary of the ranges:
116
117 i386 : signed 32 bits
118 arm : signed 26 bits
119 ppc : signed 24 bits
120 sparc : signed 32 bits
121 alpha : signed 23 bits
122 */
123
124 #if defined(__alpha__)
125 #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
126 #elif defined(__ia64)
127 #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */
128 #elif defined(__powerpc__)
129 #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
130 #else
131 #define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024)
132 #endif
133
134 //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
135
136 /* estimated block size for TB allocation */
137 /* XXX: use a per code average code fragment size and modulate it
138 according to the host CPU */
139 #if defined(CONFIG_SOFTMMU)
140 #define CODE_GEN_AVG_BLOCK_SIZE 128
141 #else
142 #define CODE_GEN_AVG_BLOCK_SIZE 64
143 #endif
144
145 #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
146
147 #if defined(__powerpc__)
148 #define USE_DIRECT_JUMP
149 #endif
150 #if defined(__i386__) && !defined(_WIN32)
151 #define USE_DIRECT_JUMP
152 #endif
153
154 typedef struct TranslationBlock {
155 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
156 target_ulong cs_base; /* CS base for this block */
157 unsigned int flags; /* flags defining in which context the code was generated */
158 uint16_t size; /* size of target code for this block (1 <=
159 size <= TARGET_PAGE_SIZE) */
160 uint16_t cflags; /* compile flags */
161 #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
162 #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
163 #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
164 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
165
166 uint8_t *tc_ptr; /* pointer to the translated code */
167 /* next matching tb for physical address. */
168 struct TranslationBlock *phys_hash_next;
169 /* first and second physical page containing code. The lower bit
170 of the pointer tells the index in page_next[] */
171 struct TranslationBlock *page_next[2];
172 target_ulong page_addr[2];
173
174 /* the following data are used to directly call another TB from
175 the code of this one. */
176 uint16_t tb_next_offset[2]; /* offset of original jump target */
177 #ifdef USE_DIRECT_JUMP
178 uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
179 #else
180 uint32_t tb_next[2]; /* address of jump generated code */
181 #endif
182 /* list of TBs jumping to this one. This is a circular list using
183 the two least significant bits of the pointers to tell what is
184 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
185 jmp_first */
186 struct TranslationBlock *jmp_next[2];
187 struct TranslationBlock *jmp_first;
188 } TranslationBlock;
189
190 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
191 {
192 return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1);
193 }
194
195 static inline unsigned int tb_phys_hash_func(unsigned long pc)
196 {
197 return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
198 }
199
200 TranslationBlock *tb_alloc(target_ulong pc);
201 void tb_flush(CPUState *env);
202 void tb_link_phys(TranslationBlock *tb,
203 target_ulong phys_pc, target_ulong phys_page2);
204
205 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
206
207 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
208 extern uint8_t *code_gen_ptr;
209
210 #if defined(USE_DIRECT_JUMP)
211
212 #if defined(__powerpc__)
213 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
214 {
215 uint32_t val, *ptr;
216
217 /* patch the branch destination */
218 ptr = (uint32_t *)jmp_addr;
219 val = *ptr;
220 val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
221 *ptr = val;
222 /* flush icache */
223 asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
224 asm volatile ("sync" : : : "memory");
225 asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
226 asm volatile ("sync" : : : "memory");
227 asm volatile ("isync" : : : "memory");
228 }
229 #elif defined(__i386__)
230 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
231 {
232 /* patch the branch destination */
233 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
234 /* no need to flush icache explicitely */
235 }
236 #endif
237
238 static inline void tb_set_jmp_target(TranslationBlock *tb,
239 int n, unsigned long addr)
240 {
241 unsigned long offset;
242
243 offset = tb->tb_jmp_offset[n];
244 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
245 offset = tb->tb_jmp_offset[n + 2];
246 if (offset != 0xffff)
247 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
248 }
249
250 #else
251
252 /* set the jump target */
253 static inline void tb_set_jmp_target(TranslationBlock *tb,
254 int n, unsigned long addr)
255 {
256 tb->tb_next[n] = addr;
257 }
258
259 #endif
260
261 static inline void tb_add_jump(TranslationBlock *tb, int n,
262 TranslationBlock *tb_next)
263 {
264 /* NOTE: this test is only needed for thread safety */
265 if (!tb->jmp_next[n]) {
266 /* patch the native jump address */
267 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
268
269 /* add in TB jmp circular list */
270 tb->jmp_next[n] = tb_next->jmp_first;
271 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
272 }
273 }
274
275 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
276
277 #ifndef offsetof
278 #define offsetof(type, field) ((size_t) &((type *)0)->field)
279 #endif
280
281 #if defined(_WIN32)
282 #define ASM_DATA_SECTION ".section \".data\"\n"
283 #define ASM_PREVIOUS_SECTION ".section .text\n"
284 #elif defined(__APPLE__)
285 #define ASM_DATA_SECTION ".data\n"
286 #define ASM_PREVIOUS_SECTION ".text\n"
287 #else
288 #define ASM_DATA_SECTION ".section \".data\"\n"
289 #define ASM_PREVIOUS_SECTION ".previous\n"
290 #endif
291
292 #define ASM_OP_LABEL_NAME(n, opname) \
293 ASM_NAME(__op_label) #n "." ASM_NAME(opname)
294
295 #if defined(__powerpc__)
296
297 /* we patch the jump instruction directly */
298 #define GOTO_TB(opname, tbparam, n)\
299 do {\
300 asm volatile (ASM_DATA_SECTION\
301 ASM_OP_LABEL_NAME(n, opname) ":\n"\
302 ".long 1f\n"\
303 ASM_PREVIOUS_SECTION \
304 "b " ASM_NAME(__op_jmp) #n "\n"\
305 "1:\n");\
306 } while (0)
307
308 #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
309
310 /* we patch the jump instruction directly */
311 #define GOTO_TB(opname, tbparam, n)\
312 do {\
313 asm volatile (".section .data\n"\
314 ASM_OP_LABEL_NAME(n, opname) ":\n"\
315 ".long 1f\n"\
316 ASM_PREVIOUS_SECTION \
317 "jmp " ASM_NAME(__op_jmp) #n "\n"\
318 "1:\n");\
319 } while (0)
320
321 #else
322
323 /* jump to next block operations (more portable code, does not need
324 cache flushing, but slower because of indirect jump) */
325 #define GOTO_TB(opname, tbparam, n)\
326 do {\
327 static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
328 static void __attribute__((unused)) *__op_label ## n \
329 __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
330 goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
331 label ## n: ;\
332 dummy_label ## n: ;\
333 } while (0)
334
335 #endif
336
337 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
338 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
339 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
340
341 #ifdef __powerpc__
342 static inline int testandset (int *p)
343 {
344 int ret;
345 __asm__ __volatile__ (
346 "0: lwarx %0,0,%1\n"
347 " xor. %0,%3,%0\n"
348 " bne 1f\n"
349 " stwcx. %2,0,%1\n"
350 " bne- 0b\n"
351 "1: "
352 : "=&r" (ret)
353 : "r" (p), "r" (1), "r" (0)
354 : "cr0", "memory");
355 return ret;
356 }
357 #endif
358
359 #ifdef __i386__
360 static inline int testandset (int *p)
361 {
362 long int readval = 0;
363
364 __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
365 : "+m" (*p), "+a" (readval)
366 : "r" (1)
367 : "cc");
368 return readval;
369 }
370 #endif
371
372 #ifdef __x86_64__
373 static inline int testandset (int *p)
374 {
375 long int readval = 0;
376
377 __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
378 : "+m" (*p), "+a" (readval)
379 : "r" (1)
380 : "cc");
381 return readval;
382 }
383 #endif
384
385 #ifdef __s390__
386 static inline int testandset (int *p)
387 {
388 int ret;
389
390 __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
391 " jl 0b"
392 : "=&d" (ret)
393 : "r" (1), "a" (p), "0" (*p)
394 : "cc", "memory" );
395 return ret;
396 }
397 #endif
398
399 #ifdef __alpha__
400 static inline int testandset (int *p)
401 {
402 int ret;
403 unsigned long one;
404
405 __asm__ __volatile__ ("0: mov 1,%2\n"
406 " ldl_l %0,%1\n"
407 " stl_c %2,%1\n"
408 " beq %2,1f\n"
409 ".subsection 2\n"
410 "1: br 0b\n"
411 ".previous"
412 : "=r" (ret), "=m" (*p), "=r" (one)
413 : "m" (*p));
414 return ret;
415 }
416 #endif
417
418 #ifdef __sparc__
419 static inline int testandset (int *p)
420 {
421 int ret;
422
423 __asm__ __volatile__("ldstub [%1], %0"
424 : "=r" (ret)
425 : "r" (p)
426 : "memory");
427
428 return (ret ? 1 : 0);
429 }
430 #endif
431
432 #ifdef __arm__
433 static inline int testandset (int *spinlock)
434 {
435 register unsigned int ret;
436 __asm__ __volatile__("swp %0, %1, [%2]"
437 : "=r"(ret)
438 : "0"(1), "r"(spinlock));
439
440 return ret;
441 }
442 #endif
443
444 #ifdef __mc68000
445 static inline int testandset (int *p)
446 {
447 char ret;
448 __asm__ __volatile__("tas %1; sne %0"
449 : "=r" (ret)
450 : "m" (p)
451 : "cc","memory");
452 return ret;
453 }
454 #endif
455
456 #ifdef __ia64
457 #include <ia64intrin.h>
458
459 static inline int testandset (int *p)
460 {
461 return __sync_lock_test_and_set (p, 1);
462 }
463 #endif
464
465 typedef int spinlock_t;
466
467 #define SPIN_LOCK_UNLOCKED 0
468
469 #if defined(CONFIG_USER_ONLY)
470 static inline void spin_lock(spinlock_t *lock)
471 {
472 while (testandset(lock));
473 }
474
475 static inline void spin_unlock(spinlock_t *lock)
476 {
477 *lock = 0;
478 }
479
480 static inline int spin_trylock(spinlock_t *lock)
481 {
482 return !testandset(lock);
483 }
484 #else
485 static inline void spin_lock(spinlock_t *lock)
486 {
487 }
488
489 static inline void spin_unlock(spinlock_t *lock)
490 {
491 }
492
493 static inline int spin_trylock(spinlock_t *lock)
494 {
495 return 1;
496 }
497 #endif
498
499 extern spinlock_t tb_lock;
500
501 extern int tb_invalidated_flag;
502
503 #if !defined(CONFIG_USER_ONLY)
504
505 void tlb_fill(target_ulong addr, int is_write, int is_user,
506 void *retaddr);
507
508 #define ACCESS_TYPE 3
509 #define MEMSUFFIX _code
510 #define env cpu_single_env
511
512 #define DATA_SIZE 1
513 #include "softmmu_header.h"
514
515 #define DATA_SIZE 2
516 #include "softmmu_header.h"
517
518 #define DATA_SIZE 4
519 #include "softmmu_header.h"
520
521 #define DATA_SIZE 8
522 #include "softmmu_header.h"
523
524 #undef ACCESS_TYPE
525 #undef MEMSUFFIX
526 #undef env
527
528 #endif
529
530 #if defined(CONFIG_USER_ONLY)
531 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
532 {
533 return addr;
534 }
535 #else
536 /* NOTE: this function can trigger an exception */
537 /* NOTE2: the returned address is not exactly the physical address: it
538 is the offset relative to phys_ram_base */
539 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
540 {
541 int is_user, index, pd;
542
543 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
544 #if defined(TARGET_I386)
545 is_user = ((env->hflags & HF_CPL_MASK) == 3);
546 #elif defined (TARGET_PPC)
547 is_user = msr_pr;
548 #elif defined (TARGET_MIPS)
549 is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
550 #elif defined (TARGET_SPARC)
551 is_user = (env->psrs == 0);
552 #else
553 #error "Unimplemented !"
554 #endif
555 if (__builtin_expect(env->tlb_read[is_user][index].address !=
556 (addr & TARGET_PAGE_MASK), 0)) {
557 ldub_code(addr);
558 }
559 pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK;
560 if (pd > IO_MEM_ROM) {
561 cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
562 }
563 return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
564 }
565 #endif
566
567
568 #ifdef USE_KQEMU
569 int kqemu_init(CPUState *env);
570 int kqemu_cpu_exec(CPUState *env);
571 void kqemu_flush_page(CPUState *env, target_ulong addr);
572 void kqemu_flush(CPUState *env, int global);
573 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
574 void kqemu_cpu_interrupt(CPUState *env);
575
576 static inline int kqemu_is_ok(CPUState *env)
577 {
578 return(env->kqemu_enabled &&
579 (env->hflags & HF_CPL_MASK) == 3 &&
580 (env->eflags & IOPL_MASK) != IOPL_MASK &&
581 (env->cr[0] & CR0_PE_MASK) &&
582 (env->eflags & IF_MASK) &&
583 !(env->eflags & VM_MASK));
584 }
585
586 #endif
Qemu copy for testing