exec.c

   1 /*
   2  *  Virtual page mapping
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #ifdef _WIN32
  21 #include <windows.h>
  22 #else
  23 #include <sys/types.h>
  24 #include <sys/mman.h>
  25 #endif
  26
  27 #include "qemu-common.h"
  28 #include "cpu.h"
  29 #include "tcg.h"
  30 #include "hw/hw.h"
  31 #include "hw/qdev.h"
  32 #include "qemu/osdep.h"
  33 #include "sysemu/kvm.h"
  34 #include "hw/xen/xen.h"
  35 #include "qemu/timer.h"
  36 #include "qemu/config-file.h"
  37 #include "exec/memory.h"
  38 #include "sysemu/dma.h"
  39 #include "exec/address-spaces.h"
  40 #if defined(CONFIG_USER_ONLY)
  41 #include <qemu.h>
  42 #else /* !CONFIG_USER_ONLY */
  43 #include "sysemu/xen-mapcache.h"
  44 #include "trace.h"
  45 #endif
  46 #include "exec/cpu-all.h"
  47
  48 #include "exec/cputlb.h"
  49 #include "translate-all.h"
  50
  51 #include "exec/memory-internal.h"
  52
  53 //#define DEBUG_SUBPAGE
  54
  55 #if !defined(CONFIG_USER_ONLY)
  56 static int in_migration;
  57
  58 RAMList ram_list = { .blocks = QTAILQ_HEAD_INITIALIZER(ram_list.blocks) };
  59
  60 static MemoryRegion *system_memory;
  61 static MemoryRegion *system_io;
  62
  63 AddressSpace address_space_io;
  64 AddressSpace address_space_memory;
  65
  66 MemoryRegion io_mem_rom, io_mem_notdirty;
  67 static MemoryRegion io_mem_unassigned;
  68
  69 #endif
  70
  71 CPUArchState *first_cpu;
  72 /* current CPU in the current thread. It is only valid inside
  73    cpu_exec() */
  74 DEFINE_TLS(CPUArchState *,cpu_single_env);
  75 /* 0 = Do not count executed instructions.
  76    1 = Precise instruction counting.
  77    2 = Adaptive rate instruction counting.  */
  78 int use_icount;
  79
  80 #if !defined(CONFIG_USER_ONLY)
  81
  82 typedef struct PhysPageEntry PhysPageEntry;
  83
  84 struct PhysPageEntry {
  85     uint16_t is_leaf : 1;
  86      /* index into phys_sections (is_leaf) or phys_map_nodes (!is_leaf) */
  87     uint16_t ptr : 15;
  88 };
  89
  90 typedef PhysPageEntry Node[L2_SIZE];
  91
  92 struct AddressSpaceDispatch {
  93     /* This is a multi-level map on the physical address space.
  94      * The bottom level has pointers to MemoryRegionSections.
  95      */
  96     PhysPageEntry phys_map;
  97     Node *nodes;
  98     MemoryRegionSection *sections;
  99     AddressSpace *as;
 100 };
 101
 102 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
 103 typedef struct subpage_t {
 104     MemoryRegion iomem;
 105     AddressSpace *as;
 106     hwaddr base;
 107     uint16_t sub_section[TARGET_PAGE_SIZE];
 108 } subpage_t;
 109
 110 #define PHYS_SECTION_UNASSIGNED 0
 111 #define PHYS_SECTION_NOTDIRTY 1
 112 #define PHYS_SECTION_ROM 2
 113 #define PHYS_SECTION_WATCH 3
 114
 115 typedef struct PhysPageMap {
 116     unsigned sections_nb;
 117     unsigned sections_nb_alloc;
 118     unsigned nodes_nb;
 119     unsigned nodes_nb_alloc;
 120     Node *nodes;
 121     MemoryRegionSection *sections;
 122 } PhysPageMap;
 123
 124 static PhysPageMap *prev_map;
 125 static PhysPageMap next_map;
 126
 127 #define PHYS_MAP_NODE_NIL (((uint16_t)~0) >> 1)
 128
 129 static void io_mem_init(void);
 130 static void memory_map_init(void);
 131 static void *qemu_safe_ram_ptr(ram_addr_t addr);
 132
 133 static MemoryRegion io_mem_watch;
 134 #endif
 135
 136 #if !defined(CONFIG_USER_ONLY)
 137
 138 static void phys_map_node_reserve(unsigned nodes)
 139 {
 140     if (next_map.nodes_nb + nodes > next_map.nodes_nb_alloc) {
 141         next_map.nodes_nb_alloc = MAX(next_map.nodes_nb_alloc * 2,
 142                                             16);
 143         next_map.nodes_nb_alloc = MAX(next_map.nodes_nb_alloc,
 144                                       next_map.nodes_nb + nodes);
 145         next_map.nodes = g_renew(Node, next_map.nodes,
 146                                  next_map.nodes_nb_alloc);
 147     }
 148 }
 149
 150 static uint16_t phys_map_node_alloc(void)
 151 {
 152     unsigned i;
 153     uint16_t ret;
 154
 155     ret = next_map.nodes_nb++;
 156     assert(ret != PHYS_MAP_NODE_NIL);
 157     assert(ret != next_map.nodes_nb_alloc);
 158     for (i = 0; i < L2_SIZE; ++i) {
 159         next_map.nodes[ret][i].is_leaf = 0;
 160         next_map.nodes[ret][i].ptr = PHYS_MAP_NODE_NIL;
 161     }
 162     return ret;
 163 }
 164
 165 static void phys_page_set_level(PhysPageEntry *lp, hwaddr *index,
 166                                 hwaddr *nb, uint16_t leaf,
 167                                 int level)
 168 {
 169     PhysPageEntry *p;
 170     int i;
 171     hwaddr step = (hwaddr)1 << (level * L2_BITS);
 172
 173     if (!lp->is_leaf && lp->ptr == PHYS_MAP_NODE_NIL) {
 174         lp->ptr = phys_map_node_alloc();
 175         p = next_map.nodes[lp->ptr];
 176         if (level == 0) {
 177             for (i = 0; i < L2_SIZE; i++) {
 178                 p[i].is_leaf = 1;
 179                 p[i].ptr = PHYS_SECTION_UNASSIGNED;
 180             }
 181         }
 182     } else {
 183         p = next_map.nodes[lp->ptr];
 184     }
 185     lp = &p[(*index >> (level * L2_BITS)) & (L2_SIZE - 1)];
 186
 187     while (*nb && lp < &p[L2_SIZE]) {
 188         if ((*index & (step - 1)) == 0 && *nb >= step) {
 189             lp->is_leaf = true;
 190             lp->ptr = leaf;
 191             *index += step;
 192             *nb -= step;
 193         } else {
 194             phys_page_set_level(lp, index, nb, leaf, level - 1);
 195         }
 196         ++lp;
 197     }
 198 }
 199
 200 static void phys_page_set(AddressSpaceDispatch *d,
 201                           hwaddr index, hwaddr nb,
 202                           uint16_t leaf)
 203 {
 204     /* Wildly overreserve - it doesn't matter much. */
 205     phys_map_node_reserve(3 * P_L2_LEVELS);
 206
 207     phys_page_set_level(&d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
 208 }
 209
 210 static MemoryRegionSection *phys_page_find(PhysPageEntry lp, hwaddr index,
 211                                            Node *nodes, MemoryRegionSection *sections)
 212 {
 213     PhysPageEntry *p;
 214     int i;
 215
 216     for (i = P_L2_LEVELS - 1; i >= 0 && !lp.is_leaf; i--) {
 217         if (lp.ptr == PHYS_MAP_NODE_NIL) {
 218             return &sections[PHYS_SECTION_UNASSIGNED];
 219         }
 220         p = nodes[lp.ptr];
 221         lp = p[(index >> (i * L2_BITS)) & (L2_SIZE - 1)];
 222     }
 223     return &sections[lp.ptr];
 224 }
 225
 226 bool memory_region_is_unassigned(MemoryRegion *mr)
 227 {
 228     return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
 229         && mr != &io_mem_watch;
 230 }
 231
 232 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
 233                                                         hwaddr addr,
 234                                                         bool resolve_subpage)
 235 {
 236     MemoryRegionSection *section;
 237     subpage_t *subpage;
 238
 239     section = phys_page_find(d->phys_map, addr >> TARGET_PAGE_BITS,
 240                              d->nodes, d->sections);
 241     if (resolve_subpage && section->mr->subpage) {
 242         subpage = container_of(section->mr, subpage_t, iomem);
 243         section = &d->sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
 244     }
 245     return section;
 246 }
 247
 248 static MemoryRegionSection *
 249 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
 250                                  hwaddr *plen, bool resolve_subpage)
 251 {
 252     MemoryRegionSection *section;
 253     Int128 diff;
 254
 255     section = address_space_lookup_region(d, addr, resolve_subpage);
 256     /* Compute offset within MemoryRegionSection */
 257     addr -= section->offset_within_address_space;
 258
 259     /* Compute offset within MemoryRegion */
 260     *xlat = addr + section->offset_within_region;
 261
 262     diff = int128_sub(section->mr->size, int128_make64(addr));
 263     *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
 264     return section;
 265 }
 266
 267 MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
 268                                       hwaddr *xlat, hwaddr *plen,
 269                                       bool is_write)
 270 {
 271     IOMMUTLBEntry iotlb;
 272     MemoryRegionSection *section;
 273     MemoryRegion *mr;
 274     hwaddr len = *plen;
 275
 276     for (;;) {
 277         section = address_space_translate_internal(as->dispatch, addr, &addr, plen, true);
 278         mr = section->mr;
 279
 280         if (!mr->iommu_ops) {
 281             break;
 282         }
 283
 284         iotlb = mr->iommu_ops->translate(mr, addr);
 285         addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
 286                 | (addr & iotlb.addr_mask));
 287         len = MIN(len, (addr | iotlb.addr_mask) - addr + 1);
 288         if (!(iotlb.perm & (1 << is_write))) {
 289             mr = &io_mem_unassigned;
 290             break;
 291         }
 292
 293         as = iotlb.target_as;
 294     }
 295
 296     *plen = len;
 297     *xlat = addr;
 298     return mr;
 299 }
 300
 301 MemoryRegionSection *
 302 address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat,
 303                                   hwaddr *plen)
 304 {
 305     MemoryRegionSection *section;
 306     section = address_space_translate_internal(as->dispatch, addr, xlat, plen, false);
 307
 308     assert(!section->mr->iommu_ops);
 309     return section;
 310 }
 311 #endif
 312
 313 void cpu_exec_init_all(void)
 314 {
 315 #if !defined(CONFIG_USER_ONLY)
 316     qemu_mutex_init(&ram_list.mutex);
 317     memory_map_init();
 318     io_mem_init();
 319 #endif
 320 }
 321
 322 #if !defined(CONFIG_USER_ONLY)
 323
 324 static int cpu_common_post_load(void *opaque, int version_id)
 325 {
 326     CPUState *cpu = opaque;
 327
 328     /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
 329        version_id is increased. */
 330     cpu->interrupt_request &= ~0x01;
 331     tlb_flush(cpu->env_ptr, 1);
 332
 333     return 0;
 334 }
 335
 336 const VMStateDescription vmstate_cpu_common = {
 337     .name = "cpu_common",
 338     .version_id = 1,
 339     .minimum_version_id = 1,
 340     .minimum_version_id_old = 1,
 341     .post_load = cpu_common_post_load,
 342     .fields      = (VMStateField []) {
 343         VMSTATE_UINT32(halted, CPUState),
 344         VMSTATE_UINT32(interrupt_request, CPUState),
 345         VMSTATE_END_OF_LIST()
 346     }
 347 };
 348
 349 #endif
 350
 351 CPUState *qemu_get_cpu(int index)
 352 {
 353     CPUArchState *env = first_cpu;
 354     CPUState *cpu = NULL;
 355
 356     while (env) {
 357         cpu = ENV_GET_CPU(env);
 358         if (cpu->cpu_index == index) {
 359             break;
 360         }
 361         env = env->next_cpu;
 362     }
 363
 364     return env ? cpu : NULL;
 365 }
 366
 367 void qemu_for_each_cpu(void (*func)(CPUState *cpu, void *data), void *data)
 368 {
 369     CPUArchState *env = first_cpu;
 370
 371     while (env) {
 372         func(ENV_GET_CPU(env), data);
 373         env = env->next_cpu;
 374     }
 375 }
 376
 377 void cpu_exec_init(CPUArchState *env)
 378 {
 379     CPUState *cpu = ENV_GET_CPU(env);
 380     CPUClass *cc = CPU_GET_CLASS(cpu);
 381     CPUArchState **penv;
 382     int cpu_index;
 383
 384 #if defined(CONFIG_USER_ONLY)
 385     cpu_list_lock();
 386 #endif
 387     env->next_cpu = NULL;
 388     penv = &first_cpu;
 389     cpu_index = 0;
 390     while (*penv != NULL) {
 391         penv = &(*penv)->next_cpu;
 392         cpu_index++;
 393     }
 394     cpu->cpu_index = cpu_index;
 395     cpu->numa_node = 0;
 396     QTAILQ_INIT(&env->breakpoints);
 397     QTAILQ_INIT(&env->watchpoints);
 398 #ifndef CONFIG_USER_ONLY
 399     cpu->thread_id = qemu_get_thread_id();
 400 #endif
 401     *penv = env;
 402 #if defined(CONFIG_USER_ONLY)
 403     cpu_list_unlock();
 404 #endif
 405     vmstate_register(NULL, cpu_index, &vmstate_cpu_common, cpu);
 406 #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
 407     register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
 408                     cpu_save, cpu_load, env);
 409     assert(cc->vmsd == NULL);
 410 #endif
 411     if (cc->vmsd != NULL) {
 412         vmstate_register(NULL, cpu_index, cc->vmsd, cpu);
 413     }
 414 }
 415
 416 #if defined(TARGET_HAS_ICE)
 417 #if defined(CONFIG_USER_ONLY)
 418 static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
 419 {
 420     tb_invalidate_phys_page_range(pc, pc + 1, 0);
 421 }
 422 #else
 423 static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
 424 {
 425     tb_invalidate_phys_addr(cpu_get_phys_page_debug(env, pc) |
 426             (pc & ~TARGET_PAGE_MASK));
 427 }
 428 #endif
 429 #endif /* TARGET_HAS_ICE */
 430
 431 #if defined(CONFIG_USER_ONLY)
 432 void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
 433
 434 {
 435 }
 436
 437 int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
 438                           int flags, CPUWatchpoint **watchpoint)
 439 {
 440     return -ENOSYS;
 441 }
 442 #else
 443 /* Add a watchpoint.  */
 444 int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
 445                           int flags, CPUWatchpoint **watchpoint)
 446 {
 447     target_ulong len_mask = ~(len - 1);
 448     CPUWatchpoint *wp;
 449
 450     /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
 451     if ((len & (len - 1)) || (addr & ~len_mask) ||
 452             len == 0 || len > TARGET_PAGE_SIZE) {
 453         fprintf(stderr, "qemu: tried to set invalid watchpoint at "
 454                 TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
 455         return -EINVAL;
 456     }
 457     wp = g_malloc(sizeof(*wp));
 458
 459     wp->vaddr = addr;
 460     wp->len_mask = len_mask;
 461     wp->flags = flags;
 462
 463     /* keep all GDB-injected watchpoints in front */
 464     if (flags & BP_GDB)
 465         QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry);
 466     else
 467         QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry);
 468
 469     tlb_flush_page(env, addr);
 470
 471     if (watchpoint)
 472         *watchpoint = wp;
 473     return 0;
 474 }
 475
 476 /* Remove a specific watchpoint.  */
 477 int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len,
 478                           int flags)
 479 {
 480     target_ulong len_mask = ~(len - 1);
 481     CPUWatchpoint *wp;
 482
 483     QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
 484         if (addr == wp->vaddr && len_mask == wp->len_mask
 485                 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
 486             cpu_watchpoint_remove_by_ref(env, wp);
 487             return 0;
 488         }
 489     }
 490     return -ENOENT;
 491 }
 492
 493 /* Remove a specific watchpoint by reference.  */
 494 void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint)
 495 {
 496     QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
 497
 498     tlb_flush_page(env, watchpoint->vaddr);
 499
 500     g_free(watchpoint);
 501 }
 502
 503 /* Remove all matching watchpoints.  */
 504 void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
 505 {
 506     CPUWatchpoint *wp, *next;
 507
 508     QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) {
 509         if (wp->flags & mask)
 510             cpu_watchpoint_remove_by_ref(env, wp);
 511     }
 512 }
 513 #endif
 514
 515 /* Add a breakpoint.  */
 516 int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
 517                           CPUBreakpoint **breakpoint)
 518 {
 519 #if defined(TARGET_HAS_ICE)
 520     CPUBreakpoint *bp;
 521
 522     bp = g_malloc(sizeof(*bp));
 523
 524     bp->pc = pc;
 525     bp->flags = flags;
 526
 527     /* keep all GDB-injected breakpoints in front */
 528     if (flags & BP_GDB)
 529         QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
 530     else
 531         QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
 532
 533     breakpoint_invalidate(env, pc);
 534
 535     if (breakpoint)
 536         *breakpoint = bp;
 537     return 0;
 538 #else
 539     return -ENOSYS;
 540 #endif
 541 }
 542
 543 /* Remove a specific breakpoint.  */
 544 int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags)
 545 {
 546 #if defined(TARGET_HAS_ICE)
 547     CPUBreakpoint *bp;
 548
 549     QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
 550         if (bp->pc == pc && bp->flags == flags) {
 551             cpu_breakpoint_remove_by_ref(env, bp);
 552             return 0;
 553         }
 554     }
 555     return -ENOENT;
 556 #else
 557     return -ENOSYS;
 558 #endif
 559 }
 560
 561 /* Remove a specific breakpoint by reference.  */
 562 void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
 563 {
 564 #if defined(TARGET_HAS_ICE)
 565     QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
 566
 567     breakpoint_invalidate(env, breakpoint->pc);
 568
 569     g_free(breakpoint);
 570 #endif
 571 }
 572
 573 /* Remove all matching breakpoints. */
 574 void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
 575 {
 576 #if defined(TARGET_HAS_ICE)
 577     CPUBreakpoint *bp, *next;
 578
 579     QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
 580         if (bp->flags & mask)
 581             cpu_breakpoint_remove_by_ref(env, bp);
 582     }
 583 #endif
 584 }
 585
 586 /* enable or disable single step mode. EXCP_DEBUG is returned by the
 587    CPU loop after each instruction */
 588 void cpu_single_step(CPUArchState *env, int enabled)
 589 {
 590 #if defined(TARGET_HAS_ICE)
 591     if (env->singlestep_enabled != enabled) {
 592         env->singlestep_enabled = enabled;
 593         if (kvm_enabled())
 594             kvm_update_guest_debug(env, 0);
 595         else {
 596             /* must flush all the translated code to avoid inconsistencies */
 597             /* XXX: only flush what is necessary */
 598             tb_flush(env);
 599         }
 600     }
 601 #endif
 602 }
 603
 604 void cpu_abort(CPUArchState *env, const char *fmt, ...)
 605 {
 606     CPUState *cpu = ENV_GET_CPU(env);
 607     va_list ap;
 608     va_list ap2;
 609
 610     va_start(ap, fmt);
 611     va_copy(ap2, ap);
 612     fprintf(stderr, "qemu: fatal: ");
 613     vfprintf(stderr, fmt, ap);
 614     fprintf(stderr, "\n");
 615     cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
 616     if (qemu_log_enabled()) {
 617         qemu_log("qemu: fatal: ");
 618         qemu_log_vprintf(fmt, ap2);
 619         qemu_log("\n");
 620         log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
 621         qemu_log_flush();
 622         qemu_log_close();
 623     }
 624     va_end(ap2);
 625     va_end(ap);
 626 #if defined(CONFIG_USER_ONLY)
 627     {
 628         struct sigaction act;
 629         sigfillset(&act.sa_mask);
 630         act.sa_handler = SIG_DFL;
 631         sigaction(SIGABRT, &act, NULL);
 632     }
 633 #endif
 634     abort();
 635 }
 636
 637 CPUArchState *cpu_copy(CPUArchState *env)
 638 {
 639     CPUArchState *new_env = cpu_init(env->cpu_model_str);
 640     CPUArchState *next_cpu = new_env->next_cpu;
 641 #if defined(TARGET_HAS_ICE)
 642     CPUBreakpoint *bp;
 643     CPUWatchpoint *wp;
 644 #endif
 645
 646     memcpy(new_env, env, sizeof(CPUArchState));
 647
 648     /* Preserve chaining. */
 649     new_env->next_cpu = next_cpu;
 650
 651     /* Clone all break/watchpoints.
 652        Note: Once we support ptrace with hw-debug register access, make sure
 653        BP_CPU break/watchpoints are handled correctly on clone. */
 654     QTAILQ_INIT(&env->breakpoints);
 655     QTAILQ_INIT(&env->watchpoints);
 656 #if defined(TARGET_HAS_ICE)
 657     QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
 658         cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
 659     }
 660     QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
 661         cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
 662                               wp->flags, NULL);
 663     }
 664 #endif
 665
 666     return new_env;
 667 }
 668
 669 #if !defined(CONFIG_USER_ONLY)
 670 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t end,
 671                                       uintptr_t length)
 672 {
 673     uintptr_t start1;
 674
 675     /* we modify the TLB cache so that the dirty bit will be set again
 676        when accessing the range */
 677     start1 = (uintptr_t)qemu_safe_ram_ptr(start);
 678     /* Check that we don't span multiple blocks - this breaks the
 679        address comparisons below.  */
 680     if ((uintptr_t)qemu_safe_ram_ptr(end - 1) - start1
 681             != (end - 1) - start) {
 682         abort();
 683     }
 684     cpu_tlb_reset_dirty_all(start1, length);
 685
 686 }
 687
 688 /* Note: start and end must be within the same ram block.  */
 689 void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
 690                                      int dirty_flags)
 691 {
 692     uintptr_t length;
 693
 694     start &= TARGET_PAGE_MASK;
 695     end = TARGET_PAGE_ALIGN(end);
 696
 697     length = end - start;
 698     if (length == 0)
 699         return;
 700     cpu_physical_memory_mask_dirty_range(start, length, dirty_flags);
 701
 702     if (tcg_enabled()) {
 703         tlb_reset_dirty_range_all(start, end, length);
 704     }
 705 }
 706
 707 static int cpu_physical_memory_set_dirty_tracking(int enable)
 708 {
 709     int ret = 0;
 710     in_migration = enable;
 711     return ret;
 712 }
 713
 714 hwaddr memory_region_section_get_iotlb(CPUArchState *env,
 715                                        MemoryRegionSection *section,
 716                                        target_ulong vaddr,
 717                                        hwaddr paddr, hwaddr xlat,
 718                                        int prot,
 719                                        target_ulong *address)
 720 {
 721     hwaddr iotlb;
 722     CPUWatchpoint *wp;
 723
 724     if (memory_region_is_ram(section->mr)) {
 725         /* Normal RAM.  */
 726         iotlb = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK)
 727             + xlat;
 728         if (!section->readonly) {
 729             iotlb |= PHYS_SECTION_NOTDIRTY;
 730         } else {
 731             iotlb |= PHYS_SECTION_ROM;
 732         }
 733     } else {
 734         iotlb = section - address_space_memory.dispatch->sections;
 735         iotlb += xlat;
 736     }
 737
 738     /* Make accesses to pages with watchpoints go via the
 739        watchpoint trap routines.  */
 740     QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
 741         if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
 742             /* Avoid trapping reads of pages with a write breakpoint. */
 743             if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
 744                 iotlb = PHYS_SECTION_WATCH + paddr;
 745                 *address |= TLB_MMIO;
 746                 break;
 747             }
 748         }
 749     }
 750
 751     return iotlb;
 752 }
 753 #endif /* defined(CONFIG_USER_ONLY) */
 754
 755 #if !defined(CONFIG_USER_ONLY)
 756
 757 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
 758                              uint16_t section);
 759 static subpage_t *subpage_init(AddressSpace *as, hwaddr base);
 760
 761 static uint16_t phys_section_add(MemoryRegionSection *section)
 762 {
 763     /* The physical section number is ORed with a page-aligned
 764      * pointer to produce the iotlb entries.  Thus it should
 765      * never overflow into the page-aligned value.
 766      */
 767     assert(next_map.sections_nb < TARGET_PAGE_SIZE);
 768
 769     if (next_map.sections_nb == next_map.sections_nb_alloc) {
 770         next_map.sections_nb_alloc = MAX(next_map.sections_nb_alloc * 2,
 771                                          16);
 772         next_map.sections = g_renew(MemoryRegionSection, next_map.sections,
 773                                     next_map.sections_nb_alloc);
 774     }
 775     next_map.sections[next_map.sections_nb] = *section;
 776     memory_region_ref(section->mr);
 777     return next_map.sections_nb++;
 778 }
 779
 780 static void phys_section_destroy(MemoryRegion *mr)
 781 {
 782     memory_region_unref(mr);
 783
 784     if (mr->subpage) {
 785         subpage_t *subpage = container_of(mr, subpage_t, iomem);
 786         memory_region_destroy(&subpage->iomem);
 787         g_free(subpage);
 788     }
 789 }
 790
 791 static void phys_sections_free(PhysPageMap *map)
 792 {
 793     while (map->sections_nb > 0) {
 794         MemoryRegionSection *section = &map->sections[--map->sections_nb];
 795         phys_section_destroy(section->mr);
 796     }
 797     g_free(map->sections);
 798     g_free(map->nodes);
 799     g_free(map);
 800 }
 801
 802 static void register_subpage(AddressSpaceDispatch *d, MemoryRegionSection *section)
 803 {
 804     subpage_t *subpage;
 805     hwaddr base = section->offset_within_address_space
 806         & TARGET_PAGE_MASK;
 807     MemoryRegionSection *existing = phys_page_find(d->phys_map, base >> TARGET_PAGE_BITS,
 808                                                    next_map.nodes, next_map.sections);
 809     MemoryRegionSection subsection = {
 810         .offset_within_address_space = base,
 811         .size = int128_make64(TARGET_PAGE_SIZE),
 812     };
 813     hwaddr start, end;
 814
 815     assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
 816
 817     if (!(existing->mr->subpage)) {
 818         subpage = subpage_init(d->as, base);
 819         subsection.mr = &subpage->iomem;
 820         phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
 821                       phys_section_add(&subsection));
 822     } else {
 823         subpage = container_of(existing->mr, subpage_t, iomem);
 824     }
 825     start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
 826     end = start + int128_get64(section->size) - 1;
 827     subpage_register(subpage, start, end, phys_section_add(section));
 828 }
 829
 830
 831 static void register_multipage(AddressSpaceDispatch *d,
 832                                MemoryRegionSection *section)
 833 {
 834     hwaddr start_addr = section->offset_within_address_space;
 835     uint16_t section_index = phys_section_add(section);
 836     uint64_t num_pages = int128_get64(int128_rshift(section->size,
 837                                                     TARGET_PAGE_BITS));
 838
 839     assert(num_pages);
 840     phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
 841 }
 842
 843 static void mem_add(MemoryListener *listener, MemoryRegionSection *section)
 844 {
 845     AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
 846     AddressSpaceDispatch *d = as->next_dispatch;
 847     MemoryRegionSection now = *section, remain = *section;
 848     Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
 849
 850     if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
 851         uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
 852                        - now.offset_within_address_space;
 853
 854         now.size = int128_min(int128_make64(left), now.size);
 855         register_subpage(d, &now);
 856     } else {
 857         now.size = int128_zero();
 858     }
 859     while (int128_ne(remain.size, now.size)) {
 860         remain.size = int128_sub(remain.size, now.size);
 861         remain.offset_within_address_space += int128_get64(now.size);
 862         remain.offset_within_region += int128_get64(now.size);
 863         now = remain;
 864         if (int128_lt(remain.size, page_size)) {
 865             register_subpage(d, &now);
 866         } else if (remain.offset_within_region & ~TARGET_PAGE_MASK) {
 867             now.size = page_size;
 868             register_subpage(d, &now);
 869         } else {
 870             now.size = int128_and(now.size, int128_neg(page_size));
 871             register_multipage(d, &now);
 872         }
 873     }
 874 }
 875
 876 void qemu_flush_coalesced_mmio_buffer(void)
 877 {
 878     if (kvm_enabled())
 879         kvm_flush_coalesced_mmio_buffer();
 880 }
 881
 882 void qemu_mutex_lock_ramlist(void)
 883 {
 884     qemu_mutex_lock(&ram_list.mutex);
 885 }
 886
 887 void qemu_mutex_unlock_ramlist(void)
 888 {
 889     qemu_mutex_unlock(&ram_list.mutex);
 890 }
 891
 892 #if defined(__linux__) && !defined(TARGET_S390X)
 893
 894 #include <sys/vfs.h>
 895
 896 #define HUGETLBFS_MAGIC       0x958458f6
 897
 898 static long gethugepagesize(const char *path)
 899 {
 900     struct statfs fs;
 901     int ret;
 902
 903     do {
 904         ret = statfs(path, &fs);
 905     } while (ret != 0 && errno == EINTR);
 906
 907     if (ret != 0) {
 908         perror(path);
 909         return 0;
 910     }
 911
 912     if (fs.f_type != HUGETLBFS_MAGIC)
 913         fprintf(stderr, "Warning: path not on HugeTLBFS: %s\n", path);
 914
 915     return fs.f_bsize;
 916 }
 917
 918 static void *file_ram_alloc(RAMBlock *block,
 919                             ram_addr_t memory,
 920                             const char *path)
 921 {
 922     char *filename;
 923     char *sanitized_name;
 924     char *c;
 925     void *area;
 926     int fd;
 927 #ifdef MAP_POPULATE
 928     int flags;
 929 #endif
 930     unsigned long hpagesize;
 931
 932     hpagesize = gethugepagesize(path);
 933     if (!hpagesize) {
 934         return NULL;
 935     }
 936
 937     if (memory < hpagesize) {
 938         return NULL;
 939     }
 940
 941     if (kvm_enabled() && !kvm_has_sync_mmu()) {
 942         fprintf(stderr, "host lacks kvm mmu notifiers, -mem-path unsupported\n");
 943         return NULL;
 944     }
 945
 946     /* Make name safe to use with mkstemp by replacing '/' with '_'. */
 947     sanitized_name = g_strdup(block->mr->name);
 948     for (c = sanitized_name; *c != '\0'; c++) {
 949         if (*c == '/')
 950             *c = '_';
 951     }
 952
 953     filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
 954                                sanitized_name);
 955     g_free(sanitized_name);
 956
 957     fd = mkstemp(filename);
 958     if (fd < 0) {
 959         perror("unable to create backing store for hugepages");
 960         g_free(filename);
 961         return NULL;
 962     }
 963     unlink(filename);
 964     g_free(filename);
 965
 966     memory = (memory+hpagesize-1) & ~(hpagesize-1);
 967
 968     /*
 969      * ftruncate is not supported by hugetlbfs in older
 970      * hosts, so don't bother bailing out on errors.
 971      * If anything goes wrong with it under other filesystems,
 972      * mmap will fail.
 973      */
 974     if (ftruncate(fd, memory))
 975         perror("ftruncate");
 976
 977 #ifdef MAP_POPULATE
 978     /* NB: MAP_POPULATE won't exhaustively alloc all phys pages in the case
 979      * MAP_PRIVATE is requested.  For mem_prealloc we mmap as MAP_SHARED
 980      * to sidestep this quirk.
 981      */
 982     flags = mem_prealloc ? MAP_POPULATE | MAP_SHARED : MAP_PRIVATE;
 983     area = mmap(0, memory, PROT_READ | PROT_WRITE, flags, fd, 0);
 984 #else
 985     area = mmap(0, memory, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
 986 #endif
 987     if (area == MAP_FAILED) {
 988         perror("file_ram_alloc: can't mmap RAM pages");
 989         close(fd);
 990         return (NULL);
 991     }
 992     block->fd = fd;
 993     return area;
 994 }
 995 #endif
 996
 997 static ram_addr_t find_ram_offset(ram_addr_t size)
 998 {
 999     RAMBlock *block, *next_block;
1000     ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1001
1002     assert(size != 0); /* it would hand out same offset multiple times */
1003
1004     if (QTAILQ_EMPTY(&ram_list.blocks))
1005         return 0;
1006
1007     QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1008         ram_addr_t end, next = RAM_ADDR_MAX;
1009
1010         end = block->offset + block->length;
1011
1012         QTAILQ_FOREACH(next_block, &ram_list.blocks, next) {
1013             if (next_block->offset >= end) {
1014                 next = MIN(next, next_block->offset);
1015             }
1016         }
1017         if (next - end >= size && next - end < mingap) {
1018             offset = end;
1019             mingap = next - end;
1020         }
1021     }
1022
1023     if (offset == RAM_ADDR_MAX) {
1024         fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1025                 (uint64_t)size);
1026         abort();
1027     }
1028
1029     return offset;
1030 }
1031
1032 ram_addr_t last_ram_offset(void)
1033 {
1034     RAMBlock *block;
1035     ram_addr_t last = 0;
1036
1037     QTAILQ_FOREACH(block, &ram_list.blocks, next)
1038         last = MAX(last, block->offset + block->length);
1039
1040     return last;
1041 }
1042
1043 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1044 {
1045     int ret;
1046     QemuOpts *machine_opts;
1047
1048     /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1049     machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
1050     if (machine_opts &&
1051         !qemu_opt_get_bool(machine_opts, "dump-guest-core", true)) {
1052         ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1053         if (ret) {
1054             perror("qemu_madvise");
1055             fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1056                             "but dump_guest_core=off specified\n");
1057         }
1058     }
1059 }
1060
1061 void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev)
1062 {
1063     RAMBlock *new_block, *block;
1064
1065     new_block = NULL;
1066     QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1067         if (block->offset == addr) {
1068             new_block = block;
1069             break;
1070         }
1071     }
1072     assert(new_block);
1073     assert(!new_block->idstr[0]);
1074
1075     if (dev) {
1076         char *id = qdev_get_dev_path(dev);
1077         if (id) {
1078             snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1079             g_free(id);
1080         }
1081     }
1082     pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1083
1084     /* This assumes the iothread lock is taken here too.  */
1085     qemu_mutex_lock_ramlist();
1086     QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1087         if (block != new_block && !strcmp(block->idstr, new_block->idstr)) {
1088             fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1089                     new_block->idstr);
1090             abort();
1091         }
1092     }
1093     qemu_mutex_unlock_ramlist();
1094 }
1095
1096 static int memory_try_enable_merging(void *addr, size_t len)
1097 {
1098     QemuOpts *opts;
1099
1100     opts = qemu_opts_find(qemu_find_opts("machine"), 0);
1101     if (opts && !qemu_opt_get_bool(opts, "mem-merge", true)) {
1102         /* disabled by the user */
1103         return 0;
1104     }
1105
1106     return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1107 }
1108
1109 ram_addr_t qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
1110                                    MemoryRegion *mr)
1111 {
1112     RAMBlock *block, *new_block;
1113
1114     size = TARGET_PAGE_ALIGN(size);
1115     new_block = g_malloc0(sizeof(*new_block));
1116
1117     /* This assumes the iothread lock is taken here too.  */
1118     qemu_mutex_lock_ramlist();
1119     new_block->mr = mr;
1120     new_block->offset = find_ram_offset(size);
1121     if (host) {
1122         new_block->host = host;
1123         new_block->flags |= RAM_PREALLOC_MASK;
1124     } else {
1125         if (mem_path) {
1126 #if defined (__linux__) && !defined(TARGET_S390X)
1127             new_block->host = file_ram_alloc(new_block, size, mem_path);
1128             if (!new_block->host) {
1129                 new_block->host = qemu_anon_ram_alloc(size);
1130                 memory_try_enable_merging(new_block->host, size);
1131             }
1132 #else
1133             fprintf(stderr, "-mem-path option unsupported\n");
1134             exit(1);
1135 #endif
1136         } else {
1137             if (xen_enabled()) {
1138                 xen_ram_alloc(new_block->offset, size, mr);
1139             } else if (kvm_enabled()) {
1140                 /* some s390/kvm configurations have special constraints */
1141                 new_block->host = kvm_ram_alloc(size);
1142             } else {
1143                 new_block->host = qemu_anon_ram_alloc(size);
1144             }
1145             memory_try_enable_merging(new_block->host, size);
1146         }
1147     }
1148     new_block->length = size;
1149
1150     /* Keep the list sorted from biggest to smallest block.  */
1151     QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1152         if (block->length < new_block->length) {
1153             break;
1154         }
1155     }
1156     if (block) {
1157         QTAILQ_INSERT_BEFORE(block, new_block, next);
1158     } else {
1159         QTAILQ_INSERT_TAIL(&ram_list.blocks, new_block, next);
1160     }
1161     ram_list.mru_block = NULL;
1162
1163     ram_list.version++;
1164     qemu_mutex_unlock_ramlist();
1165
1166     ram_list.phys_dirty = g_realloc(ram_list.phys_dirty,
1167                                        last_ram_offset() >> TARGET_PAGE_BITS);
1168     memset(ram_list.phys_dirty + (new_block->offset >> TARGET_PAGE_BITS),
1169            0, size >> TARGET_PAGE_BITS);
1170     cpu_physical_memory_set_dirty_range(new_block->offset, size, 0xff);
1171
1172     qemu_ram_setup_dump(new_block->host, size);
1173     qemu_madvise(new_block->host, size, QEMU_MADV_HUGEPAGE);
1174
1175     if (kvm_enabled())
1176         kvm_setup_guest_memory(new_block->host, size);
1177
1178     return new_block->offset;
1179 }
1180
1181 ram_addr_t qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr)
1182 {
1183     return qemu_ram_alloc_from_ptr(size, NULL, mr);
1184 }
1185
1186 void qemu_ram_free_from_ptr(ram_addr_t addr)
1187 {
1188     RAMBlock *block;
1189
1190     /* This assumes the iothread lock is taken here too.  */
1191     qemu_mutex_lock_ramlist();
1192     QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1193         if (addr == block->offset) {
1194             QTAILQ_REMOVE(&ram_list.blocks, block, next);
1195             ram_list.mru_block = NULL;
1196             ram_list.version++;
1197             g_free(block);
1198             break;
1199         }
1200     }
1201     qemu_mutex_unlock_ramlist();
1202 }
1203
1204 void qemu_ram_free(ram_addr_t addr)
1205 {
1206     RAMBlock *block;
1207
1208     /* This assumes the iothread lock is taken here too.  */
1209     qemu_mutex_lock_ramlist();
1210     QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1211         if (addr == block->offset) {
1212             QTAILQ_REMOVE(&ram_list.blocks, block, next);
1213             ram_list.mru_block = NULL;
1214             ram_list.version++;
1215             if (block->flags & RAM_PREALLOC_MASK) {
1216                 ;
1217             } else if (mem_path) {
1218 #if defined (__linux__) && !defined(TARGET_S390X)
1219                 if (block->fd) {
1220                     munmap(block->host, block->length);
1221                     close(block->fd);
1222                 } else {
1223                     qemu_anon_ram_free(block->host, block->length);
1224                 }
1225 #else
1226                 abort();
1227 #endif
1228             } else {
1229                 if (xen_enabled()) {
1230                     xen_invalidate_map_cache_entry(block->host);
1231                 } else {
1232                     qemu_anon_ram_free(block->host, block->length);
1233                 }
1234             }
1235             g_free(block);
1236             break;
1237         }
1238     }
1239     qemu_mutex_unlock_ramlist();
1240
1241 }
1242
1243 #ifndef _WIN32
1244 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
1245 {
1246     RAMBlock *block;
1247     ram_addr_t offset;
1248     int flags;
1249     void *area, *vaddr;
1250
1251     QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1252         offset = addr - block->offset;
1253         if (offset < block->length) {
1254             vaddr = block->host + offset;
1255             if (block->flags & RAM_PREALLOC_MASK) {
1256                 ;
1257             } else {
1258                 flags = MAP_FIXED;
1259                 munmap(vaddr, length);
1260                 if (mem_path) {
1261 #if defined(__linux__) && !defined(TARGET_S390X)
1262                     if (block->fd) {
1263 #ifdef MAP_POPULATE
1264                         flags |= mem_prealloc ? MAP_POPULATE | MAP_SHARED :
1265                             MAP_PRIVATE;
1266 #else
1267                         flags |= MAP_PRIVATE;
1268 #endif
1269                         area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
1270                                     flags, block->fd, offset);
1271                     } else {
1272                         flags |= MAP_PRIVATE | MAP_ANONYMOUS;
1273                         area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
1274                                     flags, -1, 0);
1275                     }
1276 #else
1277                     abort();
1278 #endif
1279                 } else {
1280 #if defined(TARGET_S390X) && defined(CONFIG_KVM)
1281                     flags |= MAP_SHARED | MAP_ANONYMOUS;
1282                     area = mmap(vaddr, length, PROT_EXEC|PROT_READ|PROT_WRITE,
1283                                 flags, -1, 0);
1284 #else
1285                     flags |= MAP_PRIVATE | MAP_ANONYMOUS;
1286                     area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
1287                                 flags, -1, 0);
1288 #endif
1289                 }
1290                 if (area != vaddr) {
1291                     fprintf(stderr, "Could not remap addr: "
1292                             RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n",
1293                             length, addr);
1294                     exit(1);
1295                 }
1296                 memory_try_enable_merging(vaddr, length);
1297                 qemu_ram_setup_dump(vaddr, length);
1298             }
1299             return;
1300         }
1301     }
1302 }
1303 #endif /* !_WIN32 */
1304
1305 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1306 {
1307     RAMBlock *block;
1308
1309     /* The list is protected by the iothread lock here.  */
1310     block = ram_list.mru_block;
1311     if (block && addr - block->offset < block->length) {
1312         goto found;
1313     }
1314     QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1315         if (addr - block->offset < block->length) {
1316             goto found;
1317         }
1318     }
1319
1320     fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1321     abort();
1322
1323 found:
1324     ram_list.mru_block = block;
1325     return block;
1326 }
1327
1328 /* Return a host pointer to ram allocated with qemu_ram_alloc.
1329    With the exception of the softmmu code in this file, this should
1330    only be used for local memory (e.g. video ram) that the device owns,
1331    and knows it isn't going to access beyond the end of the block.
1332
1333    It should not be used for general purpose DMA.
1334    Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
1335  */
1336 void *qemu_get_ram_ptr(ram_addr_t addr)
1337 {
1338     RAMBlock *block = qemu_get_ram_block(addr);
1339
1340     if (xen_enabled()) {
1341         /* We need to check if the requested address is in the RAM
1342          * because we don't want to map the entire memory in QEMU.
1343          * In that case just map until the end of the page.
1344          */
1345         if (block->offset == 0) {
1346             return xen_map_cache(addr, 0, 0);
1347         } else if (block->host == NULL) {
1348             block->host =
1349                 xen_map_cache(block->offset, block->length, 1);
1350         }
1351     }
1352     return block->host + (addr - block->offset);
1353 }
1354
1355 /* Return a host pointer to ram allocated with qemu_ram_alloc.  Same as
1356  * qemu_get_ram_ptr but do not touch ram_list.mru_block.
1357  *
1358  * ??? Is this still necessary?
1359  */
1360 static void *qemu_safe_ram_ptr(ram_addr_t addr)
1361 {
1362     RAMBlock *block;
1363
1364     /* The list is protected by the iothread lock here.  */
1365     QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1366         if (addr - block->offset < block->length) {
1367             if (xen_enabled()) {
1368                 /* We need to check if the requested address is in the RAM
1369                  * because we don't want to map the entire memory in QEMU.
1370                  * In that case just map until the end of the page.
1371                  */
1372                 if (block->offset == 0) {
1373                     return xen_map_cache(addr, 0, 0);
1374                 } else if (block->host == NULL) {
1375                     block->host =
1376                         xen_map_cache(block->offset, block->length, 1);
1377                 }
1378             }
1379             return block->host + (addr - block->offset);
1380         }
1381     }
1382
1383     fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1384     abort();
1385
1386     return NULL;
1387 }
1388
1389 /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr
1390  * but takes a size argument */
1391 static void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size)
1392 {
1393     if (*size == 0) {
1394         return NULL;
1395     }
1396     if (xen_enabled()) {
1397         return xen_map_cache(addr, *size, 1);
1398     } else {
1399         RAMBlock *block;
1400
1401         QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1402             if (addr - block->offset < block->length) {
1403                 if (addr - block->offset + *size > block->length)
1404                     *size = block->length - addr + block->offset;
1405                 return block->host + (addr - block->offset);
1406             }
1407         }
1408
1409         fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1410         abort();
1411     }
1412 }
1413
1414 /* Some of the softmmu routines need to translate from a host pointer
1415    (typically a TLB entry) back to a ram offset.  */
1416 MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr)
1417 {
1418     RAMBlock *block;
1419     uint8_t *host = ptr;
1420
1421     if (xen_enabled()) {
1422         *ram_addr = xen_ram_addr_from_mapcache(ptr);
1423         return qemu_get_ram_block(*ram_addr)->mr;
1424     }
1425
1426     block = ram_list.mru_block;
1427     if (block && block->host && host - block->host < block->length) {
1428         goto found;
1429     }
1430
1431     QTAILQ_FOREACH(block, &ram_list.blocks, next) {
1432         /* This case append when the block is not mapped. */
1433         if (block->host == NULL) {
1434             continue;
1435         }
1436         if (host - block->host < block->length) {
1437             goto found;
1438         }
1439     }
1440
1441     return NULL;
1442
1443 found:
1444     *ram_addr = block->offset + (host - block->host);
1445     return block->mr;
1446 }
1447
1448 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
1449                                uint64_t val, unsigned size)
1450 {
1451     int dirty_flags;
1452     dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
1453     if (!(dirty_flags & CODE_DIRTY_FLAG)) {
1454         tb_invalidate_phys_page_fast(ram_addr, size);
1455         dirty_flags = cpu_physical_memory_get_dirty_flags(ram_addr);
1456     }
1457     switch (size) {
1458     case 1:
1459         stb_p(qemu_get_ram_ptr(ram_addr), val);
1460         break;
1461     case 2:
1462         stw_p(qemu_get_ram_ptr(ram_addr), val);
1463         break;
1464     case 4:
1465         stl_p(qemu_get_ram_ptr(ram_addr), val);
1466         break;
1467     default:
1468         abort();
1469     }
1470     dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
1471     cpu_physical_memory_set_dirty_flags(ram_addr, dirty_flags);
1472     /* we remove the notdirty callback only if the code has been
1473        flushed */
1474     if (dirty_flags == 0xff)
1475         tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
1476 }
1477
1478 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
1479                                  unsigned size, bool is_write)
1480 {
1481     return is_write;
1482 }
1483
1484 static const MemoryRegionOps notdirty_mem_ops = {
1485     .write = notdirty_mem_write,
1486     .valid.accepts = notdirty_mem_accepts,
1487     .endianness = DEVICE_NATIVE_ENDIAN,
1488 };
1489
1490 /* Generate a debug exception if a watchpoint has been hit.  */
1491 static void check_watchpoint(int offset, int len_mask, int flags)
1492 {
1493     CPUArchState *env = cpu_single_env;
1494     target_ulong pc, cs_base;
1495     target_ulong vaddr;
1496     CPUWatchpoint *wp;
1497     int cpu_flags;
1498
1499     if (env->watchpoint_hit) {
1500         /* We re-entered the check after replacing the TB. Now raise
1501          * the debug interrupt so that is will trigger after the
1502          * current instruction. */
1503         cpu_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_DEBUG);
1504         return;
1505     }
1506     vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
1507     QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
1508         if ((vaddr == (wp->vaddr & len_mask) ||
1509              (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
1510             wp->flags |= BP_WATCHPOINT_HIT;
1511             if (!env->watchpoint_hit) {
1512                 env->watchpoint_hit = wp;
1513                 tb_check_watchpoint(env);
1514                 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
1515                     env->exception_index = EXCP_DEBUG;
1516                     cpu_loop_exit(env);
1517                 } else {
1518                     cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
1519                     tb_gen_code(env, pc, cs_base, cpu_flags, 1);
1520                     cpu_resume_from_signal(env, NULL);
1521                 }
1522             }
1523         } else {
1524             wp->flags &= ~BP_WATCHPOINT_HIT;
1525         }
1526     }
1527 }
1528
1529 /* Watchpoint access routines.  Watchpoints are inserted using TLB tricks,
1530    so these check for a hit then pass through to the normal out-of-line
1531    phys routines.  */
1532 static uint64_t watch_mem_read(void *opaque, hwaddr addr,
1533                                unsigned size)
1534 {
1535     check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
1536     switch (size) {
1537     case 1: return ldub_phys(addr);
1538     case 2: return lduw_phys(addr);
1539     case 4: return ldl_phys(addr);
1540     default: abort();
1541     }
1542 }
1543
1544 static void watch_mem_write(void *opaque, hwaddr addr,
1545                             uint64_t val, unsigned size)
1546 {
1547     check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
1548     switch (size) {
1549     case 1:
1550         stb_phys(addr, val);
1551         break;
1552     case 2:
1553         stw_phys(addr, val);
1554         break;
1555     case 4:
1556         stl_phys(addr, val);
1557         break;
1558     default: abort();
1559     }
1560 }
1561
1562 static const MemoryRegionOps watch_mem_ops = {
1563     .read = watch_mem_read,
1564     .write = watch_mem_write,
1565     .endianness = DEVICE_NATIVE_ENDIAN,
1566 };
1567
1568 static uint64_t subpage_read(void *opaque, hwaddr addr,
1569                              unsigned len)
1570 {
1571     subpage_t *subpage = opaque;
1572     uint8_t buf[4];
1573
1574 #if defined(DEBUG_SUBPAGE)
1575     printf("%s: subpage %p len %d addr " TARGET_FMT_plx "\n", __func__,
1576            subpage, len, addr);
1577 #endif
1578     address_space_read(subpage->as, addr + subpage->base, buf, len);
1579     switch (len) {
1580     case 1:
1581         return ldub_p(buf);
1582     case 2:
1583         return lduw_p(buf);
1584     case 4:
1585         return ldl_p(buf);
1586     default:
1587         abort();
1588     }
1589 }
1590
1591 static void subpage_write(void *opaque, hwaddr addr,
1592                           uint64_t value, unsigned len)
1593 {
1594     subpage_t *subpage = opaque;
1595     uint8_t buf[4];
1596
1597 #if defined(DEBUG_SUBPAGE)
1598     printf("%s: subpage %p len %d addr " TARGET_FMT_plx
1599            " value %"PRIx64"\n",
1600            __func__, subpage, len, addr, value);
1601 #endif
1602     switch (len) {
1603     case 1:
1604         stb_p(buf, value);
1605         break;
1606     case 2:
1607         stw_p(buf, value);
1608         break;
1609     case 4:
1610         stl_p(buf, value);
1611         break;
1612     default:
1613         abort();
1614     }
1615     address_space_write(subpage->as, addr + subpage->base, buf, len);
1616 }
1617
1618 static bool subpage_accepts(void *opaque, hwaddr addr,
1619                             unsigned size, bool is_write)
1620 {
1621     subpage_t *subpage = opaque;
1622 #if defined(DEBUG_SUBPAGE)
1623     printf("%s: subpage %p %c len %d addr " TARGET_FMT_plx "\n",
1624            __func__, subpage, is_write ? 'w' : 'r', len, addr);
1625 #endif
1626
1627     return address_space_access_valid(subpage->as, addr + subpage->base,
1628                                       size, is_write);
1629 }
1630
1631 static const MemoryRegionOps subpage_ops = {
1632     .read = subpage_read,
1633     .write = subpage_write,
1634     .valid.accepts = subpage_accepts,
1635     .endianness = DEVICE_NATIVE_ENDIAN,
1636 };
1637
1638 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1639                              uint16_t section)
1640 {
1641     int idx, eidx;
1642
1643     if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
1644         return -1;
1645     idx = SUBPAGE_IDX(start);
1646     eidx = SUBPAGE_IDX(end);
1647 #if defined(DEBUG_SUBPAGE)
1648     printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__,
1649            mmio, start, end, idx, eidx, memory);
1650 #endif
1651     for (; idx <= eidx; idx++) {
1652         mmio->sub_section[idx] = section;
1653     }
1654
1655     return 0;
1656 }
1657
1658 static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
1659 {
1660     subpage_t *mmio;
1661
1662     mmio = g_malloc0(sizeof(subpage_t));
1663
1664     mmio->as = as;
1665     mmio->base = base;
1666     memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
1667                           "subpage", TARGET_PAGE_SIZE);
1668     mmio->iomem.subpage = true;
1669 #if defined(DEBUG_SUBPAGE)
1670     printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
1671            mmio, base, TARGET_PAGE_SIZE, subpage_memory);
1672 #endif
1673     subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
1674
1675     return mmio;
1676 }
1677
1678 static uint16_t dummy_section(MemoryRegion *mr)
1679 {
1680     MemoryRegionSection section = {
1681         .mr = mr,
1682         .offset_within_address_space = 0,
1683         .offset_within_region = 0,
1684         .size = int128_2_64(),
1685     };
1686
1687     return phys_section_add(&section);
1688 }
1689
1690 MemoryRegion *iotlb_to_region(hwaddr index)
1691 {
1692     return address_space_memory.dispatch->sections[index & ~TARGET_PAGE_MASK].mr;
1693 }
1694
1695 static void io_mem_init(void)
1696 {
1697     memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, "rom", UINT64_MAX);
1698     memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
1699                           "unassigned", UINT64_MAX);
1700     memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
1701                           "notdirty", UINT64_MAX);
1702     memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
1703                           "watch", UINT64_MAX);
1704 }
1705
1706 static void mem_begin(MemoryListener *listener)
1707 {
1708     AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
1709     AddressSpaceDispatch *d = g_new(AddressSpaceDispatch, 1);
1710
1711     d->phys_map  = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .is_leaf = 0 };
1712     d->as = as;
1713     as->next_dispatch = d;
1714 }
1715
1716 static void mem_commit(MemoryListener *listener)
1717 {
1718     AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
1719     AddressSpaceDispatch *cur = as->dispatch;
1720     AddressSpaceDispatch *next = as->next_dispatch;
1721
1722     next->nodes = next_map.nodes;
1723     next->sections = next_map.sections;
1724
1725     as->dispatch = next;
1726     g_free(cur);
1727 }
1728
1729 static void core_begin(MemoryListener *listener)
1730 {
1731     uint16_t n;
1732
1733     prev_map = g_new(PhysPageMap, 1);
1734     *prev_map = next_map;
1735
1736     memset(&next_map, 0, sizeof(next_map));
1737     n = dummy_section(&io_mem_unassigned);
1738     assert(n == PHYS_SECTION_UNASSIGNED);
1739     n = dummy_section(&io_mem_notdirty);
1740     assert(n == PHYS_SECTION_NOTDIRTY);
1741     n = dummy_section(&io_mem_rom);
1742     assert(n == PHYS_SECTION_ROM);
1743     n = dummy_section(&io_mem_watch);
1744     assert(n == PHYS_SECTION_WATCH);
1745 }
1746
1747 /* This listener's commit run after the other AddressSpaceDispatch listeners'.
1748  * All AddressSpaceDispatch instances have switched to the next map.
1749  */
1750 static void core_commit(MemoryListener *listener)
1751 {
1752     phys_sections_free(prev_map);
1753 }
1754
1755 static void tcg_commit(MemoryListener *listener)
1756 {
1757     CPUArchState *env;
1758
1759     /* since each CPU stores ram addresses in its TLB cache, we must
1760        reset the modified entries */
1761     /* XXX: slow ! */
1762     for(env = first_cpu; env != NULL; env = env->next_cpu) {
1763         tlb_flush(env, 1);
1764     }
1765 }
1766
1767 static void core_log_global_start(MemoryListener *listener)
1768 {
1769     cpu_physical_memory_set_dirty_tracking(1);
1770 }
1771
1772 static void core_log_global_stop(MemoryListener *listener)
1773 {
1774     cpu_physical_memory_set_dirty_tracking(0);
1775 }
1776
1777 static MemoryListener core_memory_listener = {
1778     .begin = core_begin,
1779     .commit = core_commit,
1780     .log_global_start = core_log_global_start,
1781     .log_global_stop = core_log_global_stop,
1782     .priority = 1,
1783 };
1784
1785 static MemoryListener tcg_memory_listener = {
1786     .commit = tcg_commit,
1787 };
1788
1789 void address_space_init_dispatch(AddressSpace *as)
1790 {
1791     as->dispatch = NULL;
1792     as->dispatch_listener = (MemoryListener) {
1793         .begin = mem_begin,
1794         .commit = mem_commit,
1795         .region_add = mem_add,
1796         .region_nop = mem_add,
1797         .priority = 0,
1798     };
1799     memory_listener_register(&as->dispatch_listener, as);
1800 }
1801
1802 void address_space_destroy_dispatch(AddressSpace *as)
1803 {
1804     AddressSpaceDispatch *d = as->dispatch;
1805
1806     memory_listener_unregister(&as->dispatch_listener);
1807     g_free(d);
1808     as->dispatch = NULL;
1809 }
1810
1811 static void memory_map_init(void)
1812 {
1813     system_memory = g_malloc(sizeof(*system_memory));
1814     memory_region_init(system_memory, NULL, "system", INT64_MAX);
1815     address_space_init(&address_space_memory, system_memory, "memory");
1816
1817     system_io = g_malloc(sizeof(*system_io));
1818     memory_region_init(system_io, NULL, "io", 65536);
1819     address_space_init(&address_space_io, system_io, "I/O");
1820
1821     memory_listener_register(&core_memory_listener, &address_space_memory);
1822     memory_listener_register(&tcg_memory_listener, &address_space_memory);
1823 }
1824
1825 MemoryRegion *get_system_memory(void)
1826 {
1827     return system_memory;
1828 }
1829
1830 MemoryRegion *get_system_io(void)
1831 {
1832     return system_io;
1833 }
1834
1835 #endif /* !defined(CONFIG_USER_ONLY) */
1836
1837 /* physical memory access (slow version, mainly for debug) */
1838 #if defined(CONFIG_USER_ONLY)
1839 int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
1840                         uint8_t *buf, int len, int is_write)
1841 {
1842     int l, flags;
1843     target_ulong page;
1844     void * p;
1845
1846     while (len > 0) {
1847         page = addr & TARGET_PAGE_MASK;
1848         l = (page + TARGET_PAGE_SIZE) - addr;
1849         if (l > len)
1850             l = len;
1851         flags = page_get_flags(page);
1852         if (!(flags & PAGE_VALID))
1853             return -1;
1854         if (is_write) {
1855             if (!(flags & PAGE_WRITE))
1856                 return -1;
1857             /* XXX: this code should not depend on lock_user */
1858             if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
1859                 return -1;
1860             memcpy(p, buf, l);
1861             unlock_user(p, addr, l);
1862         } else {
1863             if (!(flags & PAGE_READ))
1864                 return -1;
1865             /* XXX: this code should not depend on lock_user */
1866             if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
1867                 return -1;
1868             memcpy(buf, p, l);
1869             unlock_user(p, addr, 0);
1870         }
1871         len -= l;
1872         buf += l;
1873         addr += l;
1874     }
1875     return 0;
1876 }
1877
1878 #else
1879
1880 static void invalidate_and_set_dirty(hwaddr addr,
1881                                      hwaddr length)
1882 {
1883     if (!cpu_physical_memory_is_dirty(addr)) {
1884         /* invalidate code */
1885         tb_invalidate_phys_page_range(addr, addr + length, 0);
1886         /* set dirty bit */
1887         cpu_physical_memory_set_dirty_flags(addr, (0xff & ~CODE_DIRTY_FLAG));
1888     }
1889     xen_modified_memory(addr, length);
1890 }
1891
1892 static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write)
1893 {
1894     if (memory_region_is_ram(mr)) {
1895         return !(is_write && mr->readonly);
1896     }
1897     if (memory_region_is_romd(mr)) {
1898         return !is_write;
1899     }
1900
1901     return false;
1902 }
1903
1904 static inline int memory_access_size(MemoryRegion *mr, int l, hwaddr addr)
1905 {
1906     if (l >= 4 && (((addr & 3) == 0 || mr->ops->impl.unaligned))) {
1907         return 4;
1908     }
1909     if (l >= 2 && (((addr & 1) == 0) || mr->ops->impl.unaligned)) {
1910         return 2;
1911     }
1912     return 1;
1913 }
1914
1915 bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
1916                       int len, bool is_write)
1917 {
1918     hwaddr l;
1919     uint8_t *ptr;
1920     uint64_t val;
1921     hwaddr addr1;
1922     MemoryRegion *mr;
1923     bool error = false;
1924
1925     while (len > 0) {
1926         l = len;
1927         mr = address_space_translate(as, addr, &addr1, &l, is_write);
1928
1929         if (is_write) {
1930             if (!memory_access_is_direct(mr, is_write)) {
1931                 l = memory_access_size(mr, l, addr1);
1932                 /* XXX: could force cpu_single_env to NULL to avoid
1933                    potential bugs */
1934                 if (l == 4) {
1935                     /* 32 bit write access */
1936                     val = ldl_p(buf);
1937                     error |= io_mem_write(mr, addr1, val, 4);
1938                 } else if (l == 2) {
1939                     /* 16 bit write access */
1940                     val = lduw_p(buf);
1941                     error |= io_mem_write(mr, addr1, val, 2);
1942                 } else {
1943                     /* 8 bit write access */
1944                     val = ldub_p(buf);
1945                     error |= io_mem_write(mr, addr1, val, 1);
1946                 }
1947             } else {
1948                 addr1 += memory_region_get_ram_addr(mr);
1949                 /* RAM case */
1950                 ptr = qemu_get_ram_ptr(addr1);
1951                 memcpy(ptr, buf, l);
1952                 invalidate_and_set_dirty(addr1, l);
1953             }
1954         } else {
1955             if (!memory_access_is_direct(mr, is_write)) {
1956                 /* I/O case */
1957                 l = memory_access_size(mr, l, addr1);
1958                 if (l == 4) {
1959                     /* 32 bit read access */
1960                     error |= io_mem_read(mr, addr1, &val, 4);
1961                     stl_p(buf, val);
1962                 } else if (l == 2) {
1963                     /* 16 bit read access */
1964                     error |= io_mem_read(mr, addr1, &val, 2);
1965                     stw_p(buf, val);
1966                 } else {
1967                     /* 8 bit read access */
1968                     error |= io_mem_read(mr, addr1, &val, 1);
1969                     stb_p(buf, val);
1970                 }
1971             } else {
1972                 /* RAM case */
1973                 ptr = qemu_get_ram_ptr(mr->ram_addr + addr1);
1974                 memcpy(buf, ptr, l);
1975             }
1976         }
1977         len -= l;
1978         buf += l;
1979         addr += l;
1980     }
1981
1982     return error;
1983 }
1984
1985 bool address_space_write(AddressSpace *as, hwaddr addr,
1986                          const uint8_t *buf, int len)
1987 {
1988     return address_space_rw(as, addr, (uint8_t *)buf, len, true);
1989 }
1990
1991 bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
1992 {
1993     return address_space_rw(as, addr, buf, len, false);
1994 }
1995
1996
1997 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
1998                             int len, int is_write)
1999 {
2000     address_space_rw(&address_space_memory, addr, buf, len, is_write);
2001 }
2002
2003 /* used for ROM loading : can write in RAM and ROM */
2004 void cpu_physical_memory_write_rom(hwaddr addr,
2005                                    const uint8_t *buf, int len)
2006 {
2007     hwaddr l;
2008     uint8_t *ptr;
2009     hwaddr addr1;
2010     MemoryRegion *mr;
2011
2012     while (len > 0) {
2013         l = len;
2014         mr = address_space_translate(&address_space_memory,
2015                                      addr, &addr1, &l, true);
2016
2017         if (!(memory_region_is_ram(mr) ||
2018               memory_region_is_romd(mr))) {
2019             /* do nothing */
2020         } else {
2021             addr1 += memory_region_get_ram_addr(mr);
2022             /* ROM/RAM case */
2023             ptr = qemu_get_ram_ptr(addr1);
2024             memcpy(ptr, buf, l);
2025             invalidate_and_set_dirty(addr1, l);
2026         }
2027         len -= l;
2028         buf += l;
2029         addr += l;
2030     }
2031 }
2032
2033 typedef struct {
2034     MemoryRegion *mr;
2035     void *buffer;
2036     hwaddr addr;
2037     hwaddr len;
2038 } BounceBuffer;
2039
2040 static BounceBuffer bounce;
2041
2042 typedef struct MapClient {
2043     void *opaque;
2044     void (*callback)(void *opaque);
2045     QLIST_ENTRY(MapClient) link;
2046 } MapClient;
2047
2048 static QLIST_HEAD(map_client_list, MapClient) map_client_list
2049     = QLIST_HEAD_INITIALIZER(map_client_list);
2050
2051 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque))
2052 {
2053     MapClient *client = g_malloc(sizeof(*client));
2054
2055     client->opaque = opaque;
2056     client->callback = callback;
2057     QLIST_INSERT_HEAD(&map_client_list, client, link);
2058     return client;
2059 }
2060
2061 static void cpu_unregister_map_client(void *_client)
2062 {
2063     MapClient *client = (MapClient *)_client;
2064
2065     QLIST_REMOVE(client, link);
2066     g_free(client);
2067 }
2068
2069 static void cpu_notify_map_clients(void)
2070 {
2071     MapClient *client;
2072
2073     while (!QLIST_EMPTY(&map_client_list)) {
2074         client = QLIST_FIRST(&map_client_list);
2075         client->callback(client->opaque);
2076         cpu_unregister_map_client(client);
2077     }
2078 }
2079
2080 bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write)
2081 {
2082     MemoryRegion *mr;
2083     hwaddr l, xlat;
2084
2085     while (len > 0) {
2086         l = len;
2087         mr = address_space_translate(as, addr, &xlat, &l, is_write);
2088         if (!memory_access_is_direct(mr, is_write)) {
2089             l = memory_access_size(mr, l, addr);
2090             if (!memory_region_access_valid(mr, xlat, l, is_write)) {
2091                 return false;
2092             }
2093         }
2094
2095         len -= l;
2096         addr += l;
2097     }
2098     return true;
2099 }
2100
2101 /* Map a physical memory region into a host virtual address.
2102  * May map a subset of the requested range, given by and returned in *plen.
2103  * May return NULL if resources needed to perform the mapping are exhausted.
2104  * Use only for reads OR writes - not for read-modify-write operations.
2105  * Use cpu_register_map_client() to know when retrying the map operation is
2106  * likely to succeed.
2107  */
2108 void *address_space_map(AddressSpace *as,
2109                         hwaddr addr,
2110                         hwaddr *plen,
2111                         bool is_write)
2112 {
2113     hwaddr len = *plen;
2114     hwaddr done = 0;
2115     hwaddr l, xlat, base;
2116     MemoryRegion *mr, *this_mr;
2117     ram_addr_t raddr;
2118
2119     if (len == 0) {
2120         return NULL;
2121     }
2122
2123     l = len;
2124     mr = address_space_translate(as, addr, &xlat, &l, is_write);
2125     if (!memory_access_is_direct(mr, is_write)) {
2126         if (bounce.buffer) {
2127             return NULL;
2128         }
2129         bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE);
2130         bounce.addr = addr;
2131         bounce.len = l;
2132
2133         memory_region_ref(mr);
2134         bounce.mr = mr;
2135         if (!is_write) {
2136             address_space_read(as, addr, bounce.buffer, l);
2137         }
2138
2139         *plen = l;
2140         return bounce.buffer;
2141     }
2142
2143     base = xlat;
2144     raddr = memory_region_get_ram_addr(mr);
2145
2146     for (;;) {
2147         len -= l;
2148         addr += l;
2149         done += l;
2150         if (len == 0) {
2151             break;
2152         }
2153
2154         l = len;
2155         this_mr = address_space_translate(as, addr, &xlat, &l, is_write);
2156         if (this_mr != mr || xlat != base + done) {
2157             break;
2158         }
2159     }
2160
2161     memory_region_ref(mr);
2162     *plen = done;
2163     return qemu_ram_ptr_length(raddr + base, plen);
2164 }
2165
2166 /* Unmaps a memory region previously mapped by address_space_map().
2167  * Will also mark the memory as dirty if is_write == 1.  access_len gives
2168  * the amount of memory that was actually read or written by the caller.
2169  */
2170 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
2171                          int is_write, hwaddr access_len)
2172 {
2173     if (buffer != bounce.buffer) {
2174         MemoryRegion *mr;
2175         ram_addr_t addr1;
2176
2177         mr = qemu_ram_addr_from_host(buffer, &addr1);
2178         assert(mr != NULL);
2179         if (is_write) {
2180             while (access_len) {
2181                 unsigned l;
2182                 l = TARGET_PAGE_SIZE;
2183                 if (l > access_len)
2184                     l = access_len;
2185                 invalidate_and_set_dirty(addr1, l);
2186                 addr1 += l;
2187                 access_len -= l;
2188             }
2189         }
2190         if (xen_enabled()) {
2191             xen_invalidate_map_cache_entry(buffer);
2192         }
2193         memory_region_unref(mr);
2194         return;
2195     }
2196     if (is_write) {
2197         address_space_write(as, bounce.addr, bounce.buffer, access_len);
2198     }
2199     qemu_vfree(bounce.buffer);
2200     bounce.buffer = NULL;
2201     memory_region_unref(bounce.mr);
2202     cpu_notify_map_clients();
2203 }
2204
2205 void *cpu_physical_memory_map(hwaddr addr,
2206                               hwaddr *plen,
2207                               int is_write)
2208 {
2209     return address_space_map(&address_space_memory, addr, plen, is_write);
2210 }
2211
2212 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
2213                                int is_write, hwaddr access_len)
2214 {
2215     return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
2216 }
2217
2218 /* warning: addr must be aligned */
2219 static inline uint32_t ldl_phys_internal(hwaddr addr,
2220                                          enum device_endian endian)
2221 {
2222     uint8_t *ptr;
2223     uint64_t val;
2224     MemoryRegion *mr;
2225     hwaddr l = 4;
2226     hwaddr addr1;
2227
2228     mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
2229                                  false);
2230     if (l < 4 || !memory_access_is_direct(mr, false)) {
2231         /* I/O case */
2232         io_mem_read(mr, addr1, &val, 4);
2233 #if defined(TARGET_WORDS_BIGENDIAN)
2234         if (endian == DEVICE_LITTLE_ENDIAN) {
2235             val = bswap32(val);
2236         }
2237 #else
2238         if (endian == DEVICE_BIG_ENDIAN) {
2239             val = bswap32(val);
2240         }
2241 #endif
2242     } else {
2243         /* RAM case */
2244         ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr)
2245                                 & TARGET_PAGE_MASK)
2246                                + addr1);
2247         switch (endian) {
2248         case DEVICE_LITTLE_ENDIAN:
2249             val = ldl_le_p(ptr);
2250             break;
2251         case DEVICE_BIG_ENDIAN:
2252             val = ldl_be_p(ptr);
2253             break;
2254         default:
2255             val = ldl_p(ptr);
2256             break;
2257         }
2258     }
2259     return val;
2260 }
2261
2262 uint32_t ldl_phys(hwaddr addr)
2263 {
2264     return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
2265 }
2266
2267 uint32_t ldl_le_phys(hwaddr addr)
2268 {
2269     return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
2270 }
2271
2272 uint32_t ldl_be_phys(hwaddr addr)
2273 {
2274     return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
2275 }
2276
2277 /* warning: addr must be aligned */
2278 static inline uint64_t ldq_phys_internal(hwaddr addr,
2279                                          enum device_endian endian)
2280 {
2281     uint8_t *ptr;
2282     uint64_t val;
2283     MemoryRegion *mr;
2284     hwaddr l = 8;
2285     hwaddr addr1;
2286
2287     mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
2288                                  false);
2289     if (l < 8 || !memory_access_is_direct(mr, false)) {
2290         /* I/O case */
2291         io_mem_read(mr, addr1, &val, 8);
2292 #if defined(TARGET_WORDS_BIGENDIAN)
2293         if (endian == DEVICE_LITTLE_ENDIAN) {
2294             val = bswap64(val);
2295         }
2296 #else
2297         if (endian == DEVICE_BIG_ENDIAN) {
2298             val = bswap64(val);
2299         }
2300 #endif
2301     } else {
2302         /* RAM case */
2303         ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr)
2304                                 & TARGET_PAGE_MASK)
2305                                + addr1);
2306         switch (endian) {
2307         case DEVICE_LITTLE_ENDIAN:
2308             val = ldq_le_p(ptr);
2309             break;
2310         case DEVICE_BIG_ENDIAN:
2311             val = ldq_be_p(ptr);
2312             break;
2313         default:
2314             val = ldq_p(ptr);
2315             break;
2316         }
2317     }
2318     return val;
2319 }
2320
2321 uint64_t ldq_phys(hwaddr addr)
2322 {
2323     return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
2324 }
2325
2326 uint64_t ldq_le_phys(hwaddr addr)
2327 {
2328     return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
2329 }
2330
2331 uint64_t ldq_be_phys(hwaddr addr)
2332 {
2333     return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
2334 }
2335
2336 /* XXX: optimize */
2337 uint32_t ldub_phys(hwaddr addr)
2338 {
2339     uint8_t val;
2340     cpu_physical_memory_read(addr, &val, 1);
2341     return val;
2342 }
2343
2344 /* warning: addr must be aligned */
2345 static inline uint32_t lduw_phys_internal(hwaddr addr,
2346                                           enum device_endian endian)
2347 {
2348     uint8_t *ptr;
2349     uint64_t val;
2350     MemoryRegion *mr;
2351     hwaddr l = 2;
2352     hwaddr addr1;
2353
2354     mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
2355                                  false);
2356     if (l < 2 || !memory_access_is_direct(mr, false)) {
2357         /* I/O case */
2358         io_mem_read(mr, addr1, &val, 2);
2359 #if defined(TARGET_WORDS_BIGENDIAN)
2360         if (endian == DEVICE_LITTLE_ENDIAN) {
2361             val = bswap16(val);
2362         }
2363 #else
2364         if (endian == DEVICE_BIG_ENDIAN) {
2365             val = bswap16(val);
2366         }
2367 #endif
2368     } else {
2369         /* RAM case */
2370         ptr = qemu_get_ram_ptr((memory_region_get_ram_addr(mr)
2371                                 & TARGET_PAGE_MASK)
2372                                + addr1);
2373         switch (endian) {
2374         case DEVICE_LITTLE_ENDIAN:
2375             val = lduw_le_p(ptr);
2376             break;
2377         case DEVICE_BIG_ENDIAN:
2378             val = lduw_be_p(ptr);
2379             break;
2380         default:
2381             val = lduw_p(ptr);
2382             break;
2383         }
2384     }
2385     return val;
2386 }
2387
2388 uint32_t lduw_phys(hwaddr addr)
2389 {
2390     return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
2391 }
2392
2393 uint32_t lduw_le_phys(hwaddr addr)
2394 {
2395     return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
2396 }
2397
2398 uint32_t lduw_be_phys(hwaddr addr)
2399 {
2400     return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
2401 }
2402
2403 /* warning: addr must be aligned. The ram page is not masked as dirty
2404    and the code inside is not invalidated. It is useful if the dirty
2405    bits are used to track modified PTEs */
2406 void stl_phys_notdirty(hwaddr addr, uint32_t val)
2407 {
2408     uint8_t *ptr;
2409     MemoryRegion *mr;
2410     hwaddr l = 4;
2411     hwaddr addr1;
2412
2413     mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
2414                                  true);
2415     if (l < 4 || !memory_access_is_direct(mr, true)) {
2416         io_mem_write(mr, addr1, val, 4);
2417     } else {
2418         addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK;
2419         ptr = qemu_get_ram_ptr(addr1);
2420         stl_p(ptr, val);
2421
2422         if (unlikely(in_migration)) {
2423             if (!cpu_physical_memory_is_dirty(addr1)) {
2424                 /* invalidate code */
2425                 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
2426                 /* set dirty bit */
2427                 cpu_physical_memory_set_dirty_flags(
2428                     addr1, (0xff & ~CODE_DIRTY_FLAG));
2429             }
2430         }
2431     }
2432 }
2433
2434 /* warning: addr must be aligned */
2435 static inline void stl_phys_internal(hwaddr addr, uint32_t val,
2436                                      enum device_endian endian)
2437 {
2438     uint8_t *ptr;
2439     MemoryRegion *mr;
2440     hwaddr l = 4;
2441     hwaddr addr1;
2442
2443     mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
2444                                  true);
2445     if (l < 4 || !memory_access_is_direct(mr, true)) {
2446 #if defined(TARGET_WORDS_BIGENDIAN)
2447         if (endian == DEVICE_LITTLE_ENDIAN) {
2448             val = bswap32(val);
2449         }
2450 #else
2451         if (endian == DEVICE_BIG_ENDIAN) {
2452             val = bswap32(val);
2453         }
2454 #endif
2455         io_mem_write(mr, addr1, val, 4);
2456     } else {
2457         /* RAM case */
2458         addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK;
2459         ptr = qemu_get_ram_ptr(addr1);
2460         switch (endian) {
2461         case DEVICE_LITTLE_ENDIAN:
2462             stl_le_p(ptr, val);
2463             break;
2464         case DEVICE_BIG_ENDIAN:
2465             stl_be_p(ptr, val);
2466             break;
2467         default:
2468             stl_p(ptr, val);
2469             break;
2470         }
2471         invalidate_and_set_dirty(addr1, 4);
2472     }
2473 }
2474
2475 void stl_phys(hwaddr addr, uint32_t val)
2476 {
2477     stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
2478 }
2479
2480 void stl_le_phys(hwaddr addr, uint32_t val)
2481 {
2482     stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
2483 }
2484
2485 void stl_be_phys(hwaddr addr, uint32_t val)
2486 {
2487     stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
2488 }
2489
2490 /* XXX: optimize */
2491 void stb_phys(hwaddr addr, uint32_t val)
2492 {
2493     uint8_t v = val;
2494     cpu_physical_memory_write(addr, &v, 1);
2495 }
2496
2497 /* warning: addr must be aligned */
2498 static inline void stw_phys_internal(hwaddr addr, uint32_t val,
2499                                      enum device_endian endian)
2500 {
2501     uint8_t *ptr;
2502     MemoryRegion *mr;
2503     hwaddr l = 2;
2504     hwaddr addr1;
2505
2506     mr = address_space_translate(&address_space_memory, addr, &addr1, &l,
2507                                  true);
2508     if (l < 2 || !memory_access_is_direct(mr, true)) {
2509 #if defined(TARGET_WORDS_BIGENDIAN)
2510         if (endian == DEVICE_LITTLE_ENDIAN) {
2511             val = bswap16(val);
2512         }
2513 #else
2514         if (endian == DEVICE_BIG_ENDIAN) {
2515             val = bswap16(val);
2516         }
2517 #endif
2518         io_mem_write(mr, addr1, val, 2);
2519     } else {
2520         /* RAM case */
2521         addr1 += memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK;
2522         ptr = qemu_get_ram_ptr(addr1);
2523         switch (endian) {
2524         case DEVICE_LITTLE_ENDIAN:
2525             stw_le_p(ptr, val);
2526             break;
2527         case DEVICE_BIG_ENDIAN:
2528             stw_be_p(ptr, val);
2529             break;
2530         default:
2531             stw_p(ptr, val);
2532             break;
2533         }
2534         invalidate_and_set_dirty(addr1, 2);
2535     }
2536 }
2537
2538 void stw_phys(hwaddr addr, uint32_t val)
2539 {
2540     stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
2541 }
2542
2543 void stw_le_phys(hwaddr addr, uint32_t val)
2544 {
2545     stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
2546 }
2547
2548 void stw_be_phys(hwaddr addr, uint32_t val)
2549 {
2550     stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
2551 }
2552
2553 /* XXX: optimize */
2554 void stq_phys(hwaddr addr, uint64_t val)
2555 {
2556     val = tswap64(val);
2557     cpu_physical_memory_write(addr, &val, 8);
2558 }
2559
2560 void stq_le_phys(hwaddr addr, uint64_t val)
2561 {
2562     val = cpu_to_le64(val);
2563     cpu_physical_memory_write(addr, &val, 8);
2564 }
2565
2566 void stq_be_phys(hwaddr addr, uint64_t val)
2567 {
2568     val = cpu_to_be64(val);
2569     cpu_physical_memory_write(addr, &val, 8);
2570 }
2571
2572 /* virtual memory access for debug (includes writing to ROM) */
2573 int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
2574                         uint8_t *buf, int len, int is_write)
2575 {
2576     int l;
2577     hwaddr phys_addr;
2578     target_ulong page;
2579
2580     while (len > 0) {
2581         page = addr & TARGET_PAGE_MASK;
2582         phys_addr = cpu_get_phys_page_debug(env, page);
2583         /* if no physical page mapped, return an error */
2584         if (phys_addr == -1)
2585             return -1;
2586         l = (page + TARGET_PAGE_SIZE) - addr;
2587         if (l > len)
2588             l = len;
2589         phys_addr += (addr & ~TARGET_PAGE_MASK);
2590         if (is_write)
2591             cpu_physical_memory_write_rom(phys_addr, buf, l);
2592         else
2593             cpu_physical_memory_rw(phys_addr, buf, l, is_write);
2594         len -= l;
2595         buf += l;
2596         addr += l;
2597     }
2598     return 0;
2599 }
2600 #endif
2601
2602 #if !defined(CONFIG_USER_ONLY)
2603
2604 /*
2605  * A helper function for the _utterly broken_ virtio device model to find out if
2606  * it's running on a big endian machine. Don't do this at home kids!
2607  */
2608 bool virtio_is_big_endian(void);
2609 bool virtio_is_big_endian(void)
2610 {
2611 #if defined(TARGET_WORDS_BIGENDIAN)
2612     return true;
2613 #else
2614     return false;
2615 #endif
2616 }
2617
2618 #endif
2619
2620 #ifndef CONFIG_USER_ONLY
2621 bool cpu_physical_memory_is_io(hwaddr phys_addr)
2622 {
2623     MemoryRegion*mr;
2624     hwaddr l = 1;
2625
2626     mr = address_space_translate(&address_space_memory,
2627                                  phys_addr, &phys_addr, &l, false);
2628
2629     return !(memory_region_is_ram(mr) ||
2630              memory_region_is_romd(mr));
2631 }
2632
2633 void qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
2634 {
2635     RAMBlock *block;
2636
2637     QTAILQ_FOREACH(block, &ram_list.blocks, next) {
2638         func(block->host, block->offset, block->length, opaque);
2639     }
2640 }
2641 #endif