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gdbstub/sh4: fix build with USE_SOFTFLOAT_STRUCT_TYPES
[qemu.git] / gdbstub.c
1 /*
2 * gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "config.h"
20 #include "qemu-common.h"
21 #ifdef CONFIG_USER_ONLY
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <stdarg.h>
25 #include <string.h>
26 #include <errno.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "qemu.h"
31 #else
32 #include "monitor.h"
33 #include "qemu-char.h"
34 #include "sysemu.h"
35 #include "gdbstub.h"
36 #endif
37
38 #define MAX_PACKET_LENGTH 4096
39
40 #include "cpu.h"
41 #include "qemu_socket.h"
42 #include "kvm.h"
43
44 #ifndef TARGET_CPU_MEMORY_RW_DEBUG
45 static inline int target_memory_rw_debug(CPUArchState *env, target_ulong addr,
46 uint8_t *buf, int len, int is_write)
47 {
48 return cpu_memory_rw_debug(env, addr, buf, len, is_write);
49 }
50 #else
51 /* target_memory_rw_debug() defined in cpu.h */
52 #endif
53
54 enum {
55 GDB_SIGNAL_0 = 0,
56 GDB_SIGNAL_INT = 2,
57 GDB_SIGNAL_QUIT = 3,
58 GDB_SIGNAL_TRAP = 5,
59 GDB_SIGNAL_ABRT = 6,
60 GDB_SIGNAL_ALRM = 14,
61 GDB_SIGNAL_IO = 23,
62 GDB_SIGNAL_XCPU = 24,
63 GDB_SIGNAL_UNKNOWN = 143
64 };
65
66 #ifdef CONFIG_USER_ONLY
67
68 /* Map target signal numbers to GDB protocol signal numbers and vice
69 * versa. For user emulation's currently supported systems, we can
70 * assume most signals are defined.
71 */
72
73 static int gdb_signal_table[] = {
74 0,
75 TARGET_SIGHUP,
76 TARGET_SIGINT,
77 TARGET_SIGQUIT,
78 TARGET_SIGILL,
79 TARGET_SIGTRAP,
80 TARGET_SIGABRT,
81 -1, /* SIGEMT */
82 TARGET_SIGFPE,
83 TARGET_SIGKILL,
84 TARGET_SIGBUS,
85 TARGET_SIGSEGV,
86 TARGET_SIGSYS,
87 TARGET_SIGPIPE,
88 TARGET_SIGALRM,
89 TARGET_SIGTERM,
90 TARGET_SIGURG,
91 TARGET_SIGSTOP,
92 TARGET_SIGTSTP,
93 TARGET_SIGCONT,
94 TARGET_SIGCHLD,
95 TARGET_SIGTTIN,
96 TARGET_SIGTTOU,
97 TARGET_SIGIO,
98 TARGET_SIGXCPU,
99 TARGET_SIGXFSZ,
100 TARGET_SIGVTALRM,
101 TARGET_SIGPROF,
102 TARGET_SIGWINCH,
103 -1, /* SIGLOST */
104 TARGET_SIGUSR1,
105 TARGET_SIGUSR2,
106 #ifdef TARGET_SIGPWR
107 TARGET_SIGPWR,
108 #else
109 -1,
110 #endif
111 -1, /* SIGPOLL */
112 -1,
113 -1,
114 -1,
115 -1,
116 -1,
117 -1,
118 -1,
119 -1,
120 -1,
121 -1,
122 -1,
123 #ifdef __SIGRTMIN
124 __SIGRTMIN + 1,
125 __SIGRTMIN + 2,
126 __SIGRTMIN + 3,
127 __SIGRTMIN + 4,
128 __SIGRTMIN + 5,
129 __SIGRTMIN + 6,
130 __SIGRTMIN + 7,
131 __SIGRTMIN + 8,
132 __SIGRTMIN + 9,
133 __SIGRTMIN + 10,
134 __SIGRTMIN + 11,
135 __SIGRTMIN + 12,
136 __SIGRTMIN + 13,
137 __SIGRTMIN + 14,
138 __SIGRTMIN + 15,
139 __SIGRTMIN + 16,
140 __SIGRTMIN + 17,
141 __SIGRTMIN + 18,
142 __SIGRTMIN + 19,
143 __SIGRTMIN + 20,
144 __SIGRTMIN + 21,
145 __SIGRTMIN + 22,
146 __SIGRTMIN + 23,
147 __SIGRTMIN + 24,
148 __SIGRTMIN + 25,
149 __SIGRTMIN + 26,
150 __SIGRTMIN + 27,
151 __SIGRTMIN + 28,
152 __SIGRTMIN + 29,
153 __SIGRTMIN + 30,
154 __SIGRTMIN + 31,
155 -1, /* SIGCANCEL */
156 __SIGRTMIN,
157 __SIGRTMIN + 32,
158 __SIGRTMIN + 33,
159 __SIGRTMIN + 34,
160 __SIGRTMIN + 35,
161 __SIGRTMIN + 36,
162 __SIGRTMIN + 37,
163 __SIGRTMIN + 38,
164 __SIGRTMIN + 39,
165 __SIGRTMIN + 40,
166 __SIGRTMIN + 41,
167 __SIGRTMIN + 42,
168 __SIGRTMIN + 43,
169 __SIGRTMIN + 44,
170 __SIGRTMIN + 45,
171 __SIGRTMIN + 46,
172 __SIGRTMIN + 47,
173 __SIGRTMIN + 48,
174 __SIGRTMIN + 49,
175 __SIGRTMIN + 50,
176 __SIGRTMIN + 51,
177 __SIGRTMIN + 52,
178 __SIGRTMIN + 53,
179 __SIGRTMIN + 54,
180 __SIGRTMIN + 55,
181 __SIGRTMIN + 56,
182 __SIGRTMIN + 57,
183 __SIGRTMIN + 58,
184 __SIGRTMIN + 59,
185 __SIGRTMIN + 60,
186 __SIGRTMIN + 61,
187 __SIGRTMIN + 62,
188 __SIGRTMIN + 63,
189 __SIGRTMIN + 64,
190 __SIGRTMIN + 65,
191 __SIGRTMIN + 66,
192 __SIGRTMIN + 67,
193 __SIGRTMIN + 68,
194 __SIGRTMIN + 69,
195 __SIGRTMIN + 70,
196 __SIGRTMIN + 71,
197 __SIGRTMIN + 72,
198 __SIGRTMIN + 73,
199 __SIGRTMIN + 74,
200 __SIGRTMIN + 75,
201 __SIGRTMIN + 76,
202 __SIGRTMIN + 77,
203 __SIGRTMIN + 78,
204 __SIGRTMIN + 79,
205 __SIGRTMIN + 80,
206 __SIGRTMIN + 81,
207 __SIGRTMIN + 82,
208 __SIGRTMIN + 83,
209 __SIGRTMIN + 84,
210 __SIGRTMIN + 85,
211 __SIGRTMIN + 86,
212 __SIGRTMIN + 87,
213 __SIGRTMIN + 88,
214 __SIGRTMIN + 89,
215 __SIGRTMIN + 90,
216 __SIGRTMIN + 91,
217 __SIGRTMIN + 92,
218 __SIGRTMIN + 93,
219 __SIGRTMIN + 94,
220 __SIGRTMIN + 95,
221 -1, /* SIGINFO */
222 -1, /* UNKNOWN */
223 -1, /* DEFAULT */
224 -1,
225 -1,
226 -1,
227 -1,
228 -1,
229 -1
230 #endif
231 };
232 #else
233 /* In system mode we only need SIGINT and SIGTRAP; other signals
234 are not yet supported. */
235
236 enum {
237 TARGET_SIGINT = 2,
238 TARGET_SIGTRAP = 5
239 };
240
241 static int gdb_signal_table[] = {
242 -1,
243 -1,
244 TARGET_SIGINT,
245 -1,
246 -1,
247 TARGET_SIGTRAP
248 };
249 #endif
250
251 #ifdef CONFIG_USER_ONLY
252 static int target_signal_to_gdb (int sig)
253 {
254 int i;
255 for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
256 if (gdb_signal_table[i] == sig)
257 return i;
258 return GDB_SIGNAL_UNKNOWN;
259 }
260 #endif
261
262 static int gdb_signal_to_target (int sig)
263 {
264 if (sig < ARRAY_SIZE (gdb_signal_table))
265 return gdb_signal_table[sig];
266 else
267 return -1;
268 }
269
270 //#define DEBUG_GDB
271
272 typedef struct GDBRegisterState {
273 int base_reg;
274 int num_regs;
275 gdb_reg_cb get_reg;
276 gdb_reg_cb set_reg;
277 const char *xml;
278 struct GDBRegisterState *next;
279 } GDBRegisterState;
280
281 enum RSState {
282 RS_INACTIVE,
283 RS_IDLE,
284 RS_GETLINE,
285 RS_CHKSUM1,
286 RS_CHKSUM2,
287 };
288 typedef struct GDBState {
289 CPUArchState *c_cpu; /* current CPU for step/continue ops */
290 CPUArchState *g_cpu; /* current CPU for other ops */
291 CPUArchState *query_cpu; /* for q{f|s}ThreadInfo */
292 enum RSState state; /* parsing state */
293 char line_buf[MAX_PACKET_LENGTH];
294 int line_buf_index;
295 int line_csum;
296 uint8_t last_packet[MAX_PACKET_LENGTH + 4];
297 int last_packet_len;
298 int signal;
299 #ifdef CONFIG_USER_ONLY
300 int fd;
301 int running_state;
302 #else
303 CharDriverState *chr;
304 CharDriverState *mon_chr;
305 #endif
306 char syscall_buf[256];
307 gdb_syscall_complete_cb current_syscall_cb;
308 } GDBState;
309
310 /* By default use no IRQs and no timers while single stepping so as to
311 * make single stepping like an ICE HW step.
312 */
313 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
314
315 static GDBState *gdbserver_state;
316
317 /* This is an ugly hack to cope with both new and old gdb.
318 If gdb sends qXfer:features:read then assume we're talking to a newish
319 gdb that understands target descriptions. */
320 static int gdb_has_xml;
321
322 #ifdef CONFIG_USER_ONLY
323 /* XXX: This is not thread safe. Do we care? */
324 static int gdbserver_fd = -1;
325
326 static int get_char(GDBState *s)
327 {
328 uint8_t ch;
329 int ret;
330
331 for(;;) {
332 ret = qemu_recv(s->fd, &ch, 1, 0);
333 if (ret < 0) {
334 if (errno == ECONNRESET)
335 s->fd = -1;
336 if (errno != EINTR && errno != EAGAIN)
337 return -1;
338 } else if (ret == 0) {
339 close(s->fd);
340 s->fd = -1;
341 return -1;
342 } else {
343 break;
344 }
345 }
346 return ch;
347 }
348 #endif
349
350 static enum {
351 GDB_SYS_UNKNOWN,
352 GDB_SYS_ENABLED,
353 GDB_SYS_DISABLED,
354 } gdb_syscall_mode;
355
356 /* If gdb is connected when the first semihosting syscall occurs then use
357 remote gdb syscalls. Otherwise use native file IO. */
358 int use_gdb_syscalls(void)
359 {
360 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
361 gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
362 : GDB_SYS_DISABLED);
363 }
364 return gdb_syscall_mode == GDB_SYS_ENABLED;
365 }
366
367 /* Resume execution. */
368 static inline void gdb_continue(GDBState *s)
369 {
370 #ifdef CONFIG_USER_ONLY
371 s->running_state = 1;
372 #else
373 vm_start();
374 #endif
375 }
376
377 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
378 {
379 #ifdef CONFIG_USER_ONLY
380 int ret;
381
382 while (len > 0) {
383 ret = send(s->fd, buf, len, 0);
384 if (ret < 0) {
385 if (errno != EINTR && errno != EAGAIN)
386 return;
387 } else {
388 buf += ret;
389 len -= ret;
390 }
391 }
392 #else
393 qemu_chr_fe_write(s->chr, buf, len);
394 #endif
395 }
396
397 static inline int fromhex(int v)
398 {
399 if (v >= '0' && v <= '9')
400 return v - '0';
401 else if (v >= 'A' && v <= 'F')
402 return v - 'A' + 10;
403 else if (v >= 'a' && v <= 'f')
404 return v - 'a' + 10;
405 else
406 return 0;
407 }
408
409 static inline int tohex(int v)
410 {
411 if (v < 10)
412 return v + '0';
413 else
414 return v - 10 + 'a';
415 }
416
417 static void memtohex(char *buf, const uint8_t *mem, int len)
418 {
419 int i, c;
420 char *q;
421 q = buf;
422 for(i = 0; i < len; i++) {
423 c = mem[i];
424 *q++ = tohex(c >> 4);
425 *q++ = tohex(c & 0xf);
426 }
427 *q = '\0';
428 }
429
430 static void hextomem(uint8_t *mem, const char *buf, int len)
431 {
432 int i;
433
434 for(i = 0; i < len; i++) {
435 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
436 buf += 2;
437 }
438 }
439
440 /* return -1 if error, 0 if OK */
441 static int put_packet_binary(GDBState *s, const char *buf, int len)
442 {
443 int csum, i;
444 uint8_t *p;
445
446 for(;;) {
447 p = s->last_packet;
448 *(p++) = '$';
449 memcpy(p, buf, len);
450 p += len;
451 csum = 0;
452 for(i = 0; i < len; i++) {
453 csum += buf[i];
454 }
455 *(p++) = '#';
456 *(p++) = tohex((csum >> 4) & 0xf);
457 *(p++) = tohex((csum) & 0xf);
458
459 s->last_packet_len = p - s->last_packet;
460 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
461
462 #ifdef CONFIG_USER_ONLY
463 i = get_char(s);
464 if (i < 0)
465 return -1;
466 if (i == '+')
467 break;
468 #else
469 break;
470 #endif
471 }
472 return 0;
473 }
474
475 /* return -1 if error, 0 if OK */
476 static int put_packet(GDBState *s, const char *buf)
477 {
478 #ifdef DEBUG_GDB
479 printf("reply='%s'\n", buf);
480 #endif
481
482 return put_packet_binary(s, buf, strlen(buf));
483 }
484
485 /* The GDB remote protocol transfers values in target byte order. This means
486 we can use the raw memory access routines to access the value buffer.
487 Conveniently, these also handle the case where the buffer is mis-aligned.
488 */
489 #define GET_REG8(val) do { \
490 stb_p(mem_buf, val); \
491 return 1; \
492 } while(0)
493 #define GET_REG16(val) do { \
494 stw_p(mem_buf, val); \
495 return 2; \
496 } while(0)
497 #define GET_REG32(val) do { \
498 stl_p(mem_buf, val); \
499 return 4; \
500 } while(0)
501 #define GET_REG64(val) do { \
502 stq_p(mem_buf, val); \
503 return 8; \
504 } while(0)
505
506 #if TARGET_LONG_BITS == 64
507 #define GET_REGL(val) GET_REG64(val)
508 #define ldtul_p(addr) ldq_p(addr)
509 #else
510 #define GET_REGL(val) GET_REG32(val)
511 #define ldtul_p(addr) ldl_p(addr)
512 #endif
513
514 #if defined(TARGET_I386)
515
516 #ifdef TARGET_X86_64
517 static const int gpr_map[16] = {
518 R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
519 8, 9, 10, 11, 12, 13, 14, 15
520 };
521 #else
522 #define gpr_map gpr_map32
523 #endif
524 static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
525
526 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
527
528 #define IDX_IP_REG CPU_NB_REGS
529 #define IDX_FLAGS_REG (IDX_IP_REG + 1)
530 #define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
531 #define IDX_FP_REGS (IDX_SEG_REGS + 6)
532 #define IDX_XMM_REGS (IDX_FP_REGS + 16)
533 #define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
534
535 static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n)
536 {
537 if (n < CPU_NB_REGS) {
538 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
539 GET_REG64(env->regs[gpr_map[n]]);
540 } else if (n < CPU_NB_REGS32) {
541 GET_REG32(env->regs[gpr_map32[n]]);
542 }
543 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
544 #ifdef USE_X86LDOUBLE
545 /* FIXME: byteswap float values - after fixing fpregs layout. */
546 memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
547 #else
548 memset(mem_buf, 0, 10);
549 #endif
550 return 10;
551 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
552 n -= IDX_XMM_REGS;
553 if (n < CPU_NB_REGS32 ||
554 (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
555 stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
556 stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
557 return 16;
558 }
559 } else {
560 switch (n) {
561 case IDX_IP_REG:
562 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
563 GET_REG64(env->eip);
564 } else {
565 GET_REG32(env->eip);
566 }
567 case IDX_FLAGS_REG: GET_REG32(env->eflags);
568
569 case IDX_SEG_REGS: GET_REG32(env->segs[R_CS].selector);
570 case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
571 case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
572 case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
573 case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
574 case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);
575
576 case IDX_FP_REGS + 8: GET_REG32(env->fpuc);
577 case IDX_FP_REGS + 9: GET_REG32((env->fpus & ~0x3800) |
578 (env->fpstt & 0x7) << 11);
579 case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */
580 case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */
581 case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */
582 case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */
583 case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */
584 case IDX_FP_REGS + 15: GET_REG32(0); /* fop */
585
586 case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
587 }
588 }
589 return 0;
590 }
591
592 static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf)
593 {
594 uint16_t selector = ldl_p(mem_buf);
595
596 if (selector != env->segs[sreg].selector) {
597 #if defined(CONFIG_USER_ONLY)
598 cpu_x86_load_seg(env, sreg, selector);
599 #else
600 unsigned int limit, flags;
601 target_ulong base;
602
603 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
604 base = selector << 4;
605 limit = 0xffff;
606 flags = 0;
607 } else {
608 if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
609 return 4;
610 }
611 cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
612 #endif
613 }
614 return 4;
615 }
616
617 static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
618 {
619 uint32_t tmp;
620
621 if (n < CPU_NB_REGS) {
622 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
623 env->regs[gpr_map[n]] = ldtul_p(mem_buf);
624 return sizeof(target_ulong);
625 } else if (n < CPU_NB_REGS32) {
626 n = gpr_map32[n];
627 env->regs[n] &= ~0xffffffffUL;
628 env->regs[n] |= (uint32_t)ldl_p(mem_buf);
629 return 4;
630 }
631 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
632 #ifdef USE_X86LDOUBLE
633 /* FIXME: byteswap float values - after fixing fpregs layout. */
634 memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
635 #endif
636 return 10;
637 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
638 n -= IDX_XMM_REGS;
639 if (n < CPU_NB_REGS32 ||
640 (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
641 env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
642 env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
643 return 16;
644 }
645 } else {
646 switch (n) {
647 case IDX_IP_REG:
648 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
649 env->eip = ldq_p(mem_buf);
650 return 8;
651 } else {
652 env->eip &= ~0xffffffffUL;
653 env->eip |= (uint32_t)ldl_p(mem_buf);
654 return 4;
655 }
656 case IDX_FLAGS_REG:
657 env->eflags = ldl_p(mem_buf);
658 return 4;
659
660 case IDX_SEG_REGS: return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
661 case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
662 case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
663 case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
664 case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
665 case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
666
667 case IDX_FP_REGS + 8:
668 env->fpuc = ldl_p(mem_buf);
669 return 4;
670 case IDX_FP_REGS + 9:
671 tmp = ldl_p(mem_buf);
672 env->fpstt = (tmp >> 11) & 7;
673 env->fpus = tmp & ~0x3800;
674 return 4;
675 case IDX_FP_REGS + 10: /* ftag */ return 4;
676 case IDX_FP_REGS + 11: /* fiseg */ return 4;
677 case IDX_FP_REGS + 12: /* fioff */ return 4;
678 case IDX_FP_REGS + 13: /* foseg */ return 4;
679 case IDX_FP_REGS + 14: /* fooff */ return 4;
680 case IDX_FP_REGS + 15: /* fop */ return 4;
681
682 case IDX_MXCSR_REG:
683 env->mxcsr = ldl_p(mem_buf);
684 return 4;
685 }
686 }
687 /* Unrecognised register. */
688 return 0;
689 }
690
691 #elif defined (TARGET_PPC)
692
693 /* Old gdb always expects FP registers. Newer (xml-aware) gdb only
694 expects whatever the target description contains. Due to a
695 historical mishap the FP registers appear in between core integer
696 regs and PC, MSR, CR, and so forth. We hack round this by giving the
697 FP regs zero size when talking to a newer gdb. */
698 #define NUM_CORE_REGS 71
699 #if defined (TARGET_PPC64)
700 #define GDB_CORE_XML "power64-core.xml"
701 #else
702 #define GDB_CORE_XML "power-core.xml"
703 #endif
704
705 static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n)
706 {
707 if (n < 32) {
708 /* gprs */
709 GET_REGL(env->gpr[n]);
710 } else if (n < 64) {
711 /* fprs */
712 if (gdb_has_xml)
713 return 0;
714 stfq_p(mem_buf, env->fpr[n-32]);
715 return 8;
716 } else {
717 switch (n) {
718 case 64: GET_REGL(env->nip);
719 case 65: GET_REGL(env->msr);
720 case 66:
721 {
722 uint32_t cr = 0;
723 int i;
724 for (i = 0; i < 8; i++)
725 cr |= env->crf[i] << (32 - ((i + 1) * 4));
726 GET_REG32(cr);
727 }
728 case 67: GET_REGL(env->lr);
729 case 68: GET_REGL(env->ctr);
730 case 69: GET_REGL(env->xer);
731 case 70:
732 {
733 if (gdb_has_xml)
734 return 0;
735 GET_REG32(env->fpscr);
736 }
737 }
738 }
739 return 0;
740 }
741
742 static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
743 {
744 if (n < 32) {
745 /* gprs */
746 env->gpr[n] = ldtul_p(mem_buf);
747 return sizeof(target_ulong);
748 } else if (n < 64) {
749 /* fprs */
750 if (gdb_has_xml)
751 return 0;
752 env->fpr[n-32] = ldfq_p(mem_buf);
753 return 8;
754 } else {
755 switch (n) {
756 case 64:
757 env->nip = ldtul_p(mem_buf);
758 return sizeof(target_ulong);
759 case 65:
760 ppc_store_msr(env, ldtul_p(mem_buf));
761 return sizeof(target_ulong);
762 case 66:
763 {
764 uint32_t cr = ldl_p(mem_buf);
765 int i;
766 for (i = 0; i < 8; i++)
767 env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
768 return 4;
769 }
770 case 67:
771 env->lr = ldtul_p(mem_buf);
772 return sizeof(target_ulong);
773 case 68:
774 env->ctr = ldtul_p(mem_buf);
775 return sizeof(target_ulong);
776 case 69:
777 env->xer = ldtul_p(mem_buf);
778 return sizeof(target_ulong);
779 case 70:
780 /* fpscr */
781 if (gdb_has_xml)
782 return 0;
783 return 4;
784 }
785 }
786 return 0;
787 }
788
789 #elif defined (TARGET_SPARC)
790
791 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
792 #define NUM_CORE_REGS 86
793 #else
794 #define NUM_CORE_REGS 72
795 #endif
796
797 #ifdef TARGET_ABI32
798 #define GET_REGA(val) GET_REG32(val)
799 #else
800 #define GET_REGA(val) GET_REGL(val)
801 #endif
802
803 static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
804 {
805 if (n < 8) {
806 /* g0..g7 */
807 GET_REGA(env->gregs[n]);
808 }
809 if (n < 32) {
810 /* register window */
811 GET_REGA(env->regwptr[n - 8]);
812 }
813 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
814 if (n < 64) {
815 /* fprs */
816 if (n & 1) {
817 GET_REG32(env->fpr[(n - 32) / 2].l.lower);
818 } else {
819 GET_REG32(env->fpr[(n - 32) / 2].l.upper);
820 }
821 }
822 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
823 switch (n) {
824 case 64: GET_REGA(env->y);
825 case 65: GET_REGA(cpu_get_psr(env));
826 case 66: GET_REGA(env->wim);
827 case 67: GET_REGA(env->tbr);
828 case 68: GET_REGA(env->pc);
829 case 69: GET_REGA(env->npc);
830 case 70: GET_REGA(env->fsr);
831 case 71: GET_REGA(0); /* csr */
832 default: GET_REGA(0);
833 }
834 #else
835 if (n < 64) {
836 /* f0-f31 */
837 if (n & 1) {
838 GET_REG32(env->fpr[(n - 32) / 2].l.lower);
839 } else {
840 GET_REG32(env->fpr[(n - 32) / 2].l.upper);
841 }
842 }
843 if (n < 80) {
844 /* f32-f62 (double width, even numbers only) */
845 GET_REG64(env->fpr[(n - 32) / 2].ll);
846 }
847 switch (n) {
848 case 80: GET_REGL(env->pc);
849 case 81: GET_REGL(env->npc);
850 case 82: GET_REGL((cpu_get_ccr(env) << 32) |
851 ((env->asi & 0xff) << 24) |
852 ((env->pstate & 0xfff) << 8) |
853 cpu_get_cwp64(env));
854 case 83: GET_REGL(env->fsr);
855 case 84: GET_REGL(env->fprs);
856 case 85: GET_REGL(env->y);
857 }
858 #endif
859 return 0;
860 }
861
862 static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
863 {
864 #if defined(TARGET_ABI32)
865 abi_ulong tmp;
866
867 tmp = ldl_p(mem_buf);
868 #else
869 target_ulong tmp;
870
871 tmp = ldtul_p(mem_buf);
872 #endif
873
874 if (n < 8) {
875 /* g0..g7 */
876 env->gregs[n] = tmp;
877 } else if (n < 32) {
878 /* register window */
879 env->regwptr[n - 8] = tmp;
880 }
881 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
882 else if (n < 64) {
883 /* fprs */
884 /* f0-f31 */
885 if (n & 1) {
886 env->fpr[(n - 32) / 2].l.lower = tmp;
887 } else {
888 env->fpr[(n - 32) / 2].l.upper = tmp;
889 }
890 } else {
891 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
892 switch (n) {
893 case 64: env->y = tmp; break;
894 case 65: cpu_put_psr(env, tmp); break;
895 case 66: env->wim = tmp; break;
896 case 67: env->tbr = tmp; break;
897 case 68: env->pc = tmp; break;
898 case 69: env->npc = tmp; break;
899 case 70: env->fsr = tmp; break;
900 default: return 0;
901 }
902 }
903 return 4;
904 #else
905 else if (n < 64) {
906 /* f0-f31 */
907 tmp = ldl_p(mem_buf);
908 if (n & 1) {
909 env->fpr[(n - 32) / 2].l.lower = tmp;
910 } else {
911 env->fpr[(n - 32) / 2].l.upper = tmp;
912 }
913 return 4;
914 } else if (n < 80) {
915 /* f32-f62 (double width, even numbers only) */
916 env->fpr[(n - 32) / 2].ll = tmp;
917 } else {
918 switch (n) {
919 case 80: env->pc = tmp; break;
920 case 81: env->npc = tmp; break;
921 case 82:
922 cpu_put_ccr(env, tmp >> 32);
923 env->asi = (tmp >> 24) & 0xff;
924 env->pstate = (tmp >> 8) & 0xfff;
925 cpu_put_cwp64(env, tmp & 0xff);
926 break;
927 case 83: env->fsr = tmp; break;
928 case 84: env->fprs = tmp; break;
929 case 85: env->y = tmp; break;
930 default: return 0;
931 }
932 }
933 return 8;
934 #endif
935 }
936 #elif defined (TARGET_ARM)
937
938 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
939 whatever the target description contains. Due to a historical mishap
940 the FPA registers appear in between core integer regs and the CPSR.
941 We hack round this by giving the FPA regs zero size when talking to a
942 newer gdb. */
943 #define NUM_CORE_REGS 26
944 #define GDB_CORE_XML "arm-core.xml"
945
946 static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
947 {
948 if (n < 16) {
949 /* Core integer register. */
950 GET_REG32(env->regs[n]);
951 }
952 if (n < 24) {
953 /* FPA registers. */
954 if (gdb_has_xml)
955 return 0;
956 memset(mem_buf, 0, 12);
957 return 12;
958 }
959 switch (n) {
960 case 24:
961 /* FPA status register. */
962 if (gdb_has_xml)
963 return 0;
964 GET_REG32(0);
965 case 25:
966 /* CPSR */
967 GET_REG32(cpsr_read(env));
968 }
969 /* Unknown register. */
970 return 0;
971 }
972
973 static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
974 {
975 uint32_t tmp;
976
977 tmp = ldl_p(mem_buf);
978
979 /* Mask out low bit of PC to workaround gdb bugs. This will probably
980 cause problems if we ever implement the Jazelle DBX extensions. */
981 if (n == 15)
982 tmp &= ~1;
983
984 if (n < 16) {
985 /* Core integer register. */
986 env->regs[n] = tmp;
987 return 4;
988 }
989 if (n < 24) { /* 16-23 */
990 /* FPA registers (ignored). */
991 if (gdb_has_xml)
992 return 0;
993 return 12;
994 }
995 switch (n) {
996 case 24:
997 /* FPA status register (ignored). */
998 if (gdb_has_xml)
999 return 0;
1000 return 4;
1001 case 25:
1002 /* CPSR */
1003 cpsr_write (env, tmp, 0xffffffff);
1004 return 4;
1005 }
1006 /* Unknown register. */
1007 return 0;
1008 }
1009
1010 #elif defined (TARGET_M68K)
1011
1012 #define NUM_CORE_REGS 18
1013
1014 #define GDB_CORE_XML "cf-core.xml"
1015
1016 static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
1017 {
1018 if (n < 8) {
1019 /* D0-D7 */
1020 GET_REG32(env->dregs[n]);
1021 } else if (n < 16) {
1022 /* A0-A7 */
1023 GET_REG32(env->aregs[n - 8]);
1024 } else {
1025 switch (n) {
1026 case 16: GET_REG32(env->sr);
1027 case 17: GET_REG32(env->pc);
1028 }
1029 }
1030 /* FP registers not included here because they vary between
1031 ColdFire and m68k. Use XML bits for these. */
1032 return 0;
1033 }
1034
1035 static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
1036 {
1037 uint32_t tmp;
1038
1039 tmp = ldl_p(mem_buf);
1040
1041 if (n < 8) {
1042 /* D0-D7 */
1043 env->dregs[n] = tmp;
1044 } else if (n < 16) {
1045 /* A0-A7 */
1046 env->aregs[n - 8] = tmp;
1047 } else {
1048 switch (n) {
1049 case 16: env->sr = tmp; break;
1050 case 17: env->pc = tmp; break;
1051 default: return 0;
1052 }
1053 }
1054 return 4;
1055 }
1056 #elif defined (TARGET_MIPS)
1057
1058 #define NUM_CORE_REGS 73
1059
1060 static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
1061 {
1062 if (n < 32) {
1063 GET_REGL(env->active_tc.gpr[n]);
1064 }
1065 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
1066 if (n >= 38 && n < 70) {
1067 if (env->CP0_Status & (1 << CP0St_FR))
1068 GET_REGL(env->active_fpu.fpr[n - 38].d);
1069 else
1070 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
1071 }
1072 switch (n) {
1073 case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
1074 case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
1075 }
1076 }
1077 switch (n) {
1078 case 32: GET_REGL((int32_t)env->CP0_Status);
1079 case 33: GET_REGL(env->active_tc.LO[0]);
1080 case 34: GET_REGL(env->active_tc.HI[0]);
1081 case 35: GET_REGL(env->CP0_BadVAddr);
1082 case 36: GET_REGL((int32_t)env->CP0_Cause);
1083 case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
1084 case 72: GET_REGL(0); /* fp */
1085 case 89: GET_REGL((int32_t)env->CP0_PRid);
1086 }
1087 if (n >= 73 && n <= 88) {
1088 /* 16 embedded regs. */
1089 GET_REGL(0);
1090 }
1091
1092 return 0;
1093 }
1094
1095 /* convert MIPS rounding mode in FCR31 to IEEE library */
1096 static unsigned int ieee_rm[] =
1097 {
1098 float_round_nearest_even,
1099 float_round_to_zero,
1100 float_round_up,
1101 float_round_down
1102 };
1103 #define RESTORE_ROUNDING_MODE \
1104 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1105
1106 static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
1107 {
1108 target_ulong tmp;
1109
1110 tmp = ldtul_p(mem_buf);
1111
1112 if (n < 32) {
1113 env->active_tc.gpr[n] = tmp;
1114 return sizeof(target_ulong);
1115 }
1116 if (env->CP0_Config1 & (1 << CP0C1_FP)
1117 && n >= 38 && n < 73) {
1118 if (n < 70) {
1119 if (env->CP0_Status & (1 << CP0St_FR))
1120 env->active_fpu.fpr[n - 38].d = tmp;
1121 else
1122 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1123 }
1124 switch (n) {
1125 case 70:
1126 env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1127 /* set rounding mode */
1128 RESTORE_ROUNDING_MODE;
1129 break;
1130 case 71: env->active_fpu.fcr0 = tmp; break;
1131 }
1132 return sizeof(target_ulong);
1133 }
1134 switch (n) {
1135 case 32: env->CP0_Status = tmp; break;
1136 case 33: env->active_tc.LO[0] = tmp; break;
1137 case 34: env->active_tc.HI[0] = tmp; break;
1138 case 35: env->CP0_BadVAddr = tmp; break;
1139 case 36: env->CP0_Cause = tmp; break;
1140 case 37:
1141 env->active_tc.PC = tmp & ~(target_ulong)1;
1142 if (tmp & 1) {
1143 env->hflags |= MIPS_HFLAG_M16;
1144 } else {
1145 env->hflags &= ~(MIPS_HFLAG_M16);
1146 }
1147 break;
1148 case 72: /* fp, ignored */ break;
1149 default:
1150 if (n > 89)
1151 return 0;
1152 /* Other registers are readonly. Ignore writes. */
1153 break;
1154 }
1155
1156 return sizeof(target_ulong);
1157 }
1158 #elif defined(TARGET_OPENRISC)
1159
1160 #define NUM_CORE_REGS (32 + 3)
1161
1162 static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
1163 {
1164 if (n < 32) {
1165 GET_REG32(env->gpr[n]);
1166 } else {
1167 switch (n) {
1168 case 32: /* PPC */
1169 GET_REG32(env->ppc);
1170 break;
1171
1172 case 33: /* NPC */
1173 GET_REG32(env->npc);
1174 break;
1175
1176 case 34: /* SR */
1177 GET_REG32(env->sr);
1178 break;
1179
1180 default:
1181 break;
1182 }
1183 }
1184 return 0;
1185 }
1186
1187 static int cpu_gdb_write_register(CPUOpenRISCState *env,
1188 uint8_t *mem_buf, int n)
1189 {
1190 uint32_t tmp;
1191
1192 if (n > NUM_CORE_REGS) {
1193 return 0;
1194 }
1195
1196 tmp = ldl_p(mem_buf);
1197
1198 if (n < 32) {
1199 env->gpr[n] = tmp;
1200 } else {
1201 switch (n) {
1202 case 32: /* PPC */
1203 env->ppc = tmp;
1204 break;
1205
1206 case 33: /* NPC */
1207 env->npc = tmp;
1208 break;
1209
1210 case 34: /* SR */
1211 env->sr = tmp;
1212 break;
1213
1214 default:
1215 break;
1216 }
1217 }
1218 return 4;
1219 }
1220 #elif defined (TARGET_SH4)
1221
1222 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1223 /* FIXME: We should use XML for this. */
1224
1225 #define NUM_CORE_REGS 59
1226
1227 static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
1228 {
1229 switch (n) {
1230 case 0 ... 7:
1231 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1232 GET_REGL(env->gregs[n + 16]);
1233 } else {
1234 GET_REGL(env->gregs[n]);
1235 }
1236 case 8 ... 15:
1237 GET_REGL(env->gregs[n]);
1238 case 16:
1239 GET_REGL(env->pc);
1240 case 17:
1241 GET_REGL(env->pr);
1242 case 18:
1243 GET_REGL(env->gbr);
1244 case 19:
1245 GET_REGL(env->vbr);
1246 case 20:
1247 GET_REGL(env->mach);
1248 case 21:
1249 GET_REGL(env->macl);
1250 case 22:
1251 GET_REGL(env->sr);
1252 case 23:
1253 GET_REGL(env->fpul);
1254 case 24:
1255 GET_REGL(env->fpscr);
1256 case 25 ... 40:
1257 if (env->fpscr & FPSCR_FR) {
1258 stfl_p(mem_buf, env->fregs[n - 9]);
1259 } else {
1260 stfl_p(mem_buf, env->fregs[n - 25]);
1261 }
1262 return 4;
1263 case 41:
1264 GET_REGL(env->ssr);
1265 case 42:
1266 GET_REGL(env->spc);
1267 case 43 ... 50:
1268 GET_REGL(env->gregs[n - 43]);
1269 case 51 ... 58:
1270 GET_REGL(env->gregs[n - (51 - 16)]);
1271 }
1272
1273 return 0;
1274 }
1275
1276 static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
1277 {
1278 switch (n) {
1279 case 0 ... 7:
1280 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1281 env->gregs[n + 16] = ldl_p(mem_buf);
1282 } else {
1283 env->gregs[n] = ldl_p(mem_buf);
1284 }
1285 break;
1286 case 8 ... 15:
1287 env->gregs[n] = ldl_p(mem_buf);
1288 break;
1289 case 16:
1290 env->pc = ldl_p(mem_buf);
1291 break;
1292 case 17:
1293 env->pr = ldl_p(mem_buf);
1294 break;
1295 case 18:
1296 env->gbr = ldl_p(mem_buf);
1297 break;
1298 case 19:
1299 env->vbr = ldl_p(mem_buf);
1300 break;
1301 case 20:
1302 env->mach = ldl_p(mem_buf);
1303 break;
1304 case 21:
1305 env->macl = ldl_p(mem_buf);
1306 break;
1307 case 22:
1308 env->sr = ldl_p(mem_buf);
1309 break;
1310 case 23:
1311 env->fpul = ldl_p(mem_buf);
1312 break;
1313 case 24:
1314 env->fpscr = ldl_p(mem_buf);
1315 break;
1316 case 25 ... 40:
1317 if (env->fpscr & FPSCR_FR) {
1318 env->fregs[n - 9] = ldfl_p(mem_buf);
1319 } else {
1320 env->fregs[n - 25] = ldfl_p(mem_buf);
1321 }
1322 break;
1323 case 41:
1324 env->ssr = ldl_p(mem_buf);
1325 break;
1326 case 42:
1327 env->spc = ldl_p(mem_buf);
1328 break;
1329 case 43 ... 50:
1330 env->gregs[n - 43] = ldl_p(mem_buf);
1331 break;
1332 case 51 ... 58:
1333 env->gregs[n - (51 - 16)] = ldl_p(mem_buf);
1334 break;
1335 default: return 0;
1336 }
1337
1338 return 4;
1339 }
1340 #elif defined (TARGET_MICROBLAZE)
1341
1342 #define NUM_CORE_REGS (32 + 5)
1343
1344 static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
1345 {
1346 if (n < 32) {
1347 GET_REG32(env->regs[n]);
1348 } else {
1349 GET_REG32(env->sregs[n - 32]);
1350 }
1351 return 0;
1352 }
1353
1354 static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
1355 {
1356 uint32_t tmp;
1357
1358 if (n > NUM_CORE_REGS)
1359 return 0;
1360
1361 tmp = ldl_p(mem_buf);
1362
1363 if (n < 32) {
1364 env->regs[n] = tmp;
1365 } else {
1366 env->sregs[n - 32] = tmp;
1367 }
1368 return 4;
1369 }
1370 #elif defined (TARGET_CRIS)
1371
1372 #define NUM_CORE_REGS 49
1373
1374 static int
1375 read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
1376 {
1377 if (n < 15) {
1378 GET_REG32(env->regs[n]);
1379 }
1380
1381 if (n == 15) {
1382 GET_REG32(env->pc);
1383 }
1384
1385 if (n < 32) {
1386 switch (n) {
1387 case 16:
1388 GET_REG8(env->pregs[n - 16]);
1389 break;
1390 case 17:
1391 GET_REG8(env->pregs[n - 16]);
1392 break;
1393 case 20:
1394 case 21:
1395 GET_REG16(env->pregs[n - 16]);
1396 break;
1397 default:
1398 if (n >= 23) {
1399 GET_REG32(env->pregs[n - 16]);
1400 }
1401 break;
1402 }
1403 }
1404 return 0;
1405 }
1406
1407 static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n)
1408 {
1409 uint8_t srs;
1410
1411 if (env->pregs[PR_VR] < 32)
1412 return read_register_crisv10(env, mem_buf, n);
1413
1414 srs = env->pregs[PR_SRS];
1415 if (n < 16) {
1416 GET_REG32(env->regs[n]);
1417 }
1418
1419 if (n >= 21 && n < 32) {
1420 GET_REG32(env->pregs[n - 16]);
1421 }
1422 if (n >= 33 && n < 49) {
1423 GET_REG32(env->sregs[srs][n - 33]);
1424 }
1425 switch (n) {
1426 case 16: GET_REG8(env->pregs[0]);
1427 case 17: GET_REG8(env->pregs[1]);
1428 case 18: GET_REG32(env->pregs[2]);
1429 case 19: GET_REG8(srs);
1430 case 20: GET_REG16(env->pregs[4]);
1431 case 32: GET_REG32(env->pc);
1432 }
1433
1434 return 0;
1435 }
1436
1437 static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
1438 {
1439 uint32_t tmp;
1440
1441 if (n > 49)
1442 return 0;
1443
1444 tmp = ldl_p(mem_buf);
1445
1446 if (n < 16) {
1447 env->regs[n] = tmp;
1448 }
1449
1450 if (n >= 21 && n < 32) {
1451 env->pregs[n - 16] = tmp;
1452 }
1453
1454 /* FIXME: Should support function regs be writable? */
1455 switch (n) {
1456 case 16: return 1;
1457 case 17: return 1;
1458 case 18: env->pregs[PR_PID] = tmp; break;
1459 case 19: return 1;
1460 case 20: return 2;
1461 case 32: env->pc = tmp; break;
1462 }
1463
1464 return 4;
1465 }
1466 #elif defined (TARGET_ALPHA)
1467
1468 #define NUM_CORE_REGS 67
1469
1470 static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
1471 {
1472 uint64_t val;
1473 CPU_DoubleU d;
1474
1475 switch (n) {
1476 case 0 ... 30:
1477 val = env->ir[n];
1478 break;
1479 case 32 ... 62:
1480 d.d = env->fir[n - 32];
1481 val = d.ll;
1482 break;
1483 case 63:
1484 val = cpu_alpha_load_fpcr(env);
1485 break;
1486 case 64:
1487 val = env->pc;
1488 break;
1489 case 66:
1490 val = env->unique;
1491 break;
1492 case 31:
1493 case 65:
1494 /* 31 really is the zero register; 65 is unassigned in the
1495 gdb protocol, but is still required to occupy 8 bytes. */
1496 val = 0;
1497 break;
1498 default:
1499 return 0;
1500 }
1501 GET_REGL(val);
1502 }
1503
1504 static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
1505 {
1506 target_ulong tmp = ldtul_p(mem_buf);
1507 CPU_DoubleU d;
1508
1509 switch (n) {
1510 case 0 ... 30:
1511 env->ir[n] = tmp;
1512 break;
1513 case 32 ... 62:
1514 d.ll = tmp;
1515 env->fir[n - 32] = d.d;
1516 break;
1517 case 63:
1518 cpu_alpha_store_fpcr(env, tmp);
1519 break;
1520 case 64:
1521 env->pc = tmp;
1522 break;
1523 case 66:
1524 env->unique = tmp;
1525 break;
1526 case 31:
1527 case 65:
1528 /* 31 really is the zero register; 65 is unassigned in the
1529 gdb protocol, but is still required to occupy 8 bytes. */
1530 break;
1531 default:
1532 return 0;
1533 }
1534 return 8;
1535 }
1536 #elif defined (TARGET_S390X)
1537
1538 #define NUM_CORE_REGS S390_NUM_TOTAL_REGS
1539
1540 static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
1541 {
1542 switch (n) {
1543 case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
1544 case S390_PSWA_REGNUM: GET_REGL(env->psw.addr); break;
1545 case S390_R0_REGNUM ... S390_R15_REGNUM:
1546 GET_REGL(env->regs[n-S390_R0_REGNUM]); break;
1547 case S390_A0_REGNUM ... S390_A15_REGNUM:
1548 GET_REG32(env->aregs[n-S390_A0_REGNUM]); break;
1549 case S390_FPC_REGNUM: GET_REG32(env->fpc); break;
1550 case S390_F0_REGNUM ... S390_F15_REGNUM:
1551 /* XXX */
1552 break;
1553 case S390_PC_REGNUM: GET_REGL(env->psw.addr); break;
1554 case S390_CC_REGNUM:
1555 env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
1556 env->cc_vr);
1557 GET_REG32(env->cc_op);
1558 break;
1559 }
1560
1561 return 0;
1562 }
1563
1564 static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
1565 {
1566 target_ulong tmpl;
1567 uint32_t tmp32;
1568 int r = 8;
1569 tmpl = ldtul_p(mem_buf);
1570 tmp32 = ldl_p(mem_buf);
1571
1572 switch (n) {
1573 case S390_PSWM_REGNUM: env->psw.mask = tmpl; break;
1574 case S390_PSWA_REGNUM: env->psw.addr = tmpl; break;
1575 case S390_R0_REGNUM ... S390_R15_REGNUM:
1576 env->regs[n-S390_R0_REGNUM] = tmpl; break;
1577 case S390_A0_REGNUM ... S390_A15_REGNUM:
1578 env->aregs[n-S390_A0_REGNUM] = tmp32; r=4; break;
1579 case S390_FPC_REGNUM: env->fpc = tmp32; r=4; break;
1580 case S390_F0_REGNUM ... S390_F15_REGNUM:
1581 /* XXX */
1582 break;
1583 case S390_PC_REGNUM: env->psw.addr = tmpl; break;
1584 case S390_CC_REGNUM: env->cc_op = tmp32; r=4; break;
1585 }
1586
1587 return r;
1588 }
1589 #elif defined (TARGET_LM32)
1590
1591 #include "hw/lm32_pic.h"
1592 #define NUM_CORE_REGS (32 + 7)
1593
1594 static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
1595 {
1596 if (n < 32) {
1597 GET_REG32(env->regs[n]);
1598 } else {
1599 switch (n) {
1600 case 32:
1601 GET_REG32(env->pc);
1602 break;
1603 /* FIXME: put in right exception ID */
1604 case 33:
1605 GET_REG32(0);
1606 break;
1607 case 34:
1608 GET_REG32(env->eba);
1609 break;
1610 case 35:
1611 GET_REG32(env->deba);
1612 break;
1613 case 36:
1614 GET_REG32(env->ie);
1615 break;
1616 case 37:
1617 GET_REG32(lm32_pic_get_im(env->pic_state));
1618 break;
1619 case 38:
1620 GET_REG32(lm32_pic_get_ip(env->pic_state));
1621 break;
1622 }
1623 }
1624 return 0;
1625 }
1626
1627 static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
1628 {
1629 uint32_t tmp;
1630
1631 if (n > NUM_CORE_REGS) {
1632 return 0;
1633 }
1634
1635 tmp = ldl_p(mem_buf);
1636
1637 if (n < 32) {
1638 env->regs[n] = tmp;
1639 } else {
1640 switch (n) {
1641 case 32:
1642 env->pc = tmp;
1643 break;
1644 case 34:
1645 env->eba = tmp;
1646 break;
1647 case 35:
1648 env->deba = tmp;
1649 break;
1650 case 36:
1651 env->ie = tmp;
1652 break;
1653 case 37:
1654 lm32_pic_set_im(env->pic_state, tmp);
1655 break;
1656 case 38:
1657 lm32_pic_set_ip(env->pic_state, tmp);
1658 break;
1659 }
1660 }
1661 return 4;
1662 }
1663 #elif defined(TARGET_XTENSA)
1664
1665 /* Use num_core_regs to see only non-privileged registers in an unmodified gdb.
1666 * Use num_regs to see all registers. gdb modification is required for that:
1667 * reset bit 0 in the 'flags' field of the registers definitions in the
1668 * gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
1669 */
1670 #define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
1671 #define num_g_regs NUM_CORE_REGS
1672
1673 static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
1674 {
1675 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
1676
1677 if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
1678 return 0;
1679 }
1680
1681 switch (reg->type) {
1682 case 9: /*pc*/
1683 GET_REG32(env->pc);
1684 break;
1685
1686 case 1: /*ar*/
1687 xtensa_sync_phys_from_window(env);
1688 GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]);
1689 break;
1690
1691 case 2: /*SR*/
1692 GET_REG32(env->sregs[reg->targno & 0xff]);
1693 break;
1694
1695 case 3: /*UR*/
1696 GET_REG32(env->uregs[reg->targno & 0xff]);
1697 break;
1698
1699 case 8: /*a*/
1700 GET_REG32(env->regs[reg->targno & 0x0f]);
1701 break;
1702
1703 default:
1704 qemu_log("%s from reg %d of unsupported type %d\n",
1705 __func__, n, reg->type);
1706 return 0;
1707 }
1708 }
1709
1710 static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
1711 {
1712 uint32_t tmp;
1713 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
1714
1715 if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
1716 return 0;
1717 }
1718
1719 tmp = ldl_p(mem_buf);
1720
1721 switch (reg->type) {
1722 case 9: /*pc*/
1723 env->pc = tmp;
1724 break;
1725
1726 case 1: /*ar*/
1727 env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
1728 xtensa_sync_window_from_phys(env);
1729 break;
1730
1731 case 2: /*SR*/
1732 env->sregs[reg->targno & 0xff] = tmp;
1733 break;
1734
1735 case 3: /*UR*/
1736 env->uregs[reg->targno & 0xff] = tmp;
1737 break;
1738
1739 case 8: /*a*/
1740 env->regs[reg->targno & 0x0f] = tmp;
1741 break;
1742
1743 default:
1744 qemu_log("%s to reg %d of unsupported type %d\n",
1745 __func__, n, reg->type);
1746 return 0;
1747 }
1748
1749 return 4;
1750 }
1751 #else
1752
1753 #define NUM_CORE_REGS 0
1754
1755 static int cpu_gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int n)
1756 {
1757 return 0;
1758 }
1759
1760 static int cpu_gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int n)
1761 {
1762 return 0;
1763 }
1764
1765 #endif
1766
1767 #if !defined(TARGET_XTENSA)
1768 static int num_g_regs = NUM_CORE_REGS;
1769 #endif
1770
1771 #ifdef GDB_CORE_XML
1772 /* Encode data using the encoding for 'x' packets. */
1773 static int memtox(char *buf, const char *mem, int len)
1774 {
1775 char *p = buf;
1776 char c;
1777
1778 while (len--) {
1779 c = *(mem++);
1780 switch (c) {
1781 case '#': case '$': case '*': case '}':
1782 *(p++) = '}';
1783 *(p++) = c ^ 0x20;
1784 break;
1785 default:
1786 *(p++) = c;
1787 break;
1788 }
1789 }
1790 return p - buf;
1791 }
1792
1793 static const char *get_feature_xml(const char *p, const char **newp)
1794 {
1795 size_t len;
1796 int i;
1797 const char *name;
1798 static char target_xml[1024];
1799
1800 len = 0;
1801 while (p[len] && p[len] != ':')
1802 len++;
1803 *newp = p + len;
1804
1805 name = NULL;
1806 if (strncmp(p, "target.xml", len) == 0) {
1807 /* Generate the XML description for this CPU. */
1808 if (!target_xml[0]) {
1809 GDBRegisterState *r;
1810
1811 snprintf(target_xml, sizeof(target_xml),
1812 "<?xml version=\"1.0\"?>"
1813 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1814 "<target>"
1815 "<xi:include href=\"%s\"/>",
1816 GDB_CORE_XML);
1817
1818 for (r = first_cpu->gdb_regs; r; r = r->next) {
1819 pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
1820 pstrcat(target_xml, sizeof(target_xml), r->xml);
1821 pstrcat(target_xml, sizeof(target_xml), "\"/>");
1822 }
1823 pstrcat(target_xml, sizeof(target_xml), "</target>");
1824 }
1825 return target_xml;
1826 }
1827 for (i = 0; ; i++) {
1828 name = xml_builtin[i][0];
1829 if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1830 break;
1831 }
1832 return name ? xml_builtin[i][1] : NULL;
1833 }
1834 #endif
1835
1836 static int gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int reg)
1837 {
1838 GDBRegisterState *r;
1839
1840 if (reg < NUM_CORE_REGS)
1841 return cpu_gdb_read_register(env, mem_buf, reg);
1842
1843 for (r = env->gdb_regs; r; r = r->next) {
1844 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1845 return r->get_reg(env, mem_buf, reg - r->base_reg);
1846 }
1847 }
1848 return 0;
1849 }
1850
1851 static int gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int reg)
1852 {
1853 GDBRegisterState *r;
1854
1855 if (reg < NUM_CORE_REGS)
1856 return cpu_gdb_write_register(env, mem_buf, reg);
1857
1858 for (r = env->gdb_regs; r; r = r->next) {
1859 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1860 return r->set_reg(env, mem_buf, reg - r->base_reg);
1861 }
1862 }
1863 return 0;
1864 }
1865
1866 #if !defined(TARGET_XTENSA)
1867 /* Register a supplemental set of CPU registers. If g_pos is nonzero it
1868 specifies the first register number and these registers are included in
1869 a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
1870 gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1871 */
1872
1873 void gdb_register_coprocessor(CPUArchState * env,
1874 gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1875 int num_regs, const char *xml, int g_pos)
1876 {
1877 GDBRegisterState *s;
1878 GDBRegisterState **p;
1879 static int last_reg = NUM_CORE_REGS;
1880
1881 p = &env->gdb_regs;
1882 while (*p) {
1883 /* Check for duplicates. */
1884 if (strcmp((*p)->xml, xml) == 0)
1885 return;
1886 p = &(*p)->next;
1887 }
1888
1889 s = g_new0(GDBRegisterState, 1);
1890 s->base_reg = last_reg;
1891 s->num_regs = num_regs;
1892 s->get_reg = get_reg;
1893 s->set_reg = set_reg;
1894 s->xml = xml;
1895
1896 /* Add to end of list. */
1897 last_reg += num_regs;
1898 *p = s;
1899 if (g_pos) {
1900 if (g_pos != s->base_reg) {
1901 fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1902 "Expected %d got %d\n", xml, g_pos, s->base_reg);
1903 } else {
1904 num_g_regs = last_reg;
1905 }
1906 }
1907 }
1908 #endif
1909
1910 #ifndef CONFIG_USER_ONLY
1911 static const int xlat_gdb_type[] = {
1912 [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE,
1913 [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ,
1914 [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1915 };
1916 #endif
1917
1918 static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
1919 {
1920 CPUArchState *env;
1921 int err = 0;
1922
1923 if (kvm_enabled())
1924 return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1925
1926 switch (type) {
1927 case GDB_BREAKPOINT_SW:
1928 case GDB_BREAKPOINT_HW:
1929 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1930 err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1931 if (err)
1932 break;
1933 }
1934 return err;
1935 #ifndef CONFIG_USER_ONLY
1936 case GDB_WATCHPOINT_WRITE:
1937 case GDB_WATCHPOINT_READ:
1938 case GDB_WATCHPOINT_ACCESS:
1939 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1940 err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1941 NULL);
1942 if (err)
1943 break;
1944 }
1945 return err;
1946 #endif
1947 default:
1948 return -ENOSYS;
1949 }
1950 }
1951
1952 static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
1953 {
1954 CPUArchState *env;
1955 int err = 0;
1956
1957 if (kvm_enabled())
1958 return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1959
1960 switch (type) {
1961 case GDB_BREAKPOINT_SW:
1962 case GDB_BREAKPOINT_HW:
1963 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1964 err = cpu_breakpoint_remove(env, addr, BP_GDB);
1965 if (err)
1966 break;
1967 }
1968 return err;
1969 #ifndef CONFIG_USER_ONLY
1970 case GDB_WATCHPOINT_WRITE:
1971 case GDB_WATCHPOINT_READ:
1972 case GDB_WATCHPOINT_ACCESS:
1973 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1974 err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
1975 if (err)
1976 break;
1977 }
1978 return err;
1979 #endif
1980 default:
1981 return -ENOSYS;
1982 }
1983 }
1984
1985 static void gdb_breakpoint_remove_all(void)
1986 {
1987 CPUArchState *env;
1988
1989 if (kvm_enabled()) {
1990 kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
1991 return;
1992 }
1993
1994 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1995 cpu_breakpoint_remove_all(env, BP_GDB);
1996 #ifndef CONFIG_USER_ONLY
1997 cpu_watchpoint_remove_all(env, BP_GDB);
1998 #endif
1999 }
2000 }
2001
2002 static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
2003 {
2004 cpu_synchronize_state(s->c_cpu);
2005 #if defined(TARGET_I386)
2006 s->c_cpu->eip = pc;
2007 #elif defined (TARGET_PPC)
2008 s->c_cpu->nip = pc;
2009 #elif defined (TARGET_SPARC)
2010 s->c_cpu->pc = pc;
2011 s->c_cpu->npc = pc + 4;
2012 #elif defined (TARGET_ARM)
2013 s->c_cpu->regs[15] = pc;
2014 #elif defined (TARGET_SH4)
2015 s->c_cpu->pc = pc;
2016 #elif defined (TARGET_MIPS)
2017 s->c_cpu->active_tc.PC = pc & ~(target_ulong)1;
2018 if (pc & 1) {
2019 s->c_cpu->hflags |= MIPS_HFLAG_M16;
2020 } else {
2021 s->c_cpu->hflags &= ~(MIPS_HFLAG_M16);
2022 }
2023 #elif defined (TARGET_MICROBLAZE)
2024 s->c_cpu->sregs[SR_PC] = pc;
2025 #elif defined(TARGET_OPENRISC)
2026 s->c_cpu->pc = pc;
2027 #elif defined (TARGET_CRIS)
2028 s->c_cpu->pc = pc;
2029 #elif defined (TARGET_ALPHA)
2030 s->c_cpu->pc = pc;
2031 #elif defined (TARGET_S390X)
2032 s->c_cpu->psw.addr = pc;
2033 #elif defined (TARGET_LM32)
2034 s->c_cpu->pc = pc;
2035 #elif defined(TARGET_XTENSA)
2036 s->c_cpu->pc = pc;
2037 #endif
2038 }
2039
2040 static CPUArchState *find_cpu(uint32_t thread_id)
2041 {
2042 CPUArchState *env;
2043
2044 for (env = first_cpu; env != NULL; env = env->next_cpu) {
2045 if (cpu_index(env) == thread_id) {
2046 return env;
2047 }
2048 }
2049
2050 return NULL;
2051 }
2052
2053 static int gdb_handle_packet(GDBState *s, const char *line_buf)
2054 {
2055 CPUArchState *env;
2056 const char *p;
2057 uint32_t thread;
2058 int ch, reg_size, type, res;
2059 char buf[MAX_PACKET_LENGTH];
2060 uint8_t mem_buf[MAX_PACKET_LENGTH];
2061 uint8_t *registers;
2062 target_ulong addr, len;
2063
2064 #ifdef DEBUG_GDB
2065 printf("command='%s'\n", line_buf);
2066 #endif
2067 p = line_buf;
2068 ch = *p++;
2069 switch(ch) {
2070 case '?':
2071 /* TODO: Make this return the correct value for user-mode. */
2072 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
2073 cpu_index(s->c_cpu));
2074 put_packet(s, buf);
2075 /* Remove all the breakpoints when this query is issued,
2076 * because gdb is doing and initial connect and the state
2077 * should be cleaned up.
2078 */
2079 gdb_breakpoint_remove_all();
2080 break;
2081 case 'c':
2082 if (*p != '\0') {
2083 addr = strtoull(p, (char **)&p, 16);
2084 gdb_set_cpu_pc(s, addr);
2085 }
2086 s->signal = 0;
2087 gdb_continue(s);
2088 return RS_IDLE;
2089 case 'C':
2090 s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16));
2091 if (s->signal == -1)
2092 s->signal = 0;
2093 gdb_continue(s);
2094 return RS_IDLE;
2095 case 'v':
2096 if (strncmp(p, "Cont", 4) == 0) {
2097 int res_signal, res_thread;
2098
2099 p += 4;
2100 if (*p == '?') {
2101 put_packet(s, "vCont;c;C;s;S");
2102 break;
2103 }
2104 res = 0;
2105 res_signal = 0;
2106 res_thread = 0;
2107 while (*p) {
2108 int action, signal;
2109
2110 if (*p++ != ';') {
2111 res = 0;
2112 break;
2113 }
2114 action = *p++;
2115 signal = 0;
2116 if (action == 'C' || action == 'S') {
2117 signal = strtoul(p, (char **)&p, 16);
2118 } else if (action != 'c' && action != 's') {
2119 res = 0;
2120 break;
2121 }
2122 thread = 0;
2123 if (*p == ':') {
2124 thread = strtoull(p+1, (char **)&p, 16);
2125 }
2126 action = tolower(action);
2127 if (res == 0 || (res == 'c' && action == 's')) {
2128 res = action;
2129 res_signal = signal;
2130 res_thread = thread;
2131 }
2132 }
2133 if (res) {
2134 if (res_thread != -1 && res_thread != 0) {
2135 env = find_cpu(res_thread);
2136 if (env == NULL) {
2137 put_packet(s, "E22");
2138 break;
2139 }
2140 s->c_cpu = env;
2141 }
2142 if (res == 's') {
2143 cpu_single_step(s->c_cpu, sstep_flags);
2144 }
2145 s->signal = res_signal;
2146 gdb_continue(s);
2147 return RS_IDLE;
2148 }
2149 break;
2150 } else {
2151 goto unknown_command;
2152 }
2153 case 'k':
2154 #ifdef CONFIG_USER_ONLY
2155 /* Kill the target */
2156 fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
2157 exit(0);
2158 #endif
2159 case 'D':
2160 /* Detach packet */
2161 gdb_breakpoint_remove_all();
2162 gdb_syscall_mode = GDB_SYS_DISABLED;
2163 gdb_continue(s);
2164 put_packet(s, "OK");
2165 break;
2166 case 's':
2167 if (*p != '\0') {
2168 addr = strtoull(p, (char **)&p, 16);
2169 gdb_set_cpu_pc(s, addr);
2170 }
2171 cpu_single_step(s->c_cpu, sstep_flags);
2172 gdb_continue(s);
2173 return RS_IDLE;
2174 case 'F':
2175 {
2176 target_ulong ret;
2177 target_ulong err;
2178
2179 ret = strtoull(p, (char **)&p, 16);
2180 if (*p == ',') {
2181 p++;
2182 err = strtoull(p, (char **)&p, 16);
2183 } else {
2184 err = 0;
2185 }
2186 if (*p == ',')
2187 p++;
2188 type = *p;
2189 if (s->current_syscall_cb) {
2190 s->current_syscall_cb(s->c_cpu, ret, err);
2191 s->current_syscall_cb = NULL;
2192 }
2193 if (type == 'C') {
2194 put_packet(s, "T02");
2195 } else {
2196 gdb_continue(s);
2197 }
2198 }
2199 break;
2200 case 'g':
2201 cpu_synchronize_state(s->g_cpu);
2202 env = s->g_cpu;
2203 len = 0;
2204 for (addr = 0; addr < num_g_regs; addr++) {
2205 reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
2206 len += reg_size;
2207 }
2208 memtohex(buf, mem_buf, len);
2209 put_packet(s, buf);
2210 break;
2211 case 'G':
2212 cpu_synchronize_state(s->g_cpu);
2213 env = s->g_cpu;
2214 registers = mem_buf;
2215 len = strlen(p) / 2;
2216 hextomem((uint8_t *)registers, p, len);
2217 for (addr = 0; addr < num_g_regs && len > 0; addr++) {
2218 reg_size = gdb_write_register(s->g_cpu, registers, addr);
2219 len -= reg_size;
2220 registers += reg_size;
2221 }
2222 put_packet(s, "OK");
2223 break;
2224 case 'm':
2225 addr = strtoull(p, (char **)&p, 16);
2226 if (*p == ',')
2227 p++;
2228 len = strtoull(p, NULL, 16);
2229 if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
2230 put_packet (s, "E14");
2231 } else {
2232 memtohex(buf, mem_buf, len);
2233 put_packet(s, buf);
2234 }
2235 break;
2236 case 'M':
2237 addr = strtoull(p, (char **)&p, 16);
2238 if (*p == ',')
2239 p++;
2240 len = strtoull(p, (char **)&p, 16);
2241 if (*p == ':')
2242 p++;
2243 hextomem(mem_buf, p, len);
2244 if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0) {
2245 put_packet(s, "E14");
2246 } else {
2247 put_packet(s, "OK");
2248 }
2249 break;
2250 case 'p':
2251 /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
2252 This works, but can be very slow. Anything new enough to
2253 understand XML also knows how to use this properly. */
2254 if (!gdb_has_xml)
2255 goto unknown_command;
2256 addr = strtoull(p, (char **)&p, 16);
2257 reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
2258 if (reg_size) {
2259 memtohex(buf, mem_buf, reg_size);
2260 put_packet(s, buf);
2261 } else {
2262 put_packet(s, "E14");
2263 }
2264 break;
2265 case 'P':
2266 if (!gdb_has_xml)
2267 goto unknown_command;
2268 addr = strtoull(p, (char **)&p, 16);
2269 if (*p == '=')
2270 p++;
2271 reg_size = strlen(p) / 2;
2272 hextomem(mem_buf, p, reg_size);
2273 gdb_write_register(s->g_cpu, mem_buf, addr);
2274 put_packet(s, "OK");
2275 break;
2276 case 'Z':
2277 case 'z':
2278 type = strtoul(p, (char **)&p, 16);
2279 if (*p == ',')
2280 p++;
2281 addr = strtoull(p, (char **)&p, 16);
2282 if (*p == ',')
2283 p++;
2284 len = strtoull(p, (char **)&p, 16);
2285 if (ch == 'Z')
2286 res = gdb_breakpoint_insert(addr, len, type);
2287 else
2288 res = gdb_breakpoint_remove(addr, len, type);
2289 if (res >= 0)
2290 put_packet(s, "OK");
2291 else if (res == -ENOSYS)
2292 put_packet(s, "");
2293 else
2294 put_packet(s, "E22");
2295 break;
2296 case 'H':
2297 type = *p++;
2298 thread = strtoull(p, (char **)&p, 16);
2299 if (thread == -1 || thread == 0) {
2300 put_packet(s, "OK");
2301 break;
2302 }
2303 env = find_cpu(thread);
2304 if (env == NULL) {
2305 put_packet(s, "E22");
2306 break;
2307 }
2308 switch (type) {
2309 case 'c':
2310 s->c_cpu = env;
2311 put_packet(s, "OK");
2312 break;
2313 case 'g':
2314 s->g_cpu = env;
2315 put_packet(s, "OK");
2316 break;
2317 default:
2318 put_packet(s, "E22");
2319 break;
2320 }
2321 break;
2322 case 'T':
2323 thread = strtoull(p, (char **)&p, 16);
2324 env = find_cpu(thread);
2325
2326 if (env != NULL) {
2327 put_packet(s, "OK");
2328 } else {
2329 put_packet(s, "E22");
2330 }
2331 break;
2332 case 'q':
2333 case 'Q':
2334 /* parse any 'q' packets here */
2335 if (!strcmp(p,"qemu.sstepbits")) {
2336 /* Query Breakpoint bit definitions */
2337 snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
2338 SSTEP_ENABLE,
2339 SSTEP_NOIRQ,
2340 SSTEP_NOTIMER);
2341 put_packet(s, buf);
2342 break;
2343 } else if (strncmp(p,"qemu.sstep",10) == 0) {
2344 /* Display or change the sstep_flags */
2345 p += 10;
2346 if (*p != '=') {
2347 /* Display current setting */
2348 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
2349 put_packet(s, buf);
2350 break;
2351 }
2352 p++;
2353 type = strtoul(p, (char **)&p, 16);
2354 sstep_flags = type;
2355 put_packet(s, "OK");
2356 break;
2357 } else if (strcmp(p,"C") == 0) {
2358 /* "Current thread" remains vague in the spec, so always return
2359 * the first CPU (gdb returns the first thread). */
2360 put_packet(s, "QC1");
2361 break;
2362 } else if (strcmp(p,"fThreadInfo") == 0) {
2363 s->query_cpu = first_cpu;
2364 goto report_cpuinfo;
2365 } else if (strcmp(p,"sThreadInfo") == 0) {
2366 report_cpuinfo:
2367 if (s->query_cpu) {
2368 snprintf(buf, sizeof(buf), "m%x", cpu_index(s->query_cpu));
2369 put_packet(s, buf);
2370 s->query_cpu = s->query_cpu->next_cpu;
2371 } else
2372 put_packet(s, "l");
2373 break;
2374 } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
2375 thread = strtoull(p+16, (char **)&p, 16);
2376 env = find_cpu(thread);
2377 if (env != NULL) {
2378 cpu_synchronize_state(env);
2379 len = snprintf((char *)mem_buf, sizeof(mem_buf),
2380 "CPU#%d [%s]", env->cpu_index,
2381 env->halted ? "halted " : "running");
2382 memtohex(buf, mem_buf, len);
2383 put_packet(s, buf);
2384 }
2385 break;
2386 }
2387 #ifdef CONFIG_USER_ONLY
2388 else if (strncmp(p, "Offsets", 7) == 0) {
2389 TaskState *ts = s->c_cpu->opaque;
2390
2391 snprintf(buf, sizeof(buf),
2392 "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
2393 ";Bss=" TARGET_ABI_FMT_lx,
2394 ts->info->code_offset,
2395 ts->info->data_offset,
2396 ts->info->data_offset);
2397 put_packet(s, buf);
2398 break;
2399 }
2400 #else /* !CONFIG_USER_ONLY */
2401 else if (strncmp(p, "Rcmd,", 5) == 0) {
2402 int len = strlen(p + 5);
2403
2404 if ((len % 2) != 0) {
2405 put_packet(s, "E01");
2406 break;
2407 }
2408 hextomem(mem_buf, p + 5, len);
2409 len = len / 2;
2410 mem_buf[len++] = 0;
2411 qemu_chr_be_write(s->mon_chr, mem_buf, len);
2412 put_packet(s, "OK");
2413 break;
2414 }
2415 #endif /* !CONFIG_USER_ONLY */
2416 if (strncmp(p, "Supported", 9) == 0) {
2417 snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
2418 #ifdef GDB_CORE_XML
2419 pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
2420 #endif
2421 put_packet(s, buf);
2422 break;
2423 }
2424 #ifdef GDB_CORE_XML
2425 if (strncmp(p, "Xfer:features:read:", 19) == 0) {
2426 const char *xml;
2427 target_ulong total_len;
2428
2429 gdb_has_xml = 1;
2430 p += 19;
2431 xml = get_feature_xml(p, &p);
2432 if (!xml) {
2433 snprintf(buf, sizeof(buf), "E00");
2434 put_packet(s, buf);
2435 break;
2436 }
2437
2438 if (*p == ':')
2439 p++;
2440 addr = strtoul(p, (char **)&p, 16);
2441 if (*p == ',')
2442 p++;
2443 len = strtoul(p, (char **)&p, 16);
2444
2445 total_len = strlen(xml);
2446 if (addr > total_len) {
2447 snprintf(buf, sizeof(buf), "E00");
2448 put_packet(s, buf);
2449 break;
2450 }
2451 if (len > (MAX_PACKET_LENGTH - 5) / 2)
2452 len = (MAX_PACKET_LENGTH - 5) / 2;
2453 if (len < total_len - addr) {
2454 buf[0] = 'm';
2455 len = memtox(buf + 1, xml + addr, len);
2456 } else {
2457 buf[0] = 'l';
2458 len = memtox(buf + 1, xml + addr, total_len - addr);
2459 }
2460 put_packet_binary(s, buf, len + 1);
2461 break;
2462 }
2463 #endif
2464 /* Unrecognised 'q' command. */
2465 goto unknown_command;
2466
2467 default:
2468 unknown_command:
2469 /* put empty packet */
2470 buf[0] = '\0';
2471 put_packet(s, buf);
2472 break;
2473 }
2474 return RS_IDLE;
2475 }
2476
2477 void gdb_set_stop_cpu(CPUArchState *env)
2478 {
2479 gdbserver_state->c_cpu = env;
2480 gdbserver_state->g_cpu = env;
2481 }
2482
2483 #ifndef CONFIG_USER_ONLY
2484 static void gdb_vm_state_change(void *opaque, int running, RunState state)
2485 {
2486 GDBState *s = gdbserver_state;
2487 CPUArchState *env = s->c_cpu;
2488 char buf[256];
2489 const char *type;
2490 int ret;
2491
2492 if (running || s->state == RS_INACTIVE) {
2493 return;
2494 }
2495 /* Is there a GDB syscall waiting to be sent? */
2496 if (s->current_syscall_cb) {
2497 put_packet(s, s->syscall_buf);
2498 return;
2499 }
2500 switch (state) {
2501 case RUN_STATE_DEBUG:
2502 if (env->watchpoint_hit) {
2503 switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
2504 case BP_MEM_READ:
2505 type = "r";
2506 break;
2507 case BP_MEM_ACCESS:
2508 type = "a";
2509 break;
2510 default:
2511 type = "";
2512 break;
2513 }
2514 snprintf(buf, sizeof(buf),
2515 "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
2516 GDB_SIGNAL_TRAP, cpu_index(env), type,
2517 env->watchpoint_hit->vaddr);
2518 env->watchpoint_hit = NULL;
2519 goto send_packet;
2520 }
2521 tb_flush(env);
2522 ret = GDB_SIGNAL_TRAP;
2523 break;
2524 case RUN_STATE_PAUSED:
2525 ret = GDB_SIGNAL_INT;
2526 break;
2527 case RUN_STATE_SHUTDOWN:
2528 ret = GDB_SIGNAL_QUIT;
2529 break;
2530 case RUN_STATE_IO_ERROR:
2531 ret = GDB_SIGNAL_IO;
2532 break;
2533 case RUN_STATE_WATCHDOG:
2534 ret = GDB_SIGNAL_ALRM;
2535 break;
2536 case RUN_STATE_INTERNAL_ERROR:
2537 ret = GDB_SIGNAL_ABRT;
2538 break;
2539 case RUN_STATE_SAVE_VM:
2540 case RUN_STATE_RESTORE_VM:
2541 return;
2542 case RUN_STATE_FINISH_MIGRATE:
2543 ret = GDB_SIGNAL_XCPU;
2544 break;
2545 default:
2546 ret = GDB_SIGNAL_UNKNOWN;
2547 break;
2548 }
2549 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, cpu_index(env));
2550
2551 send_packet:
2552 put_packet(s, buf);
2553
2554 /* disable single step if it was enabled */
2555 cpu_single_step(env, 0);
2556 }
2557 #endif
2558
2559 /* Send a gdb syscall request.
2560 This accepts limited printf-style format specifiers, specifically:
2561 %x - target_ulong argument printed in hex.
2562 %lx - 64-bit argument printed in hex.
2563 %s - string pointer (target_ulong) and length (int) pair. */
2564 void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
2565 {
2566 va_list va;
2567 char *p;
2568 char *p_end;
2569 target_ulong addr;
2570 uint64_t i64;
2571 GDBState *s;
2572
2573 s = gdbserver_state;
2574 if (!s)
2575 return;
2576 s->current_syscall_cb = cb;
2577 #ifndef CONFIG_USER_ONLY
2578 vm_stop(RUN_STATE_DEBUG);
2579 #endif
2580 va_start(va, fmt);
2581 p = s->syscall_buf;
2582 p_end = &s->syscall_buf[sizeof(s->syscall_buf)];
2583 *(p++) = 'F';
2584 while (*fmt) {
2585 if (*fmt == '%') {
2586 fmt++;
2587 switch (*fmt++) {
2588 case 'x':
2589 addr = va_arg(va, target_ulong);
2590 p += snprintf(p, p_end - p, TARGET_FMT_lx, addr);
2591 break;
2592 case 'l':
2593 if (*(fmt++) != 'x')
2594 goto bad_format;
2595 i64 = va_arg(va, uint64_t);
2596 p += snprintf(p, p_end - p, "%" PRIx64, i64);
2597 break;
2598 case 's':
2599 addr = va_arg(va, target_ulong);
2600 p += snprintf(p, p_end - p, TARGET_FMT_lx "/%x",
2601 addr, va_arg(va, int));
2602 break;
2603 default:
2604 bad_format:
2605 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
2606 fmt - 1);
2607 break;
2608 }
2609 } else {
2610 *(p++) = *(fmt++);
2611 }
2612 }
2613 *p = 0;
2614 va_end(va);
2615 #ifdef CONFIG_USER_ONLY
2616 put_packet(s, s->syscall_buf);
2617 gdb_handlesig(s->c_cpu, 0);
2618 #else
2619 /* In this case wait to send the syscall packet until notification that
2620 the CPU has stopped. This must be done because if the packet is sent
2621 now the reply from the syscall request could be received while the CPU
2622 is still in the running state, which can cause packets to be dropped
2623 and state transition 'T' packets to be sent while the syscall is still
2624 being processed. */
2625 cpu_exit(s->c_cpu);
2626 #endif
2627 }
2628
2629 static void gdb_read_byte(GDBState *s, int ch)
2630 {
2631 int i, csum;
2632 uint8_t reply;
2633
2634 #ifndef CONFIG_USER_ONLY
2635 if (s->last_packet_len) {
2636 /* Waiting for a response to the last packet. If we see the start
2637 of a new command then abandon the previous response. */
2638 if (ch == '-') {
2639 #ifdef DEBUG_GDB
2640 printf("Got NACK, retransmitting\n");
2641 #endif
2642 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
2643 }
2644 #ifdef DEBUG_GDB
2645 else if (ch == '+')
2646 printf("Got ACK\n");
2647 else
2648 printf("Got '%c' when expecting ACK/NACK\n", ch);
2649 #endif
2650 if (ch == '+' || ch == '$')
2651 s->last_packet_len = 0;
2652 if (ch != '$')
2653 return;
2654 }
2655 if (runstate_is_running()) {
2656 /* when the CPU is running, we cannot do anything except stop
2657 it when receiving a char */
2658 vm_stop(RUN_STATE_PAUSED);
2659 } else
2660 #endif
2661 {
2662 switch(s->state) {
2663 case RS_IDLE:
2664 if (ch == '$') {
2665 s->line_buf_index = 0;
2666 s->state = RS_GETLINE;
2667 }
2668 break;
2669 case RS_GETLINE:
2670 if (ch == '#') {
2671 s->state = RS_CHKSUM1;
2672 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
2673 s->state = RS_IDLE;
2674 } else {
2675 s->line_buf[s->line_buf_index++] = ch;
2676 }
2677 break;
2678 case RS_CHKSUM1:
2679 s->line_buf[s->line_buf_index] = '\0';
2680 s->line_csum = fromhex(ch) << 4;
2681 s->state = RS_CHKSUM2;
2682 break;
2683 case RS_CHKSUM2:
2684 s->line_csum |= fromhex(ch);
2685 csum = 0;
2686 for(i = 0; i < s->line_buf_index; i++) {
2687 csum += s->line_buf[i];
2688 }
2689 if (s->line_csum != (csum & 0xff)) {
2690 reply = '-';
2691 put_buffer(s, &reply, 1);
2692 s->state = RS_IDLE;
2693 } else {
2694 reply = '+';
2695 put_buffer(s, &reply, 1);
2696 s->state = gdb_handle_packet(s, s->line_buf);
2697 }
2698 break;
2699 default:
2700 abort();
2701 }
2702 }
2703 }
2704
2705 /* Tell the remote gdb that the process has exited. */
2706 void gdb_exit(CPUArchState *env, int code)
2707 {
2708 GDBState *s;
2709 char buf[4];
2710
2711 s = gdbserver_state;
2712 if (!s) {
2713 return;
2714 }
2715 #ifdef CONFIG_USER_ONLY
2716 if (gdbserver_fd < 0 || s->fd < 0) {
2717 return;
2718 }
2719 #endif
2720
2721 snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
2722 put_packet(s, buf);
2723
2724 #ifndef CONFIG_USER_ONLY
2725 if (s->chr) {
2726 qemu_chr_delete(s->chr);
2727 }
2728 #endif
2729 }
2730
2731 #ifdef CONFIG_USER_ONLY
2732 int
2733 gdb_queuesig (void)
2734 {
2735 GDBState *s;
2736
2737 s = gdbserver_state;
2738
2739 if (gdbserver_fd < 0 || s->fd < 0)
2740 return 0;
2741 else
2742 return 1;
2743 }
2744
2745 int
2746 gdb_handlesig (CPUArchState *env, int sig)
2747 {
2748 GDBState *s;
2749 char buf[256];
2750 int n;
2751
2752 s = gdbserver_state;
2753 if (gdbserver_fd < 0 || s->fd < 0)
2754 return sig;
2755
2756 /* disable single step if it was enabled */
2757 cpu_single_step(env, 0);
2758 tb_flush(env);
2759
2760 if (sig != 0)
2761 {
2762 snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
2763 put_packet(s, buf);
2764 }
2765 /* put_packet() might have detected that the peer terminated the
2766 connection. */
2767 if (s->fd < 0)
2768 return sig;
2769
2770 sig = 0;
2771 s->state = RS_IDLE;
2772 s->running_state = 0;
2773 while (s->running_state == 0) {
2774 n = read (s->fd, buf, 256);
2775 if (n > 0)
2776 {
2777 int i;
2778
2779 for (i = 0; i < n; i++)
2780 gdb_read_byte (s, buf[i]);
2781 }
2782 else if (n == 0 || errno != EAGAIN)
2783 {
2784 /* XXX: Connection closed. Should probably wait for another
2785 connection before continuing. */
2786 return sig;
2787 }
2788 }
2789 sig = s->signal;
2790 s->signal = 0;
2791 return sig;
2792 }
2793
2794 /* Tell the remote gdb that the process has exited due to SIG. */
2795 void gdb_signalled(CPUArchState *env, int sig)
2796 {
2797 GDBState *s;
2798 char buf[4];
2799
2800 s = gdbserver_state;
2801 if (gdbserver_fd < 0 || s->fd < 0)
2802 return;
2803
2804 snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
2805 put_packet(s, buf);
2806 }
2807
2808 static void gdb_accept(void)
2809 {
2810 GDBState *s;
2811 struct sockaddr_in sockaddr;
2812 socklen_t len;
2813 int val, fd;
2814
2815 for(;;) {
2816 len = sizeof(sockaddr);
2817 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
2818 if (fd < 0 && errno != EINTR) {
2819 perror("accept");
2820 return;
2821 } else if (fd >= 0) {
2822 #ifndef _WIN32
2823 fcntl(fd, F_SETFD, FD_CLOEXEC);
2824 #endif
2825 break;
2826 }
2827 }
2828
2829 /* set short latency */
2830 val = 1;
2831 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
2832
2833 s = g_malloc0(sizeof(GDBState));
2834 s->c_cpu = first_cpu;
2835 s->g_cpu = first_cpu;
2836 s->fd = fd;
2837 gdb_has_xml = 0;
2838
2839 gdbserver_state = s;
2840
2841 fcntl(fd, F_SETFL, O_NONBLOCK);
2842 }
2843
2844 static int gdbserver_open(int port)
2845 {
2846 struct sockaddr_in sockaddr;
2847 int fd, val, ret;
2848
2849 fd = socket(PF_INET, SOCK_STREAM, 0);
2850 if (fd < 0) {
2851 perror("socket");
2852 return -1;
2853 }
2854 #ifndef _WIN32
2855 fcntl(fd, F_SETFD, FD_CLOEXEC);
2856 #endif
2857
2858 /* allow fast reuse */
2859 val = 1;
2860 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
2861
2862 sockaddr.sin_family = AF_INET;
2863 sockaddr.sin_port = htons(port);
2864 sockaddr.sin_addr.s_addr = 0;
2865 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
2866 if (ret < 0) {
2867 perror("bind");
2868 close(fd);
2869 return -1;
2870 }
2871 ret = listen(fd, 0);
2872 if (ret < 0) {
2873 perror("listen");
2874 close(fd);
2875 return -1;
2876 }
2877 return fd;
2878 }
2879
2880 int gdbserver_start(int port)
2881 {
2882 gdbserver_fd = gdbserver_open(port);
2883 if (gdbserver_fd < 0)
2884 return -1;
2885 /* accept connections */
2886 gdb_accept();
2887 return 0;
2888 }
2889
2890 /* Disable gdb stub for child processes. */
2891 void gdbserver_fork(CPUArchState *env)
2892 {
2893 GDBState *s = gdbserver_state;
2894 if (gdbserver_fd < 0 || s->fd < 0)
2895 return;
2896 close(s->fd);
2897 s->fd = -1;
2898 cpu_breakpoint_remove_all(env, BP_GDB);
2899 cpu_watchpoint_remove_all(env, BP_GDB);
2900 }
2901 #else
2902 static int gdb_chr_can_receive(void *opaque)
2903 {
2904 /* We can handle an arbitrarily large amount of data.
2905 Pick the maximum packet size, which is as good as anything. */
2906 return MAX_PACKET_LENGTH;
2907 }
2908
2909 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
2910 {
2911 int i;
2912
2913 for (i = 0; i < size; i++) {
2914 gdb_read_byte(gdbserver_state, buf[i]);
2915 }
2916 }
2917
2918 static void gdb_chr_event(void *opaque, int event)
2919 {
2920 switch (event) {
2921 case CHR_EVENT_OPENED:
2922 vm_stop(RUN_STATE_PAUSED);
2923 gdb_has_xml = 0;
2924 break;
2925 default:
2926 break;
2927 }
2928 }
2929
2930 static void gdb_monitor_output(GDBState *s, const char *msg, int len)
2931 {
2932 char buf[MAX_PACKET_LENGTH];
2933
2934 buf[0] = 'O';
2935 if (len > (MAX_PACKET_LENGTH/2) - 1)
2936 len = (MAX_PACKET_LENGTH/2) - 1;
2937 memtohex(buf + 1, (uint8_t *)msg, len);
2938 put_packet(s, buf);
2939 }
2940
2941 static int gdb_monitor_write(CharDriverState *chr, const uint8_t *buf, int len)
2942 {
2943 const char *p = (const char *)buf;
2944 int max_sz;
2945
2946 max_sz = (sizeof(gdbserver_state->last_packet) - 2) / 2;
2947 for (;;) {
2948 if (len <= max_sz) {
2949 gdb_monitor_output(gdbserver_state, p, len);
2950 break;
2951 }
2952 gdb_monitor_output(gdbserver_state, p, max_sz);
2953 p += max_sz;
2954 len -= max_sz;
2955 }
2956 return len;
2957 }
2958
2959 #ifndef _WIN32
2960 static void gdb_sigterm_handler(int signal)
2961 {
2962 if (runstate_is_running()) {
2963 vm_stop(RUN_STATE_PAUSED);
2964 }
2965 }
2966 #endif
2967
2968 int gdbserver_start(const char *device)
2969 {
2970 GDBState *s;
2971 char gdbstub_device_name[128];
2972 CharDriverState *chr = NULL;
2973 CharDriverState *mon_chr;
2974
2975 if (!device)
2976 return -1;
2977 if (strcmp(device, "none") != 0) {
2978 if (strstart(device, "tcp:", NULL)) {
2979 /* enforce required TCP attributes */
2980 snprintf(gdbstub_device_name, sizeof(gdbstub_device_name),
2981 "%s,nowait,nodelay,server", device);
2982 device = gdbstub_device_name;
2983 }
2984 #ifndef _WIN32
2985 else if (strcmp(device, "stdio") == 0) {
2986 struct sigaction act;
2987
2988 memset(&act, 0, sizeof(act));
2989 act.sa_handler = gdb_sigterm_handler;
2990 sigaction(SIGINT, &act, NULL);
2991 }
2992 #endif
2993 chr = qemu_chr_new("gdb", device, NULL);
2994 if (!chr)
2995 return -1;
2996
2997 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
2998 gdb_chr_event, NULL);
2999 }
3000
3001 s = gdbserver_state;
3002 if (!s) {
3003 s = g_malloc0(sizeof(GDBState));
3004 gdbserver_state = s;
3005
3006 qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL);
3007
3008 /* Initialize a monitor terminal for gdb */
3009 mon_chr = g_malloc0(sizeof(*mon_chr));
3010 mon_chr->chr_write = gdb_monitor_write;
3011 monitor_init(mon_chr, 0);
3012 } else {
3013 if (s->chr)
3014 qemu_chr_delete(s->chr);
3015 mon_chr = s->mon_chr;
3016 memset(s, 0, sizeof(GDBState));
3017 }
3018 s->c_cpu = first_cpu;
3019 s->g_cpu = first_cpu;
3020 s->chr = chr;
3021 s->state = chr ? RS_IDLE : RS_INACTIVE;
3022 s->mon_chr = mon_chr;
3023 s->current_syscall_cb = NULL;
3024
3025 return 0;
3026 }
3027 #endif
Qemu copy for testing