hw/alpha_pci.c

   1 /*
   2  * QEMU Alpha PCI support functions.
   3  *
   4  * Some of this isn't very Alpha specific at all.
   5  *
   6  * ??? Sparse memory access not implemented.
   7  */
   8
   9 #include "config.h"
  10 #include "alpha_sys.h"
  11 #include "qemu-log.h"
  12 #include "sysemu.h"
  13 #include "vmware_vga.h"
  14
  15
  16 /* PCI IO reads/writes, to byte-word addressable memory.  */
  17 /* ??? Doesn't handle multiple PCI busses.  */
  18
  19 static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned size)
  20 {
  21     switch (size) {
  22     case 1:
  23         return cpu_inb(addr);
  24     case 2:
  25         return cpu_inw(addr);
  26     case 4:
  27         return cpu_inl(addr);
  28     }
  29     abort();
  30 }
  31
  32 static void bw_io_write(void *opaque, target_phys_addr_t addr,
  33                         uint64_t val, unsigned size)
  34 {
  35     switch (size) {
  36     case 1:
  37         cpu_outb(addr, val);
  38         break;
  39     case 2:
  40         cpu_outw(addr, val);
  41         break;
  42     case 4:
  43         cpu_outl(addr, val);
  44         break;
  45     default:
  46         abort();
  47     }
  48 }
  49
  50 const MemoryRegionOps alpha_pci_bw_io_ops = {
  51     .read = bw_io_read,
  52     .write = bw_io_write,
  53     .endianness = DEVICE_LITTLE_ENDIAN,
  54     .impl = {
  55         .min_access_size = 1,
  56         .max_access_size = 4,
  57     },
  58 };
  59
  60 /* PCI config space reads/writes, to byte-word addressable memory.  */
  61 static uint64_t bw_conf1_read(void *opaque, target_phys_addr_t addr,
  62                               unsigned size)
  63 {
  64     PCIBus *b = opaque;
  65     return pci_data_read(b, addr, size);
  66 }
  67
  68 static void bw_conf1_write(void *opaque, target_phys_addr_t addr,
  69                            uint64_t val, unsigned size)
  70 {
  71     PCIBus *b = opaque;
  72     pci_data_write(b, addr, val, size);
  73 }
  74
  75 const MemoryRegionOps alpha_pci_conf1_ops = {
  76     .read = bw_conf1_read,
  77     .write = bw_conf1_write,
  78     .endianness = DEVICE_LITTLE_ENDIAN,
  79     .impl = {
  80         .min_access_size = 1,
  81         .max_access_size = 4,
  82     },
  83 };
  84
  85 /* PCI/EISA Interrupt Acknowledge Cycle.  */
  86
  87 static uint64_t iack_read(void *opaque, target_phys_addr_t addr, unsigned size)
  88 {
  89     return pic_read_irq(isa_pic);
  90 }
  91
  92 static void special_write(void *opaque, target_phys_addr_t addr,
  93                           uint64_t val, unsigned size)
  94 {
  95     qemu_log("pci: special write cycle");
  96 }
  97
  98 const MemoryRegionOps alpha_pci_iack_ops = {
  99     .read = iack_read,
 100     .write = special_write,
 101     .endianness = DEVICE_LITTLE_ENDIAN,
 102     .valid = {
 103         .min_access_size = 4,
 104         .max_access_size = 4,
 105     },
 106     .impl = {
 107         .min_access_size = 4,
 108         .max_access_size = 4,
 109     },
 110 };
 111 \f
 112 void alpha_pci_vga_setup(PCIBus *pci_bus)
 113 {
 114     switch (vga_interface_type) {
 115 #ifdef CONFIG_SPICE
 116     case VGA_QXL:
 117         pci_create_simple(pci_bus, -1, "qxl-vga");
 118         return;
 119 #endif
 120     case VGA_CIRRUS:
 121         pci_cirrus_vga_init(pci_bus);
 122         return;
 123     case VGA_VMWARE:
 124         if (pci_vmsvga_init(pci_bus)) {
 125             return;
 126         }
 127         break;
 128     }
 129     /* If VGA is enabled at all, and one of the above didn't work, then
 130        fallback to Standard VGA.  */
 131     if (vga_interface_type != VGA_NONE) {
 132         pci_vga_init(pci_bus);
 133     }
 134 }