hw/arm/mainstone.c

   1 /*
   2  * PXA270-based Intel Mainstone platforms.
   3  *
   4  * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
   5  *                                    <akuster@mvista.com>
   6  *
   7  * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
   8  *
   9  * This code is licensed under the GNU GPL v2.
  10  *
  11  * Contributions after 2012-01-13 are licensed under the terms of the
  12  * GNU GPL, version 2 or (at your option) any later version.
  13  */
  14 #include "hw/hw.h"
  15 #include "hw/arm/pxa.h"
  16 #include "hw/arm/arm.h"
  17 #include "net/net.h"
  18 #include "hw/devices.h"
  19 #include "hw/boards.h"
  20 #include "hw/block/flash.h"
  21 #include "sysemu/blockdev.h"
  22 #include "hw/sysbus.h"
  23 #include "exec/address-spaces.h"
  24 #include "sysemu/qtest.h"
  25
  26 /* Device addresses */
  27 #define MST_FPGA_PHYS   0x08000000
  28 #define MST_ETH_PHYS    0x10000300
  29 #define MST_FLASH_0             0x00000000
  30 #define MST_FLASH_1             0x04000000
  31
  32 /* IRQ definitions */
  33 #define MMC_IRQ       0
  34 #define USIM_IRQ      1
  35 #define USBC_IRQ      2
  36 #define ETHERNET_IRQ  3
  37 #define AC97_IRQ      4
  38 #define PEN_IRQ       5
  39 #define MSINS_IRQ     6
  40 #define EXBRD_IRQ     7
  41 #define S0_CD_IRQ     9
  42 #define S0_STSCHG_IRQ 10
  43 #define S0_IRQ        11
  44 #define S1_CD_IRQ     13
  45 #define S1_STSCHG_IRQ 14
  46 #define S1_IRQ        15
  47
  48 static struct keymap map[0xE0] = {
  49     [0 ... 0xDF] = { -1, -1 },
  50     [0x1e] = {0,0}, /* a */
  51     [0x30] = {0,1}, /* b */
  52     [0x2e] = {0,2}, /* c */
  53     [0x20] = {0,3}, /* d */
  54     [0x12] = {0,4}, /* e */
  55     [0x21] = {0,5}, /* f */
  56     [0x22] = {1,0}, /* g */
  57     [0x23] = {1,1}, /* h */
  58     [0x17] = {1,2}, /* i */
  59     [0x24] = {1,3}, /* j */
  60     [0x25] = {1,4}, /* k */
  61     [0x26] = {1,5}, /* l */
  62     [0x32] = {2,0}, /* m */
  63     [0x31] = {2,1}, /* n */
  64     [0x18] = {2,2}, /* o */
  65     [0x19] = {2,3}, /* p */
  66     [0x10] = {2,4}, /* q */
  67     [0x13] = {2,5}, /* r */
  68     [0x1f] = {3,0}, /* s */
  69     [0x14] = {3,1}, /* t */
  70     [0x16] = {3,2}, /* u */
  71     [0x2f] = {3,3}, /* v */
  72     [0x11] = {3,4}, /* w */
  73     [0x2d] = {3,5}, /* x */
  74     [0x15] = {4,2}, /* y */
  75     [0x2c] = {4,3}, /* z */
  76     [0xc7] = {5,0}, /* Home */
  77     [0x2a] = {5,1}, /* shift */
  78     [0x39] = {5,2}, /* space */
  79     [0x39] = {5,3}, /* space */
  80     [0x1c] = {5,5}, /*  enter */
  81     [0xc8] = {6,0}, /* up */
  82     [0xd0] = {6,1}, /* down */
  83     [0xcb] = {6,2}, /* left */
  84     [0xcd] = {6,3}, /* right */
  85 };
  86
  87 enum mainstone_model_e { mainstone };
  88
  89 #define MAINSTONE_RAM   0x04000000
  90 #define MAINSTONE_ROM   0x00800000
  91 #define MAINSTONE_FLASH 0x02000000
  92
  93 static struct arm_boot_info mainstone_binfo = {
  94     .loader_start = PXA2XX_SDRAM_BASE,
  95     .ram_size = 0x04000000,
  96 };
  97
  98 static void mainstone_common_init(MemoryRegion *address_space_mem,
  99                                   QEMUMachineInitArgs *args,
 100                                   enum mainstone_model_e model, int arm_id)
 101 {
 102     uint32_t sector_len = 256 * 1024;
 103     hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
 104     PXA2xxState *mpu;
 105     DeviceState *mst_irq;
 106     DriveInfo *dinfo;
 107     int i;
 108     int be;
 109     MemoryRegion *rom = g_new(MemoryRegion, 1);
 110     const char *cpu_model = args->cpu_model;
 111
 112     if (!cpu_model)
 113         cpu_model = "pxa270-c5";
 114
 115     /* Setup CPU & memory */
 116     mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);
 117     memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM);
 118     vmstate_register_ram_global(rom);
 119     memory_region_set_readonly(rom, true);
 120     memory_region_add_subregion(address_space_mem, 0, rom);
 121
 122 #ifdef TARGET_WORDS_BIGENDIAN
 123     be = 1;
 124 #else
 125     be = 0;
 126 #endif
 127     /* There are two 32MiB flash devices on the board */
 128     for (i = 0; i < 2; i ++) {
 129         dinfo = drive_get(IF_PFLASH, 0, i);
 130         if (!dinfo) {
 131             if (qtest_enabled()) {
 132                 break;
 133             }
 134             fprintf(stderr, "Two flash images must be given with the "
 135                     "'pflash' parameter\n");
 136             exit(1);
 137         }
 138
 139         if (!pflash_cfi01_register(mainstone_flash_base[i], NULL,
 140                                    i ? "mainstone.flash1" : "mainstone.flash0",
 141                                    MAINSTONE_FLASH,
 142                                    dinfo->bdrv, sector_len,
 143                                    MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0,
 144                                    be)) {
 145             fprintf(stderr, "qemu: Error registering flash memory.\n");
 146             exit(1);
 147         }
 148     }
 149
 150     mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
 151                     qdev_get_gpio_in(mpu->gpio, 0));
 152
 153     /* setup keypad */
 154     pxa27x_register_keypad(mpu->kp, map, 0xe0);
 155
 156     /* MMC/SD host */
 157     pxa2xx_mmci_handlers(mpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
 158
 159     pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[0],
 160             qdev_get_gpio_in(mst_irq, S0_IRQ),
 161             qdev_get_gpio_in(mst_irq, S0_CD_IRQ));
 162     pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[1],
 163             qdev_get_gpio_in(mst_irq, S1_IRQ),
 164             qdev_get_gpio_in(mst_irq, S1_CD_IRQ));
 165
 166     smc91c111_init(&nd_table[0], MST_ETH_PHYS,
 167                     qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
 168
 169     mainstone_binfo.kernel_filename = args->kernel_filename;
 170     mainstone_binfo.kernel_cmdline = args->kernel_cmdline;
 171     mainstone_binfo.initrd_filename = args->initrd_filename;
 172     mainstone_binfo.board_id = arm_id;
 173     arm_load_kernel(mpu->cpu, &mainstone_binfo);
 174 }
 175
 176 static void mainstone_init(QEMUMachineInitArgs *args)
 177 {
 178     mainstone_common_init(get_system_memory(), args, mainstone, 0x196);
 179 }
 180
 181 static QEMUMachine mainstone2_machine = {
 182     .name = "mainstone",
 183     .desc = "Mainstone II (PXA27x)",
 184     .init = mainstone_init,
 185 };
 186
 187 static void mainstone_machine_init(void)
 188 {
 189     qemu_register_machine(&mainstone2_machine);
 190 }
 191
 192 machine_init(mainstone_machine_init);