hw/arm/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "hw/sysbus.h"
  25 #include "hw/arm-misc.h"
  26 #include "hw/primecell.h"
  27 #include "hw/devices.h"
  28 #include "net/net.h"
  29 #include "sysemu/sysemu.h"
  30 #include "hw/boards.h"
  31 #include "exec/address-spaces.h"
  32 #include "sysemu/blockdev.h"
  33 #include "hw/flash.h"
  34
  35 #define VEXPRESS_BOARD_ID 0x8e0
  36 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  37 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  38
  39 static struct arm_boot_info vexpress_binfo;
  40
  41 /* Address maps for peripherals:
  42  * the Versatile Express motherboard has two possible maps,
  43  * the "legacy" one (used for A9) and the "Cortex-A Series"
  44  * map (used for newer cores).
  45  * Individual daughterboards can also have different maps for
  46  * their peripherals.
  47  */
  48
  49 enum {
  50     VE_SYSREGS,
  51     VE_SP810,
  52     VE_SERIALPCI,
  53     VE_PL041,
  54     VE_MMCI,
  55     VE_KMI0,
  56     VE_KMI1,
  57     VE_UART0,
  58     VE_UART1,
  59     VE_UART2,
  60     VE_UART3,
  61     VE_WDT,
  62     VE_TIMER01,
  63     VE_TIMER23,
  64     VE_SERIALDVI,
  65     VE_RTC,
  66     VE_COMPACTFLASH,
  67     VE_CLCD,
  68     VE_NORFLASH0,
  69     VE_NORFLASH1,
  70     VE_SRAM,
  71     VE_VIDEORAM,
  72     VE_ETHERNET,
  73     VE_USB,
  74     VE_DAPROM,
  75 };
  76
  77 static hwaddr motherboard_legacy_map[] = {
  78     /* CS7: 0x10000000 .. 0x10020000 */
  79     [VE_SYSREGS] = 0x10000000,
  80     [VE_SP810] = 0x10001000,
  81     [VE_SERIALPCI] = 0x10002000,
  82     [VE_PL041] = 0x10004000,
  83     [VE_MMCI] = 0x10005000,
  84     [VE_KMI0] = 0x10006000,
  85     [VE_KMI1] = 0x10007000,
  86     [VE_UART0] = 0x10009000,
  87     [VE_UART1] = 0x1000a000,
  88     [VE_UART2] = 0x1000b000,
  89     [VE_UART3] = 0x1000c000,
  90     [VE_WDT] = 0x1000f000,
  91     [VE_TIMER01] = 0x10011000,
  92     [VE_TIMER23] = 0x10012000,
  93     [VE_SERIALDVI] = 0x10016000,
  94     [VE_RTC] = 0x10017000,
  95     [VE_COMPACTFLASH] = 0x1001a000,
  96     [VE_CLCD] = 0x1001f000,
  97     /* CS0: 0x40000000 .. 0x44000000 */
  98     [VE_NORFLASH0] = 0x40000000,
  99     /* CS1: 0x44000000 .. 0x48000000 */
 100     [VE_NORFLASH1] = 0x44000000,
 101     /* CS2: 0x48000000 .. 0x4a000000 */
 102     [VE_SRAM] = 0x48000000,
 103     /* CS3: 0x4c000000 .. 0x50000000 */
 104     [VE_VIDEORAM] = 0x4c000000,
 105     [VE_ETHERNET] = 0x4e000000,
 106     [VE_USB] = 0x4f000000,
 107 };
 108
 109 static hwaddr motherboard_aseries_map[] = {
 110     /* CS0: 0x08000000 .. 0x0c000000 */
 111     [VE_NORFLASH0] = 0x08000000,
 112     /* CS4: 0x0c000000 .. 0x10000000 */
 113     [VE_NORFLASH1] = 0x0c000000,
 114     /* CS5: 0x10000000 .. 0x14000000 */
 115     /* CS1: 0x14000000 .. 0x18000000 */
 116     [VE_SRAM] = 0x14000000,
 117     /* CS2: 0x18000000 .. 0x1c000000 */
 118     [VE_VIDEORAM] = 0x18000000,
 119     [VE_ETHERNET] = 0x1a000000,
 120     [VE_USB] = 0x1b000000,
 121     /* CS3: 0x1c000000 .. 0x20000000 */
 122     [VE_DAPROM] = 0x1c000000,
 123     [VE_SYSREGS] = 0x1c010000,
 124     [VE_SP810] = 0x1c020000,
 125     [VE_SERIALPCI] = 0x1c030000,
 126     [VE_PL041] = 0x1c040000,
 127     [VE_MMCI] = 0x1c050000,
 128     [VE_KMI0] = 0x1c060000,
 129     [VE_KMI1] = 0x1c070000,
 130     [VE_UART0] = 0x1c090000,
 131     [VE_UART1] = 0x1c0a0000,
 132     [VE_UART2] = 0x1c0b0000,
 133     [VE_UART3] = 0x1c0c0000,
 134     [VE_WDT] = 0x1c0f0000,
 135     [VE_TIMER01] = 0x1c110000,
 136     [VE_TIMER23] = 0x1c120000,
 137     [VE_SERIALDVI] = 0x1c160000,
 138     [VE_RTC] = 0x1c170000,
 139     [VE_COMPACTFLASH] = 0x1c1a0000,
 140     [VE_CLCD] = 0x1c1f0000,
 141 };
 142
 143 /* Structure defining the peculiarities of a specific daughterboard */
 144
 145 typedef struct VEDBoardInfo VEDBoardInfo;
 146
 147 typedef void DBoardInitFn(const VEDBoardInfo *daughterboard,
 148                           ram_addr_t ram_size,
 149                           const char *cpu_model,
 150                           qemu_irq *pic);
 151
 152 struct VEDBoardInfo {
 153     const hwaddr *motherboard_map;
 154     hwaddr loader_start;
 155     const hwaddr gic_cpu_if_addr;
 156     uint32_t proc_id;
 157     uint32_t num_voltage_sensors;
 158     const uint32_t *voltages;
 159     uint32_t num_clocks;
 160     const uint32_t *clocks;
 161     DBoardInitFn *init;
 162 };
 163
 164 static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
 165                                   ram_addr_t ram_size,
 166                                   const char *cpu_model,
 167                                   qemu_irq *pic)
 168 {
 169     MemoryRegion *sysmem = get_system_memory();
 170     MemoryRegion *ram = g_new(MemoryRegion, 1);
 171     MemoryRegion *lowram = g_new(MemoryRegion, 1);
 172     DeviceState *dev;
 173     SysBusDevice *busdev;
 174     qemu_irq *irqp;
 175     int n;
 176     qemu_irq cpu_irq[4];
 177     ram_addr_t low_ram_size;
 178
 179     if (!cpu_model) {
 180         cpu_model = "cortex-a9";
 181     }
 182
 183     for (n = 0; n < smp_cpus; n++) {
 184         ARMCPU *cpu = cpu_arm_init(cpu_model);
 185         if (!cpu) {
 186             fprintf(stderr, "Unable to find CPU definition\n");
 187             exit(1);
 188         }
 189         irqp = arm_pic_init_cpu(cpu);
 190         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 191     }
 192
 193     if (ram_size > 0x40000000) {
 194         /* 1GB is the maximum the address space permits */
 195         fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
 196         exit(1);
 197     }
 198
 199     memory_region_init_ram(ram, "vexpress.highmem", ram_size);
 200     vmstate_register_ram_global(ram);
 201     low_ram_size = ram_size;
 202     if (low_ram_size > 0x4000000) {
 203         low_ram_size = 0x4000000;
 204     }
 205     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 206      * address space should in theory be remappable to various
 207      * things including ROM or RAM; we always map the RAM there.
 208      */
 209     memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size);
 210     memory_region_add_subregion(sysmem, 0x0, lowram);
 211     memory_region_add_subregion(sysmem, 0x60000000, ram);
 212
 213     /* 0x1e000000 A9MPCore (SCU) private memory region */
 214     dev = qdev_create(NULL, "a9mpcore_priv");
 215     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 216     qdev_init_nofail(dev);
 217     busdev = SYS_BUS_DEVICE(dev);
 218     sysbus_mmio_map(busdev, 0, 0x1e000000);
 219     for (n = 0; n < smp_cpus; n++) {
 220         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 221     }
 222     /* Interrupts [42:0] are from the motherboard;
 223      * [47:43] are reserved; [63:48] are daughterboard
 224      * peripherals. Note that some documentation numbers
 225      * external interrupts starting from 32 (because the
 226      * A9MP has internal interrupts 0..31).
 227      */
 228     for (n = 0; n < 64; n++) {
 229         pic[n] = qdev_get_gpio_in(dev, n);
 230     }
 231
 232     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 233
 234     /* 0x10020000 PL111 CLCD (daughterboard) */
 235     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 236
 237     /* 0x10060000 AXI RAM */
 238     /* 0x100e0000 PL341 Dynamic Memory Controller */
 239     /* 0x100e1000 PL354 Static Memory Controller */
 240     /* 0x100e2000 System Configuration Controller */
 241
 242     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 243     /* 0x100e5000 SP805 Watchdog module */
 244     /* 0x100e6000 BP147 TrustZone Protection Controller */
 245     /* 0x100e9000 PL301 'Fast' AXI matrix */
 246     /* 0x100ea000 PL301 'Slow' AXI matrix */
 247     /* 0x100ec000 TrustZone Address Space Controller */
 248     /* 0x10200000 CoreSight debug APB */
 249     /* 0x1e00a000 PL310 L2 Cache Controller */
 250     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 251 }
 252
 253 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
 254  * values are in microvolts.
 255  */
 256 static const uint32_t a9_voltages[] = {
 257     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
 258     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
 259     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
 260     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
 261     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
 262     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
 263 };
 264
 265 /* Reset values for daughterboard oscillators (in Hz) */
 266 static const uint32_t a9_clocks[] = {
 267     45000000, /* AMBA AXI ACLK: 45MHz */
 268     23750000, /* daughterboard CLCD clock: 23.75MHz */
 269     66670000, /* Test chip reference clock: 66.67MHz */
 270 };
 271
 272 static const VEDBoardInfo a9_daughterboard = {
 273     .motherboard_map = motherboard_legacy_map,
 274     .loader_start = 0x60000000,
 275     .gic_cpu_if_addr = 0x1e000100,
 276     .proc_id = 0x0c000191,
 277     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
 278     .voltages = a9_voltages,
 279     .num_clocks = ARRAY_SIZE(a9_clocks),
 280     .clocks = a9_clocks,
 281     .init = a9_daughterboard_init,
 282 };
 283
 284 static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
 285                                    ram_addr_t ram_size,
 286                                    const char *cpu_model,
 287                                    qemu_irq *pic)
 288 {
 289     int n;
 290     MemoryRegion *sysmem = get_system_memory();
 291     MemoryRegion *ram = g_new(MemoryRegion, 1);
 292     MemoryRegion *sram = g_new(MemoryRegion, 1);
 293     qemu_irq cpu_irq[4];
 294     DeviceState *dev;
 295     SysBusDevice *busdev;
 296
 297     if (!cpu_model) {
 298         cpu_model = "cortex-a15";
 299     }
 300
 301     for (n = 0; n < smp_cpus; n++) {
 302         ARMCPU *cpu;
 303         qemu_irq *irqp;
 304
 305         cpu = cpu_arm_init(cpu_model);
 306         if (!cpu) {
 307             fprintf(stderr, "Unable to find CPU definition\n");
 308             exit(1);
 309         }
 310         irqp = arm_pic_init_cpu(cpu);
 311         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 312     }
 313
 314     {
 315         /* We have to use a separate 64 bit variable here to avoid the gcc
 316          * "comparison is always false due to limited range of data type"
 317          * warning if we are on a host where ram_addr_t is 32 bits.
 318          */
 319         uint64_t rsz = ram_size;
 320         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 321             fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
 322             exit(1);
 323         }
 324     }
 325
 326     memory_region_init_ram(ram, "vexpress.highmem", ram_size);
 327     vmstate_register_ram_global(ram);
 328     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 329     memory_region_add_subregion(sysmem, 0x80000000, ram);
 330
 331     /* 0x2c000000 A15MPCore private memory region (GIC) */
 332     dev = qdev_create(NULL, "a15mpcore_priv");
 333     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 334     qdev_init_nofail(dev);
 335     busdev = SYS_BUS_DEVICE(dev);
 336     sysbus_mmio_map(busdev, 0, 0x2c000000);
 337     for (n = 0; n < smp_cpus; n++) {
 338         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 339     }
 340     /* Interrupts [42:0] are from the motherboard;
 341      * [47:43] are reserved; [63:48] are daughterboard
 342      * peripherals. Note that some documentation numbers
 343      * external interrupts starting from 32 (because there
 344      * are internal interrupts 0..31).
 345      */
 346     for (n = 0; n < 64; n++) {
 347         pic[n] = qdev_get_gpio_in(dev, n);
 348     }
 349
 350     /* A15 daughterboard peripherals: */
 351
 352     /* 0x20000000: CoreSight interfaces: not modelled */
 353     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 354     /* 0x2a420000: SCC: not modelled */
 355     /* 0x2a430000: system counter: not modelled */
 356     /* 0x2b000000: HDLCD controller: not modelled */
 357     /* 0x2b060000: SP805 watchdog: not modelled */
 358     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 359     /* 0x2e000000: system SRAM */
 360     memory_region_init_ram(sram, "vexpress.a15sram", 0x10000);
 361     vmstate_register_ram_global(sram);
 362     memory_region_add_subregion(sysmem, 0x2e000000, sram);
 363
 364     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 365     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 366 }
 367
 368 static const uint32_t a15_voltages[] = {
 369     900000, /* Vcore: 0.9V : CPU core voltage */
 370 };
 371
 372 static const uint32_t a15_clocks[] = {
 373     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
 374     0, /* OSCCLK1: reserved */
 375     0, /* OSCCLK2: reserved */
 376     0, /* OSCCLK3: reserved */
 377     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
 378     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
 379     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
 380     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
 381     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
 382 };
 383
 384 static const VEDBoardInfo a15_daughterboard = {
 385     .motherboard_map = motherboard_aseries_map,
 386     .loader_start = 0x80000000,
 387     .gic_cpu_if_addr = 0x2c002000,
 388     .proc_id = 0x14000237,
 389     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
 390     .voltages = a15_voltages,
 391     .num_clocks = ARRAY_SIZE(a15_clocks),
 392     .clocks = a15_clocks,
 393     .init = a15_daughterboard_init,
 394 };
 395
 396 static void vexpress_common_init(const VEDBoardInfo *daughterboard,
 397                                  QEMUMachineInitArgs *args)
 398 {
 399     DeviceState *dev, *sysctl, *pl041;
 400     qemu_irq pic[64];
 401     uint32_t sys_id;
 402     DriveInfo *dinfo;
 403     ram_addr_t vram_size, sram_size;
 404     MemoryRegion *sysmem = get_system_memory();
 405     MemoryRegion *vram = g_new(MemoryRegion, 1);
 406     MemoryRegion *sram = g_new(MemoryRegion, 1);
 407     const hwaddr *map = daughterboard->motherboard_map;
 408     int i;
 409
 410     daughterboard->init(daughterboard, args->ram_size, args->cpu_model, pic);
 411
 412     /* Motherboard peripherals: the wiring is the same but the
 413      * addresses vary between the legacy and A-Series memory maps.
 414      */
 415
 416     sys_id = 0x1190f500;
 417
 418     sysctl = qdev_create(NULL, "realview_sysctl");
 419     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 420     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
 421     qdev_prop_set_uint32(sysctl, "len-db-voltage",
 422                          daughterboard->num_voltage_sensors);
 423     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
 424         char *propname = g_strdup_printf("db-voltage[%d]", i);
 425         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
 426         g_free(propname);
 427     }
 428     qdev_prop_set_uint32(sysctl, "len-db-clock",
 429                          daughterboard->num_clocks);
 430     for (i = 0; i < daughterboard->num_clocks; i++) {
 431         char *propname = g_strdup_printf("db-clock[%d]", i);
 432         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
 433         g_free(propname);
 434     }
 435     qdev_init_nofail(sysctl);
 436     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 437
 438     /* VE_SP810: not modelled */
 439     /* VE_SERIALPCI: not modelled */
 440
 441     pl041 = qdev_create(NULL, "pl041");
 442     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 443     qdev_init_nofail(pl041);
 444     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
 445     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
 446
 447     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 448     /* Wire up MMC card detect and read-only signals */
 449     qdev_connect_gpio_out(dev, 0,
 450                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 451     qdev_connect_gpio_out(dev, 1,
 452                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 453
 454     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 455     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 456
 457     sysbus_create_simple("pl011", map[VE_UART0], pic[5]);
 458     sysbus_create_simple("pl011", map[VE_UART1], pic[6]);
 459     sysbus_create_simple("pl011", map[VE_UART2], pic[7]);
 460     sysbus_create_simple("pl011", map[VE_UART3], pic[8]);
 461
 462     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 463     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 464
 465     /* VE_SERIALDVI: not modelled */
 466
 467     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 468
 469     /* VE_COMPACTFLASH: not modelled */
 470
 471     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 472
 473     dinfo = drive_get_next(IF_PFLASH);
 474     if (!pflash_cfi01_register(map[VE_NORFLASH0], NULL, "vexpress.flash0",
 475             VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
 476             VEXPRESS_FLASH_SECT_SIZE,
 477             VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
 478             0x00, 0x89, 0x00, 0x18, 0)) {
 479         fprintf(stderr, "vexpress: error registering flash 0.\n");
 480         exit(1);
 481     }
 482
 483     dinfo = drive_get_next(IF_PFLASH);
 484     if (!pflash_cfi01_register(map[VE_NORFLASH1], NULL, "vexpress.flash1",
 485             VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
 486             VEXPRESS_FLASH_SECT_SIZE,
 487             VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
 488             0x00, 0x89, 0x00, 0x18, 0)) {
 489         fprintf(stderr, "vexpress: error registering flash 1.\n");
 490         exit(1);
 491     }
 492
 493     sram_size = 0x2000000;
 494     memory_region_init_ram(sram, "vexpress.sram", sram_size);
 495     vmstate_register_ram_global(sram);
 496     memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
 497
 498     vram_size = 0x800000;
 499     memory_region_init_ram(vram, "vexpress.vram", vram_size);
 500     vmstate_register_ram_global(vram);
 501     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
 502
 503     /* 0x4e000000 LAN9118 Ethernet */
 504     if (nd_table[0].used) {
 505         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 506     }
 507
 508     /* VE_USB: not modelled */
 509
 510     /* VE_DAPROM: not modelled */
 511
 512     vexpress_binfo.ram_size = args->ram_size;
 513     vexpress_binfo.kernel_filename = args->kernel_filename;
 514     vexpress_binfo.kernel_cmdline = args->kernel_cmdline;
 515     vexpress_binfo.initrd_filename = args->initrd_filename;
 516     vexpress_binfo.nb_cpus = smp_cpus;
 517     vexpress_binfo.board_id = VEXPRESS_BOARD_ID;
 518     vexpress_binfo.loader_start = daughterboard->loader_start;
 519     vexpress_binfo.smp_loader_start = map[VE_SRAM];
 520     vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 521     vexpress_binfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 522     arm_load_kernel(arm_env_get_cpu(first_cpu), &vexpress_binfo);
 523 }
 524
 525 static void vexpress_a9_init(QEMUMachineInitArgs *args)
 526 {
 527     vexpress_common_init(&a9_daughterboard, args);
 528 }
 529
 530 static void vexpress_a15_init(QEMUMachineInitArgs *args)
 531 {
 532     vexpress_common_init(&a15_daughterboard, args);
 533 }
 534
 535 static QEMUMachine vexpress_a9_machine = {
 536     .name = "vexpress-a9",
 537     .desc = "ARM Versatile Express for Cortex-A9",
 538     .init = vexpress_a9_init,
 539     .block_default_type = IF_SCSI,
 540     .max_cpus = 4,
 541     DEFAULT_MACHINE_OPTIONS,
 542 };
 543
 544 static QEMUMachine vexpress_a15_machine = {
 545     .name = "vexpress-a15",
 546     .desc = "ARM Versatile Express for Cortex-A15",
 547     .init = vexpress_a15_init,
 548     .block_default_type = IF_SCSI,
 549     .max_cpus = 4,
 550     DEFAULT_MACHINE_OPTIONS,
 551 };
 552
 553 static void vexpress_machine_init(void)
 554 {
 555     qemu_register_machine(&vexpress_a9_machine);
 556     qemu_register_machine(&vexpress_a15_machine);
 557 }
 558
 559 machine_init(vexpress_machine_init);