hw/arm/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "hw/sysbus.h"
  25 #include "hw/arm/arm.h"
  26 #include "hw/arm/primecell.h"
  27 #include "hw/devices.h"
  28 #include "net/net.h"
  29 #include "sysemu/sysemu.h"
  30 #include "hw/boards.h"
  31 #include "exec/address-spaces.h"
  32 #include "sysemu/blockdev.h"
  33 #include "hw/block/flash.h"
  34 #include "sysemu/device_tree.h"
  35 #include <libfdt.h>
  36
  37 #define VEXPRESS_BOARD_ID 0x8e0
  38 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  39 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  40
  41 /* Number of virtio transports to create (0..8; limited by
  42  * number of available IRQ lines).
  43  */
  44 #define NUM_VIRTIO_TRANSPORTS 4
  45
  46 /* Address maps for peripherals:
  47  * the Versatile Express motherboard has two possible maps,
  48  * the "legacy" one (used for A9) and the "Cortex-A Series"
  49  * map (used for newer cores).
  50  * Individual daughterboards can also have different maps for
  51  * their peripherals.
  52  */
  53
  54 enum {
  55     VE_SYSREGS,
  56     VE_SP810,
  57     VE_SERIALPCI,
  58     VE_PL041,
  59     VE_MMCI,
  60     VE_KMI0,
  61     VE_KMI1,
  62     VE_UART0,
  63     VE_UART1,
  64     VE_UART2,
  65     VE_UART3,
  66     VE_WDT,
  67     VE_TIMER01,
  68     VE_TIMER23,
  69     VE_SERIALDVI,
  70     VE_RTC,
  71     VE_COMPACTFLASH,
  72     VE_CLCD,
  73     VE_NORFLASH0,
  74     VE_NORFLASH1,
  75     VE_NORFLASHALIAS,
  76     VE_SRAM,
  77     VE_VIDEORAM,
  78     VE_ETHERNET,
  79     VE_USB,
  80     VE_DAPROM,
  81     VE_VIRTIO,
  82 };
  83
  84 static hwaddr motherboard_legacy_map[] = {
  85     /* CS7: 0x10000000 .. 0x10020000 */
  86     [VE_SYSREGS] = 0x10000000,
  87     [VE_SP810] = 0x10001000,
  88     [VE_SERIALPCI] = 0x10002000,
  89     [VE_PL041] = 0x10004000,
  90     [VE_MMCI] = 0x10005000,
  91     [VE_KMI0] = 0x10006000,
  92     [VE_KMI1] = 0x10007000,
  93     [VE_UART0] = 0x10009000,
  94     [VE_UART1] = 0x1000a000,
  95     [VE_UART2] = 0x1000b000,
  96     [VE_UART3] = 0x1000c000,
  97     [VE_WDT] = 0x1000f000,
  98     [VE_TIMER01] = 0x10011000,
  99     [VE_TIMER23] = 0x10012000,
 100     [VE_VIRTIO] = 0x10013000,
 101     [VE_SERIALDVI] = 0x10016000,
 102     [VE_RTC] = 0x10017000,
 103     [VE_COMPACTFLASH] = 0x1001a000,
 104     [VE_CLCD] = 0x1001f000,
 105     /* CS0: 0x40000000 .. 0x44000000 */
 106     [VE_NORFLASH0] = 0x40000000,
 107     /* CS1: 0x44000000 .. 0x48000000 */
 108     [VE_NORFLASH1] = 0x44000000,
 109     /* CS2: 0x48000000 .. 0x4a000000 */
 110     [VE_SRAM] = 0x48000000,
 111     /* CS3: 0x4c000000 .. 0x50000000 */
 112     [VE_VIDEORAM] = 0x4c000000,
 113     [VE_ETHERNET] = 0x4e000000,
 114     [VE_USB] = 0x4f000000,
 115     [VE_NORFLASHALIAS] = -1, /* not present */
 116 };
 117
 118 static hwaddr motherboard_aseries_map[] = {
 119     [VE_NORFLASHALIAS] = 0,
 120     /* CS0: 0x08000000 .. 0x0c000000 */
 121     [VE_NORFLASH0] = 0x08000000,
 122     /* CS4: 0x0c000000 .. 0x10000000 */
 123     [VE_NORFLASH1] = 0x0c000000,
 124     /* CS5: 0x10000000 .. 0x14000000 */
 125     /* CS1: 0x14000000 .. 0x18000000 */
 126     [VE_SRAM] = 0x14000000,
 127     /* CS2: 0x18000000 .. 0x1c000000 */
 128     [VE_VIDEORAM] = 0x18000000,
 129     [VE_ETHERNET] = 0x1a000000,
 130     [VE_USB] = 0x1b000000,
 131     /* CS3: 0x1c000000 .. 0x20000000 */
 132     [VE_DAPROM] = 0x1c000000,
 133     [VE_SYSREGS] = 0x1c010000,
 134     [VE_SP810] = 0x1c020000,
 135     [VE_SERIALPCI] = 0x1c030000,
 136     [VE_PL041] = 0x1c040000,
 137     [VE_MMCI] = 0x1c050000,
 138     [VE_KMI0] = 0x1c060000,
 139     [VE_KMI1] = 0x1c070000,
 140     [VE_UART0] = 0x1c090000,
 141     [VE_UART1] = 0x1c0a0000,
 142     [VE_UART2] = 0x1c0b0000,
 143     [VE_UART3] = 0x1c0c0000,
 144     [VE_WDT] = 0x1c0f0000,
 145     [VE_TIMER01] = 0x1c110000,
 146     [VE_TIMER23] = 0x1c120000,
 147     [VE_VIRTIO] = 0x1c130000,
 148     [VE_SERIALDVI] = 0x1c160000,
 149     [VE_RTC] = 0x1c170000,
 150     [VE_COMPACTFLASH] = 0x1c1a0000,
 151     [VE_CLCD] = 0x1c1f0000,
 152 };
 153
 154 /* Structure defining the peculiarities of a specific daughterboard */
 155
 156 typedef struct VEDBoardInfo VEDBoardInfo;
 157
 158 typedef void DBoardInitFn(const VEDBoardInfo *daughterboard,
 159                           ram_addr_t ram_size,
 160                           const char *cpu_model,
 161                           qemu_irq *pic);
 162
 163 struct VEDBoardInfo {
 164     struct arm_boot_info bootinfo;
 165     const hwaddr *motherboard_map;
 166     hwaddr loader_start;
 167     const hwaddr gic_cpu_if_addr;
 168     uint32_t proc_id;
 169     uint32_t num_voltage_sensors;
 170     const uint32_t *voltages;
 171     uint32_t num_clocks;
 172     const uint32_t *clocks;
 173     DBoardInitFn *init;
 174 };
 175
 176 static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
 177                                   ram_addr_t ram_size,
 178                                   const char *cpu_model,
 179                                   qemu_irq *pic)
 180 {
 181     MemoryRegion *sysmem = get_system_memory();
 182     MemoryRegion *ram = g_new(MemoryRegion, 1);
 183     MemoryRegion *lowram = g_new(MemoryRegion, 1);
 184     DeviceState *dev;
 185     SysBusDevice *busdev;
 186     qemu_irq *irqp;
 187     int n;
 188     qemu_irq cpu_irq[4];
 189     ram_addr_t low_ram_size;
 190
 191     if (!cpu_model) {
 192         cpu_model = "cortex-a9";
 193     }
 194
 195     for (n = 0; n < smp_cpus; n++) {
 196         ARMCPU *cpu = cpu_arm_init(cpu_model);
 197         if (!cpu) {
 198             fprintf(stderr, "Unable to find CPU definition\n");
 199             exit(1);
 200         }
 201         irqp = arm_pic_init_cpu(cpu);
 202         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 203     }
 204
 205     if (ram_size > 0x40000000) {
 206         /* 1GB is the maximum the address space permits */
 207         fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
 208         exit(1);
 209     }
 210
 211     memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size);
 212     vmstate_register_ram_global(ram);
 213     low_ram_size = ram_size;
 214     if (low_ram_size > 0x4000000) {
 215         low_ram_size = 0x4000000;
 216     }
 217     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 218      * address space should in theory be remappable to various
 219      * things including ROM or RAM; we always map the RAM there.
 220      */
 221     memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size);
 222     memory_region_add_subregion(sysmem, 0x0, lowram);
 223     memory_region_add_subregion(sysmem, 0x60000000, ram);
 224
 225     /* 0x1e000000 A9MPCore (SCU) private memory region */
 226     dev = qdev_create(NULL, "a9mpcore_priv");
 227     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 228     qdev_init_nofail(dev);
 229     busdev = SYS_BUS_DEVICE(dev);
 230     sysbus_mmio_map(busdev, 0, 0x1e000000);
 231     for (n = 0; n < smp_cpus; n++) {
 232         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 233     }
 234     /* Interrupts [42:0] are from the motherboard;
 235      * [47:43] are reserved; [63:48] are daughterboard
 236      * peripherals. Note that some documentation numbers
 237      * external interrupts starting from 32 (because the
 238      * A9MP has internal interrupts 0..31).
 239      */
 240     for (n = 0; n < 64; n++) {
 241         pic[n] = qdev_get_gpio_in(dev, n);
 242     }
 243
 244     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 245
 246     /* 0x10020000 PL111 CLCD (daughterboard) */
 247     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 248
 249     /* 0x10060000 AXI RAM */
 250     /* 0x100e0000 PL341 Dynamic Memory Controller */
 251     /* 0x100e1000 PL354 Static Memory Controller */
 252     /* 0x100e2000 System Configuration Controller */
 253
 254     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 255     /* 0x100e5000 SP805 Watchdog module */
 256     /* 0x100e6000 BP147 TrustZone Protection Controller */
 257     /* 0x100e9000 PL301 'Fast' AXI matrix */
 258     /* 0x100ea000 PL301 'Slow' AXI matrix */
 259     /* 0x100ec000 TrustZone Address Space Controller */
 260     /* 0x10200000 CoreSight debug APB */
 261     /* 0x1e00a000 PL310 L2 Cache Controller */
 262     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 263 }
 264
 265 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
 266  * values are in microvolts.
 267  */
 268 static const uint32_t a9_voltages[] = {
 269     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
 270     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
 271     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
 272     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
 273     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
 274     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
 275 };
 276
 277 /* Reset values for daughterboard oscillators (in Hz) */
 278 static const uint32_t a9_clocks[] = {
 279     45000000, /* AMBA AXI ACLK: 45MHz */
 280     23750000, /* daughterboard CLCD clock: 23.75MHz */
 281     66670000, /* Test chip reference clock: 66.67MHz */
 282 };
 283
 284 static VEDBoardInfo a9_daughterboard = {
 285     .motherboard_map = motherboard_legacy_map,
 286     .loader_start = 0x60000000,
 287     .gic_cpu_if_addr = 0x1e000100,
 288     .proc_id = 0x0c000191,
 289     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
 290     .voltages = a9_voltages,
 291     .num_clocks = ARRAY_SIZE(a9_clocks),
 292     .clocks = a9_clocks,
 293     .init = a9_daughterboard_init,
 294 };
 295
 296 static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
 297                                    ram_addr_t ram_size,
 298                                    const char *cpu_model,
 299                                    qemu_irq *pic)
 300 {
 301     int n;
 302     MemoryRegion *sysmem = get_system_memory();
 303     MemoryRegion *ram = g_new(MemoryRegion, 1);
 304     MemoryRegion *sram = g_new(MemoryRegion, 1);
 305     qemu_irq cpu_irq[4];
 306     DeviceState *dev;
 307     SysBusDevice *busdev;
 308
 309     if (!cpu_model) {
 310         cpu_model = "cortex-a15";
 311     }
 312
 313     for (n = 0; n < smp_cpus; n++) {
 314         ARMCPU *cpu;
 315         qemu_irq *irqp;
 316
 317         cpu = cpu_arm_init(cpu_model);
 318         if (!cpu) {
 319             fprintf(stderr, "Unable to find CPU definition\n");
 320             exit(1);
 321         }
 322         irqp = arm_pic_init_cpu(cpu);
 323         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 324     }
 325
 326     {
 327         /* We have to use a separate 64 bit variable here to avoid the gcc
 328          * "comparison is always false due to limited range of data type"
 329          * warning if we are on a host where ram_addr_t is 32 bits.
 330          */
 331         uint64_t rsz = ram_size;
 332         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 333             fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
 334             exit(1);
 335         }
 336     }
 337
 338     memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size);
 339     vmstate_register_ram_global(ram);
 340     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 341     memory_region_add_subregion(sysmem, 0x80000000, ram);
 342
 343     /* 0x2c000000 A15MPCore private memory region (GIC) */
 344     dev = qdev_create(NULL, "a15mpcore_priv");
 345     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 346     qdev_init_nofail(dev);
 347     busdev = SYS_BUS_DEVICE(dev);
 348     sysbus_mmio_map(busdev, 0, 0x2c000000);
 349     for (n = 0; n < smp_cpus; n++) {
 350         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 351     }
 352     /* Interrupts [42:0] are from the motherboard;
 353      * [47:43] are reserved; [63:48] are daughterboard
 354      * peripherals. Note that some documentation numbers
 355      * external interrupts starting from 32 (because there
 356      * are internal interrupts 0..31).
 357      */
 358     for (n = 0; n < 64; n++) {
 359         pic[n] = qdev_get_gpio_in(dev, n);
 360     }
 361
 362     /* A15 daughterboard peripherals: */
 363
 364     /* 0x20000000: CoreSight interfaces: not modelled */
 365     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 366     /* 0x2a420000: SCC: not modelled */
 367     /* 0x2a430000: system counter: not modelled */
 368     /* 0x2b000000: HDLCD controller: not modelled */
 369     /* 0x2b060000: SP805 watchdog: not modelled */
 370     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 371     /* 0x2e000000: system SRAM */
 372     memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000);
 373     vmstate_register_ram_global(sram);
 374     memory_region_add_subregion(sysmem, 0x2e000000, sram);
 375
 376     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 377     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 378 }
 379
 380 static const uint32_t a15_voltages[] = {
 381     900000, /* Vcore: 0.9V : CPU core voltage */
 382 };
 383
 384 static const uint32_t a15_clocks[] = {
 385     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
 386     0, /* OSCCLK1: reserved */
 387     0, /* OSCCLK2: reserved */
 388     0, /* OSCCLK3: reserved */
 389     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
 390     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
 391     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
 392     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
 393     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
 394 };
 395
 396 static VEDBoardInfo a15_daughterboard = {
 397     .motherboard_map = motherboard_aseries_map,
 398     .loader_start = 0x80000000,
 399     .gic_cpu_if_addr = 0x2c002000,
 400     .proc_id = 0x14000237,
 401     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
 402     .voltages = a15_voltages,
 403     .num_clocks = ARRAY_SIZE(a15_clocks),
 404     .clocks = a15_clocks,
 405     .init = a15_daughterboard_init,
 406 };
 407
 408 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
 409                                 hwaddr addr, hwaddr size, uint32_t intc,
 410                                 int irq)
 411 {
 412     /* Add a virtio_mmio node to the device tree blob:
 413      *   virtio_mmio@ADDRESS {
 414      *       compatible = "virtio,mmio";
 415      *       reg = <ADDRESS, SIZE>;
 416      *       interrupt-parent = <&intc>;
 417      *       interrupts = <0, irq, 1>;
 418      *   }
 419      * (Note that the format of the interrupts property is dependent on the
 420      * interrupt controller that interrupt-parent points to; these are for
 421      * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
 422      */
 423     int rc;
 424     char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
 425
 426     rc = qemu_devtree_add_subnode(fdt, nodename);
 427     rc |= qemu_devtree_setprop_string(fdt, nodename,
 428                                       "compatible", "virtio,mmio");
 429     rc |= qemu_devtree_setprop_sized_cells(fdt, nodename, "reg",
 430                                            acells, addr, scells, size);
 431     qemu_devtree_setprop_cells(fdt, nodename, "interrupt-parent", intc);
 432     qemu_devtree_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
 433     g_free(nodename);
 434     if (rc) {
 435         return -1;
 436     }
 437     return 0;
 438 }
 439
 440 static uint32_t find_int_controller(void *fdt)
 441 {
 442     /* Find the FDT node corresponding to the interrupt controller
 443      * for virtio-mmio devices. We do this by scanning the fdt for
 444      * a node with the right compatibility, since we know there is
 445      * only one GIC on a vexpress board.
 446      * We return the phandle of the node, or 0 if none was found.
 447      */
 448     const char *compat = "arm,cortex-a9-gic";
 449     int offset;
 450
 451     offset = fdt_node_offset_by_compatible(fdt, -1, compat);
 452     if (offset >= 0) {
 453         return fdt_get_phandle(fdt, offset);
 454     }
 455     return 0;
 456 }
 457
 458 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
 459 {
 460     uint32_t acells, scells, intc;
 461     const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
 462
 463     acells = qemu_devtree_getprop_cell(fdt, "/", "#address-cells");
 464     scells = qemu_devtree_getprop_cell(fdt, "/", "#size-cells");
 465     intc = find_int_controller(fdt);
 466     if (!intc) {
 467         /* Not fatal, we just won't provide virtio. This will
 468          * happen with older device tree blobs.
 469          */
 470         fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in "
 471                 "dtb; will not include virtio-mmio devices in the dtb.\n");
 472     } else {
 473         int i;
 474         const hwaddr *map = daughterboard->motherboard_map;
 475
 476         /* We iterate backwards here because adding nodes
 477          * to the dtb puts them in last-first.
 478          */
 479         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 480             add_virtio_mmio_node(fdt, acells, scells,
 481                                  map[VE_VIRTIO] + 0x200 * i,
 482                                  0x200, intc, 40 + i);
 483         }
 484     }
 485 }
 486
 487 static void vexpress_common_init(VEDBoardInfo *daughterboard,
 488                                  QEMUMachineInitArgs *args)
 489 {
 490     DeviceState *dev, *sysctl, *pl041;
 491     qemu_irq pic[64];
 492     uint32_t sys_id;
 493     DriveInfo *dinfo;
 494     pflash_t *pflash0;
 495     ram_addr_t vram_size, sram_size;
 496     MemoryRegion *sysmem = get_system_memory();
 497     MemoryRegion *vram = g_new(MemoryRegion, 1);
 498     MemoryRegion *sram = g_new(MemoryRegion, 1);
 499     MemoryRegion *flashalias = g_new(MemoryRegion, 1);
 500     MemoryRegion *flash0mem;
 501     const hwaddr *map = daughterboard->motherboard_map;
 502     int i;
 503
 504     daughterboard->init(daughterboard, args->ram_size, args->cpu_model, pic);
 505
 506     /* Motherboard peripherals: the wiring is the same but the
 507      * addresses vary between the legacy and A-Series memory maps.
 508      */
 509
 510     sys_id = 0x1190f500;
 511
 512     sysctl = qdev_create(NULL, "realview_sysctl");
 513     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 514     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
 515     qdev_prop_set_uint32(sysctl, "len-db-voltage",
 516                          daughterboard->num_voltage_sensors);
 517     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
 518         char *propname = g_strdup_printf("db-voltage[%d]", i);
 519         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
 520         g_free(propname);
 521     }
 522     qdev_prop_set_uint32(sysctl, "len-db-clock",
 523                          daughterboard->num_clocks);
 524     for (i = 0; i < daughterboard->num_clocks; i++) {
 525         char *propname = g_strdup_printf("db-clock[%d]", i);
 526         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
 527         g_free(propname);
 528     }
 529     qdev_init_nofail(sysctl);
 530     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 531
 532     /* VE_SP810: not modelled */
 533     /* VE_SERIALPCI: not modelled */
 534
 535     pl041 = qdev_create(NULL, "pl041");
 536     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 537     qdev_init_nofail(pl041);
 538     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
 539     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
 540
 541     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 542     /* Wire up MMC card detect and read-only signals */
 543     qdev_connect_gpio_out(dev, 0,
 544                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 545     qdev_connect_gpio_out(dev, 1,
 546                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 547
 548     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 549     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 550
 551     sysbus_create_simple("pl011", map[VE_UART0], pic[5]);
 552     sysbus_create_simple("pl011", map[VE_UART1], pic[6]);
 553     sysbus_create_simple("pl011", map[VE_UART2], pic[7]);
 554     sysbus_create_simple("pl011", map[VE_UART3], pic[8]);
 555
 556     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 557     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 558
 559     /* VE_SERIALDVI: not modelled */
 560
 561     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 562
 563     /* VE_COMPACTFLASH: not modelled */
 564
 565     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 566
 567     dinfo = drive_get_next(IF_PFLASH);
 568     pflash0 = pflash_cfi01_register(map[VE_NORFLASH0], NULL, "vexpress.flash0",
 569             VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
 570             VEXPRESS_FLASH_SECT_SIZE,
 571             VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
 572             0x00, 0x89, 0x00, 0x18, 0);
 573     if (!pflash0) {
 574         fprintf(stderr, "vexpress: error registering flash 0.\n");
 575         exit(1);
 576     }
 577
 578     if (map[VE_NORFLASHALIAS] != -1) {
 579         /* Map flash 0 as an alias into low memory */
 580         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
 581         memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
 582                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);
 583         memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
 584     }
 585
 586     dinfo = drive_get_next(IF_PFLASH);
 587     if (!pflash_cfi01_register(map[VE_NORFLASH1], NULL, "vexpress.flash1",
 588             VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
 589             VEXPRESS_FLASH_SECT_SIZE,
 590             VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
 591             0x00, 0x89, 0x00, 0x18, 0)) {
 592         fprintf(stderr, "vexpress: error registering flash 1.\n");
 593         exit(1);
 594     }
 595
 596     sram_size = 0x2000000;
 597     memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size);
 598     vmstate_register_ram_global(sram);
 599     memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
 600
 601     vram_size = 0x800000;
 602     memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size);
 603     vmstate_register_ram_global(vram);
 604     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
 605
 606     /* 0x4e000000 LAN9118 Ethernet */
 607     if (nd_table[0].used) {
 608         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 609     }
 610
 611     /* VE_USB: not modelled */
 612
 613     /* VE_DAPROM: not modelled */
 614
 615     /* Create mmio transports, so the user can create virtio backends
 616      * (which will be automatically plugged in to the transports). If
 617      * no backend is created the transport will just sit harmlessly idle.
 618      */
 619     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 620         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
 621                              pic[40 + i]);
 622     }
 623
 624     daughterboard->bootinfo.ram_size = args->ram_size;
 625     daughterboard->bootinfo.kernel_filename = args->kernel_filename;
 626     daughterboard->bootinfo.kernel_cmdline = args->kernel_cmdline;
 627     daughterboard->bootinfo.initrd_filename = args->initrd_filename;
 628     daughterboard->bootinfo.nb_cpus = smp_cpus;
 629     daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
 630     daughterboard->bootinfo.loader_start = daughterboard->loader_start;
 631     daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
 632     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 633     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 634     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
 635     arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
 636 }
 637
 638 static void vexpress_a9_init(QEMUMachineInitArgs *args)
 639 {
 640     vexpress_common_init(&a9_daughterboard, args);
 641 }
 642
 643 static void vexpress_a15_init(QEMUMachineInitArgs *args)
 644 {
 645     vexpress_common_init(&a15_daughterboard, args);
 646 }
 647
 648 static QEMUMachine vexpress_a9_machine = {
 649     .name = "vexpress-a9",
 650     .desc = "ARM Versatile Express for Cortex-A9",
 651     .init = vexpress_a9_init,
 652     .block_default_type = IF_SCSI,
 653     .max_cpus = 4,
 654     DEFAULT_MACHINE_OPTIONS,
 655 };
 656
 657 static QEMUMachine vexpress_a15_machine = {
 658     .name = "vexpress-a15",
 659     .desc = "ARM Versatile Express for Cortex-A15",
 660     .init = vexpress_a15_init,
 661     .block_default_type = IF_SCSI,
 662     .max_cpus = 4,
 663     DEFAULT_MACHINE_OPTIONS,
 664 };
 665
 666 static void vexpress_machine_init(void)
 667 {
 668     qemu_register_machine(&vexpress_a9_machine);
 669     qemu_register_machine(&vexpress_a15_machine);
 670 }
 671
 672 machine_init(vexpress_machine_init);