2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu-common.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "qapi/error.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/sysemu.h"
48 #include "sysemu/kvm.h"
49 #include "hw/loader.h"
50 #include "exec/address-spaces.h"
51 #include "qemu/bitops.h"
52 #include "qemu/error-report.h"
53 #include "qemu/module.h"
54 #include "hw/pci-host/gpex.h"
55 #include "hw/arm/sysbus-fdt.h"
56 #include "hw/platform-bus.h"
57 #include "hw/arm/fdt.h"
58 #include "hw/intc/arm_gic.h"
59 #include "hw/intc/arm_gicv3_common.h"
61 #include "hw/firmware/smbios.h"
62 #include "qapi/visitor.h"
63 #include "standard-headers/linux/input.h"
64 #include "hw/arm/smmuv3.h"
65 #include "hw/acpi/acpi.h"
66 #include "target/arm/internals.h"
68 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
69 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
72 MachineClass *mc = MACHINE_CLASS(oc); \
73 virt_machine_##major##_##minor##_options(mc); \
74 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
79 static const TypeInfo machvirt_##major##_##minor##_info = { \
80 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
81 .parent = TYPE_VIRT_MACHINE, \
82 .class_init = virt_##major##_##minor##_class_init, \
84 static void machvirt_machine_##major##_##minor##_init(void) \
86 type_register_static(&machvirt_##major##_##minor##_info); \
88 type_init(machvirt_machine_##major##_##minor##_init);
90 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
91 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
92 #define DEFINE_VIRT_MACHINE(major, minor) \
93 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
96 /* Number of external interrupt lines to configure the GIC with */
99 #define PLATFORM_BUS_NUM_IRQS 64
101 /* Legacy RAM limit in GB (< version 4.0) */
102 #define LEGACY_RAMLIMIT_GB 255
103 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
105 /* Addresses and sizes of our components.
106 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
107 * 128MB..256MB is used for miscellaneous device I/O.
108 * 256MB..1GB is reserved for possible future PCI support (ie where the
109 * PCI memory window will go if we add a PCI host controller).
110 * 1GB and up is RAM (which may happily spill over into the
111 * high memory region beyond 4GB).
112 * This represents a compromise between how much RAM can be given to
113 * a 32 bit VM and leaving space for expansion and in particular for PCI.
114 * Note that devices should generally be placed at multiples of 0x10000,
115 * to accommodate guests using 64K pages.
117 static const MemMapEntry base_memmap
[] = {
118 /* Space up to 0x8000000 is reserved for a boot ROM */
119 [VIRT_FLASH
] = { 0, 0x08000000 },
120 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
121 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
122 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
123 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
124 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
125 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
126 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
127 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
128 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
129 /* This redistributor space allows up to 2*64kB*123 CPUs */
130 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
131 [VIRT_UART
] = { 0x09000000, 0x00001000 },
132 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
133 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
134 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
135 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
136 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
137 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
138 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
139 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
140 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
141 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
142 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
143 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
144 /* Actual RAM size depends on initial RAM and device memory settings */
145 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
149 * Highmem IO Regions: This memory map is floating, located after the RAM.
150 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
151 * top of the RAM, so that its base get the same alignment as the size,
152 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
153 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
154 * Note the extended_memmap is sized so that it eventually also includes the
155 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
156 * index of base_memmap).
158 static MemMapEntry extended_memmap
[] = {
159 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
160 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
161 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
162 /* Second PCIe window */
163 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
166 static const int a15irqmap
[] = {
169 [VIRT_PCIE
] = 3, /* ... to 6 */
171 [VIRT_SECURE_UART
] = 8,
172 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
173 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
174 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
175 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
178 static const char *valid_cpus
[] = {
179 ARM_CPU_TYPE_NAME("cortex-a7"),
180 ARM_CPU_TYPE_NAME("cortex-a15"),
181 ARM_CPU_TYPE_NAME("cortex-a53"),
182 ARM_CPU_TYPE_NAME("cortex-a57"),
183 ARM_CPU_TYPE_NAME("cortex-a72"),
184 ARM_CPU_TYPE_NAME("host"),
185 ARM_CPU_TYPE_NAME("max"),
188 static bool cpu_type_valid(const char *cpu
)
192 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
193 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
200 static void create_fdt(VirtMachineState
*vms
)
202 void *fdt
= create_device_tree(&vms
->fdt_size
);
205 error_report("create_device_tree() failed");
212 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
213 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
214 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
216 /* /chosen must exist for load_dtb to fill in necessary properties later */
217 qemu_fdt_add_subnode(fdt
, "/chosen");
219 /* Clock node, for the benefit of the UART. The kernel device tree
220 * binding documentation claims the PL011 node clock properties are
221 * optional but in practice if you omit them the kernel refuses to
222 * probe for the device.
224 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
225 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
226 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
227 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
228 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
229 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
231 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
233 if (have_numa_distance
) {
234 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
235 uint32_t *matrix
= g_malloc0(size
);
238 for (i
= 0; i
< nb_numa_nodes
; i
++) {
239 for (j
= 0; j
< nb_numa_nodes
; j
++) {
240 idx
= (i
* nb_numa_nodes
+ j
) * 3;
241 matrix
[idx
+ 0] = cpu_to_be32(i
);
242 matrix
[idx
+ 1] = cpu_to_be32(j
);
243 matrix
[idx
+ 2] = cpu_to_be32(numa_info
[i
].distance
[j
]);
247 qemu_fdt_add_subnode(fdt
, "/distance-map");
248 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
249 "numa-distance-map-v1");
250 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
256 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
258 /* On real hardware these interrupts are level-triggered.
259 * On KVM they were edge-triggered before host kernel version 4.4,
260 * and level-triggered afterwards.
261 * On emulated QEMU they are level-triggered.
263 * Getting the DTB info about them wrong is awkward for some
265 * pre-4.8 ignore the DT and leave the interrupt configured
266 * with whatever the GIC reset value (or the bootloader) left it at
267 * 4.8 before rc6 honour the incorrect data by programming it back
268 * into the GIC, causing problems
269 * 4.8rc6 and later ignore the DT and always write "level triggered"
272 * For backwards-compatibility, virt-2.8 and earlier will continue
273 * to say these are edge-triggered, but later machines will report
274 * the correct information.
277 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
278 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
280 if (vmc
->claim_edge_triggered_timers
) {
281 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
284 if (vms
->gic_version
== 2) {
285 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
286 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
287 (1 << vms
->smp_cpus
) - 1);
290 qemu_fdt_add_subnode(vms
->fdt
, "/timer");
292 armcpu
= ARM_CPU(qemu_get_cpu(0));
293 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
294 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
295 qemu_fdt_setprop(vms
->fdt
, "/timer", "compatible",
296 compat
, sizeof(compat
));
298 qemu_fdt_setprop_string(vms
->fdt
, "/timer", "compatible",
301 qemu_fdt_setprop(vms
->fdt
, "/timer", "always-on", NULL
, 0);
302 qemu_fdt_setprop_cells(vms
->fdt
, "/timer", "interrupts",
303 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
304 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
305 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
306 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
309 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
313 const MachineState
*ms
= MACHINE(vms
);
316 * From Documentation/devicetree/bindings/arm/cpus.txt
317 * On ARM v8 64-bit systems value should be set to 2,
318 * that corresponds to the MPIDR_EL1 register size.
319 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
320 * in the system, #address-cells can be set to 1, since
321 * MPIDR_EL1[63:32] bits are not used for CPUs
324 * Here we actually don't know whether our system is 32- or 64-bit one.
325 * The simplest way to go is to examine affinity IDs of all our CPUs. If
326 * at least one of them has Aff3 populated, we set #address-cells to 2.
328 for (cpu
= 0; cpu
< vms
->smp_cpus
; cpu
++) {
329 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
331 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
337 qemu_fdt_add_subnode(vms
->fdt
, "/cpus");
338 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#address-cells", addr_cells
);
339 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#size-cells", 0x0);
341 for (cpu
= vms
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
342 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
343 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
344 CPUState
*cs
= CPU(armcpu
);
346 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
347 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "cpu");
348 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
349 armcpu
->dtb_compatible
);
351 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
352 && vms
->smp_cpus
> 1) {
353 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
354 "enable-method", "psci");
357 if (addr_cells
== 2) {
358 qemu_fdt_setprop_u64(vms
->fdt
, nodename
, "reg",
359 armcpu
->mp_affinity
);
361 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "reg",
362 armcpu
->mp_affinity
);
365 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
366 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "numa-node-id",
367 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
374 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
378 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
379 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
380 vms
->memmap
[VIRT_GIC_ITS
].base
);
381 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
382 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
384 qemu_fdt_setprop(vms
->fdt
, nodename
, "msi-controller", NULL
, 0);
385 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
386 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
387 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
388 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
392 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
396 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
397 vms
->memmap
[VIRT_GIC_V2M
].base
);
398 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
399 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
400 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
401 "arm,gic-v2m-frame");
402 qemu_fdt_setprop(vms
->fdt
, nodename
, "msi-controller", NULL
, 0);
403 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
404 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
405 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
406 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
410 static void fdt_add_gic_node(VirtMachineState
*vms
)
414 vms
->gic_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
415 qemu_fdt_setprop_cell(vms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
417 nodename
= g_strdup_printf("/intc@%" PRIx64
,
418 vms
->memmap
[VIRT_GIC_DIST
].base
);
419 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
420 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 3);
421 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
422 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 0x2);
423 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 0x2);
424 qemu_fdt_setprop(vms
->fdt
, nodename
, "ranges", NULL
, 0);
425 if (vms
->gic_version
== 3) {
426 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
428 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
431 qemu_fdt_setprop_cell(vms
->fdt
, nodename
,
432 "#redistributor-regions", nb_redist_regions
);
434 if (nb_redist_regions
== 1) {
435 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
436 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
437 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
438 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
439 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
441 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
442 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
443 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
444 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
445 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
446 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
447 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
451 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
452 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
453 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
456 /* 'cortex-a15-gic' means 'GIC v2' */
457 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
458 "arm,cortex-a15-gic");
460 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
461 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
462 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
463 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
464 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
466 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
467 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
468 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
469 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
470 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
471 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
472 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
473 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
474 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
475 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
476 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
477 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
481 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
485 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
489 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
492 armcpu
= ARM_CPU(cpu
);
493 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
497 if (kvm_irqchip_in_kernel()) {
498 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
500 kvm_arm_pmu_init(cpu
);
504 if (vms
->gic_version
== 2) {
505 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
506 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
507 (1 << vms
->smp_cpus
) - 1);
510 armcpu
= ARM_CPU(qemu_get_cpu(0));
511 qemu_fdt_add_subnode(vms
->fdt
, "/pmu");
512 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
513 const char compat
[] = "arm,armv8-pmuv3";
514 qemu_fdt_setprop(vms
->fdt
, "/pmu", "compatible",
515 compat
, sizeof(compat
));
516 qemu_fdt_setprop_cells(vms
->fdt
, "/pmu", "interrupts",
517 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
521 static void create_its(VirtMachineState
*vms
, DeviceState
*gicdev
)
523 const char *itsclass
= its_class_name();
527 /* Do nothing if not supported */
531 dev
= qdev_create(NULL
, itsclass
);
533 object_property_set_link(OBJECT(dev
), OBJECT(gicdev
), "parent-gicv3",
535 qdev_init_nofail(dev
);
536 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
538 fdt_add_its_gic_node(vms
);
541 static void create_v2m(VirtMachineState
*vms
, qemu_irq
*pic
)
544 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
547 dev
= qdev_create(NULL
, "arm-gicv2m");
548 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
549 qdev_prop_set_uint32(dev
, "base-spi", irq
);
550 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
551 qdev_init_nofail(dev
);
553 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
554 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
557 fdt_add_v2m_gic_node(vms
);
560 static void create_gic(VirtMachineState
*vms
, qemu_irq
*pic
)
562 MachineState
*ms
= MACHINE(vms
);
563 /* We create a standalone GIC */
565 SysBusDevice
*gicbusdev
;
567 int type
= vms
->gic_version
, i
;
568 unsigned int smp_cpus
= ms
->smp
.cpus
;
569 uint32_t nb_redist_regions
= 0;
571 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
573 gicdev
= qdev_create(NULL
, gictype
);
574 qdev_prop_set_uint32(gicdev
, "revision", type
);
575 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
576 /* Note that the num-irq property counts both internal and external
577 * interrupts; there are always 32 of the former (mandated by GIC spec).
579 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
580 if (!kvm_irqchip_in_kernel()) {
581 qdev_prop_set_bit(gicdev
, "has-security-extensions", vms
->secure
);
585 uint32_t redist0_capacity
=
586 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
587 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
589 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
591 qdev_prop_set_uint32(gicdev
, "len-redist-region-count",
593 qdev_prop_set_uint32(gicdev
, "redist-region-count[0]", redist0_count
);
595 if (nb_redist_regions
== 2) {
596 uint32_t redist1_capacity
=
597 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
599 qdev_prop_set_uint32(gicdev
, "redist-region-count[1]",
600 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
603 if (!kvm_irqchip_in_kernel()) {
604 qdev_prop_set_bit(gicdev
, "has-virtualization-extensions",
608 qdev_init_nofail(gicdev
);
609 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
610 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
612 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
613 if (nb_redist_regions
== 2) {
614 sysbus_mmio_map(gicbusdev
, 2,
615 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
618 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
620 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
621 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
625 /* Wire the outputs from each CPU's generic timer and the GICv3
626 * maintenance interrupt signal to the appropriate GIC PPI inputs,
627 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
629 for (i
= 0; i
< smp_cpus
; i
++) {
630 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
631 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
633 /* Mapping from the output timer irq lines from the CPU to the
634 * GIC PPI inputs we use for the virt board.
636 const int timer_irq
[] = {
637 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
638 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
639 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
640 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
643 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
644 qdev_connect_gpio_out(cpudev
, irq
,
645 qdev_get_gpio_in(gicdev
,
646 ppibase
+ timer_irq
[irq
]));
650 qemu_irq irq
= qdev_get_gpio_in(gicdev
,
651 ppibase
+ ARCH_GIC_MAINT_IRQ
);
652 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
654 } else if (vms
->virt
) {
655 qemu_irq irq
= qdev_get_gpio_in(gicdev
,
656 ppibase
+ ARCH_GIC_MAINT_IRQ
);
657 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
660 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
661 qdev_get_gpio_in(gicdev
, ppibase
664 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
665 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
666 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
667 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
668 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
669 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
670 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
673 for (i
= 0; i
< NUM_IRQS
; i
++) {
674 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
677 fdt_add_gic_node(vms
);
679 if (type
== 3 && vms
->its
) {
680 create_its(vms
, gicdev
);
681 } else if (type
== 2) {
682 create_v2m(vms
, pic
);
686 static void create_uart(const VirtMachineState
*vms
, qemu_irq
*pic
, int uart
,
687 MemoryRegion
*mem
, Chardev
*chr
)
690 hwaddr base
= vms
->memmap
[uart
].base
;
691 hwaddr size
= vms
->memmap
[uart
].size
;
692 int irq
= vms
->irqmap
[uart
];
693 const char compat
[] = "arm,pl011\0arm,primecell";
694 const char clocknames
[] = "uartclk\0apb_pclk";
695 DeviceState
*dev
= qdev_create(NULL
, "pl011");
696 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
698 qdev_prop_set_chr(dev
, "chardev", chr
);
699 qdev_init_nofail(dev
);
700 memory_region_add_subregion(mem
, base
,
701 sysbus_mmio_get_region(s
, 0));
702 sysbus_connect_irq(s
, 0, pic
[irq
]);
704 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
705 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
706 /* Note that we can't use setprop_string because of the embedded NUL */
707 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible",
708 compat
, sizeof(compat
));
709 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
711 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
712 GIC_FDT_IRQ_TYPE_SPI
, irq
,
713 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
714 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "clocks",
715 vms
->clock_phandle
, vms
->clock_phandle
);
716 qemu_fdt_setprop(vms
->fdt
, nodename
, "clock-names",
717 clocknames
, sizeof(clocknames
));
719 if (uart
== VIRT_UART
) {
720 qemu_fdt_setprop_string(vms
->fdt
, "/chosen", "stdout-path", nodename
);
722 /* Mark as not usable by the normal world */
723 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
724 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
726 qemu_fdt_add_subnode(vms
->fdt
, "/secure-chosen");
727 qemu_fdt_setprop_string(vms
->fdt
, "/secure-chosen", "stdout-path",
734 static void create_rtc(const VirtMachineState
*vms
, qemu_irq
*pic
)
737 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
738 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
739 int irq
= vms
->irqmap
[VIRT_RTC
];
740 const char compat
[] = "arm,pl031\0arm,primecell";
742 sysbus_create_simple("pl031", base
, pic
[irq
]);
744 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
745 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
746 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
747 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
749 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
750 GIC_FDT_IRQ_TYPE_SPI
, irq
,
751 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
752 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
753 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
757 static DeviceState
*gpio_key_dev
;
758 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
760 /* use gpio Pin 3 for power button event */
761 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
764 static Notifier virt_system_powerdown_notifier
= {
765 .notify
= virt_powerdown_req
768 static void create_gpio(const VirtMachineState
*vms
, qemu_irq
*pic
)
771 DeviceState
*pl061_dev
;
772 hwaddr base
= vms
->memmap
[VIRT_GPIO
].base
;
773 hwaddr size
= vms
->memmap
[VIRT_GPIO
].size
;
774 int irq
= vms
->irqmap
[VIRT_GPIO
];
775 const char compat
[] = "arm,pl061\0arm,primecell";
777 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
779 uint32_t phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
780 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
781 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
782 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
784 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
785 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#gpio-cells", 2);
786 qemu_fdt_setprop(vms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
787 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
788 GIC_FDT_IRQ_TYPE_SPI
, irq
,
789 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
790 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
791 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
792 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", phandle
);
794 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
795 qdev_get_gpio_in(pl061_dev
, 3));
796 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys");
797 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
798 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#size-cells", 0);
799 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#address-cells", 1);
801 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys/poweroff");
802 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys/poweroff",
803 "label", "GPIO Key Poweroff");
804 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys/poweroff", "linux,code",
806 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-keys/poweroff",
807 "gpios", phandle
, 3, 0);
809 /* connect powerdown request */
810 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
815 static void create_virtio_devices(const VirtMachineState
*vms
, qemu_irq
*pic
)
818 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
820 /* We create the transports in forwards order. Since qbus_realize()
821 * prepends (not appends) new child buses, the incrementing loop below will
822 * create a list of virtio-mmio buses with decreasing base addresses.
824 * When a -device option is processed from the command line,
825 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
826 * order. The upshot is that -device options in increasing command line
827 * order are mapped to virtio-mmio buses with decreasing base addresses.
829 * When this code was originally written, that arrangement ensured that the
830 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
831 * the first -device on the command line. (The end-to-end order is a
832 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
833 * guest kernel's name-to-address assignment strategy.)
835 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
836 * the message, if not necessarily the code, of commit 70161ff336.
837 * Therefore the loop now establishes the inverse of the original intent.
839 * Unfortunately, we can't counteract the kernel change by reversing the
840 * loop; it would break existing command lines.
842 * In any case, the kernel makes no guarantee about the stability of
843 * enumeration order of virtio devices (as demonstrated by it changing
844 * between kernel versions). For reliable and stable identification
845 * of disks users must use UUIDs or similar mechanisms.
847 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
848 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
849 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
851 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
854 /* We add dtb nodes in reverse order so that they appear in the finished
855 * device tree lowest address first.
857 * Note that this mapping is independent of the loop above. The previous
858 * loop influences virtio device to virtio transport assignment, whereas
859 * this loop controls how virtio transports are laid out in the dtb.
861 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
863 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
864 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
866 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
867 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
868 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
869 "compatible", "virtio,mmio");
870 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
872 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
873 GIC_FDT_IRQ_TYPE_SPI
, irq
,
874 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
875 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
880 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
882 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
884 const char *alias_prop_name
)
887 * Create a single flash device. We use the same parameters as
888 * the flash devices on the Versatile Express board.
890 DeviceState
*dev
= qdev_create(NULL
, TYPE_PFLASH_CFI01
);
892 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
893 qdev_prop_set_uint8(dev
, "width", 4);
894 qdev_prop_set_uint8(dev
, "device-width", 2);
895 qdev_prop_set_bit(dev
, "big-endian", false);
896 qdev_prop_set_uint16(dev
, "id0", 0x89);
897 qdev_prop_set_uint16(dev
, "id1", 0x18);
898 qdev_prop_set_uint16(dev
, "id2", 0x00);
899 qdev_prop_set_uint16(dev
, "id3", 0x00);
900 qdev_prop_set_string(dev
, "name", name
);
901 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
),
903 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
904 OBJECT(dev
), "drive", &error_abort
);
905 return PFLASH_CFI01(dev
);
908 static void virt_flash_create(VirtMachineState
*vms
)
910 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
911 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
914 static void virt_flash_map1(PFlashCFI01
*flash
,
915 hwaddr base
, hwaddr size
,
916 MemoryRegion
*sysmem
)
918 DeviceState
*dev
= DEVICE(flash
);
920 assert(size
% VIRT_FLASH_SECTOR_SIZE
== 0);
921 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
922 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
923 qdev_init_nofail(dev
);
925 memory_region_add_subregion(sysmem
, base
,
926 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
930 static void virt_flash_map(VirtMachineState
*vms
,
931 MemoryRegion
*sysmem
,
932 MemoryRegion
*secure_sysmem
)
935 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
936 * sysmem is the system memory space. secure_sysmem is the secure view
937 * of the system, and the first flash device should be made visible only
938 * there. The second flash device is visible to both secure and nonsecure.
939 * If sysmem == secure_sysmem this means there is no separate Secure
940 * address space and both flash devices are generally visible.
942 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
943 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
945 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
947 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
951 static void virt_flash_fdt(VirtMachineState
*vms
,
952 MemoryRegion
*sysmem
,
953 MemoryRegion
*secure_sysmem
)
955 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
956 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
959 if (sysmem
== secure_sysmem
) {
960 /* Report both flash devices as a single node in the DT */
961 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
962 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
963 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
964 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
965 2, flashbase
, 2, flashsize
,
966 2, flashbase
+ flashsize
, 2, flashsize
);
967 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
971 * Report the devices as separate nodes so we can mark one as
972 * only visible to the secure world.
974 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
975 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
976 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
977 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
978 2, flashbase
, 2, flashsize
);
979 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
980 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
981 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
984 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
985 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
986 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
987 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
988 2, flashbase
+ flashsize
, 2, flashsize
);
989 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
994 static bool virt_firmware_init(VirtMachineState
*vms
,
995 MemoryRegion
*sysmem
,
996 MemoryRegion
*secure_sysmem
)
999 BlockBackend
*pflash_blk0
;
1001 /* Map legacy -drive if=pflash to machine properties */
1002 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1003 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1004 drive_get(IF_PFLASH
, 0, i
));
1007 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1009 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1017 error_report("The contents of the first flash device may be "
1018 "specified with -bios or with -drive if=pflash... "
1019 "but you cannot use both options at once");
1023 /* Fall back to -bios */
1025 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1027 error_report("Could not find ROM image '%s'", bios_name
);
1030 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1031 image_size
= load_image_mr(fname
, mr
);
1033 if (image_size
< 0) {
1034 error_report("Could not load ROM image '%s'", bios_name
);
1039 return pflash_blk0
|| bios_name
;
1042 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1044 MachineState
*ms
= MACHINE(vms
);
1045 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1046 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1050 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1051 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1053 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1054 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1055 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1056 "compatible", "qemu,fw-cfg-mmio");
1057 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1059 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1064 static void create_pcie_irq_map(const VirtMachineState
*vms
,
1065 uint32_t gic_phandle
,
1066 int first_irq
, const char *nodename
)
1069 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1070 uint32_t *irq_map
= full_irq_map
;
1072 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1073 for (pin
= 0; pin
< 4; pin
++) {
1074 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1075 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1076 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1080 devfn
<< 8, 0, 0, /* devfn */
1081 pin
+ 1, /* PCI pin */
1082 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1084 /* Convert map to big endian */
1085 for (i
= 0; i
< 10; i
++) {
1086 irq_map
[i
] = cpu_to_be32(map
[i
]);
1092 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-map",
1093 full_irq_map
, sizeof(full_irq_map
));
1095 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupt-map-mask",
1096 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
1100 static void create_smmu(const VirtMachineState
*vms
, qemu_irq
*pic
,
1104 const char compat
[] = "arm,smmu-v3";
1105 int irq
= vms
->irqmap
[VIRT_SMMU
];
1107 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1108 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1109 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1112 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1116 dev
= qdev_create(NULL
, "arm-smmuv3");
1118 object_property_set_link(OBJECT(dev
), OBJECT(bus
), "primary-bus",
1120 qdev_init_nofail(dev
);
1121 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1122 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1123 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1126 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1127 qemu_fdt_add_subnode(vms
->fdt
, node
);
1128 qemu_fdt_setprop(vms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1129 qemu_fdt_setprop_sized_cells(vms
->fdt
, node
, "reg", 2, base
, 2, size
);
1131 qemu_fdt_setprop_cells(vms
->fdt
, node
, "interrupts",
1132 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1133 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1134 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1135 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1137 qemu_fdt_setprop(vms
->fdt
, node
, "interrupt-names", irq_names
,
1140 qemu_fdt_setprop_cell(vms
->fdt
, node
, "clocks", vms
->clock_phandle
);
1141 qemu_fdt_setprop_string(vms
->fdt
, node
, "clock-names", "apb_pclk");
1142 qemu_fdt_setprop(vms
->fdt
, node
, "dma-coherent", NULL
, 0);
1144 qemu_fdt_setprop_cell(vms
->fdt
, node
, "#iommu-cells", 1);
1146 qemu_fdt_setprop_cell(vms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1150 static void create_pcie(VirtMachineState
*vms
, qemu_irq
*pic
)
1152 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1153 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1154 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1155 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1156 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1157 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1158 hwaddr base_ecam
, size_ecam
;
1159 hwaddr base
= base_mmio
;
1161 int irq
= vms
->irqmap
[VIRT_PCIE
];
1162 MemoryRegion
*mmio_alias
;
1163 MemoryRegion
*mmio_reg
;
1164 MemoryRegion
*ecam_alias
;
1165 MemoryRegion
*ecam_reg
;
1171 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
1172 qdev_init_nofail(dev
);
1174 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1175 base_ecam
= vms
->memmap
[ecam_id
].base
;
1176 size_ecam
= vms
->memmap
[ecam_id
].size
;
1177 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1178 /* Map only the first size_ecam bytes of ECAM space */
1179 ecam_alias
= g_new0(MemoryRegion
, 1);
1180 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1181 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1182 ecam_reg
, 0, size_ecam
);
1183 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1185 /* Map the MMIO window into system address space so as to expose
1186 * the section of PCI MMIO space which starts at the same base address
1187 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1190 mmio_alias
= g_new0(MemoryRegion
, 1);
1191 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1192 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1193 mmio_reg
, base_mmio
, size_mmio
);
1194 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1197 /* Map high MMIO space */
1198 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1200 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1201 mmio_reg
, base_mmio_high
, size_mmio_high
);
1202 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1206 /* Map IO port space */
1207 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1209 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1210 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1211 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1214 pci
= PCI_HOST_BRIDGE(dev
);
1216 for (i
= 0; i
< nb_nics
; i
++) {
1217 NICInfo
*nd
= &nd_table
[i
];
1220 nd
->model
= g_strdup("virtio");
1223 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1227 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1228 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1229 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1230 "compatible", "pci-host-ecam-generic");
1231 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "pci");
1232 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 3);
1233 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 2);
1234 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "linux,pci-domain", 0);
1235 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "bus-range", 0,
1237 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1239 if (vms
->msi_phandle
) {
1240 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "msi-parent",
1244 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1245 2, base_ecam
, 2, size_ecam
);
1248 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1249 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1250 2, base_pio
, 2, size_pio
,
1251 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1252 2, base_mmio
, 2, size_mmio
,
1253 1, FDT_PCI_RANGE_MMIO_64BIT
,
1255 2, base_mmio_high
, 2, size_mmio_high
);
1257 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1258 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1259 2, base_pio
, 2, size_pio
,
1260 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1261 2, base_mmio
, 2, size_mmio
);
1264 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 1);
1265 create_pcie_irq_map(vms
, vms
->gic_phandle
, irq
, nodename
);
1268 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
1270 create_smmu(vms
, pic
, pci
->bus
);
1272 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "iommu-map",
1273 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1279 static void create_platform_bus(VirtMachineState
*vms
, qemu_irq
*pic
)
1284 MemoryRegion
*sysmem
= get_system_memory();
1286 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1287 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1288 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1289 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1290 qdev_init_nofail(dev
);
1291 vms
->platform_bus_dev
= dev
;
1293 s
= SYS_BUS_DEVICE(dev
);
1294 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1295 int irqn
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1296 sysbus_connect_irq(s
, i
, pic
[irqn
]);
1299 memory_region_add_subregion(sysmem
,
1300 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1301 sysbus_mmio_get_region(s
, 0));
1304 static void create_secure_ram(VirtMachineState
*vms
,
1305 MemoryRegion
*secure_sysmem
)
1307 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1309 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1310 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1312 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1314 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1316 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1317 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1318 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "memory");
1319 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1320 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1321 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1326 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1328 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1331 *fdt_size
= board
->fdt_size
;
1335 static void virt_build_smbios(VirtMachineState
*vms
)
1337 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1338 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1339 uint8_t *smbios_tables
, *smbios_anchor
;
1340 size_t smbios_tables_len
, smbios_anchor_len
;
1341 const char *product
= "QEMU Virtual Machine";
1343 if (kvm_enabled()) {
1344 product
= "KVM Virtual Machine";
1347 smbios_set_defaults("QEMU", product
,
1348 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1349 true, SMBIOS_ENTRY_POINT_30
);
1351 smbios_get_tables(MACHINE(vms
), NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1352 &smbios_anchor
, &smbios_anchor_len
);
1354 if (smbios_anchor
) {
1355 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1356 smbios_tables
, smbios_tables_len
);
1357 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1358 smbios_anchor
, smbios_anchor_len
);
1363 void virt_machine_done(Notifier
*notifier
, void *data
)
1365 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1367 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1368 struct arm_boot_info
*info
= &vms
->bootinfo
;
1369 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1372 * If the user provided a dtb, we assume the dynamic sysbus nodes
1373 * already are integrated there. This corresponds to a use case where
1374 * the dynamic sysbus nodes are complex and their generation is not yet
1375 * supported. In that case the user can take charge of the guest dt
1376 * while qemu takes charge of the qom stuff.
1378 if (info
->dtb_filename
== NULL
) {
1379 platform_bus_add_all_fdt_nodes(vms
->fdt
, "/intc",
1380 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1381 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1382 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1384 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
) < 0) {
1388 virt_acpi_setup(vms
);
1389 virt_build_smbios(vms
);
1392 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1394 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1395 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1397 if (!vmc
->disallow_affinity_adjustment
) {
1398 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1399 * GIC's target-list limitations. 32-bit KVM hosts currently
1400 * always create clusters of 4 CPUs, but that is expected to
1401 * change when they gain support for gicv3. When KVM is enabled
1402 * it will override the changes we make here, therefore our
1403 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1404 * and to improve SGI efficiency.
1406 if (vms
->gic_version
== 3) {
1407 clustersz
= GICV3_TARGETLIST_BITS
;
1409 clustersz
= GIC_TARGETLIST_BITS
;
1412 return arm_cpu_mp_affinity(idx
, clustersz
);
1415 static void virt_set_memmap(VirtMachineState
*vms
)
1417 MachineState
*ms
= MACHINE(vms
);
1418 hwaddr base
, device_memory_base
, device_memory_size
;
1421 vms
->memmap
= extended_memmap
;
1423 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1424 vms
->memmap
[i
] = base_memmap
[i
];
1427 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1428 error_report("unsupported number of memory slots: %"PRIu64
,
1434 * We compute the base of the high IO region depending on the
1435 * amount of initial and device memory. The device memory start/size
1436 * is aligned on 1GiB. We never put the high IO region below 256GiB
1437 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1438 * The device region size assumes 1GiB page max alignment per slot.
1440 device_memory_base
=
1441 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1442 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1444 /* Base address of the high IO region */
1445 base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1446 if (base
< device_memory_base
) {
1447 error_report("maxmem/slots too huge");
1450 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1451 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1454 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1455 hwaddr size
= extended_memmap
[i
].size
;
1457 base
= ROUND_UP(base
, size
);
1458 vms
->memmap
[i
].base
= base
;
1459 vms
->memmap
[i
].size
= size
;
1462 vms
->highest_gpa
= base
- 1;
1463 if (device_memory_size
> 0) {
1464 ms
->device_memory
= g_malloc0(sizeof(*ms
->device_memory
));
1465 ms
->device_memory
->base
= device_memory_base
;
1466 memory_region_init(&ms
->device_memory
->mr
, OBJECT(vms
),
1467 "device-memory", device_memory_size
);
1471 static void machvirt_init(MachineState
*machine
)
1473 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1474 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1475 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1476 const CPUArchIdList
*possible_cpus
;
1477 qemu_irq pic
[NUM_IRQS
];
1478 MemoryRegion
*sysmem
= get_system_memory();
1479 MemoryRegion
*secure_sysmem
= NULL
;
1480 int n
, virt_max_cpus
;
1481 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1482 bool firmware_loaded
;
1483 bool aarch64
= true;
1484 unsigned int smp_cpus
= machine
->smp
.cpus
;
1485 unsigned int max_cpus
= machine
->smp
.max_cpus
;
1488 * In accelerated mode, the memory map is computed earlier in kvm_type()
1489 * to create a VM with the right number of IPA bits.
1492 virt_set_memmap(vms
);
1495 /* We can probe only here because during property set
1496 * KVM is not available yet
1498 if (vms
->gic_version
<= 0) {
1499 /* "host" or "max" */
1500 if (!kvm_enabled()) {
1501 if (vms
->gic_version
== 0) {
1502 error_report("gic-version=host requires KVM");
1505 /* "max": currently means 3 for TCG */
1506 vms
->gic_version
= 3;
1509 vms
->gic_version
= kvm_arm_vgic_probe();
1510 if (!vms
->gic_version
) {
1512 "Unable to determine GIC version supported by host");
1518 if (!cpu_type_valid(machine
->cpu_type
)) {
1519 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
1524 if (kvm_enabled()) {
1525 error_report("mach-virt: KVM does not support Security extensions");
1530 * The Secure view of the world is the same as the NonSecure,
1531 * but with a few extra devices. Create it as a container region
1532 * containing the system memory at low priority; any secure-only
1533 * devices go in at higher priority and take precedence.
1535 secure_sysmem
= g_new(MemoryRegion
, 1);
1536 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1538 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1541 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
1542 secure_sysmem
?: sysmem
);
1544 /* If we have an EL3 boot ROM then the assumption is that it will
1545 * implement PSCI itself, so disable QEMU's internal implementation
1546 * so it doesn't get in the way. Instead of starting secondary
1547 * CPUs in PSCI powerdown state we will start them all running and
1548 * let the boot ROM sort them out.
1549 * The usual case is that we do use QEMU's PSCI implementation;
1550 * if the guest has EL2 then we will use SMC as the conduit,
1551 * and otherwise we will use HVC (for backwards compatibility and
1552 * because if we're using KVM then we must use HVC).
1554 if (vms
->secure
&& firmware_loaded
) {
1555 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
1556 } else if (vms
->virt
) {
1557 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
1559 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
1562 /* The maximum number of CPUs depends on the GIC version, or on how
1563 * many redistributors we can fit into the memory map.
1565 if (vms
->gic_version
== 3) {
1567 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
1569 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
1571 virt_max_cpus
= GIC_NCPU
;
1574 if (max_cpus
> virt_max_cpus
) {
1575 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1576 "supported by machine 'mach-virt' (%d)",
1577 max_cpus
, virt_max_cpus
);
1581 vms
->smp_cpus
= smp_cpus
;
1583 if (vms
->virt
&& kvm_enabled()) {
1584 error_report("mach-virt: KVM does not support providing "
1585 "Virtualization extensions to the guest CPU");
1591 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1592 for (n
= 0; n
< possible_cpus
->len
; n
++) {
1596 if (n
>= smp_cpus
) {
1600 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
1601 object_property_set_int(cpuobj
, possible_cpus
->cpus
[n
].arch_id
,
1602 "mp-affinity", NULL
);
1607 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
1610 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
1613 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1616 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2", NULL
)) {
1617 object_property_set_bool(cpuobj
, false, "has_el2", NULL
);
1620 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
) {
1621 object_property_set_int(cpuobj
, vms
->psci_conduit
,
1622 "psci-conduit", NULL
);
1624 /* Secondary CPUs start in PSCI powered-down state */
1626 object_property_set_bool(cpuobj
, true,
1627 "start-powered-off", NULL
);
1631 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu", NULL
)) {
1632 object_property_set_bool(cpuobj
, false, "pmu", NULL
);
1635 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1636 object_property_set_int(cpuobj
, vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1637 "reset-cbar", &error_abort
);
1640 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1643 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1644 "secure-memory", &error_abort
);
1647 object_property_set_bool(cpuobj
, true, "realized", &error_fatal
);
1648 object_unref(cpuobj
);
1650 fdt_add_timer_nodes(vms
);
1651 fdt_add_cpu_nodes(vms
);
1653 if (!kvm_enabled()) {
1654 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1655 bool aarch64
= object_property_get_bool(OBJECT(cpu
), "aarch64", NULL
);
1657 if (aarch64
&& vms
->highmem
) {
1658 int requested_pa_size
, pamax
= arm_pamax(cpu
);
1660 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1661 if (pamax
< requested_pa_size
) {
1662 error_report("VCPU supports less PA bits (%d) than requested "
1663 "by the memory map (%d)", pamax
, requested_pa_size
);
1669 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1671 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
, ram
);
1672 if (machine
->device_memory
) {
1673 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
1674 &machine
->device_memory
->mr
);
1677 virt_flash_fdt(vms
, sysmem
, secure_sysmem
);
1679 create_gic(vms
, pic
);
1681 fdt_add_pmu_nodes(vms
);
1683 create_uart(vms
, pic
, VIRT_UART
, sysmem
, serial_hd(0));
1686 create_secure_ram(vms
, secure_sysmem
);
1687 create_uart(vms
, pic
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
1690 vms
->highmem_ecam
&= vms
->highmem
&& (!firmware_loaded
|| aarch64
);
1692 create_rtc(vms
, pic
);
1694 create_pcie(vms
, pic
);
1696 create_gpio(vms
, pic
);
1698 /* Create mmio transports, so the user can create virtio backends
1699 * (which will be automatically plugged in to the transports). If
1700 * no backend is created the transport will just sit harmlessly idle.
1702 create_virtio_devices(vms
, pic
);
1704 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
1705 rom_set_fw(vms
->fw_cfg
);
1707 create_platform_bus(vms
, pic
);
1709 vms
->bootinfo
.ram_size
= machine
->ram_size
;
1710 vms
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1711 vms
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1712 vms
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1713 vms
->bootinfo
.nb_cpus
= smp_cpus
;
1714 vms
->bootinfo
.board_id
= -1;
1715 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
1716 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
1717 vms
->bootinfo
.skip_dtb_autoload
= true;
1718 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
1719 arm_load_kernel(ARM_CPU(first_cpu
), &vms
->bootinfo
);
1721 vms
->machine_done
.notify
= virt_machine_done
;
1722 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
1725 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1727 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1732 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1734 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1736 vms
->secure
= value
;
1739 static bool virt_get_virt(Object
*obj
, Error
**errp
)
1741 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1746 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
1748 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1753 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1755 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1757 return vms
->highmem
;
1760 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1762 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1764 vms
->highmem
= value
;
1767 static bool virt_get_its(Object
*obj
, Error
**errp
)
1769 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1774 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
1776 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1781 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1783 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1784 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1786 return g_strdup(val
);
1789 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1791 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1793 if (!strcmp(value
, "3")) {
1794 vms
->gic_version
= 3;
1795 } else if (!strcmp(value
, "2")) {
1796 vms
->gic_version
= 2;
1797 } else if (!strcmp(value
, "host")) {
1798 vms
->gic_version
= 0; /* Will probe later */
1799 } else if (!strcmp(value
, "max")) {
1800 vms
->gic_version
= -1; /* Will probe later */
1802 error_setg(errp
, "Invalid gic-version value");
1803 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
1807 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
1809 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1811 switch (vms
->iommu
) {
1812 case VIRT_IOMMU_NONE
:
1813 return g_strdup("none");
1814 case VIRT_IOMMU_SMMUV3
:
1815 return g_strdup("smmuv3");
1817 g_assert_not_reached();
1821 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
1823 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1825 if (!strcmp(value
, "smmuv3")) {
1826 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
1827 } else if (!strcmp(value
, "none")) {
1828 vms
->iommu
= VIRT_IOMMU_NONE
;
1830 error_setg(errp
, "Invalid iommu value");
1831 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
1835 static CpuInstanceProperties
1836 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
1838 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
1839 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1841 assert(cpu_index
< possible_cpus
->len
);
1842 return possible_cpus
->cpus
[cpu_index
].props
;
1845 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
1847 return idx
% nb_numa_nodes
;
1850 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
1853 unsigned int max_cpus
= ms
->smp
.max_cpus
;
1854 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
1856 if (ms
->possible_cpus
) {
1857 assert(ms
->possible_cpus
->len
== max_cpus
);
1858 return ms
->possible_cpus
;
1861 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
1862 sizeof(CPUArchId
) * max_cpus
);
1863 ms
->possible_cpus
->len
= max_cpus
;
1864 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
1865 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
1866 ms
->possible_cpus
->cpus
[n
].arch_id
=
1867 virt_cpu_mp_affinity(vms
, n
);
1868 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
1869 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
1871 return ms
->possible_cpus
;
1874 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
1875 DeviceState
*dev
, Error
**errp
)
1877 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
1879 if (vms
->platform_bus_dev
) {
1880 if (object_dynamic_cast(OBJECT(dev
), TYPE_SYS_BUS_DEVICE
)) {
1881 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
1882 SYS_BUS_DEVICE(dev
));
1887 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
1890 if (object_dynamic_cast(OBJECT(dev
), TYPE_SYS_BUS_DEVICE
)) {
1891 return HOTPLUG_HANDLER(machine
);
1898 * for arm64 kvm_type [7-0] encodes the requested number of bits
1899 * in the IPA address space
1901 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
1903 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
1904 int max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
);
1905 int requested_pa_size
;
1907 /* we freeze the memory map to compute the highest gpa */
1908 virt_set_memmap(vms
);
1910 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1912 if (requested_pa_size
> max_vm_pa_size
) {
1913 error_report("-m and ,maxmem option values "
1914 "require an IPA range (%d bits) larger than "
1915 "the one supported by the host (%d bits)",
1916 requested_pa_size
, max_vm_pa_size
);
1920 * By default we return 0 which corresponds to an implicit legacy
1921 * 40b IPA setting. Otherwise we return the actual requested PA
1924 return requested_pa_size
> 40 ? requested_pa_size
: 0;
1927 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1929 MachineClass
*mc
= MACHINE_CLASS(oc
);
1930 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
1932 mc
->init
= machvirt_init
;
1933 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
1934 * The value may be reduced later when we have more information about the
1935 * configuration of the particular instance.
1938 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
1939 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
1940 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
1941 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
1942 mc
->block_default_type
= IF_VIRTIO
;
1944 mc
->pci_allow_0_address
= true;
1945 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1946 mc
->minimum_page_bits
= 12;
1947 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
1948 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
1949 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
1950 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
1951 mc
->kvm_type
= virt_kvm_type
;
1952 assert(!mc
->get_hotplug_handler
);
1953 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
1954 hc
->plug
= virt_machine_device_plug_cb
;
1955 mc
->numa_mem_supported
= true;
1958 static void virt_instance_init(Object
*obj
)
1960 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1961 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1963 /* EL3 is disabled by default on virt: this makes us consistent
1964 * between KVM and TCG for this board, and it also allows us to
1965 * boot UEFI blobs which assume no TrustZone support.
1967 vms
->secure
= false;
1968 object_property_add_bool(obj
, "secure", virt_get_secure
,
1969 virt_set_secure
, NULL
);
1970 object_property_set_description(obj
, "secure",
1971 "Set on/off to enable/disable the ARM "
1972 "Security Extensions (TrustZone)",
1975 /* EL2 is also disabled by default, for similar reasons */
1977 object_property_add_bool(obj
, "virtualization", virt_get_virt
,
1978 virt_set_virt
, NULL
);
1979 object_property_set_description(obj
, "virtualization",
1980 "Set on/off to enable/disable emulating a "
1981 "guest CPU which implements the ARM "
1982 "Virtualization Extensions",
1985 /* High memory is enabled by default */
1986 vms
->highmem
= true;
1987 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1988 virt_set_highmem
, NULL
);
1989 object_property_set_description(obj
, "highmem",
1990 "Set on/off to enable/disable using "
1991 "physical address space above 32 bits",
1993 /* Default GIC type is v2 */
1994 vms
->gic_version
= 2;
1995 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1996 virt_set_gic_version
, NULL
);
1997 object_property_set_description(obj
, "gic-version",
1999 "Valid values are 2, 3 and host", NULL
);
2001 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
2006 /* Default allows ITS instantiation */
2008 object_property_add_bool(obj
, "its", virt_get_its
,
2009 virt_set_its
, NULL
);
2010 object_property_set_description(obj
, "its",
2011 "Set on/off to enable/disable "
2012 "ITS instantiation",
2016 /* Default disallows iommu instantiation */
2017 vms
->iommu
= VIRT_IOMMU_NONE
;
2018 object_property_add_str(obj
, "iommu", virt_get_iommu
, virt_set_iommu
, NULL
);
2019 object_property_set_description(obj
, "iommu",
2020 "Set the IOMMU type. "
2021 "Valid values are none and smmuv3",
2024 vms
->irqmap
= a15irqmap
;
2026 virt_flash_create(vms
);
2029 static const TypeInfo virt_machine_info
= {
2030 .name
= TYPE_VIRT_MACHINE
,
2031 .parent
= TYPE_MACHINE
,
2033 .instance_size
= sizeof(VirtMachineState
),
2034 .class_size
= sizeof(VirtMachineClass
),
2035 .class_init
= virt_machine_class_init
,
2036 .instance_init
= virt_instance_init
,
2037 .interfaces
= (InterfaceInfo
[]) {
2038 { TYPE_HOTPLUG_HANDLER
},
2043 static void machvirt_machine_init(void)
2045 type_register_static(&virt_machine_info
);
2047 type_init(machvirt_machine_init
);
2049 static void virt_machine_4_1_options(MachineClass
*mc
)
2052 DEFINE_VIRT_MACHINE_AS_LATEST(4, 1)
2054 static void virt_machine_4_0_options(MachineClass
*mc
)
2056 virt_machine_4_1_options(mc
);
2057 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
2059 DEFINE_VIRT_MACHINE(4, 0)
2061 static void virt_machine_3_1_options(MachineClass
*mc
)
2063 virt_machine_4_0_options(mc
);
2064 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
2066 DEFINE_VIRT_MACHINE(3, 1)
2068 static void virt_machine_3_0_options(MachineClass
*mc
)
2070 virt_machine_3_1_options(mc
);
2071 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
2073 DEFINE_VIRT_MACHINE(3, 0)
2075 static void virt_machine_2_12_options(MachineClass
*mc
)
2077 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2079 virt_machine_3_0_options(mc
);
2080 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
2081 vmc
->no_highmem_ecam
= true;
2084 DEFINE_VIRT_MACHINE(2, 12)
2086 static void virt_machine_2_11_options(MachineClass
*mc
)
2088 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2090 virt_machine_2_12_options(mc
);
2091 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
2092 vmc
->smbios_old_sys_ver
= true;
2094 DEFINE_VIRT_MACHINE(2, 11)
2096 static void virt_machine_2_10_options(MachineClass
*mc
)
2098 virt_machine_2_11_options(mc
);
2099 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
2100 /* before 2.11 we never faulted accesses to bad addresses */
2101 mc
->ignore_memory_transaction_failures
= true;
2103 DEFINE_VIRT_MACHINE(2, 10)
2105 static void virt_machine_2_9_options(MachineClass
*mc
)
2107 virt_machine_2_10_options(mc
);
2108 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
2110 DEFINE_VIRT_MACHINE(2, 9)
2112 static void virt_machine_2_8_options(MachineClass
*mc
)
2114 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2116 virt_machine_2_9_options(mc
);
2117 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
2118 /* For 2.8 and earlier we falsely claimed in the DT that
2119 * our timers were edge-triggered, not level-triggered.
2121 vmc
->claim_edge_triggered_timers
= true;
2123 DEFINE_VIRT_MACHINE(2, 8)
2125 static void virt_machine_2_7_options(MachineClass
*mc
)
2127 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2129 virt_machine_2_8_options(mc
);
2130 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
2131 /* ITS was introduced with 2.8 */
2133 /* Stick with 1K pages for migration compatibility */
2134 mc
->minimum_page_bits
= 0;
2136 DEFINE_VIRT_MACHINE(2, 7)
2138 static void virt_machine_2_6_options(MachineClass
*mc
)
2140 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2142 virt_machine_2_7_options(mc
);
2143 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
2144 vmc
->disallow_affinity_adjustment
= true;
2145 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2148 DEFINE_VIRT_MACHINE(2, 6)