2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/runstate.h"
48 #include "sysemu/tpm.h"
49 #include "sysemu/tcg.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "sysemu/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/intc/arm_gicv3_its_common.h"
69 #include "hw/firmware/smbios.h"
70 #include "qapi/visitor.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/qmp/qlist.h"
73 #include "standard-headers/linux/input.h"
74 #include "hw/arm/smmuv3.h"
75 #include "hw/acpi/acpi.h"
76 #include "target/arm/cpu-qom.h"
77 #include "target/arm/internals.h"
78 #include "target/arm/multiprocessing.h"
79 #include "target/arm/gtimer.h"
80 #include "hw/mem/pc-dimm.h"
81 #include "hw/mem/nvdimm.h"
82 #include "hw/acpi/generic_event_device.h"
83 #include "hw/virtio/virtio-md-pci.h"
84 #include "hw/virtio/virtio-iommu.h"
85 #include "hw/char/pl011.h"
86 #include "qemu/guest-random.h"
88 static GlobalProperty arm_virt_compat
[] = {
89 { TYPE_VIRTIO_IOMMU_PCI
, "aw-bits", "48" },
91 static const size_t arm_virt_compat_len
= G_N_ELEMENTS(arm_virt_compat
);
94 * This cannot be called from the virt_machine_class_init() because
95 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new()
96 * only is called on virt non abstract class init.
98 static void arm_virt_compat_set(MachineClass
*mc
)
100 compat_props_add(mc
->compat_props
, arm_virt_compat
,
101 arm_virt_compat_len
);
104 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
105 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
108 MachineClass *mc = MACHINE_CLASS(oc); \
109 arm_virt_compat_set(mc); \
110 virt_machine_##major##_##minor##_options(mc); \
111 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
113 mc->alias = "virt"; \
116 static const TypeInfo machvirt_##major##_##minor##_info = { \
117 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
118 .parent = TYPE_VIRT_MACHINE, \
119 .class_init = virt_##major##_##minor##_class_init, \
121 static void machvirt_machine_##major##_##minor##_init(void) \
123 type_register_static(&machvirt_##major##_##minor##_info); \
125 type_init(machvirt_machine_##major##_##minor##_init);
127 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
128 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
129 #define DEFINE_VIRT_MACHINE(major, minor) \
130 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
133 /* Number of external interrupt lines to configure the GIC with */
136 #define PLATFORM_BUS_NUM_IRQS 64
138 /* Legacy RAM limit in GB (< version 4.0) */
139 #define LEGACY_RAMLIMIT_GB 255
140 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
142 /* Addresses and sizes of our components.
143 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
144 * 128MB..256MB is used for miscellaneous device I/O.
145 * 256MB..1GB is reserved for possible future PCI support (ie where the
146 * PCI memory window will go if we add a PCI host controller).
147 * 1GB and up is RAM (which may happily spill over into the
148 * high memory region beyond 4GB).
149 * This represents a compromise between how much RAM can be given to
150 * a 32 bit VM and leaving space for expansion and in particular for PCI.
151 * Note that devices should generally be placed at multiples of 0x10000,
152 * to accommodate guests using 64K pages.
154 static const MemMapEntry base_memmap
[] = {
155 /* Space up to 0x8000000 is reserved for a boot ROM */
156 [VIRT_FLASH
] = { 0, 0x08000000 },
157 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
158 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
159 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
160 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
161 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
162 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
163 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
164 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
165 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
166 /* This redistributor space allows up to 2*64kB*123 CPUs */
167 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
168 [VIRT_UART
] = { 0x09000000, 0x00001000 },
169 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
170 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
171 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
172 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
173 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
174 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
175 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
176 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
177 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
178 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
179 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
180 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
181 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
182 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
183 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
184 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
185 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
186 /* Actual RAM size depends on initial RAM and device memory settings */
187 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
191 * Highmem IO Regions: This memory map is floating, located after the RAM.
192 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
193 * top of the RAM, so that its base get the same alignment as the size,
194 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
195 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
196 * Note the extended_memmap is sized so that it eventually also includes the
197 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
198 * index of base_memmap).
200 * The memory map for these Highmem IO Regions can be in legacy or compact
201 * layout, depending on 'compact-highmem' property. With legacy layout, the
202 * PA space for one specific region is always reserved, even if the region
203 * has been disabled or doesn't fit into the PA space. However, the PA space
204 * for the region won't be reserved in these circumstances with compact layout.
206 static MemMapEntry extended_memmap
[] = {
207 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
208 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
209 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
210 /* Second PCIe window */
211 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
214 static const int a15irqmap
[] = {
217 [VIRT_PCIE
] = 3, /* ... to 6 */
219 [VIRT_SECURE_UART
] = 8,
221 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
222 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
223 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
224 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
227 static void create_randomness(MachineState
*ms
, const char *node
)
234 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
237 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
.kaslr
);
238 qemu_fdt_setprop(ms
->fdt
, node
, "rng-seed", seed
.rng
, sizeof(seed
.rng
));
242 * The CPU object always exposes the NS EL2 virt timer IRQ line,
243 * but we don't want to advertise it to the guest in the dtb or ACPI
244 * table unless it's really going to do something.
246 static bool ns_el2_virt_timer_present(void)
248 ARMCPU
*cpu
= ARM_CPU(qemu_get_cpu(0));
249 CPUARMState
*env
= &cpu
->env
;
251 return arm_feature(env
, ARM_FEATURE_AARCH64
) &&
252 arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
);
255 static void create_fdt(VirtMachineState
*vms
)
257 MachineState
*ms
= MACHINE(vms
);
258 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
259 void *fdt
= create_device_tree(&vms
->fdt_size
);
262 error_report("create_device_tree() failed");
269 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
270 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
271 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
272 qemu_fdt_setprop_string(fdt
, "/", "model", "linux,dummy-virt");
274 /* /chosen must exist for load_dtb to fill in necessary properties later */
275 qemu_fdt_add_subnode(fdt
, "/chosen");
276 if (vms
->dtb_randomness
) {
277 create_randomness(ms
, "/chosen");
281 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
282 if (vms
->dtb_randomness
) {
283 create_randomness(ms
, "/secure-chosen");
287 /* Clock node, for the benefit of the UART. The kernel device tree
288 * binding documentation claims the PL011 node clock properties are
289 * optional but in practice if you omit them the kernel refuses to
290 * probe for the device.
292 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
293 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
294 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
295 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
296 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
297 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
299 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
301 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
302 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
303 uint32_t *matrix
= g_malloc0(size
);
306 for (i
= 0; i
< nb_numa_nodes
; i
++) {
307 for (j
= 0; j
< nb_numa_nodes
; j
++) {
308 idx
= (i
* nb_numa_nodes
+ j
) * 3;
309 matrix
[idx
+ 0] = cpu_to_be32(i
);
310 matrix
[idx
+ 1] = cpu_to_be32(j
);
312 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
316 qemu_fdt_add_subnode(fdt
, "/distance-map");
317 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
318 "numa-distance-map-v1");
319 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
325 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
327 /* On real hardware these interrupts are level-triggered.
328 * On KVM they were edge-triggered before host kernel version 4.4,
329 * and level-triggered afterwards.
330 * On emulated QEMU they are level-triggered.
332 * Getting the DTB info about them wrong is awkward for some
334 * pre-4.8 ignore the DT and leave the interrupt configured
335 * with whatever the GIC reset value (or the bootloader) left it at
336 * 4.8 before rc6 honour the incorrect data by programming it back
337 * into the GIC, causing problems
338 * 4.8rc6 and later ignore the DT and always write "level triggered"
341 * For backwards-compatibility, virt-2.8 and earlier will continue
342 * to say these are edge-triggered, but later machines will report
343 * the correct information.
346 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
347 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
348 MachineState
*ms
= MACHINE(vms
);
350 if (vmc
->claim_edge_triggered_timers
) {
351 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
354 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
355 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
356 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
357 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
360 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
362 armcpu
= ARM_CPU(qemu_get_cpu(0));
363 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
364 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
365 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
366 compat
, sizeof(compat
));
368 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
371 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
372 if (vms
->ns_el2_virt_timer_irq
) {
373 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
374 GIC_FDT_IRQ_TYPE_PPI
,
375 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ
), irqflags
,
376 GIC_FDT_IRQ_TYPE_PPI
,
377 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ
), irqflags
,
378 GIC_FDT_IRQ_TYPE_PPI
,
379 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ
), irqflags
,
380 GIC_FDT_IRQ_TYPE_PPI
,
381 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ
), irqflags
,
382 GIC_FDT_IRQ_TYPE_PPI
,
383 INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ
), irqflags
);
385 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
386 GIC_FDT_IRQ_TYPE_PPI
,
387 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ
), irqflags
,
388 GIC_FDT_IRQ_TYPE_PPI
,
389 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ
), irqflags
,
390 GIC_FDT_IRQ_TYPE_PPI
,
391 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ
), irqflags
,
392 GIC_FDT_IRQ_TYPE_PPI
,
393 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ
), irqflags
);
397 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
401 const MachineState
*ms
= MACHINE(vms
);
402 const VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
403 int smp_cpus
= ms
->smp
.cpus
;
406 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
407 * On ARM v8 64-bit systems value should be set to 2,
408 * that corresponds to the MPIDR_EL1 register size.
409 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
410 * in the system, #address-cells can be set to 1, since
411 * MPIDR_EL1[63:32] bits are not used for CPUs
414 * Here we actually don't know whether our system is 32- or 64-bit one.
415 * The simplest way to go is to examine affinity IDs of all our CPUs. If
416 * at least one of them has Aff3 populated, we set #address-cells to 2.
418 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
419 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
421 if (arm_cpu_mp_affinity(armcpu
) & ARM_AFF3_MASK
) {
427 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
428 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
429 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
431 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
432 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
433 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
434 CPUState
*cs
= CPU(armcpu
);
436 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
437 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
438 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
439 armcpu
->dtb_compatible
);
441 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
442 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
443 "enable-method", "psci");
446 if (addr_cells
== 2) {
447 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
448 arm_cpu_mp_affinity(armcpu
));
450 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
451 arm_cpu_mp_affinity(armcpu
));
454 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
455 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
456 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
459 if (!vmc
->no_cpu_topology
) {
460 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle",
461 qemu_fdt_alloc_phandle(ms
->fdt
));
467 if (!vmc
->no_cpu_topology
) {
469 * Add vCPU topology description through fdt node cpu-map.
471 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
472 * In a SMP system, the hierarchy of CPUs can be defined through
473 * four entities that are used to describe the layout of CPUs in
474 * the system: socket/cluster/core/thread.
476 * A socket node represents the boundary of system physical package
477 * and its child nodes must be one or more cluster nodes. A system
478 * can contain several layers of clustering within a single physical
479 * package and cluster nodes can be contained in parent cluster nodes.
481 * Note: currently we only support one layer of clustering within
482 * each physical package.
484 qemu_fdt_add_subnode(ms
->fdt
, "/cpus/cpu-map");
486 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
487 char *cpu_path
= g_strdup_printf("/cpus/cpu@%d", cpu
);
490 if (ms
->smp
.threads
> 1) {
491 map_path
= g_strdup_printf(
492 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
493 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
),
494 (cpu
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
,
495 (cpu
/ ms
->smp
.threads
) % ms
->smp
.cores
,
496 cpu
% ms
->smp
.threads
);
498 map_path
= g_strdup_printf(
499 "/cpus/cpu-map/socket%d/cluster%d/core%d",
500 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
),
501 (cpu
/ ms
->smp
.cores
) % ms
->smp
.clusters
,
502 cpu
% ms
->smp
.cores
);
504 qemu_fdt_add_path(ms
->fdt
, map_path
);
505 qemu_fdt_setprop_phandle(ms
->fdt
, map_path
, "cpu", cpu_path
);
513 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
516 MachineState
*ms
= MACHINE(vms
);
518 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
519 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
520 vms
->memmap
[VIRT_GIC_ITS
].base
);
521 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
522 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
524 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
525 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#msi-cells", 1);
526 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
527 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
528 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
529 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
533 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
535 MachineState
*ms
= MACHINE(vms
);
538 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
539 vms
->memmap
[VIRT_GIC_V2M
].base
);
540 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
541 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
542 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
543 "arm,gic-v2m-frame");
544 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
545 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
546 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
547 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
548 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
552 static void fdt_add_gic_node(VirtMachineState
*vms
)
554 MachineState
*ms
= MACHINE(vms
);
557 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
558 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
560 nodename
= g_strdup_printf("/intc@%" PRIx64
,
561 vms
->memmap
[VIRT_GIC_DIST
].base
);
562 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
563 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
564 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
565 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
566 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
567 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
568 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
569 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
571 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
574 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
575 "#redistributor-regions", nb_redist_regions
);
577 if (nb_redist_regions
== 1) {
578 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
579 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
580 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
581 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
582 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
584 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
585 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
586 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
587 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
588 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
589 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
590 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
594 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
595 GIC_FDT_IRQ_TYPE_PPI
,
596 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ
),
597 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
600 /* 'cortex-a15-gic' means 'GIC v2' */
601 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
602 "arm,cortex-a15-gic");
604 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
605 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
606 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
607 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
608 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
610 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
611 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
612 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
613 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
614 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
615 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
616 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
617 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
618 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
619 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
620 GIC_FDT_IRQ_TYPE_PPI
,
621 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ
),
622 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
626 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
630 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
632 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
633 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
634 MachineState
*ms
= MACHINE(vms
);
636 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
637 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
641 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
642 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
643 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
644 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
647 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
648 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
649 const char compat
[] = "arm,armv8-pmuv3";
650 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
651 compat
, sizeof(compat
));
652 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
653 GIC_FDT_IRQ_TYPE_PPI
,
654 INTID_TO_PPI(VIRTUAL_PMU_IRQ
), irqflags
);
658 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
661 MachineState
*ms
= MACHINE(vms
);
662 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
663 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
666 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
669 if (ms
->nvdimms_state
->is_enabled
) {
670 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
673 dev
= qdev_new(TYPE_ACPI_GED
);
674 qdev_prop_set_uint32(dev
, "ged-event", event
);
675 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
677 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
678 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
679 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
684 static void create_its(VirtMachineState
*vms
)
686 const char *itsclass
= its_class_name();
689 if (!strcmp(itsclass
, "arm-gicv3-its")) {
696 /* Do nothing if not supported */
700 dev
= qdev_new(itsclass
);
702 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
704 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
705 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
707 fdt_add_its_gic_node(vms
);
708 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
711 static void create_v2m(VirtMachineState
*vms
)
714 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
717 dev
= qdev_new("arm-gicv2m");
718 qdev_prop_set_uint32(dev
, "base-spi", irq
);
719 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
720 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
721 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
723 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
724 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
725 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
728 fdt_add_v2m_gic_node(vms
);
729 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
733 * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too.
734 * It's permitted to have a configuration with NMI in the CPU (and thus the
735 * GICv3 CPU interface) but not in the distributor/redistributors, but it's
738 static bool gicv3_nmi_present(VirtMachineState
*vms
)
740 ARMCPU
*cpu
= ARM_CPU(qemu_get_cpu(0));
742 return tcg_enabled() && cpu_isar_feature(aa64_nmi
, cpu
) &&
743 (vms
->gic_version
!= VIRT_GIC_VERSION_2
);
746 static void create_gic(VirtMachineState
*vms
, MemoryRegion
*mem
)
748 MachineState
*ms
= MACHINE(vms
);
749 /* We create a standalone GIC */
750 SysBusDevice
*gicbusdev
;
753 unsigned int smp_cpus
= ms
->smp
.cpus
;
754 uint32_t nb_redist_regions
= 0;
757 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
758 gictype
= gic_class_name();
760 gictype
= gicv3_class_name();
763 switch (vms
->gic_version
) {
764 case VIRT_GIC_VERSION_2
:
767 case VIRT_GIC_VERSION_3
:
770 case VIRT_GIC_VERSION_4
:
774 g_assert_not_reached();
776 vms
->gic
= qdev_new(gictype
);
777 qdev_prop_set_uint32(vms
->gic
, "revision", revision
);
778 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
779 /* Note that the num-irq property counts both internal and external
780 * interrupts; there are always 32 of the former (mandated by GIC spec).
782 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
783 if (!kvm_irqchip_in_kernel()) {
784 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
787 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
788 QList
*redist_region_count
;
789 uint32_t redist0_capacity
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
790 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
792 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
794 redist_region_count
= qlist_new();
795 qlist_append_int(redist_region_count
, redist0_count
);
796 if (nb_redist_regions
== 2) {
797 uint32_t redist1_capacity
=
798 virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
800 qlist_append_int(redist_region_count
,
801 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
803 qdev_prop_set_array(vms
->gic
, "redist-region-count",
804 redist_region_count
);
806 if (!kvm_irqchip_in_kernel()) {
808 object_property_set_link(OBJECT(vms
->gic
), "sysmem",
809 OBJECT(mem
), &error_fatal
);
810 qdev_prop_set_bit(vms
->gic
, "has-lpi", true);
814 if (!kvm_irqchip_in_kernel()) {
815 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
820 if (gicv3_nmi_present(vms
)) {
821 qdev_prop_set_bit(vms
->gic
, "has-nmi", true);
824 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
825 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
826 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
827 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
828 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
829 if (nb_redist_regions
== 2) {
830 sysbus_mmio_map(gicbusdev
, 2,
831 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
834 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
836 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
837 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
841 /* Wire the outputs from each CPU's generic timer and the GICv3
842 * maintenance interrupt signal to the appropriate GIC PPI inputs,
843 * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the
846 for (i
= 0; i
< smp_cpus
; i
++) {
847 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
848 int intidbase
= NUM_IRQS
+ i
* GIC_INTERNAL
;
849 /* Mapping from the output timer irq lines from the CPU to the
850 * GIC PPI inputs we use for the virt board.
852 const int timer_irq
[] = {
853 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
854 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
855 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
856 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
857 [GTIMER_HYPVIRT
] = ARCH_TIMER_NS_EL2_VIRT_IRQ
,
860 for (unsigned irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
861 qdev_connect_gpio_out(cpudev
, irq
,
862 qdev_get_gpio_in(vms
->gic
,
863 intidbase
+ timer_irq
[irq
]));
866 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
867 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
868 intidbase
+ ARCH_GIC_MAINT_IRQ
);
869 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
871 } else if (vms
->virt
) {
872 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
873 intidbase
+ ARCH_GIC_MAINT_IRQ
);
874 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
877 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
878 qdev_get_gpio_in(vms
->gic
, intidbase
881 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
882 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
883 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
884 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
885 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
886 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
887 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
889 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
890 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
,
891 qdev_get_gpio_in(cpudev
, ARM_CPU_NMI
));
892 sysbus_connect_irq(gicbusdev
, i
+ 5 * smp_cpus
,
893 qdev_get_gpio_in(cpudev
, ARM_CPU_VINMI
));
897 fdt_add_gic_node(vms
);
899 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& vms
->its
) {
901 } else if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
906 static void create_uart(const VirtMachineState
*vms
, int uart
,
907 MemoryRegion
*mem
, Chardev
*chr
)
910 hwaddr base
= vms
->memmap
[uart
].base
;
911 hwaddr size
= vms
->memmap
[uart
].size
;
912 int irq
= vms
->irqmap
[uart
];
913 const char compat
[] = "arm,pl011\0arm,primecell";
914 const char clocknames
[] = "uartclk\0apb_pclk";
915 DeviceState
*dev
= qdev_new(TYPE_PL011
);
916 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
917 MachineState
*ms
= MACHINE(vms
);
919 qdev_prop_set_chr(dev
, "chardev", chr
);
920 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
921 memory_region_add_subregion(mem
, base
,
922 sysbus_mmio_get_region(s
, 0));
923 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
925 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
926 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
927 /* Note that we can't use setprop_string because of the embedded NUL */
928 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
929 compat
, sizeof(compat
));
930 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
932 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
933 GIC_FDT_IRQ_TYPE_SPI
, irq
,
934 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
935 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
936 vms
->clock_phandle
, vms
->clock_phandle
);
937 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
938 clocknames
, sizeof(clocknames
));
940 if (uart
== VIRT_UART
) {
941 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
943 /* Mark as not usable by the normal world */
944 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
945 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
947 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
954 static void create_rtc(const VirtMachineState
*vms
)
957 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
958 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
959 int irq
= vms
->irqmap
[VIRT_RTC
];
960 const char compat
[] = "arm,pl031\0arm,primecell";
961 MachineState
*ms
= MACHINE(vms
);
963 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
965 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
966 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
967 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
968 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
970 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
971 GIC_FDT_IRQ_TYPE_SPI
, irq
,
972 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
973 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
974 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
978 static DeviceState
*gpio_key_dev
;
979 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
981 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
984 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
986 /* use gpio Pin 3 for power button event */
987 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
991 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
994 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
995 qdev_get_gpio_in(pl061_dev
, 3));
997 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
998 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
1000 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
1001 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
1002 "label", "GPIO Key Poweroff");
1003 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
1005 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
1006 "gpios", phandle
, 3, 0);
1009 #define SECURE_GPIO_POWEROFF 0
1010 #define SECURE_GPIO_RESET 1
1012 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
1015 DeviceState
*gpio_pwr_dev
;
1018 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
1020 /* connect secure pl061 to gpio-pwr */
1021 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
1022 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
1023 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
1024 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
1026 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
1027 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
1029 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
1030 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
1031 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
1032 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
1035 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
1036 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
1038 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
1039 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
1040 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
1041 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
1045 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
1049 DeviceState
*pl061_dev
;
1050 hwaddr base
= vms
->memmap
[gpio
].base
;
1051 hwaddr size
= vms
->memmap
[gpio
].size
;
1052 int irq
= vms
->irqmap
[gpio
];
1053 const char compat
[] = "arm,pl061\0arm,primecell";
1055 MachineState
*ms
= MACHINE(vms
);
1057 pl061_dev
= qdev_new("pl061");
1058 /* Pull lines down to 0 if not driven by the PL061 */
1059 qdev_prop_set_uint32(pl061_dev
, "pullups", 0);
1060 qdev_prop_set_uint32(pl061_dev
, "pulldowns", 0xff);
1061 s
= SYS_BUS_DEVICE(pl061_dev
);
1062 sysbus_realize_and_unref(s
, &error_fatal
);
1063 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
1064 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
1066 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1067 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
1068 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1069 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1071 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
1072 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
1073 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
1074 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1075 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1076 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
1077 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
1078 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
1079 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
1081 if (gpio
!= VIRT_GPIO
) {
1082 /* Mark as not usable by the normal world */
1083 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1084 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1088 /* Child gpio devices */
1089 if (gpio
== VIRT_GPIO
) {
1090 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
1092 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
1096 static void create_virtio_devices(const VirtMachineState
*vms
)
1099 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
1100 MachineState
*ms
= MACHINE(vms
);
1102 /* We create the transports in forwards order. Since qbus_realize()
1103 * prepends (not appends) new child buses, the incrementing loop below will
1104 * create a list of virtio-mmio buses with decreasing base addresses.
1106 * When a -device option is processed from the command line,
1107 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1108 * order. The upshot is that -device options in increasing command line
1109 * order are mapped to virtio-mmio buses with decreasing base addresses.
1111 * When this code was originally written, that arrangement ensured that the
1112 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1113 * the first -device on the command line. (The end-to-end order is a
1114 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1115 * guest kernel's name-to-address assignment strategy.)
1117 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1118 * the message, if not necessarily the code, of commit 70161ff336.
1119 * Therefore the loop now establishes the inverse of the original intent.
1121 * Unfortunately, we can't counteract the kernel change by reversing the
1122 * loop; it would break existing command lines.
1124 * In any case, the kernel makes no guarantee about the stability of
1125 * enumeration order of virtio devices (as demonstrated by it changing
1126 * between kernel versions). For reliable and stable identification
1127 * of disks users must use UUIDs or similar mechanisms.
1129 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
1130 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1131 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1133 sysbus_create_simple("virtio-mmio", base
,
1134 qdev_get_gpio_in(vms
->gic
, irq
));
1137 /* We add dtb nodes in reverse order so that they appear in the finished
1138 * device tree lowest address first.
1140 * Note that this mapping is independent of the loop above. The previous
1141 * loop influences virtio device to virtio transport assignment, whereas
1142 * this loop controls how virtio transports are laid out in the dtb.
1144 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
1146 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1147 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1149 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
1150 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1151 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1152 "compatible", "virtio,mmio");
1153 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1155 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1156 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1157 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1158 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1163 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1165 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1167 const char *alias_prop_name
)
1170 * Create a single flash device. We use the same parameters as
1171 * the flash devices on the Versatile Express board.
1173 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1175 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1176 qdev_prop_set_uint8(dev
, "width", 4);
1177 qdev_prop_set_uint8(dev
, "device-width", 2);
1178 qdev_prop_set_bit(dev
, "big-endian", false);
1179 qdev_prop_set_uint16(dev
, "id0", 0x89);
1180 qdev_prop_set_uint16(dev
, "id1", 0x18);
1181 qdev_prop_set_uint16(dev
, "id2", 0x00);
1182 qdev_prop_set_uint16(dev
, "id3", 0x00);
1183 qdev_prop_set_string(dev
, "name", name
);
1184 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1185 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1186 OBJECT(dev
), "drive");
1187 return PFLASH_CFI01(dev
);
1190 static void virt_flash_create(VirtMachineState
*vms
)
1192 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1193 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1196 static void virt_flash_map1(PFlashCFI01
*flash
,
1197 hwaddr base
, hwaddr size
,
1198 MemoryRegion
*sysmem
)
1200 DeviceState
*dev
= DEVICE(flash
);
1202 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1203 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1204 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1205 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1207 memory_region_add_subregion(sysmem
, base
,
1208 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1212 static void virt_flash_map(VirtMachineState
*vms
,
1213 MemoryRegion
*sysmem
,
1214 MemoryRegion
*secure_sysmem
)
1217 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1218 * sysmem is the system memory space. secure_sysmem is the secure view
1219 * of the system, and the first flash device should be made visible only
1220 * there. The second flash device is visible to both secure and nonsecure.
1221 * If sysmem == secure_sysmem this means there is no separate Secure
1222 * address space and both flash devices are generally visible.
1224 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1225 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1227 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1229 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1233 static void virt_flash_fdt(VirtMachineState
*vms
,
1234 MemoryRegion
*sysmem
,
1235 MemoryRegion
*secure_sysmem
)
1237 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1238 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1239 MachineState
*ms
= MACHINE(vms
);
1242 if (sysmem
== secure_sysmem
) {
1243 /* Report both flash devices as a single node in the DT */
1244 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1245 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1246 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1247 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1248 2, flashbase
, 2, flashsize
,
1249 2, flashbase
+ flashsize
, 2, flashsize
);
1250 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1254 * Report the devices as separate nodes so we can mark one as
1255 * only visible to the secure world.
1257 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1258 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1259 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1260 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1261 2, flashbase
, 2, flashsize
);
1262 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1263 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1264 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1267 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
+ flashsize
);
1268 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1269 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1270 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1271 2, flashbase
+ flashsize
, 2, flashsize
);
1272 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1277 static bool virt_firmware_init(VirtMachineState
*vms
,
1278 MemoryRegion
*sysmem
,
1279 MemoryRegion
*secure_sysmem
)
1282 const char *bios_name
;
1283 BlockBackend
*pflash_blk0
;
1285 /* Map legacy -drive if=pflash to machine properties */
1286 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1287 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1288 drive_get(IF_PFLASH
, 0, i
));
1291 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1293 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1295 bios_name
= MACHINE(vms
)->firmware
;
1302 error_report("The contents of the first flash device may be "
1303 "specified with -bios or with -drive if=pflash... "
1304 "but you cannot use both options at once");
1308 /* Fall back to -bios */
1310 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1312 error_report("Could not find ROM image '%s'", bios_name
);
1315 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1316 image_size
= load_image_mr(fname
, mr
);
1318 if (image_size
< 0) {
1319 error_report("Could not load ROM image '%s'", bios_name
);
1324 return pflash_blk0
|| bios_name
;
1327 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1329 MachineState
*ms
= MACHINE(vms
);
1330 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1331 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1335 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1336 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1338 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1339 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1340 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1341 "compatible", "qemu,fw-cfg-mmio");
1342 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1344 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1349 static void create_pcie_irq_map(const MachineState
*ms
,
1350 uint32_t gic_phandle
,
1351 int first_irq
, const char *nodename
)
1354 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1355 uint32_t *irq_map
= full_irq_map
;
1357 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1358 for (pin
= 0; pin
< 4; pin
++) {
1359 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1360 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1361 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1365 devfn
<< 8, 0, 0, /* devfn */
1366 pin
+ 1, /* PCI pin */
1367 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1369 /* Convert map to big endian */
1370 for (i
= 0; i
< 10; i
++) {
1371 irq_map
[i
] = cpu_to_be32(map
[i
]);
1377 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1378 full_irq_map
, sizeof(full_irq_map
));
1380 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1381 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1386 static void create_smmu(const VirtMachineState
*vms
,
1390 const char compat
[] = "arm,smmu-v3";
1391 int irq
= vms
->irqmap
[VIRT_SMMU
];
1393 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1394 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1395 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1397 MachineState
*ms
= MACHINE(vms
);
1399 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1403 dev
= qdev_new(TYPE_ARM_SMMUV3
);
1405 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1407 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1408 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1409 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1410 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1411 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1414 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1415 qemu_fdt_add_subnode(ms
->fdt
, node
);
1416 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1417 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1419 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1420 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1421 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1422 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1423 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1425 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1428 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1430 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1432 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1436 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1438 const char compat
[] = "virtio,pci-iommu\0pci1af4,1057";
1439 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1440 MachineState
*ms
= MACHINE(vms
);
1443 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1445 node
= g_strdup_printf("%s/virtio_iommu@%x,%x", vms
->pciehb_nodename
,
1446 PCI_SLOT(bdf
), PCI_FUNC(bdf
));
1447 qemu_fdt_add_subnode(ms
->fdt
, node
);
1448 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1449 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1450 1, bdf
<< 8, 1, 0, 1, 0,
1453 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1454 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1457 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1458 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1459 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1462 static void create_pcie(VirtMachineState
*vms
)
1464 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1465 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1466 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1467 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1468 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1469 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1470 hwaddr base_ecam
, size_ecam
;
1471 hwaddr base
= base_mmio
;
1473 int irq
= vms
->irqmap
[VIRT_PCIE
];
1474 MemoryRegion
*mmio_alias
;
1475 MemoryRegion
*mmio_reg
;
1476 MemoryRegion
*ecam_alias
;
1477 MemoryRegion
*ecam_reg
;
1482 MachineState
*ms
= MACHINE(vms
);
1483 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
1485 dev
= qdev_new(TYPE_GPEX_HOST
);
1486 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1488 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1489 base_ecam
= vms
->memmap
[ecam_id
].base
;
1490 size_ecam
= vms
->memmap
[ecam_id
].size
;
1491 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1492 /* Map only the first size_ecam bytes of ECAM space */
1493 ecam_alias
= g_new0(MemoryRegion
, 1);
1494 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1495 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1496 ecam_reg
, 0, size_ecam
);
1497 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1499 /* Map the MMIO window into system address space so as to expose
1500 * the section of PCI MMIO space which starts at the same base address
1501 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1504 mmio_alias
= g_new0(MemoryRegion
, 1);
1505 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1506 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1507 mmio_reg
, base_mmio
, size_mmio
);
1508 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1510 if (vms
->highmem_mmio
) {
1511 /* Map high MMIO space */
1512 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1514 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1515 mmio_reg
, base_mmio_high
, size_mmio_high
);
1516 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1520 /* Map IO port space */
1521 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1523 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1524 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1525 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1526 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1529 pci
= PCI_HOST_BRIDGE(dev
);
1530 pci
->bypass_iommu
= vms
->default_bus_bypass_iommu
;
1531 vms
->bus
= pci
->bus
;
1533 pci_init_nic_devices(pci
->bus
, mc
->default_nic
);
1536 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1537 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1538 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1539 "compatible", "pci-host-ecam-generic");
1540 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1541 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1542 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1543 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1544 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1546 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1548 if (vms
->msi_phandle
) {
1549 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-map",
1550 0, vms
->msi_phandle
, 0, 0x10000);
1553 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1554 2, base_ecam
, 2, size_ecam
);
1556 if (vms
->highmem_mmio
) {
1557 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1558 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1559 2, base_pio
, 2, size_pio
,
1560 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1561 2, base_mmio
, 2, size_mmio
,
1562 1, FDT_PCI_RANGE_MMIO_64BIT
,
1564 2, base_mmio_high
, 2, size_mmio_high
);
1566 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1567 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1568 2, base_pio
, 2, size_pio
,
1569 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1570 2, base_mmio
, 2, size_mmio
);
1573 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1574 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1577 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1579 switch (vms
->iommu
) {
1580 case VIRT_IOMMU_SMMUV3
:
1581 create_smmu(vms
, vms
->bus
);
1582 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1583 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1586 g_assert_not_reached();
1591 static void create_platform_bus(VirtMachineState
*vms
)
1596 MemoryRegion
*sysmem
= get_system_memory();
1598 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1599 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1600 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1601 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1602 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1603 vms
->platform_bus_dev
= dev
;
1605 s
= SYS_BUS_DEVICE(dev
);
1606 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1607 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1608 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1611 memory_region_add_subregion(sysmem
,
1612 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1613 sysbus_mmio_get_region(s
, 0));
1616 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1617 hwaddr base
, hwaddr size
,
1620 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1622 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1623 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1626 static void create_secure_ram(VirtMachineState
*vms
,
1627 MemoryRegion
*secure_sysmem
,
1628 MemoryRegion
*secure_tag_sysmem
)
1630 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1632 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1633 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1634 MachineState
*ms
= MACHINE(vms
);
1636 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1638 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1640 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1641 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1642 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1643 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1644 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1645 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1647 if (secure_tag_sysmem
) {
1648 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1654 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1656 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1658 MachineState
*ms
= MACHINE(board
);
1661 *fdt_size
= board
->fdt_size
;
1665 static void virt_build_smbios(VirtMachineState
*vms
)
1667 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1668 MachineState
*ms
= MACHINE(vms
);
1669 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1670 uint8_t *smbios_tables
, *smbios_anchor
;
1671 size_t smbios_tables_len
, smbios_anchor_len
;
1672 struct smbios_phys_mem_area mem_array
;
1673 const char *product
= "QEMU Virtual Machine";
1675 if (kvm_enabled()) {
1676 product
= "KVM Virtual Machine";
1679 smbios_set_defaults("QEMU", product
,
1680 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
,
1683 /* build the array of physical mem area from base_memmap */
1684 mem_array
.address
= vms
->memmap
[VIRT_MEM
].base
;
1685 mem_array
.length
= ms
->ram_size
;
1687 smbios_get_tables(ms
, SMBIOS_ENTRY_POINT_TYPE_64
, &mem_array
, 1,
1688 &smbios_tables
, &smbios_tables_len
,
1689 &smbios_anchor
, &smbios_anchor_len
,
1692 if (smbios_anchor
) {
1693 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1694 smbios_tables
, smbios_tables_len
);
1695 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1696 smbios_anchor
, smbios_anchor_len
);
1701 void virt_machine_done(Notifier
*notifier
, void *data
)
1703 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1705 MachineState
*ms
= MACHINE(vms
);
1706 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1707 struct arm_boot_info
*info
= &vms
->bootinfo
;
1708 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1711 * If the user provided a dtb, we assume the dynamic sysbus nodes
1712 * already are integrated there. This corresponds to a use case where
1713 * the dynamic sysbus nodes are complex and their generation is not yet
1714 * supported. In that case the user can take charge of the guest dt
1715 * while qemu takes charge of the qom stuff.
1717 if (info
->dtb_filename
== NULL
) {
1718 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1719 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1720 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1721 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1723 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1727 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1729 virt_acpi_setup(vms
);
1730 virt_build_smbios(vms
);
1733 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1735 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1736 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1738 if (!vmc
->disallow_affinity_adjustment
) {
1739 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1740 * GIC's target-list limitations. 32-bit KVM hosts currently
1741 * always create clusters of 4 CPUs, but that is expected to
1742 * change when they gain support for gicv3. When KVM is enabled
1743 * it will override the changes we make here, therefore our
1744 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1745 * and to improve SGI efficiency.
1747 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
1748 clustersz
= GIC_TARGETLIST_BITS
;
1750 clustersz
= GICV3_TARGETLIST_BITS
;
1753 return arm_build_mp_affinity(idx
, clustersz
);
1756 static inline bool *virt_get_high_memmap_enabled(VirtMachineState
*vms
,
1759 bool *enabled_array
[] = {
1760 &vms
->highmem_redists
,
1765 assert(ARRAY_SIZE(extended_memmap
) - VIRT_LOWMEMMAP_LAST
==
1766 ARRAY_SIZE(enabled_array
));
1767 assert(index
- VIRT_LOWMEMMAP_LAST
< ARRAY_SIZE(enabled_array
));
1769 return enabled_array
[index
- VIRT_LOWMEMMAP_LAST
];
1772 static void virt_set_high_memmap(VirtMachineState
*vms
,
1773 hwaddr base
, int pa_bits
)
1775 hwaddr region_base
, region_size
;
1776 bool *region_enabled
, fits
;
1779 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1780 region_enabled
= virt_get_high_memmap_enabled(vms
, i
);
1781 region_base
= ROUND_UP(base
, extended_memmap
[i
].size
);
1782 region_size
= extended_memmap
[i
].size
;
1784 vms
->memmap
[i
].base
= region_base
;
1785 vms
->memmap
[i
].size
= region_size
;
1788 * Check each device to see if it fits in the PA space,
1789 * moving highest_gpa as we go. For compatibility, move
1790 * highest_gpa for disabled fitting devices as well, if
1791 * the compact layout has been disabled.
1793 * For each device that doesn't fit, disable it.
1795 fits
= (region_base
+ region_size
) <= BIT_ULL(pa_bits
);
1796 *region_enabled
&= fits
;
1797 if (vms
->highmem_compact
&& !*region_enabled
) {
1801 base
= region_base
+ region_size
;
1803 vms
->highest_gpa
= base
- 1;
1808 static void virt_set_memmap(VirtMachineState
*vms
, int pa_bits
)
1810 MachineState
*ms
= MACHINE(vms
);
1811 hwaddr base
, device_memory_base
, device_memory_size
, memtop
;
1814 vms
->memmap
= extended_memmap
;
1816 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1817 vms
->memmap
[i
] = base_memmap
[i
];
1820 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1821 error_report("unsupported number of memory slots: %"PRIu64
,
1827 * !highmem is exactly the same as limiting the PA space to 32bit,
1828 * irrespective of the underlying capabilities of the HW.
1830 if (!vms
->highmem
) {
1835 * We compute the base of the high IO region depending on the
1836 * amount of initial and device memory. The device memory start/size
1837 * is aligned on 1GiB. We never put the high IO region below 256GiB
1838 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1839 * The device region size assumes 1GiB page max alignment per slot.
1841 device_memory_base
=
1842 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1843 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1845 /* Base address of the high IO region */
1846 memtop
= base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1847 if (memtop
> BIT_ULL(pa_bits
)) {
1848 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes",
1849 pa_bits
, memtop
- BIT_ULL(pa_bits
));
1852 if (base
< device_memory_base
) {
1853 error_report("maxmem/slots too huge");
1856 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1857 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1860 /* We know for sure that at least the memory fits in the PA space */
1861 vms
->highest_gpa
= memtop
- 1;
1863 virt_set_high_memmap(vms
, base
, pa_bits
);
1865 if (device_memory_size
> 0) {
1866 machine_memory_devices_init(ms
, device_memory_base
, device_memory_size
);
1870 static VirtGICType
finalize_gic_version_do(const char *accel_name
,
1871 VirtGICType gic_version
,
1873 unsigned int max_cpus
)
1875 /* Convert host/max/nosel to GIC version number */
1876 switch (gic_version
) {
1877 case VIRT_GIC_VERSION_HOST
:
1878 if (!kvm_enabled()) {
1879 error_report("gic-version=host requires KVM");
1883 /* For KVM, gic-version=host means gic-version=max */
1884 return finalize_gic_version_do(accel_name
, VIRT_GIC_VERSION_MAX
,
1885 gics_supported
, max_cpus
);
1886 case VIRT_GIC_VERSION_MAX
:
1887 if (gics_supported
& VIRT_GIC_VERSION_4_MASK
) {
1888 gic_version
= VIRT_GIC_VERSION_4
;
1889 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1890 gic_version
= VIRT_GIC_VERSION_3
;
1892 gic_version
= VIRT_GIC_VERSION_2
;
1895 case VIRT_GIC_VERSION_NOSEL
:
1896 if ((gics_supported
& VIRT_GIC_VERSION_2_MASK
) &&
1897 max_cpus
<= GIC_NCPU
) {
1898 gic_version
= VIRT_GIC_VERSION_2
;
1899 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1901 * in case the host does not support v2 emulation or
1902 * the end-user requested more than 8 VCPUs we now default
1903 * to v3. In any case defaulting to v2 would be broken.
1905 gic_version
= VIRT_GIC_VERSION_3
;
1906 } else if (max_cpus
> GIC_NCPU
) {
1907 error_report("%s only supports GICv2 emulation but more than 8 "
1908 "vcpus are requested", accel_name
);
1912 case VIRT_GIC_VERSION_2
:
1913 case VIRT_GIC_VERSION_3
:
1914 case VIRT_GIC_VERSION_4
:
1918 /* Check chosen version is effectively supported */
1919 switch (gic_version
) {
1920 case VIRT_GIC_VERSION_2
:
1921 if (!(gics_supported
& VIRT_GIC_VERSION_2_MASK
)) {
1922 error_report("%s does not support GICv2 emulation", accel_name
);
1926 case VIRT_GIC_VERSION_3
:
1927 if (!(gics_supported
& VIRT_GIC_VERSION_3_MASK
)) {
1928 error_report("%s does not support GICv3 emulation", accel_name
);
1932 case VIRT_GIC_VERSION_4
:
1933 if (!(gics_supported
& VIRT_GIC_VERSION_4_MASK
)) {
1934 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1940 error_report("logic error in finalize_gic_version");
1949 * finalize_gic_version - Determines the final gic_version
1950 * according to the gic-version property
1952 * Default GIC type is v2
1954 static void finalize_gic_version(VirtMachineState
*vms
)
1956 const char *accel_name
= current_accel_name();
1957 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1958 int gics_supported
= 0;
1960 /* Determine which GIC versions the current environment supports */
1961 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1962 int probe_bitmap
= kvm_arm_vgic_probe();
1964 if (!probe_bitmap
) {
1965 error_report("Unable to determine GIC version supported by host");
1969 if (probe_bitmap
& KVM_ARM_VGIC_V2
) {
1970 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1972 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1973 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1975 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
1976 /* KVM w/o kernel irqchip can only deal with GICv2 */
1977 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1978 accel_name
= "KVM with kernel-irqchip=off";
1979 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
1980 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1981 if (module_object_class_by_name("arm-gicv3")) {
1982 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1984 /* GICv4 only makes sense if CPU has EL2 */
1985 gics_supported
|= VIRT_GIC_VERSION_4_MASK
;
1989 error_report("Unsupported accelerator, can not determine GIC support");
1994 * Then convert helpers like host/max to concrete GIC versions and ensure
1995 * the desired version is supported
1997 vms
->gic_version
= finalize_gic_version_do(accel_name
, vms
->gic_version
,
1998 gics_supported
, max_cpus
);
2002 * virt_cpu_post_init() must be called after the CPUs have
2003 * been realized and the GIC has been created.
2005 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
2007 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
2008 bool aarch64
, pmu
, steal_time
;
2011 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
2012 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
2013 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
2014 "kvm-steal-time", NULL
);
2016 if (kvm_enabled()) {
2017 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
2018 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
2021 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
2022 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
2024 /* The memory region size must be a multiple of host page size. */
2025 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
2027 if (pvtime_size
> pvtime_reg_size
) {
2028 error_report("pvtime requires a %" HWADDR_PRId
2029 " byte memory region for %d CPUs,"
2030 " but only %" HWADDR_PRId
" has been reserved",
2031 pvtime_size
, max_cpus
, pvtime_reg_size
);
2035 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
2036 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
2041 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
2042 if (kvm_irqchip_in_kernel()) {
2043 kvm_arm_pmu_set_irq(ARM_CPU(cpu
), VIRTUAL_PMU_IRQ
);
2045 kvm_arm_pmu_init(ARM_CPU(cpu
));
2048 kvm_arm_pvtime_init(ARM_CPU(cpu
), pvtime_reg_base
2050 * PVTIME_SIZE_PER_CPU
);
2054 if (aarch64
&& vms
->highmem
) {
2055 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2056 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
2058 if (pamax
< requested_pa_size
) {
2059 error_report("VCPU supports less PA bits (%d) than "
2060 "requested by the memory map (%d)",
2061 pamax
, requested_pa_size
);
2068 static void machvirt_init(MachineState
*machine
)
2070 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
2071 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
2072 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2073 const CPUArchIdList
*possible_cpus
;
2074 MemoryRegion
*sysmem
= get_system_memory();
2075 MemoryRegion
*secure_sysmem
= NULL
;
2076 MemoryRegion
*tag_sysmem
= NULL
;
2077 MemoryRegion
*secure_tag_sysmem
= NULL
;
2078 int n
, virt_max_cpus
;
2079 bool firmware_loaded
;
2080 bool aarch64
= true;
2081 bool has_ged
= !vmc
->no_ged
;
2082 unsigned int smp_cpus
= machine
->smp
.cpus
;
2083 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2085 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2088 * In accelerated mode, the memory map is computed earlier in kvm_type()
2089 * to create a VM with the right number of IPA bits.
2097 * Instantiate a temporary CPU object to find out about what
2098 * we are about to deal with. Once this is done, get rid of
2101 cpuobj
= object_new(possible_cpus
->cpus
[0].type
);
2102 armcpu
= ARM_CPU(cpuobj
);
2104 pa_bits
= arm_pamax(armcpu
);
2106 object_unref(cpuobj
);
2108 virt_set_memmap(vms
, pa_bits
);
2111 /* We can probe only here because during property set
2112 * KVM is not available yet
2114 finalize_gic_version(vms
);
2118 * The Secure view of the world is the same as the NonSecure,
2119 * but with a few extra devices. Create it as a container region
2120 * containing the system memory at low priority; any secure-only
2121 * devices go in at higher priority and take precedence.
2123 secure_sysmem
= g_new(MemoryRegion
, 1);
2124 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
2126 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
2129 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
2130 secure_sysmem
?: sysmem
);
2132 /* If we have an EL3 boot ROM then the assumption is that it will
2133 * implement PSCI itself, so disable QEMU's internal implementation
2134 * so it doesn't get in the way. Instead of starting secondary
2135 * CPUs in PSCI powerdown state we will start them all running and
2136 * let the boot ROM sort them out.
2137 * The usual case is that we do use QEMU's PSCI implementation;
2138 * if the guest has EL2 then we will use SMC as the conduit,
2139 * and otherwise we will use HVC (for backwards compatibility and
2140 * because if we're using KVM then we must use HVC).
2142 if (vms
->secure
&& firmware_loaded
) {
2143 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
2144 } else if (vms
->virt
) {
2145 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
2147 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
2151 * The maximum number of CPUs depends on the GIC version, or on how
2152 * many redistributors we can fit into the memory map (which in turn
2153 * depends on whether this is a GICv3 or v4).
2155 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
2156 virt_max_cpus
= GIC_NCPU
;
2158 virt_max_cpus
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
2159 if (vms
->highmem_redists
) {
2160 virt_max_cpus
+= virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
2164 if (max_cpus
> virt_max_cpus
) {
2165 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2166 "supported by machine 'mach-virt' (%d)",
2167 max_cpus
, virt_max_cpus
);
2168 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& !vms
->highmem_redists
) {
2169 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2175 if (vms
->secure
&& (kvm_enabled() || hvf_enabled())) {
2176 error_report("mach-virt: %s does not support providing "
2177 "Security extensions (TrustZone) to the guest CPU",
2178 current_accel_name());
2182 if (vms
->virt
&& (kvm_enabled() || hvf_enabled())) {
2183 error_report("mach-virt: %s does not support providing "
2184 "Virtualization extensions to the guest CPU",
2185 current_accel_name());
2189 if (vms
->mte
&& (kvm_enabled() || hvf_enabled())) {
2190 error_report("mach-virt: %s does not support providing "
2191 "MTE to the guest CPU",
2192 current_accel_name());
2198 assert(possible_cpus
->len
== max_cpus
);
2199 for (n
= 0; n
< possible_cpus
->len
; n
++) {
2203 if (n
>= smp_cpus
) {
2207 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
2208 object_property_set_int(cpuobj
, "mp-affinity",
2209 possible_cpus
->cpus
[n
].arch_id
, NULL
);
2214 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
2217 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
2220 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
2223 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
2224 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
2227 if (vmc
->kvm_no_adjvtime
&&
2228 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
2229 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
2232 if (vmc
->no_kvm_steal_time
&&
2233 object_property_find(cpuobj
, "kvm-steal-time")) {
2234 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
2237 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
2238 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
2241 if (vmc
->no_tcg_lpa2
&& object_property_find(cpuobj
, "lpa2")) {
2242 object_property_set_bool(cpuobj
, "lpa2", false, NULL
);
2245 if (object_property_find(cpuobj
, "reset-cbar")) {
2246 object_property_set_int(cpuobj
, "reset-cbar",
2247 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
2251 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
2254 object_property_set_link(cpuobj
, "secure-memory",
2255 OBJECT(secure_sysmem
), &error_abort
);
2259 /* Create the memory region only once, but link to all cpus. */
2262 * The property exists only if MemTag is supported.
2263 * If it is, we must allocate the ram to back that up.
2265 if (!object_property_find(cpuobj
, "tag-memory")) {
2266 error_report("MTE requested, but not supported "
2267 "by the guest CPU");
2271 tag_sysmem
= g_new(MemoryRegion
, 1);
2272 memory_region_init(tag_sysmem
, OBJECT(machine
),
2273 "tag-memory", UINT64_MAX
/ 32);
2276 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2277 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2278 "secure-tag-memory", UINT64_MAX
/ 32);
2280 /* As with ram, secure-tag takes precedence over tag. */
2281 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2286 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2289 object_property_set_link(cpuobj
, "secure-tag-memory",
2290 OBJECT(secure_tag_sysmem
),
2295 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2296 object_unref(cpuobj
);
2299 /* Now we've created the CPUs we can see if they have the hypvirt timer */
2300 vms
->ns_el2_virt_timer_irq
= ns_el2_virt_timer_present() &&
2301 !vmc
->no_ns_el2_virt_timer_irq
;
2303 fdt_add_timer_nodes(vms
);
2304 fdt_add_cpu_nodes(vms
);
2306 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2309 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2311 create_gic(vms
, sysmem
);
2313 virt_cpu_post_init(vms
, sysmem
);
2315 fdt_add_pmu_nodes(vms
);
2317 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2320 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2321 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2325 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2326 machine
->ram_size
, "mach-virt.tag");
2329 vms
->highmem_ecam
&= (!firmware_loaded
|| aarch64
);
2335 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2336 vms
->acpi_dev
= create_acpi_ged(vms
);
2338 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2341 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2342 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2345 /* connect powerdown request */
2346 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2347 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2349 /* Create mmio transports, so the user can create virtio backends
2350 * (which will be automatically plugged in to the transports). If
2351 * no backend is created the transport will just sit harmlessly idle.
2353 create_virtio_devices(vms
);
2355 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2356 rom_set_fw(vms
->fw_cfg
);
2358 create_platform_bus(vms
);
2360 if (machine
->nvdimms_state
->is_enabled
) {
2361 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2362 .space_id
= AML_AS_SYSTEM_MEMORY
,
2363 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2364 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2367 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2368 arm_virt_nvdimm_acpi_dsmio
,
2369 vms
->fw_cfg
, OBJECT(vms
));
2372 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2373 vms
->bootinfo
.board_id
= -1;
2374 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2375 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2376 vms
->bootinfo
.skip_dtb_autoload
= true;
2377 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2378 vms
->bootinfo
.psci_conduit
= vms
->psci_conduit
;
2379 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2381 vms
->machine_done
.notify
= virt_machine_done
;
2382 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2385 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2387 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2392 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2394 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2396 vms
->secure
= value
;
2399 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2401 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2406 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2408 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2413 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2415 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2417 return vms
->highmem
;
2420 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2422 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2424 vms
->highmem
= value
;
2427 static bool virt_get_compact_highmem(Object
*obj
, Error
**errp
)
2429 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2431 return vms
->highmem_compact
;
2434 static void virt_set_compact_highmem(Object
*obj
, bool value
, Error
**errp
)
2436 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2438 vms
->highmem_compact
= value
;
2441 static bool virt_get_highmem_redists(Object
*obj
, Error
**errp
)
2443 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2445 return vms
->highmem_redists
;
2448 static void virt_set_highmem_redists(Object
*obj
, bool value
, Error
**errp
)
2450 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2452 vms
->highmem_redists
= value
;
2455 static bool virt_get_highmem_ecam(Object
*obj
, Error
**errp
)
2457 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2459 return vms
->highmem_ecam
;
2462 static void virt_set_highmem_ecam(Object
*obj
, bool value
, Error
**errp
)
2464 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2466 vms
->highmem_ecam
= value
;
2469 static bool virt_get_highmem_mmio(Object
*obj
, Error
**errp
)
2471 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2473 return vms
->highmem_mmio
;
2476 static void virt_set_highmem_mmio(Object
*obj
, bool value
, Error
**errp
)
2478 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2480 vms
->highmem_mmio
= value
;
2484 static bool virt_get_its(Object
*obj
, Error
**errp
)
2486 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2491 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2493 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2498 static bool virt_get_dtb_randomness(Object
*obj
, Error
**errp
)
2500 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2502 return vms
->dtb_randomness
;
2505 static void virt_set_dtb_randomness(Object
*obj
, bool value
, Error
**errp
)
2507 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2509 vms
->dtb_randomness
= value
;
2512 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2514 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2516 return g_strdup(vms
->oem_id
);
2519 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2521 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2522 size_t len
= strlen(value
);
2526 "User specified oem-id value is bigger than 6 bytes in size");
2530 strncpy(vms
->oem_id
, value
, 6);
2533 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2535 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2537 return g_strdup(vms
->oem_table_id
);
2540 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2543 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2544 size_t len
= strlen(value
);
2548 "User specified oem-table-id value is bigger than 8 bytes in size");
2551 strncpy(vms
->oem_table_id
, value
, 8);
2555 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2557 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2563 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2564 void *opaque
, Error
**errp
)
2566 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2567 OnOffAuto acpi
= vms
->acpi
;
2569 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2572 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2573 void *opaque
, Error
**errp
)
2575 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2577 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2580 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2582 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2587 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2589 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2594 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2596 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2601 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2603 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2608 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2610 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2613 switch (vms
->gic_version
) {
2614 case VIRT_GIC_VERSION_4
:
2617 case VIRT_GIC_VERSION_3
:
2624 return g_strdup(val
);
2627 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2629 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2631 if (!strcmp(value
, "4")) {
2632 vms
->gic_version
= VIRT_GIC_VERSION_4
;
2633 } else if (!strcmp(value
, "3")) {
2634 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2635 } else if (!strcmp(value
, "2")) {
2636 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2637 } else if (!strcmp(value
, "host")) {
2638 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2639 } else if (!strcmp(value
, "max")) {
2640 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2642 error_setg(errp
, "Invalid gic-version value");
2643 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2647 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2649 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2651 switch (vms
->iommu
) {
2652 case VIRT_IOMMU_NONE
:
2653 return g_strdup("none");
2654 case VIRT_IOMMU_SMMUV3
:
2655 return g_strdup("smmuv3");
2657 g_assert_not_reached();
2661 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2663 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2665 if (!strcmp(value
, "smmuv3")) {
2666 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2667 } else if (!strcmp(value
, "none")) {
2668 vms
->iommu
= VIRT_IOMMU_NONE
;
2670 error_setg(errp
, "Invalid iommu value");
2671 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2675 static bool virt_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
2677 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2679 return vms
->default_bus_bypass_iommu
;
2682 static void virt_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
2685 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2687 vms
->default_bus_bypass_iommu
= value
;
2690 static CpuInstanceProperties
2691 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2693 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2694 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2696 assert(cpu_index
< possible_cpus
->len
);
2697 return possible_cpus
->cpus
[cpu_index
].props
;
2700 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2702 int64_t socket_id
= ms
->possible_cpus
->cpus
[idx
].props
.socket_id
;
2704 return socket_id
% ms
->numa_state
->num_nodes
;
2707 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2710 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2711 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2712 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2714 if (ms
->possible_cpus
) {
2715 assert(ms
->possible_cpus
->len
== max_cpus
);
2716 return ms
->possible_cpus
;
2719 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2720 sizeof(CPUArchId
) * max_cpus
);
2721 ms
->possible_cpus
->len
= max_cpus
;
2722 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2723 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2724 ms
->possible_cpus
->cpus
[n
].arch_id
=
2725 virt_cpu_mp_affinity(vms
, n
);
2727 assert(!mc
->smp_props
.dies_supported
);
2728 ms
->possible_cpus
->cpus
[n
].props
.has_socket_id
= true;
2729 ms
->possible_cpus
->cpus
[n
].props
.socket_id
=
2730 n
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
);
2731 ms
->possible_cpus
->cpus
[n
].props
.has_cluster_id
= true;
2732 ms
->possible_cpus
->cpus
[n
].props
.cluster_id
=
2733 (n
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
;
2734 ms
->possible_cpus
->cpus
[n
].props
.has_core_id
= true;
2735 ms
->possible_cpus
->cpus
[n
].props
.core_id
=
2736 (n
/ ms
->smp
.threads
) % ms
->smp
.cores
;
2737 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2738 ms
->possible_cpus
->cpus
[n
].props
.thread_id
=
2739 n
% ms
->smp
.threads
;
2741 return ms
->possible_cpus
;
2744 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2747 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2748 const MachineState
*ms
= MACHINE(hotplug_dev
);
2749 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2751 if (!vms
->acpi_dev
) {
2753 "memory hotplug is not enabled: missing acpi-ged device");
2758 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2762 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2763 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2767 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2770 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2771 DeviceState
*dev
, Error
**errp
)
2773 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2774 MachineState
*ms
= MACHINE(hotplug_dev
);
2775 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2777 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2780 nvdimm_plug(ms
->nvdimms_state
);
2783 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2787 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2788 DeviceState
*dev
, Error
**errp
)
2790 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2792 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2793 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2794 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2795 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2796 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2797 hwaddr db_start
= 0, db_end
= 0;
2798 QList
*reserved_regions
;
2799 char *resv_prop_str
;
2801 if (vms
->iommu
!= VIRT_IOMMU_NONE
) {
2802 error_setg(errp
, "virt machine does not support multiple IOMMUs");
2806 switch (vms
->msi_controller
) {
2807 case VIRT_MSI_CTRL_NONE
:
2809 case VIRT_MSI_CTRL_ITS
:
2810 /* GITS_TRANSLATER page */
2811 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2812 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2813 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2815 case VIRT_MSI_CTRL_GICV2M
:
2816 /* MSI_SETSPI_NS page */
2817 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2818 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2821 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2823 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2825 reserved_regions
= qlist_new();
2826 qlist_append_str(reserved_regions
, resv_prop_str
);
2827 qdev_prop_set_array(dev
, "reserved-regions", reserved_regions
);
2828 g_free(resv_prop_str
);
2832 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2833 DeviceState
*dev
, Error
**errp
)
2835 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2837 if (vms
->platform_bus_dev
) {
2838 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2840 if (device_is_dynamic_sysbus(mc
, dev
)) {
2841 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2842 SYS_BUS_DEVICE(dev
));
2846 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2847 virt_memory_plug(hotplug_dev
, dev
, errp
);
2848 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2849 virtio_md_pci_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2852 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2853 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2855 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2856 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2857 create_virtio_iommu_dt_bindings(vms
);
2861 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2862 DeviceState
*dev
, Error
**errp
)
2864 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2866 if (!vms
->acpi_dev
) {
2868 "memory hotplug is not enabled: missing acpi-ged device");
2872 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2873 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
2877 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2881 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2882 DeviceState
*dev
, Error
**errp
)
2884 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2885 Error
*local_err
= NULL
;
2887 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2892 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2893 qdev_unrealize(dev
);
2896 error_propagate(errp
, local_err
);
2899 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2900 DeviceState
*dev
, Error
**errp
)
2902 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2903 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2904 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2905 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
),
2908 error_setg(errp
, "device unplug request for unsupported device"
2909 " type: %s", object_get_typename(OBJECT(dev
)));
2913 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2914 DeviceState
*dev
, Error
**errp
)
2916 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2917 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2918 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2919 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2921 error_setg(errp
, "virt: device unplug for unsupported device"
2922 " type: %s", object_get_typename(OBJECT(dev
)));
2926 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2929 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2931 if (device_is_dynamic_sysbus(mc
, dev
) ||
2932 object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2933 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
) ||
2934 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2935 return HOTPLUG_HANDLER(machine
);
2941 * for arm64 kvm_type [7-0] encodes the requested number of bits
2942 * in the IPA address space
2944 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2946 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2947 int max_vm_pa_size
, requested_pa_size
;
2950 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
2952 /* we freeze the memory map to compute the highest gpa */
2953 virt_set_memmap(vms
, max_vm_pa_size
);
2955 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2958 * KVM requires the IPA size to be at least 32 bits.
2960 if (requested_pa_size
< 32) {
2961 requested_pa_size
= 32;
2964 if (requested_pa_size
> max_vm_pa_size
) {
2965 error_report("-m and ,maxmem option values "
2966 "require an IPA range (%d bits) larger than "
2967 "the one supported by the host (%d bits)",
2968 requested_pa_size
, max_vm_pa_size
);
2972 * We return the requested PA log size, unless KVM only supports
2973 * the implicit legacy 40b IPA setting, in which case the kvm_type
2976 return fixed_ipa
? 0 : requested_pa_size
;
2979 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2981 MachineClass
*mc
= MACHINE_CLASS(oc
);
2982 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2983 static const char * const valid_cpu_types
[] = {
2985 ARM_CPU_TYPE_NAME("cortex-a7"),
2986 ARM_CPU_TYPE_NAME("cortex-a15"),
2987 #ifdef TARGET_AARCH64
2988 ARM_CPU_TYPE_NAME("cortex-a35"),
2989 ARM_CPU_TYPE_NAME("cortex-a55"),
2990 ARM_CPU_TYPE_NAME("cortex-a72"),
2991 ARM_CPU_TYPE_NAME("cortex-a76"),
2992 ARM_CPU_TYPE_NAME("cortex-a710"),
2993 ARM_CPU_TYPE_NAME("a64fx"),
2994 ARM_CPU_TYPE_NAME("neoverse-n1"),
2995 ARM_CPU_TYPE_NAME("neoverse-v1"),
2996 ARM_CPU_TYPE_NAME("neoverse-n2"),
2997 #endif /* TARGET_AARCH64 */
2998 #endif /* CONFIG_TCG */
2999 #ifdef TARGET_AARCH64
3000 ARM_CPU_TYPE_NAME("cortex-a53"),
3001 ARM_CPU_TYPE_NAME("cortex-a57"),
3002 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3003 ARM_CPU_TYPE_NAME("host"),
3004 #endif /* CONFIG_KVM || CONFIG_HVF */
3005 #endif /* TARGET_AARCH64 */
3006 ARM_CPU_TYPE_NAME("max"),
3010 mc
->init
= machvirt_init
;
3011 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
3012 * The value may be reduced later when we have more information about the
3013 * configuration of the particular instance.
3016 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
3017 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
3018 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
3019 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
3021 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
3023 mc
->block_default_type
= IF_VIRTIO
;
3025 mc
->pci_allow_0_address
= true;
3026 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
3027 mc
->minimum_page_bits
= 12;
3028 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
3029 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
3031 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
3033 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("max");
3035 mc
->valid_cpu_types
= valid_cpu_types
;
3036 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
3037 mc
->kvm_type
= virt_kvm_type
;
3038 assert(!mc
->get_hotplug_handler
);
3039 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
3040 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
3041 hc
->plug
= virt_machine_device_plug_cb
;
3042 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
3043 hc
->unplug
= virt_machine_device_unplug_cb
;
3044 mc
->nvdimm_supported
= true;
3045 mc
->smp_props
.clusters_supported
= true;
3046 mc
->auto_enable_numa_with_memhp
= true;
3047 mc
->auto_enable_numa_with_memdev
= true;
3048 /* platform instead of architectural choice */
3049 mc
->cpu_cluster_has_numa_boundary
= true;
3050 mc
->default_ram_id
= "mach-virt.ram";
3051 mc
->default_nic
= "virtio-net-pci";
3053 object_class_property_add(oc
, "acpi", "OnOffAuto",
3054 virt_get_acpi
, virt_set_acpi
,
3056 object_class_property_set_description(oc
, "acpi",
3058 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
3060 object_class_property_set_description(oc
, "secure",
3061 "Set on/off to enable/disable the ARM "
3062 "Security Extensions (TrustZone)");
3064 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
3066 object_class_property_set_description(oc
, "virtualization",
3067 "Set on/off to enable/disable emulating a "
3068 "guest CPU which implements the ARM "
3069 "Virtualization Extensions");
3071 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
3073 object_class_property_set_description(oc
, "highmem",
3074 "Set on/off to enable/disable using "
3075 "physical address space above 32 bits");
3077 object_class_property_add_bool(oc
, "compact-highmem",
3078 virt_get_compact_highmem
,
3079 virt_set_compact_highmem
);
3080 object_class_property_set_description(oc
, "compact-highmem",
3081 "Set on/off to enable/disable compact "
3082 "layout for high memory regions");
3084 object_class_property_add_bool(oc
, "highmem-redists",
3085 virt_get_highmem_redists
,
3086 virt_set_highmem_redists
);
3087 object_class_property_set_description(oc
, "highmem-redists",
3088 "Set on/off to enable/disable high "
3089 "memory region for GICv3 or GICv4 "
3092 object_class_property_add_bool(oc
, "highmem-ecam",
3093 virt_get_highmem_ecam
,
3094 virt_set_highmem_ecam
);
3095 object_class_property_set_description(oc
, "highmem-ecam",
3096 "Set on/off to enable/disable high "
3097 "memory region for PCI ECAM");
3099 object_class_property_add_bool(oc
, "highmem-mmio",
3100 virt_get_highmem_mmio
,
3101 virt_set_highmem_mmio
);
3102 object_class_property_set_description(oc
, "highmem-mmio",
3103 "Set on/off to enable/disable high "
3104 "memory region for PCI MMIO");
3106 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
3107 virt_set_gic_version
);
3108 object_class_property_set_description(oc
, "gic-version",
3110 "Valid values are 2, 3, 4, host and max");
3112 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
3113 object_class_property_set_description(oc
, "iommu",
3114 "Set the IOMMU type. "
3115 "Valid values are none and smmuv3");
3117 object_class_property_add_bool(oc
, "default-bus-bypass-iommu",
3118 virt_get_default_bus_bypass_iommu
,
3119 virt_set_default_bus_bypass_iommu
);
3120 object_class_property_set_description(oc
, "default-bus-bypass-iommu",
3121 "Set on/off to enable/disable "
3122 "bypass_iommu for default root bus");
3124 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
3126 object_class_property_set_description(oc
, "ras",
3127 "Set on/off to enable/disable reporting host memory errors "
3128 "to a KVM guest using ACPI and guest external abort exceptions");
3130 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
3131 object_class_property_set_description(oc
, "mte",
3132 "Set on/off to enable/disable emulating a "
3133 "guest CPU which implements the ARM "
3134 "Memory Tagging Extension");
3136 object_class_property_add_bool(oc
, "its", virt_get_its
,
3138 object_class_property_set_description(oc
, "its",
3139 "Set on/off to enable/disable "
3140 "ITS instantiation");
3142 object_class_property_add_bool(oc
, "dtb-randomness",
3143 virt_get_dtb_randomness
,
3144 virt_set_dtb_randomness
);
3145 object_class_property_set_description(oc
, "dtb-randomness",
3146 "Set off to disable passing random or "
3147 "non-deterministic dtb nodes to guest");
3149 object_class_property_add_bool(oc
, "dtb-kaslr-seed",
3150 virt_get_dtb_randomness
,
3151 virt_set_dtb_randomness
);
3152 object_class_property_set_description(oc
, "dtb-kaslr-seed",
3153 "Deprecated synonym of dtb-randomness");
3155 object_class_property_add_str(oc
, "x-oem-id",
3158 object_class_property_set_description(oc
, "x-oem-id",
3159 "Override the default value of field OEMID "
3160 "in ACPI table header."
3161 "The string may be up to 6 bytes in size");
3164 object_class_property_add_str(oc
, "x-oem-table-id",
3165 virt_get_oem_table_id
,
3166 virt_set_oem_table_id
);
3167 object_class_property_set_description(oc
, "x-oem-table-id",
3168 "Override the default value of field OEM Table ID "
3169 "in ACPI table header."
3170 "The string may be up to 8 bytes in size");
3174 static void virt_instance_init(Object
*obj
)
3176 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
3177 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
3179 /* EL3 is disabled by default on virt: this makes us consistent
3180 * between KVM and TCG for this board, and it also allows us to
3181 * boot UEFI blobs which assume no TrustZone support.
3183 vms
->secure
= false;
3185 /* EL2 is also disabled by default, for similar reasons */
3188 /* High memory is enabled by default */
3189 vms
->highmem
= true;
3190 vms
->highmem_compact
= !vmc
->no_highmem_compact
;
3191 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
3193 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
3194 vms
->highmem_mmio
= true;
3195 vms
->highmem_redists
= true;
3200 /* Default allows ITS instantiation */
3203 if (vmc
->no_tcg_its
) {
3204 vms
->tcg_its
= false;
3206 vms
->tcg_its
= true;
3210 /* Default disallows iommu instantiation */
3211 vms
->iommu
= VIRT_IOMMU_NONE
;
3213 /* The default root bus is attached to iommu by default */
3214 vms
->default_bus_bypass_iommu
= false;
3216 /* Default disallows RAS instantiation */
3219 /* MTE is disabled by default. */
3222 /* Supply kaslr-seed and rng-seed by default */
3223 vms
->dtb_randomness
= true;
3225 vms
->irqmap
= a15irqmap
;
3227 virt_flash_create(vms
);
3229 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
3230 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
3233 static const TypeInfo virt_machine_info
= {
3234 .name
= TYPE_VIRT_MACHINE
,
3235 .parent
= TYPE_MACHINE
,
3237 .instance_size
= sizeof(VirtMachineState
),
3238 .class_size
= sizeof(VirtMachineClass
),
3239 .class_init
= virt_machine_class_init
,
3240 .instance_init
= virt_instance_init
,
3241 .interfaces
= (InterfaceInfo
[]) {
3242 { TYPE_HOTPLUG_HANDLER
},
3247 static void machvirt_machine_init(void)
3249 type_register_static(&virt_machine_info
);
3251 type_init(machvirt_machine_init
);
3253 static void virt_machine_9_1_options(MachineClass
*mc
)
3256 DEFINE_VIRT_MACHINE_AS_LATEST(9, 1)
3258 static void virt_machine_9_0_options(MachineClass
*mc
)
3260 virt_machine_9_1_options(mc
);
3261 compat_props_add(mc
->compat_props
, hw_compat_9_0
, hw_compat_9_0_len
);
3263 DEFINE_VIRT_MACHINE(9, 0)
3265 static void virt_machine_8_2_options(MachineClass
*mc
)
3267 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3269 virt_machine_9_0_options(mc
);
3270 compat_props_add(mc
->compat_props
, hw_compat_8_2
, hw_compat_8_2_len
);
3272 * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
3273 * earlier machines. (Exposing it tickles a bug in older EDK2
3274 * guest BIOS binaries.)
3276 vmc
->no_ns_el2_virt_timer_irq
= true;
3278 DEFINE_VIRT_MACHINE(8, 2)
3280 static void virt_machine_8_1_options(MachineClass
*mc
)
3282 virt_machine_8_2_options(mc
);
3283 compat_props_add(mc
->compat_props
, hw_compat_8_1
, hw_compat_8_1_len
);
3285 DEFINE_VIRT_MACHINE(8, 1)
3287 static void virt_machine_8_0_options(MachineClass
*mc
)
3289 virt_machine_8_1_options(mc
);
3290 compat_props_add(mc
->compat_props
, hw_compat_8_0
, hw_compat_8_0_len
);
3292 DEFINE_VIRT_MACHINE(8, 0)
3294 static void virt_machine_7_2_options(MachineClass
*mc
)
3296 virt_machine_8_0_options(mc
);
3297 compat_props_add(mc
->compat_props
, hw_compat_7_2
, hw_compat_7_2_len
);
3299 DEFINE_VIRT_MACHINE(7, 2)
3301 static void virt_machine_7_1_options(MachineClass
*mc
)
3303 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3305 virt_machine_7_2_options(mc
);
3306 compat_props_add(mc
->compat_props
, hw_compat_7_1
, hw_compat_7_1_len
);
3307 /* Compact layout for high memory regions was introduced with 7.2 */
3308 vmc
->no_highmem_compact
= true;
3310 DEFINE_VIRT_MACHINE(7, 1)
3312 static void virt_machine_7_0_options(MachineClass
*mc
)
3314 virt_machine_7_1_options(mc
);
3315 compat_props_add(mc
->compat_props
, hw_compat_7_0
, hw_compat_7_0_len
);
3317 DEFINE_VIRT_MACHINE(7, 0)
3319 static void virt_machine_6_2_options(MachineClass
*mc
)
3321 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3323 virt_machine_7_0_options(mc
);
3324 compat_props_add(mc
->compat_props
, hw_compat_6_2
, hw_compat_6_2_len
);
3325 vmc
->no_tcg_lpa2
= true;
3327 DEFINE_VIRT_MACHINE(6, 2)
3329 static void virt_machine_6_1_options(MachineClass
*mc
)
3331 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3333 virt_machine_6_2_options(mc
);
3334 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
3335 mc
->smp_props
.prefer_sockets
= true;
3336 vmc
->no_cpu_topology
= true;
3338 /* qemu ITS was introduced with 6.2 */
3339 vmc
->no_tcg_its
= true;
3341 DEFINE_VIRT_MACHINE(6, 1)
3343 static void virt_machine_6_0_options(MachineClass
*mc
)
3345 virt_machine_6_1_options(mc
);
3346 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
3348 DEFINE_VIRT_MACHINE(6, 0)
3350 static void virt_machine_5_2_options(MachineClass
*mc
)
3352 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3354 virt_machine_6_0_options(mc
);
3355 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
3356 vmc
->no_secure_gpio
= true;
3358 DEFINE_VIRT_MACHINE(5, 2)
3360 static void virt_machine_5_1_options(MachineClass
*mc
)
3362 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3364 virt_machine_5_2_options(mc
);
3365 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
3366 vmc
->no_kvm_steal_time
= true;
3368 DEFINE_VIRT_MACHINE(5, 1)
3370 static void virt_machine_5_0_options(MachineClass
*mc
)
3372 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3374 virt_machine_5_1_options(mc
);
3375 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
3376 mc
->numa_mem_supported
= true;
3377 vmc
->acpi_expose_flash
= true;
3378 mc
->auto_enable_numa_with_memdev
= false;
3380 DEFINE_VIRT_MACHINE(5, 0)
3382 static void virt_machine_4_2_options(MachineClass
*mc
)
3384 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3386 virt_machine_5_0_options(mc
);
3387 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
3388 vmc
->kvm_no_adjvtime
= true;
3390 DEFINE_VIRT_MACHINE(4, 2)
3392 static void virt_machine_4_1_options(MachineClass
*mc
)
3394 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3396 virt_machine_4_2_options(mc
);
3397 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
3399 mc
->auto_enable_numa_with_memhp
= false;
3401 DEFINE_VIRT_MACHINE(4, 1)
3403 static void virt_machine_4_0_options(MachineClass
*mc
)
3405 virt_machine_4_1_options(mc
);
3406 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
3408 DEFINE_VIRT_MACHINE(4, 0)
3410 static void virt_machine_3_1_options(MachineClass
*mc
)
3412 virt_machine_4_0_options(mc
);
3413 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
3415 DEFINE_VIRT_MACHINE(3, 1)
3417 static void virt_machine_3_0_options(MachineClass
*mc
)
3419 virt_machine_3_1_options(mc
);
3420 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
3422 DEFINE_VIRT_MACHINE(3, 0)
3424 static void virt_machine_2_12_options(MachineClass
*mc
)
3426 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3428 virt_machine_3_0_options(mc
);
3429 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
3430 vmc
->no_highmem_ecam
= true;
3433 DEFINE_VIRT_MACHINE(2, 12)
3435 static void virt_machine_2_11_options(MachineClass
*mc
)
3437 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3439 virt_machine_2_12_options(mc
);
3440 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
3441 vmc
->smbios_old_sys_ver
= true;
3443 DEFINE_VIRT_MACHINE(2, 11)
3445 static void virt_machine_2_10_options(MachineClass
*mc
)
3447 virt_machine_2_11_options(mc
);
3448 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
3449 /* before 2.11 we never faulted accesses to bad addresses */
3450 mc
->ignore_memory_transaction_failures
= true;
3452 DEFINE_VIRT_MACHINE(2, 10)
3454 static void virt_machine_2_9_options(MachineClass
*mc
)
3456 virt_machine_2_10_options(mc
);
3457 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
3459 DEFINE_VIRT_MACHINE(2, 9)
3461 static void virt_machine_2_8_options(MachineClass
*mc
)
3463 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3465 virt_machine_2_9_options(mc
);
3466 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
3467 /* For 2.8 and earlier we falsely claimed in the DT that
3468 * our timers were edge-triggered, not level-triggered.
3470 vmc
->claim_edge_triggered_timers
= true;
3472 DEFINE_VIRT_MACHINE(2, 8)
3474 static void virt_machine_2_7_options(MachineClass
*mc
)
3476 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3478 virt_machine_2_8_options(mc
);
3479 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
3480 /* ITS was introduced with 2.8 */
3482 /* Stick with 1K pages for migration compatibility */
3483 mc
->minimum_page_bits
= 0;
3485 DEFINE_VIRT_MACHINE(2, 7)
3487 static void virt_machine_2_6_options(MachineClass
*mc
)
3489 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3491 virt_machine_2_7_options(mc
);
3492 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
3493 vmc
->disallow_affinity_adjustment
= true;
3494 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3497 DEFINE_VIRT_MACHINE(2, 6)