2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu-common.h"
33 #include "qemu/datadir.h"
34 #include "qemu/units.h"
35 #include "qemu/option.h"
36 #include "monitor/qdev.h"
37 #include "qapi/error.h"
38 #include "hw/sysbus.h"
39 #include "hw/boards.h"
40 #include "hw/arm/boot.h"
41 #include "hw/arm/primecell.h"
42 #include "hw/arm/virt.h"
43 #include "hw/block/flash.h"
44 #include "hw/vfio/vfio-calxeda-xgmac.h"
45 #include "hw/vfio/vfio-amd-xgbe.h"
46 #include "hw/display/ramfb.h"
48 #include "sysemu/device_tree.h"
49 #include "sysemu/numa.h"
50 #include "sysemu/runstate.h"
51 #include "sysemu/sysemu.h"
52 #include "sysemu/tpm.h"
53 #include "sysemu/kvm.h"
54 #include "hw/loader.h"
55 #include "exec/address-spaces.h"
56 #include "qapi/error.h"
57 #include "qemu/bitops.h"
58 #include "qemu/error-report.h"
59 #include "qemu/module.h"
60 #include "hw/pci-host/gpex.h"
61 #include "hw/virtio/virtio-pci.h"
62 #include "hw/arm/sysbus-fdt.h"
63 #include "hw/platform-bus.h"
64 #include "hw/qdev-properties.h"
65 #include "hw/arm/fdt.h"
66 #include "hw/intc/arm_gic.h"
67 #include "hw/intc/arm_gicv3_common.h"
70 #include "hw/firmware/smbios.h"
71 #include "qapi/visitor.h"
72 #include "qapi/qapi-visit-common.h"
73 #include "standard-headers/linux/input.h"
74 #include "hw/arm/smmuv3.h"
75 #include "hw/acpi/acpi.h"
76 #include "target/arm/internals.h"
77 #include "hw/mem/pc-dimm.h"
78 #include "hw/mem/nvdimm.h"
79 #include "hw/acpi/generic_event_device.h"
80 #include "hw/virtio/virtio-iommu.h"
81 #include "hw/char/pl011.h"
82 #include "qemu/guest-random.h"
84 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
85 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
88 MachineClass *mc = MACHINE_CLASS(oc); \
89 virt_machine_##major##_##minor##_options(mc); \
90 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
95 static const TypeInfo machvirt_##major##_##minor##_info = { \
96 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
97 .parent = TYPE_VIRT_MACHINE, \
98 .class_init = virt_##major##_##minor##_class_init, \
100 static void machvirt_machine_##major##_##minor##_init(void) \
102 type_register_static(&machvirt_##major##_##minor##_info); \
104 type_init(machvirt_machine_##major##_##minor##_init);
106 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
107 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
108 #define DEFINE_VIRT_MACHINE(major, minor) \
109 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
112 /* Number of external interrupt lines to configure the GIC with */
115 #define PLATFORM_BUS_NUM_IRQS 64
117 /* Legacy RAM limit in GB (< version 4.0) */
118 #define LEGACY_RAMLIMIT_GB 255
119 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
121 /* Addresses and sizes of our components.
122 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
123 * 128MB..256MB is used for miscellaneous device I/O.
124 * 256MB..1GB is reserved for possible future PCI support (ie where the
125 * PCI memory window will go if we add a PCI host controller).
126 * 1GB and up is RAM (which may happily spill over into the
127 * high memory region beyond 4GB).
128 * This represents a compromise between how much RAM can be given to
129 * a 32 bit VM and leaving space for expansion and in particular for PCI.
130 * Note that devices should generally be placed at multiples of 0x10000,
131 * to accommodate guests using 64K pages.
133 static const MemMapEntry base_memmap
[] = {
134 /* Space up to 0x8000000 is reserved for a boot ROM */
135 [VIRT_FLASH
] = { 0, 0x08000000 },
136 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
137 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
138 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
139 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
140 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
141 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
142 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
143 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
144 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
145 /* This redistributor space allows up to 2*64kB*123 CPUs */
146 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
147 [VIRT_UART
] = { 0x09000000, 0x00001000 },
148 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
149 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
150 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
151 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
152 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
153 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
154 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
155 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
156 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
157 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
158 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
159 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
160 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
161 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
162 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
163 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
164 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
165 /* Actual RAM size depends on initial RAM and device memory settings */
166 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
170 * Highmem IO Regions: This memory map is floating, located after the RAM.
171 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
172 * top of the RAM, so that its base get the same alignment as the size,
173 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
174 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
175 * Note the extended_memmap is sized so that it eventually also includes the
176 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
177 * index of base_memmap).
179 static MemMapEntry extended_memmap
[] = {
180 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
181 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
182 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
183 /* Second PCIe window */
184 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
187 static const int a15irqmap
[] = {
190 [VIRT_PCIE
] = 3, /* ... to 6 */
192 [VIRT_SECURE_UART
] = 8,
194 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
195 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
196 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
197 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
200 static const char *valid_cpus
[] = {
201 ARM_CPU_TYPE_NAME("cortex-a7"),
202 ARM_CPU_TYPE_NAME("cortex-a15"),
203 ARM_CPU_TYPE_NAME("cortex-a53"),
204 ARM_CPU_TYPE_NAME("cortex-a57"),
205 ARM_CPU_TYPE_NAME("cortex-a72"),
206 ARM_CPU_TYPE_NAME("host"),
207 ARM_CPU_TYPE_NAME("max"),
210 static bool cpu_type_valid(const char *cpu
)
214 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
215 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
222 static void create_kaslr_seed(MachineState
*ms
, const char *node
)
226 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
229 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
);
232 static void create_fdt(VirtMachineState
*vms
)
234 MachineState
*ms
= MACHINE(vms
);
235 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
236 void *fdt
= create_device_tree(&vms
->fdt_size
);
239 error_report("create_device_tree() failed");
246 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
247 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
248 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
250 /* /chosen must exist for load_dtb to fill in necessary properties later */
251 qemu_fdt_add_subnode(fdt
, "/chosen");
252 create_kaslr_seed(ms
, "/chosen");
255 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
256 create_kaslr_seed(ms
, "/secure-chosen");
259 /* Clock node, for the benefit of the UART. The kernel device tree
260 * binding documentation claims the PL011 node clock properties are
261 * optional but in practice if you omit them the kernel refuses to
262 * probe for the device.
264 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
265 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
266 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
267 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
268 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
269 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
271 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
273 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
274 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
275 uint32_t *matrix
= g_malloc0(size
);
278 for (i
= 0; i
< nb_numa_nodes
; i
++) {
279 for (j
= 0; j
< nb_numa_nodes
; j
++) {
280 idx
= (i
* nb_numa_nodes
+ j
) * 3;
281 matrix
[idx
+ 0] = cpu_to_be32(i
);
282 matrix
[idx
+ 1] = cpu_to_be32(j
);
284 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
288 qemu_fdt_add_subnode(fdt
, "/distance-map");
289 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
290 "numa-distance-map-v1");
291 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
297 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
299 /* On real hardware these interrupts are level-triggered.
300 * On KVM they were edge-triggered before host kernel version 4.4,
301 * and level-triggered afterwards.
302 * On emulated QEMU they are level-triggered.
304 * Getting the DTB info about them wrong is awkward for some
306 * pre-4.8 ignore the DT and leave the interrupt configured
307 * with whatever the GIC reset value (or the bootloader) left it at
308 * 4.8 before rc6 honour the incorrect data by programming it back
309 * into the GIC, causing problems
310 * 4.8rc6 and later ignore the DT and always write "level triggered"
313 * For backwards-compatibility, virt-2.8 and earlier will continue
314 * to say these are edge-triggered, but later machines will report
315 * the correct information.
318 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
319 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
320 MachineState
*ms
= MACHINE(vms
);
322 if (vmc
->claim_edge_triggered_timers
) {
323 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
326 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
327 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
328 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
329 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
332 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
334 armcpu
= ARM_CPU(qemu_get_cpu(0));
335 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
336 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
337 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
338 compat
, sizeof(compat
));
340 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
343 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
344 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
345 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
346 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
347 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
348 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
351 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
355 const MachineState
*ms
= MACHINE(vms
);
356 int smp_cpus
= ms
->smp
.cpus
;
359 * From Documentation/devicetree/bindings/arm/cpus.txt
360 * On ARM v8 64-bit systems value should be set to 2,
361 * that corresponds to the MPIDR_EL1 register size.
362 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
363 * in the system, #address-cells can be set to 1, since
364 * MPIDR_EL1[63:32] bits are not used for CPUs
367 * Here we actually don't know whether our system is 32- or 64-bit one.
368 * The simplest way to go is to examine affinity IDs of all our CPUs. If
369 * at least one of them has Aff3 populated, we set #address-cells to 2.
371 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
372 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
374 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
380 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
381 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
382 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
384 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
385 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
386 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
387 CPUState
*cs
= CPU(armcpu
);
389 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
390 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
391 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
392 armcpu
->dtb_compatible
);
394 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
395 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
396 "enable-method", "psci");
399 if (addr_cells
== 2) {
400 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
401 armcpu
->mp_affinity
);
403 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
404 armcpu
->mp_affinity
);
407 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
408 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
409 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
416 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
419 MachineState
*ms
= MACHINE(vms
);
421 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
422 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
423 vms
->memmap
[VIRT_GIC_ITS
].base
);
424 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
425 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
427 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
428 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
429 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
430 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
431 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
435 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
437 MachineState
*ms
= MACHINE(vms
);
440 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
441 vms
->memmap
[VIRT_GIC_V2M
].base
);
442 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
443 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
444 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
445 "arm,gic-v2m-frame");
446 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
447 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
448 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
449 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
450 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
454 static void fdt_add_gic_node(VirtMachineState
*vms
)
456 MachineState
*ms
= MACHINE(vms
);
459 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
460 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
462 nodename
= g_strdup_printf("/intc@%" PRIx64
,
463 vms
->memmap
[VIRT_GIC_DIST
].base
);
464 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
465 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
466 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
467 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
468 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
469 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
470 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
471 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
473 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
476 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
477 "#redistributor-regions", nb_redist_regions
);
479 if (nb_redist_regions
== 1) {
480 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
481 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
482 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
483 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
484 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
486 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
487 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
488 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
489 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
490 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
491 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
492 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
496 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
497 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
498 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
501 /* 'cortex-a15-gic' means 'GIC v2' */
502 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
503 "arm,cortex-a15-gic");
505 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
506 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
507 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
508 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
509 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
511 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
512 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
513 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
514 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
515 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
516 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
517 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
518 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
519 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
520 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
521 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
522 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
526 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
530 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
532 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
533 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
534 MachineState
*ms
= MACHINE(vms
);
536 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
537 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
541 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
542 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
543 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
544 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
547 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
548 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
549 const char compat
[] = "arm,armv8-pmuv3";
550 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
551 compat
, sizeof(compat
));
552 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
553 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
557 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
560 MachineState
*ms
= MACHINE(vms
);
561 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
562 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
565 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
568 if (ms
->nvdimms_state
->is_enabled
) {
569 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
572 dev
= qdev_new(TYPE_ACPI_GED
);
573 qdev_prop_set_uint32(dev
, "ged-event", event
);
575 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
576 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
577 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
579 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
584 static void create_its(VirtMachineState
*vms
)
586 const char *itsclass
= its_class_name();
590 /* Do nothing if not supported */
594 dev
= qdev_new(itsclass
);
596 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
598 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
599 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
601 fdt_add_its_gic_node(vms
);
602 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
605 static void create_v2m(VirtMachineState
*vms
)
608 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
611 dev
= qdev_new("arm-gicv2m");
612 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
613 qdev_prop_set_uint32(dev
, "base-spi", irq
);
614 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
615 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
617 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
618 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
619 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
622 fdt_add_v2m_gic_node(vms
);
623 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
626 static void create_gic(VirtMachineState
*vms
)
628 MachineState
*ms
= MACHINE(vms
);
629 /* We create a standalone GIC */
630 SysBusDevice
*gicbusdev
;
632 int type
= vms
->gic_version
, i
;
633 unsigned int smp_cpus
= ms
->smp
.cpus
;
634 uint32_t nb_redist_regions
= 0;
636 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
638 vms
->gic
= qdev_new(gictype
);
639 qdev_prop_set_uint32(vms
->gic
, "revision", type
);
640 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
641 /* Note that the num-irq property counts both internal and external
642 * interrupts; there are always 32 of the former (mandated by GIC spec).
644 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
645 if (!kvm_irqchip_in_kernel()) {
646 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
650 uint32_t redist0_capacity
=
651 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
652 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
654 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
656 qdev_prop_set_uint32(vms
->gic
, "len-redist-region-count",
658 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[0]", redist0_count
);
660 if (nb_redist_regions
== 2) {
661 uint32_t redist1_capacity
=
662 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
664 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[1]",
665 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
668 if (!kvm_irqchip_in_kernel()) {
669 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
673 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
674 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
675 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
677 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
678 if (nb_redist_regions
== 2) {
679 sysbus_mmio_map(gicbusdev
, 2,
680 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
683 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
685 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
686 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
690 /* Wire the outputs from each CPU's generic timer and the GICv3
691 * maintenance interrupt signal to the appropriate GIC PPI inputs,
692 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
694 for (i
= 0; i
< smp_cpus
; i
++) {
695 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
696 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
698 /* Mapping from the output timer irq lines from the CPU to the
699 * GIC PPI inputs we use for the virt board.
701 const int timer_irq
[] = {
702 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
703 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
704 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
705 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
708 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
709 qdev_connect_gpio_out(cpudev
, irq
,
710 qdev_get_gpio_in(vms
->gic
,
711 ppibase
+ timer_irq
[irq
]));
715 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
716 ppibase
+ ARCH_GIC_MAINT_IRQ
);
717 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
719 } else if (vms
->virt
) {
720 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
721 ppibase
+ ARCH_GIC_MAINT_IRQ
);
722 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
725 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
726 qdev_get_gpio_in(vms
->gic
, ppibase
729 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
730 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
731 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
732 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
733 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
734 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
735 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
738 fdt_add_gic_node(vms
);
740 if (type
== 3 && vms
->its
) {
742 } else if (type
== 2) {
747 static void create_uart(const VirtMachineState
*vms
, int uart
,
748 MemoryRegion
*mem
, Chardev
*chr
)
751 hwaddr base
= vms
->memmap
[uart
].base
;
752 hwaddr size
= vms
->memmap
[uart
].size
;
753 int irq
= vms
->irqmap
[uart
];
754 const char compat
[] = "arm,pl011\0arm,primecell";
755 const char clocknames
[] = "uartclk\0apb_pclk";
756 DeviceState
*dev
= qdev_new(TYPE_PL011
);
757 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
758 MachineState
*ms
= MACHINE(vms
);
760 qdev_prop_set_chr(dev
, "chardev", chr
);
761 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
762 memory_region_add_subregion(mem
, base
,
763 sysbus_mmio_get_region(s
, 0));
764 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
766 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
767 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
768 /* Note that we can't use setprop_string because of the embedded NUL */
769 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
770 compat
, sizeof(compat
));
771 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
773 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
774 GIC_FDT_IRQ_TYPE_SPI
, irq
,
775 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
776 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
777 vms
->clock_phandle
, vms
->clock_phandle
);
778 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
779 clocknames
, sizeof(clocknames
));
781 if (uart
== VIRT_UART
) {
782 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
784 /* Mark as not usable by the normal world */
785 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
786 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
788 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
795 static void create_rtc(const VirtMachineState
*vms
)
798 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
799 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
800 int irq
= vms
->irqmap
[VIRT_RTC
];
801 const char compat
[] = "arm,pl031\0arm,primecell";
802 MachineState
*ms
= MACHINE(vms
);
804 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
806 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
807 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
808 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
809 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
811 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
812 GIC_FDT_IRQ_TYPE_SPI
, irq
,
813 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
814 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
815 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
819 static DeviceState
*gpio_key_dev
;
820 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
822 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
825 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
827 /* use gpio Pin 3 for power button event */
828 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
832 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
835 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
836 qdev_get_gpio_in(pl061_dev
, 3));
838 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
839 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
840 qemu_fdt_setprop_cell(fdt
, "/gpio-keys", "#size-cells", 0);
841 qemu_fdt_setprop_cell(fdt
, "/gpio-keys", "#address-cells", 1);
843 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
844 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
845 "label", "GPIO Key Poweroff");
846 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
848 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
849 "gpios", phandle
, 3, 0);
852 #define SECURE_GPIO_POWEROFF 0
853 #define SECURE_GPIO_RESET 1
855 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
858 DeviceState
*gpio_pwr_dev
;
861 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
863 /* connect secure pl061 to gpio-pwr */
864 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
865 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
866 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
867 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
869 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
870 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
872 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
873 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
874 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
875 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
878 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
879 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
881 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
882 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
883 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
884 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
888 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
892 DeviceState
*pl061_dev
;
893 hwaddr base
= vms
->memmap
[gpio
].base
;
894 hwaddr size
= vms
->memmap
[gpio
].size
;
895 int irq
= vms
->irqmap
[gpio
];
896 const char compat
[] = "arm,pl061\0arm,primecell";
898 MachineState
*ms
= MACHINE(vms
);
900 pl061_dev
= qdev_new("pl061");
901 s
= SYS_BUS_DEVICE(pl061_dev
);
902 sysbus_realize_and_unref(s
, &error_fatal
);
903 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
904 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
906 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
907 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
908 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
909 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
911 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
912 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
913 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
914 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
915 GIC_FDT_IRQ_TYPE_SPI
, irq
,
916 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
917 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
918 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
919 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
921 if (gpio
!= VIRT_GPIO
) {
922 /* Mark as not usable by the normal world */
923 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
924 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
928 /* Child gpio devices */
929 if (gpio
== VIRT_GPIO
) {
930 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
932 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
936 static void create_virtio_devices(const VirtMachineState
*vms
)
939 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
940 MachineState
*ms
= MACHINE(vms
);
942 /* We create the transports in forwards order. Since qbus_realize()
943 * prepends (not appends) new child buses, the incrementing loop below will
944 * create a list of virtio-mmio buses with decreasing base addresses.
946 * When a -device option is processed from the command line,
947 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
948 * order. The upshot is that -device options in increasing command line
949 * order are mapped to virtio-mmio buses with decreasing base addresses.
951 * When this code was originally written, that arrangement ensured that the
952 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
953 * the first -device on the command line. (The end-to-end order is a
954 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
955 * guest kernel's name-to-address assignment strategy.)
957 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
958 * the message, if not necessarily the code, of commit 70161ff336.
959 * Therefore the loop now establishes the inverse of the original intent.
961 * Unfortunately, we can't counteract the kernel change by reversing the
962 * loop; it would break existing command lines.
964 * In any case, the kernel makes no guarantee about the stability of
965 * enumeration order of virtio devices (as demonstrated by it changing
966 * between kernel versions). For reliable and stable identification
967 * of disks users must use UUIDs or similar mechanisms.
969 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
970 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
971 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
973 sysbus_create_simple("virtio-mmio", base
,
974 qdev_get_gpio_in(vms
->gic
, irq
));
977 /* We add dtb nodes in reverse order so that they appear in the finished
978 * device tree lowest address first.
980 * Note that this mapping is independent of the loop above. The previous
981 * loop influences virtio device to virtio transport assignment, whereas
982 * this loop controls how virtio transports are laid out in the dtb.
984 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
986 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
987 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
989 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
990 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
991 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
992 "compatible", "virtio,mmio");
993 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
995 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
996 GIC_FDT_IRQ_TYPE_SPI
, irq
,
997 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
998 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1003 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1005 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1007 const char *alias_prop_name
)
1010 * Create a single flash device. We use the same parameters as
1011 * the flash devices on the Versatile Express board.
1013 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1015 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1016 qdev_prop_set_uint8(dev
, "width", 4);
1017 qdev_prop_set_uint8(dev
, "device-width", 2);
1018 qdev_prop_set_bit(dev
, "big-endian", false);
1019 qdev_prop_set_uint16(dev
, "id0", 0x89);
1020 qdev_prop_set_uint16(dev
, "id1", 0x18);
1021 qdev_prop_set_uint16(dev
, "id2", 0x00);
1022 qdev_prop_set_uint16(dev
, "id3", 0x00);
1023 qdev_prop_set_string(dev
, "name", name
);
1024 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1025 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1026 OBJECT(dev
), "drive");
1027 return PFLASH_CFI01(dev
);
1030 static void virt_flash_create(VirtMachineState
*vms
)
1032 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1033 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1036 static void virt_flash_map1(PFlashCFI01
*flash
,
1037 hwaddr base
, hwaddr size
,
1038 MemoryRegion
*sysmem
)
1040 DeviceState
*dev
= DEVICE(flash
);
1042 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1043 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1044 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1045 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1047 memory_region_add_subregion(sysmem
, base
,
1048 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1052 static void virt_flash_map(VirtMachineState
*vms
,
1053 MemoryRegion
*sysmem
,
1054 MemoryRegion
*secure_sysmem
)
1057 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1058 * sysmem is the system memory space. secure_sysmem is the secure view
1059 * of the system, and the first flash device should be made visible only
1060 * there. The second flash device is visible to both secure and nonsecure.
1061 * If sysmem == secure_sysmem this means there is no separate Secure
1062 * address space and both flash devices are generally visible.
1064 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1065 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1067 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1069 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1073 static void virt_flash_fdt(VirtMachineState
*vms
,
1074 MemoryRegion
*sysmem
,
1075 MemoryRegion
*secure_sysmem
)
1077 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1078 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1079 MachineState
*ms
= MACHINE(vms
);
1082 if (sysmem
== secure_sysmem
) {
1083 /* Report both flash devices as a single node in the DT */
1084 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1085 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1086 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1087 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1088 2, flashbase
, 2, flashsize
,
1089 2, flashbase
+ flashsize
, 2, flashsize
);
1090 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1094 * Report the devices as separate nodes so we can mark one as
1095 * only visible to the secure world.
1097 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1098 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1099 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1100 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1101 2, flashbase
, 2, flashsize
);
1102 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1103 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1104 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1107 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1108 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1109 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1110 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1111 2, flashbase
+ flashsize
, 2, flashsize
);
1112 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1117 static bool virt_firmware_init(VirtMachineState
*vms
,
1118 MemoryRegion
*sysmem
,
1119 MemoryRegion
*secure_sysmem
)
1122 const char *bios_name
;
1123 BlockBackend
*pflash_blk0
;
1125 /* Map legacy -drive if=pflash to machine properties */
1126 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1127 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1128 drive_get(IF_PFLASH
, 0, i
));
1131 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1133 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1135 bios_name
= MACHINE(vms
)->firmware
;
1142 error_report("The contents of the first flash device may be "
1143 "specified with -bios or with -drive if=pflash... "
1144 "but you cannot use both options at once");
1148 /* Fall back to -bios */
1150 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1152 error_report("Could not find ROM image '%s'", bios_name
);
1155 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1156 image_size
= load_image_mr(fname
, mr
);
1158 if (image_size
< 0) {
1159 error_report("Could not load ROM image '%s'", bios_name
);
1164 return pflash_blk0
|| bios_name
;
1167 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1169 MachineState
*ms
= MACHINE(vms
);
1170 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1171 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1175 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1176 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1178 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1179 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1180 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1181 "compatible", "qemu,fw-cfg-mmio");
1182 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1184 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1189 static void create_pcie_irq_map(const MachineState
*ms
,
1190 uint32_t gic_phandle
,
1191 int first_irq
, const char *nodename
)
1194 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1195 uint32_t *irq_map
= full_irq_map
;
1197 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1198 for (pin
= 0; pin
< 4; pin
++) {
1199 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1200 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1201 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1205 devfn
<< 8, 0, 0, /* devfn */
1206 pin
+ 1, /* PCI pin */
1207 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1209 /* Convert map to big endian */
1210 for (i
= 0; i
< 10; i
++) {
1211 irq_map
[i
] = cpu_to_be32(map
[i
]);
1217 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1218 full_irq_map
, sizeof(full_irq_map
));
1220 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1221 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1226 static void create_smmu(const VirtMachineState
*vms
,
1230 const char compat
[] = "arm,smmu-v3";
1231 int irq
= vms
->irqmap
[VIRT_SMMU
];
1233 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1234 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1235 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1237 MachineState
*ms
= MACHINE(vms
);
1239 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1243 dev
= qdev_new("arm-smmuv3");
1245 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1247 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1248 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1249 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1250 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1251 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1254 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1255 qemu_fdt_add_subnode(ms
->fdt
, node
);
1256 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1257 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1259 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1260 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1261 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1262 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1263 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1265 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1268 qemu_fdt_setprop_cell(ms
->fdt
, node
, "clocks", vms
->clock_phandle
);
1269 qemu_fdt_setprop_string(ms
->fdt
, node
, "clock-names", "apb_pclk");
1270 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1272 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1274 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1278 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1280 const char compat
[] = "virtio,pci-iommu";
1281 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1282 MachineState
*ms
= MACHINE(vms
);
1285 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1287 node
= g_strdup_printf("%s/virtio_iommu@%d", vms
->pciehb_nodename
, bdf
);
1288 qemu_fdt_add_subnode(ms
->fdt
, node
);
1289 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1290 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1291 1, bdf
<< 8, 1, 0, 1, 0,
1294 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1295 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1298 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1299 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1300 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1303 static void create_pcie(VirtMachineState
*vms
)
1305 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1306 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1307 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1308 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1309 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1310 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1311 hwaddr base_ecam
, size_ecam
;
1312 hwaddr base
= base_mmio
;
1314 int irq
= vms
->irqmap
[VIRT_PCIE
];
1315 MemoryRegion
*mmio_alias
;
1316 MemoryRegion
*mmio_reg
;
1317 MemoryRegion
*ecam_alias
;
1318 MemoryRegion
*ecam_reg
;
1323 MachineState
*ms
= MACHINE(vms
);
1325 dev
= qdev_new(TYPE_GPEX_HOST
);
1326 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1328 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1329 base_ecam
= vms
->memmap
[ecam_id
].base
;
1330 size_ecam
= vms
->memmap
[ecam_id
].size
;
1331 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1332 /* Map only the first size_ecam bytes of ECAM space */
1333 ecam_alias
= g_new0(MemoryRegion
, 1);
1334 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1335 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1336 ecam_reg
, 0, size_ecam
);
1337 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1339 /* Map the MMIO window into system address space so as to expose
1340 * the section of PCI MMIO space which starts at the same base address
1341 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1344 mmio_alias
= g_new0(MemoryRegion
, 1);
1345 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1346 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1347 mmio_reg
, base_mmio
, size_mmio
);
1348 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1351 /* Map high MMIO space */
1352 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1354 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1355 mmio_reg
, base_mmio_high
, size_mmio_high
);
1356 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1360 /* Map IO port space */
1361 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1363 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1364 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1365 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1366 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1369 pci
= PCI_HOST_BRIDGE(dev
);
1370 vms
->bus
= pci
->bus
;
1372 for (i
= 0; i
< nb_nics
; i
++) {
1373 NICInfo
*nd
= &nd_table
[i
];
1376 nd
->model
= g_strdup("virtio");
1379 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1383 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1384 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1385 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1386 "compatible", "pci-host-ecam-generic");
1387 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1388 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1389 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1390 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1391 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1393 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1395 if (vms
->msi_phandle
) {
1396 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-parent",
1400 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1401 2, base_ecam
, 2, size_ecam
);
1404 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1405 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1406 2, base_pio
, 2, size_pio
,
1407 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1408 2, base_mmio
, 2, size_mmio
,
1409 1, FDT_PCI_RANGE_MMIO_64BIT
,
1411 2, base_mmio_high
, 2, size_mmio_high
);
1413 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1414 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1415 2, base_pio
, 2, size_pio
,
1416 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1417 2, base_mmio
, 2, size_mmio
);
1420 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1421 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1424 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1426 switch (vms
->iommu
) {
1427 case VIRT_IOMMU_SMMUV3
:
1428 create_smmu(vms
, vms
->bus
);
1429 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1430 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1433 g_assert_not_reached();
1438 static void create_platform_bus(VirtMachineState
*vms
)
1443 MemoryRegion
*sysmem
= get_system_memory();
1445 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1446 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1447 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1448 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1449 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1450 vms
->platform_bus_dev
= dev
;
1452 s
= SYS_BUS_DEVICE(dev
);
1453 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1454 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1455 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1458 memory_region_add_subregion(sysmem
,
1459 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1460 sysbus_mmio_get_region(s
, 0));
1463 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1464 hwaddr base
, hwaddr size
,
1467 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1469 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1470 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1473 static void create_secure_ram(VirtMachineState
*vms
,
1474 MemoryRegion
*secure_sysmem
,
1475 MemoryRegion
*secure_tag_sysmem
)
1477 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1479 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1480 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1481 MachineState
*ms
= MACHINE(vms
);
1483 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1485 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1487 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1488 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1489 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1490 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1491 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1492 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1494 if (secure_tag_sysmem
) {
1495 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1501 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1503 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1505 MachineState
*ms
= MACHINE(board
);
1508 *fdt_size
= board
->fdt_size
;
1512 static void virt_build_smbios(VirtMachineState
*vms
)
1514 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1515 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1516 uint8_t *smbios_tables
, *smbios_anchor
;
1517 size_t smbios_tables_len
, smbios_anchor_len
;
1518 const char *product
= "QEMU Virtual Machine";
1520 if (kvm_enabled()) {
1521 product
= "KVM Virtual Machine";
1524 smbios_set_defaults("QEMU", product
,
1525 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1526 true, SMBIOS_ENTRY_POINT_30
);
1528 smbios_get_tables(MACHINE(vms
), NULL
, 0,
1529 &smbios_tables
, &smbios_tables_len
,
1530 &smbios_anchor
, &smbios_anchor_len
,
1533 if (smbios_anchor
) {
1534 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1535 smbios_tables
, smbios_tables_len
);
1536 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1537 smbios_anchor
, smbios_anchor_len
);
1542 void virt_machine_done(Notifier
*notifier
, void *data
)
1544 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1546 MachineState
*ms
= MACHINE(vms
);
1547 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1548 struct arm_boot_info
*info
= &vms
->bootinfo
;
1549 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1552 * If the user provided a dtb, we assume the dynamic sysbus nodes
1553 * already are integrated there. This corresponds to a use case where
1554 * the dynamic sysbus nodes are complex and their generation is not yet
1555 * supported. In that case the user can take charge of the guest dt
1556 * while qemu takes charge of the qom stuff.
1558 if (info
->dtb_filename
== NULL
) {
1559 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1560 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1561 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1562 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1564 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1568 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1570 virt_acpi_setup(vms
);
1571 virt_build_smbios(vms
);
1574 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1576 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1577 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1579 if (!vmc
->disallow_affinity_adjustment
) {
1580 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1581 * GIC's target-list limitations. 32-bit KVM hosts currently
1582 * always create clusters of 4 CPUs, but that is expected to
1583 * change when they gain support for gicv3. When KVM is enabled
1584 * it will override the changes we make here, therefore our
1585 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1586 * and to improve SGI efficiency.
1588 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
1589 clustersz
= GICV3_TARGETLIST_BITS
;
1591 clustersz
= GIC_TARGETLIST_BITS
;
1594 return arm_cpu_mp_affinity(idx
, clustersz
);
1597 static void virt_set_memmap(VirtMachineState
*vms
)
1599 MachineState
*ms
= MACHINE(vms
);
1600 hwaddr base
, device_memory_base
, device_memory_size
;
1603 vms
->memmap
= extended_memmap
;
1605 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1606 vms
->memmap
[i
] = base_memmap
[i
];
1609 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1610 error_report("unsupported number of memory slots: %"PRIu64
,
1616 * We compute the base of the high IO region depending on the
1617 * amount of initial and device memory. The device memory start/size
1618 * is aligned on 1GiB. We never put the high IO region below 256GiB
1619 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1620 * The device region size assumes 1GiB page max alignment per slot.
1622 device_memory_base
=
1623 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1624 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1626 /* Base address of the high IO region */
1627 base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1628 if (base
< device_memory_base
) {
1629 error_report("maxmem/slots too huge");
1632 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1633 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1636 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1637 hwaddr size
= extended_memmap
[i
].size
;
1639 base
= ROUND_UP(base
, size
);
1640 vms
->memmap
[i
].base
= base
;
1641 vms
->memmap
[i
].size
= size
;
1644 vms
->highest_gpa
= base
- 1;
1645 if (device_memory_size
> 0) {
1646 ms
->device_memory
= g_malloc0(sizeof(*ms
->device_memory
));
1647 ms
->device_memory
->base
= device_memory_base
;
1648 memory_region_init(&ms
->device_memory
->mr
, OBJECT(vms
),
1649 "device-memory", device_memory_size
);
1654 * finalize_gic_version - Determines the final gic_version
1655 * according to the gic-version property
1657 * Default GIC type is v2
1659 static void finalize_gic_version(VirtMachineState
*vms
)
1661 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1663 if (kvm_enabled()) {
1666 if (!kvm_irqchip_in_kernel()) {
1667 switch (vms
->gic_version
) {
1668 case VIRT_GIC_VERSION_HOST
:
1670 "gic-version=host not relevant with kernel-irqchip=off "
1671 "as only userspace GICv2 is supported. Using v2 ...");
1673 case VIRT_GIC_VERSION_MAX
:
1674 case VIRT_GIC_VERSION_NOSEL
:
1675 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1677 case VIRT_GIC_VERSION_2
:
1679 case VIRT_GIC_VERSION_3
:
1681 "gic-version=3 is not supported with kernel-irqchip=off");
1686 probe_bitmap
= kvm_arm_vgic_probe();
1687 if (!probe_bitmap
) {
1688 error_report("Unable to determine GIC version supported by host");
1692 switch (vms
->gic_version
) {
1693 case VIRT_GIC_VERSION_HOST
:
1694 case VIRT_GIC_VERSION_MAX
:
1695 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1696 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1698 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1701 case VIRT_GIC_VERSION_NOSEL
:
1702 if ((probe_bitmap
& KVM_ARM_VGIC_V2
) && max_cpus
<= GIC_NCPU
) {
1703 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1704 } else if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1706 * in case the host does not support v2 in-kernel emulation or
1707 * the end-user requested more than 8 VCPUs we now default
1708 * to v3. In any case defaulting to v2 would be broken.
1710 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1711 } else if (max_cpus
> GIC_NCPU
) {
1712 error_report("host only supports in-kernel GICv2 emulation "
1713 "but more than 8 vcpus are requested");
1717 case VIRT_GIC_VERSION_2
:
1718 case VIRT_GIC_VERSION_3
:
1722 /* Check chosen version is effectively supported by the host */
1723 if (vms
->gic_version
== VIRT_GIC_VERSION_2
&&
1724 !(probe_bitmap
& KVM_ARM_VGIC_V2
)) {
1725 error_report("host does not support in-kernel GICv2 emulation");
1727 } else if (vms
->gic_version
== VIRT_GIC_VERSION_3
&&
1728 !(probe_bitmap
& KVM_ARM_VGIC_V3
)) {
1729 error_report("host does not support in-kernel GICv3 emulation");
1736 switch (vms
->gic_version
) {
1737 case VIRT_GIC_VERSION_NOSEL
:
1738 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1740 case VIRT_GIC_VERSION_MAX
:
1741 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1743 case VIRT_GIC_VERSION_HOST
:
1744 error_report("gic-version=host requires KVM");
1746 case VIRT_GIC_VERSION_2
:
1747 case VIRT_GIC_VERSION_3
:
1753 * virt_cpu_post_init() must be called after the CPUs have
1754 * been realized and the GIC has been created.
1756 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
1758 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1759 bool aarch64
, pmu
, steal_time
;
1762 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
1763 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
1764 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
1765 "kvm-steal-time", NULL
);
1767 if (kvm_enabled()) {
1768 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
1769 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
1772 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
1773 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
1775 /* The memory region size must be a multiple of host page size. */
1776 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
1778 if (pvtime_size
> pvtime_reg_size
) {
1779 error_report("pvtime requires a %" HWADDR_PRId
1780 " byte memory region for %d CPUs,"
1781 " but only %" HWADDR_PRId
" has been reserved",
1782 pvtime_size
, max_cpus
, pvtime_reg_size
);
1786 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
1787 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
1792 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
1793 if (kvm_irqchip_in_kernel()) {
1794 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
1796 kvm_arm_pmu_init(cpu
);
1799 kvm_arm_pvtime_init(cpu
, pvtime_reg_base
+
1800 cpu
->cpu_index
* PVTIME_SIZE_PER_CPU
);
1804 if (aarch64
&& vms
->highmem
) {
1805 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1806 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
1808 if (pamax
< requested_pa_size
) {
1809 error_report("VCPU supports less PA bits (%d) than "
1810 "requested by the memory map (%d)",
1811 pamax
, requested_pa_size
);
1818 static void machvirt_init(MachineState
*machine
)
1820 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1821 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1822 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1823 const CPUArchIdList
*possible_cpus
;
1824 MemoryRegion
*sysmem
= get_system_memory();
1825 MemoryRegion
*secure_sysmem
= NULL
;
1826 MemoryRegion
*tag_sysmem
= NULL
;
1827 MemoryRegion
*secure_tag_sysmem
= NULL
;
1828 int n
, virt_max_cpus
;
1829 bool firmware_loaded
;
1830 bool aarch64
= true;
1831 bool has_ged
= !vmc
->no_ged
;
1832 unsigned int smp_cpus
= machine
->smp
.cpus
;
1833 unsigned int max_cpus
= machine
->smp
.max_cpus
;
1836 * In accelerated mode, the memory map is computed earlier in kvm_type()
1837 * to create a VM with the right number of IPA bits.
1840 virt_set_memmap(vms
);
1843 /* We can probe only here because during property set
1844 * KVM is not available yet
1846 finalize_gic_version(vms
);
1848 if (!cpu_type_valid(machine
->cpu_type
)) {
1849 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
1854 if (kvm_enabled()) {
1855 error_report("mach-virt: KVM does not support Security extensions");
1860 * The Secure view of the world is the same as the NonSecure,
1861 * but with a few extra devices. Create it as a container region
1862 * containing the system memory at low priority; any secure-only
1863 * devices go in at higher priority and take precedence.
1865 secure_sysmem
= g_new(MemoryRegion
, 1);
1866 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1868 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1871 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
1872 secure_sysmem
?: sysmem
);
1874 /* If we have an EL3 boot ROM then the assumption is that it will
1875 * implement PSCI itself, so disable QEMU's internal implementation
1876 * so it doesn't get in the way. Instead of starting secondary
1877 * CPUs in PSCI powerdown state we will start them all running and
1878 * let the boot ROM sort them out.
1879 * The usual case is that we do use QEMU's PSCI implementation;
1880 * if the guest has EL2 then we will use SMC as the conduit,
1881 * and otherwise we will use HVC (for backwards compatibility and
1882 * because if we're using KVM then we must use HVC).
1884 if (vms
->secure
&& firmware_loaded
) {
1885 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
1886 } else if (vms
->virt
) {
1887 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
1889 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
1892 /* The maximum number of CPUs depends on the GIC version, or on how
1893 * many redistributors we can fit into the memory map.
1895 if (vms
->gic_version
== VIRT_GIC_VERSION_3
) {
1897 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
1899 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
1901 virt_max_cpus
= GIC_NCPU
;
1904 if (max_cpus
> virt_max_cpus
) {
1905 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1906 "supported by machine 'mach-virt' (%d)",
1907 max_cpus
, virt_max_cpus
);
1911 if (vms
->virt
&& kvm_enabled()) {
1912 error_report("mach-virt: KVM does not support providing "
1913 "Virtualization extensions to the guest CPU");
1917 if (vms
->mte
&& kvm_enabled()) {
1918 error_report("mach-virt: KVM does not support providing "
1919 "MTE to the guest CPU");
1925 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1926 assert(possible_cpus
->len
== max_cpus
);
1927 for (n
= 0; n
< possible_cpus
->len
; n
++) {
1931 if (n
>= smp_cpus
) {
1935 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
1936 object_property_set_int(cpuobj
, "mp-affinity",
1937 possible_cpus
->cpus
[n
].arch_id
, NULL
);
1942 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
1945 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
1948 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
1951 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
1952 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
1955 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
) {
1956 object_property_set_int(cpuobj
, "psci-conduit", vms
->psci_conduit
,
1959 /* Secondary CPUs start in PSCI powered-down state */
1961 object_property_set_bool(cpuobj
, "start-powered-off", true,
1966 if (vmc
->kvm_no_adjvtime
&&
1967 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
1968 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
1971 if (vmc
->no_kvm_steal_time
&&
1972 object_property_find(cpuobj
, "kvm-steal-time")) {
1973 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
1976 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
1977 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
1980 if (object_property_find(cpuobj
, "reset-cbar")) {
1981 object_property_set_int(cpuobj
, "reset-cbar",
1982 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1986 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
1989 object_property_set_link(cpuobj
, "secure-memory",
1990 OBJECT(secure_sysmem
), &error_abort
);
1994 /* Create the memory region only once, but link to all cpus. */
1997 * The property exists only if MemTag is supported.
1998 * If it is, we must allocate the ram to back that up.
2000 if (!object_property_find(cpuobj
, "tag-memory")) {
2001 error_report("MTE requested, but not supported "
2002 "by the guest CPU");
2006 tag_sysmem
= g_new(MemoryRegion
, 1);
2007 memory_region_init(tag_sysmem
, OBJECT(machine
),
2008 "tag-memory", UINT64_MAX
/ 32);
2011 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2012 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2013 "secure-tag-memory", UINT64_MAX
/ 32);
2015 /* As with ram, secure-tag takes precedence over tag. */
2016 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2021 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2024 object_property_set_link(cpuobj
, "secure-tag-memory",
2025 OBJECT(secure_tag_sysmem
),
2030 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2031 object_unref(cpuobj
);
2033 fdt_add_timer_nodes(vms
);
2034 fdt_add_cpu_nodes(vms
);
2036 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2038 if (machine
->device_memory
) {
2039 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2040 &machine
->device_memory
->mr
);
2043 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2047 virt_cpu_post_init(vms
, sysmem
);
2049 fdt_add_pmu_nodes(vms
);
2051 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2054 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2055 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2059 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2060 machine
->ram_size
, "mach-virt.tag");
2063 vms
->highmem_ecam
&= vms
->highmem
&& (!firmware_loaded
|| aarch64
);
2069 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2070 vms
->acpi_dev
= create_acpi_ged(vms
);
2072 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2075 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2076 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2079 /* connect powerdown request */
2080 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2081 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2083 /* Create mmio transports, so the user can create virtio backends
2084 * (which will be automatically plugged in to the transports). If
2085 * no backend is created the transport will just sit harmlessly idle.
2087 create_virtio_devices(vms
);
2089 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2090 rom_set_fw(vms
->fw_cfg
);
2092 create_platform_bus(vms
);
2094 if (machine
->nvdimms_state
->is_enabled
) {
2095 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2096 .space_id
= AML_AS_SYSTEM_MEMORY
,
2097 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2098 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2101 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2102 arm_virt_nvdimm_acpi_dsmio
,
2103 vms
->fw_cfg
, OBJECT(vms
));
2106 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2107 vms
->bootinfo
.nb_cpus
= smp_cpus
;
2108 vms
->bootinfo
.board_id
= -1;
2109 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2110 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2111 vms
->bootinfo
.skip_dtb_autoload
= true;
2112 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2113 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2115 vms
->machine_done
.notify
= virt_machine_done
;
2116 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2119 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2121 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2126 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2128 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2130 vms
->secure
= value
;
2133 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2135 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2140 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2142 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2147 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2149 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2151 return vms
->highmem
;
2154 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2156 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2158 vms
->highmem
= value
;
2161 static bool virt_get_its(Object
*obj
, Error
**errp
)
2163 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2168 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2170 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2175 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2177 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2179 return g_strdup(vms
->oem_id
);
2182 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2184 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2185 size_t len
= strlen(value
);
2189 "User specified oem-id value is bigger than 6 bytes in size");
2193 strncpy(vms
->oem_id
, value
, 6);
2196 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2198 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2200 return g_strdup(vms
->oem_table_id
);
2203 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2206 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2207 size_t len
= strlen(value
);
2211 "User specified oem-table-id value is bigger than 8 bytes in size");
2214 strncpy(vms
->oem_table_id
, value
, 8);
2218 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2220 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2226 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2227 void *opaque
, Error
**errp
)
2229 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2230 OnOffAuto acpi
= vms
->acpi
;
2232 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2235 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2236 void *opaque
, Error
**errp
)
2238 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2240 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2243 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2245 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2250 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2252 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2257 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2259 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2264 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2266 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2271 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2273 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2274 const char *val
= vms
->gic_version
== VIRT_GIC_VERSION_3
? "3" : "2";
2276 return g_strdup(val
);
2279 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2281 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2283 if (!strcmp(value
, "3")) {
2284 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2285 } else if (!strcmp(value
, "2")) {
2286 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2287 } else if (!strcmp(value
, "host")) {
2288 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2289 } else if (!strcmp(value
, "max")) {
2290 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2292 error_setg(errp
, "Invalid gic-version value");
2293 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2297 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2299 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2301 switch (vms
->iommu
) {
2302 case VIRT_IOMMU_NONE
:
2303 return g_strdup("none");
2304 case VIRT_IOMMU_SMMUV3
:
2305 return g_strdup("smmuv3");
2307 g_assert_not_reached();
2311 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2313 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2315 if (!strcmp(value
, "smmuv3")) {
2316 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2317 } else if (!strcmp(value
, "none")) {
2318 vms
->iommu
= VIRT_IOMMU_NONE
;
2320 error_setg(errp
, "Invalid iommu value");
2321 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2325 static CpuInstanceProperties
2326 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2328 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2329 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2331 assert(cpu_index
< possible_cpus
->len
);
2332 return possible_cpus
->cpus
[cpu_index
].props
;
2335 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2337 return idx
% ms
->numa_state
->num_nodes
;
2340 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2343 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2344 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2346 if (ms
->possible_cpus
) {
2347 assert(ms
->possible_cpus
->len
== max_cpus
);
2348 return ms
->possible_cpus
;
2351 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2352 sizeof(CPUArchId
) * max_cpus
);
2353 ms
->possible_cpus
->len
= max_cpus
;
2354 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2355 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2356 ms
->possible_cpus
->cpus
[n
].arch_id
=
2357 virt_cpu_mp_affinity(vms
, n
);
2358 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2359 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
2361 return ms
->possible_cpus
;
2364 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2367 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2368 const MachineState
*ms
= MACHINE(hotplug_dev
);
2369 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2371 if (!vms
->acpi_dev
) {
2373 "memory hotplug is not enabled: missing acpi-ged device");
2378 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2382 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2383 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2387 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2390 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2391 DeviceState
*dev
, Error
**errp
)
2393 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2394 MachineState
*ms
= MACHINE(hotplug_dev
);
2395 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2397 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2400 nvdimm_plug(ms
->nvdimms_state
);
2403 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2407 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2408 DeviceState
*dev
, Error
**errp
)
2410 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2412 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2413 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2414 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2415 hwaddr db_start
= 0, db_end
= 0;
2416 char *resv_prop_str
;
2418 switch (vms
->msi_controller
) {
2419 case VIRT_MSI_CTRL_NONE
:
2421 case VIRT_MSI_CTRL_ITS
:
2422 /* GITS_TRANSLATER page */
2423 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2424 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2425 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2427 case VIRT_MSI_CTRL_GICV2M
:
2428 /* MSI_SETSPI_NS page */
2429 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2430 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2433 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2435 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2437 qdev_prop_set_uint32(dev
, "len-reserved-regions", 1);
2438 qdev_prop_set_string(dev
, "reserved-regions[0]", resv_prop_str
);
2439 g_free(resv_prop_str
);
2443 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2444 DeviceState
*dev
, Error
**errp
)
2446 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2448 if (vms
->platform_bus_dev
) {
2449 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2451 if (device_is_dynamic_sysbus(mc
, dev
)) {
2452 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2453 SYS_BUS_DEVICE(dev
));
2456 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2457 virt_memory_plug(hotplug_dev
, dev
, errp
);
2459 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2460 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2462 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2463 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2464 create_virtio_iommu_dt_bindings(vms
);
2468 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2469 DeviceState
*dev
, Error
**errp
)
2471 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2472 Error
*local_err
= NULL
;
2474 if (!vms
->acpi_dev
) {
2475 error_setg(&local_err
,
2476 "memory hotplug is not enabled: missing acpi-ged device");
2480 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2481 error_setg(&local_err
,
2482 "nvdimm device hot unplug is not supported yet.");
2486 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2489 error_propagate(errp
, local_err
);
2492 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2493 DeviceState
*dev
, Error
**errp
)
2495 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2496 Error
*local_err
= NULL
;
2498 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2503 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2504 qdev_unrealize(dev
);
2507 error_propagate(errp
, local_err
);
2510 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2511 DeviceState
*dev
, Error
**errp
)
2513 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2514 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2516 error_setg(errp
, "device unplug request for unsupported device"
2517 " type: %s", object_get_typename(OBJECT(dev
)));
2521 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2522 DeviceState
*dev
, Error
**errp
)
2524 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2525 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2527 error_setg(errp
, "virt: device unplug for unsupported device"
2528 " type: %s", object_get_typename(OBJECT(dev
)));
2532 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2535 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2537 if (device_is_dynamic_sysbus(mc
, dev
) ||
2538 (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
))) {
2539 return HOTPLUG_HANDLER(machine
);
2541 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2542 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
2544 if (!vms
->bootinfo
.firmware_loaded
|| !virt_is_acpi_enabled(vms
)) {
2545 return HOTPLUG_HANDLER(machine
);
2552 * for arm64 kvm_type [7-0] encodes the requested number of bits
2553 * in the IPA address space
2555 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2557 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2558 int max_vm_pa_size
, requested_pa_size
;
2561 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
2563 /* we freeze the memory map to compute the highest gpa */
2564 virt_set_memmap(vms
);
2566 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2569 * KVM requires the IPA size to be at least 32 bits.
2571 if (requested_pa_size
< 32) {
2572 requested_pa_size
= 32;
2575 if (requested_pa_size
> max_vm_pa_size
) {
2576 error_report("-m and ,maxmem option values "
2577 "require an IPA range (%d bits) larger than "
2578 "the one supported by the host (%d bits)",
2579 requested_pa_size
, max_vm_pa_size
);
2583 * We return the requested PA log size, unless KVM only supports
2584 * the implicit legacy 40b IPA setting, in which case the kvm_type
2587 return fixed_ipa
? 0 : requested_pa_size
;
2590 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2592 MachineClass
*mc
= MACHINE_CLASS(oc
);
2593 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2595 mc
->init
= machvirt_init
;
2596 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2597 * The value may be reduced later when we have more information about the
2598 * configuration of the particular instance.
2601 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2602 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2603 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2604 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2605 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2606 mc
->block_default_type
= IF_VIRTIO
;
2608 mc
->pci_allow_0_address
= true;
2609 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2610 mc
->minimum_page_bits
= 12;
2611 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
2612 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
2613 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
2614 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
2615 mc
->kvm_type
= virt_kvm_type
;
2616 assert(!mc
->get_hotplug_handler
);
2617 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
2618 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
2619 hc
->plug
= virt_machine_device_plug_cb
;
2620 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
2621 hc
->unplug
= virt_machine_device_unplug_cb
;
2622 mc
->nvdimm_supported
= true;
2623 mc
->auto_enable_numa_with_memhp
= true;
2624 mc
->auto_enable_numa_with_memdev
= true;
2625 mc
->default_ram_id
= "mach-virt.ram";
2627 object_class_property_add(oc
, "acpi", "OnOffAuto",
2628 virt_get_acpi
, virt_set_acpi
,
2630 object_class_property_set_description(oc
, "acpi",
2632 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
2634 object_class_property_set_description(oc
, "secure",
2635 "Set on/off to enable/disable the ARM "
2636 "Security Extensions (TrustZone)");
2638 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
2640 object_class_property_set_description(oc
, "virtualization",
2641 "Set on/off to enable/disable emulating a "
2642 "guest CPU which implements the ARM "
2643 "Virtualization Extensions");
2645 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
2647 object_class_property_set_description(oc
, "highmem",
2648 "Set on/off to enable/disable using "
2649 "physical address space above 32 bits");
2651 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
2652 virt_set_gic_version
);
2653 object_class_property_set_description(oc
, "gic-version",
2655 "Valid values are 2, 3, host and max");
2657 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
2658 object_class_property_set_description(oc
, "iommu",
2659 "Set the IOMMU type. "
2660 "Valid values are none and smmuv3");
2662 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
2664 object_class_property_set_description(oc
, "ras",
2665 "Set on/off to enable/disable reporting host memory errors "
2666 "to a KVM guest using ACPI and guest external abort exceptions");
2668 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
2669 object_class_property_set_description(oc
, "mte",
2670 "Set on/off to enable/disable emulating a "
2671 "guest CPU which implements the ARM "
2672 "Memory Tagging Extension");
2674 object_class_property_add_bool(oc
, "its", virt_get_its
,
2676 object_class_property_set_description(oc
, "its",
2677 "Set on/off to enable/disable "
2678 "ITS instantiation");
2680 object_class_property_add_str(oc
, "x-oem-id",
2683 object_class_property_set_description(oc
, "x-oem-id",
2684 "Override the default value of field OEMID "
2685 "in ACPI table header."
2686 "The string may be up to 6 bytes in size");
2689 object_class_property_add_str(oc
, "x-oem-table-id",
2690 virt_get_oem_table_id
,
2691 virt_set_oem_table_id
);
2692 object_class_property_set_description(oc
, "x-oem-table-id",
2693 "Override the default value of field OEM Table ID "
2694 "in ACPI table header."
2695 "The string may be up to 8 bytes in size");
2699 static void virt_instance_init(Object
*obj
)
2701 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2702 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
2704 /* EL3 is disabled by default on virt: this makes us consistent
2705 * between KVM and TCG for this board, and it also allows us to
2706 * boot UEFI blobs which assume no TrustZone support.
2708 vms
->secure
= false;
2710 /* EL2 is also disabled by default, for similar reasons */
2713 /* High memory is enabled by default */
2714 vms
->highmem
= true;
2715 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
2717 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
2722 /* Default allows ITS instantiation */
2726 /* Default disallows iommu instantiation */
2727 vms
->iommu
= VIRT_IOMMU_NONE
;
2729 /* Default disallows RAS instantiation */
2732 /* MTE is disabled by default. */
2735 vms
->irqmap
= a15irqmap
;
2737 virt_flash_create(vms
);
2739 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
2740 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
2743 static const TypeInfo virt_machine_info
= {
2744 .name
= TYPE_VIRT_MACHINE
,
2745 .parent
= TYPE_MACHINE
,
2747 .instance_size
= sizeof(VirtMachineState
),
2748 .class_size
= sizeof(VirtMachineClass
),
2749 .class_init
= virt_machine_class_init
,
2750 .instance_init
= virt_instance_init
,
2751 .interfaces
= (InterfaceInfo
[]) {
2752 { TYPE_HOTPLUG_HANDLER
},
2757 static void machvirt_machine_init(void)
2759 type_register_static(&virt_machine_info
);
2761 type_init(machvirt_machine_init
);
2763 static void virt_machine_6_0_options(MachineClass
*mc
)
2766 DEFINE_VIRT_MACHINE_AS_LATEST(6, 0)
2768 static void virt_machine_5_2_options(MachineClass
*mc
)
2770 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2772 virt_machine_6_0_options(mc
);
2773 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
2774 vmc
->no_secure_gpio
= true;
2776 DEFINE_VIRT_MACHINE(5, 2)
2778 static void virt_machine_5_1_options(MachineClass
*mc
)
2780 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2782 virt_machine_5_2_options(mc
);
2783 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
2784 vmc
->no_kvm_steal_time
= true;
2786 DEFINE_VIRT_MACHINE(5, 1)
2788 static void virt_machine_5_0_options(MachineClass
*mc
)
2790 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2792 virt_machine_5_1_options(mc
);
2793 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
2794 mc
->numa_mem_supported
= true;
2795 vmc
->acpi_expose_flash
= true;
2796 mc
->auto_enable_numa_with_memdev
= false;
2798 DEFINE_VIRT_MACHINE(5, 0)
2800 static void virt_machine_4_2_options(MachineClass
*mc
)
2802 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2804 virt_machine_5_0_options(mc
);
2805 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
2806 vmc
->kvm_no_adjvtime
= true;
2808 DEFINE_VIRT_MACHINE(4, 2)
2810 static void virt_machine_4_1_options(MachineClass
*mc
)
2812 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2814 virt_machine_4_2_options(mc
);
2815 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
2817 mc
->auto_enable_numa_with_memhp
= false;
2819 DEFINE_VIRT_MACHINE(4, 1)
2821 static void virt_machine_4_0_options(MachineClass
*mc
)
2823 virt_machine_4_1_options(mc
);
2824 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
2826 DEFINE_VIRT_MACHINE(4, 0)
2828 static void virt_machine_3_1_options(MachineClass
*mc
)
2830 virt_machine_4_0_options(mc
);
2831 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
2833 DEFINE_VIRT_MACHINE(3, 1)
2835 static void virt_machine_3_0_options(MachineClass
*mc
)
2837 virt_machine_3_1_options(mc
);
2838 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
2840 DEFINE_VIRT_MACHINE(3, 0)
2842 static void virt_machine_2_12_options(MachineClass
*mc
)
2844 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2846 virt_machine_3_0_options(mc
);
2847 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
2848 vmc
->no_highmem_ecam
= true;
2851 DEFINE_VIRT_MACHINE(2, 12)
2853 static void virt_machine_2_11_options(MachineClass
*mc
)
2855 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2857 virt_machine_2_12_options(mc
);
2858 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
2859 vmc
->smbios_old_sys_ver
= true;
2861 DEFINE_VIRT_MACHINE(2, 11)
2863 static void virt_machine_2_10_options(MachineClass
*mc
)
2865 virt_machine_2_11_options(mc
);
2866 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
2867 /* before 2.11 we never faulted accesses to bad addresses */
2868 mc
->ignore_memory_transaction_failures
= true;
2870 DEFINE_VIRT_MACHINE(2, 10)
2872 static void virt_machine_2_9_options(MachineClass
*mc
)
2874 virt_machine_2_10_options(mc
);
2875 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
2877 DEFINE_VIRT_MACHINE(2, 9)
2879 static void virt_machine_2_8_options(MachineClass
*mc
)
2881 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2883 virt_machine_2_9_options(mc
);
2884 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
2885 /* For 2.8 and earlier we falsely claimed in the DT that
2886 * our timers were edge-triggered, not level-triggered.
2888 vmc
->claim_edge_triggered_timers
= true;
2890 DEFINE_VIRT_MACHINE(2, 8)
2892 static void virt_machine_2_7_options(MachineClass
*mc
)
2894 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2896 virt_machine_2_8_options(mc
);
2897 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
2898 /* ITS was introduced with 2.8 */
2900 /* Stick with 1K pages for migration compatibility */
2901 mc
->minimum_page_bits
= 0;
2903 DEFINE_VIRT_MACHINE(2, 7)
2905 static void virt_machine_2_6_options(MachineClass
*mc
)
2907 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2909 virt_machine_2_7_options(mc
);
2910 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
2911 vmc
->disallow_affinity_adjustment
= true;
2912 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2915 DEFINE_VIRT_MACHINE(2, 6)