2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/runstate.h"
48 #include "sysemu/tpm.h"
49 #include "sysemu/tcg.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "sysemu/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/intc/arm_gicv3_its_common.h"
69 #include "hw/firmware/smbios.h"
70 #include "qapi/visitor.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "qapi/qmp/qlist.h"
73 #include "standard-headers/linux/input.h"
74 #include "hw/arm/smmuv3.h"
75 #include "hw/acpi/acpi.h"
76 #include "target/arm/internals.h"
77 #include "hw/mem/pc-dimm.h"
78 #include "hw/mem/nvdimm.h"
79 #include "hw/acpi/generic_event_device.h"
80 #include "hw/virtio/virtio-md-pci.h"
81 #include "hw/virtio/virtio-iommu.h"
82 #include "hw/char/pl011.h"
83 #include "qemu/guest-random.h"
85 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
86 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
89 MachineClass *mc = MACHINE_CLASS(oc); \
90 virt_machine_##major##_##minor##_options(mc); \
91 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
96 static const TypeInfo machvirt_##major##_##minor##_info = { \
97 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
98 .parent = TYPE_VIRT_MACHINE, \
99 .class_init = virt_##major##_##minor##_class_init, \
101 static void machvirt_machine_##major##_##minor##_init(void) \
103 type_register_static(&machvirt_##major##_##minor##_info); \
105 type_init(machvirt_machine_##major##_##minor##_init);
107 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
108 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
109 #define DEFINE_VIRT_MACHINE(major, minor) \
110 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
113 /* Number of external interrupt lines to configure the GIC with */
116 #define PLATFORM_BUS_NUM_IRQS 64
118 /* Legacy RAM limit in GB (< version 4.0) */
119 #define LEGACY_RAMLIMIT_GB 255
120 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
122 /* Addresses and sizes of our components.
123 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
124 * 128MB..256MB is used for miscellaneous device I/O.
125 * 256MB..1GB is reserved for possible future PCI support (ie where the
126 * PCI memory window will go if we add a PCI host controller).
127 * 1GB and up is RAM (which may happily spill over into the
128 * high memory region beyond 4GB).
129 * This represents a compromise between how much RAM can be given to
130 * a 32 bit VM and leaving space for expansion and in particular for PCI.
131 * Note that devices should generally be placed at multiples of 0x10000,
132 * to accommodate guests using 64K pages.
134 static const MemMapEntry base_memmap
[] = {
135 /* Space up to 0x8000000 is reserved for a boot ROM */
136 [VIRT_FLASH
] = { 0, 0x08000000 },
137 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
138 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
139 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
140 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
141 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
142 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
143 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
144 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
145 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
146 /* This redistributor space allows up to 2*64kB*123 CPUs */
147 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
148 [VIRT_UART
] = { 0x09000000, 0x00001000 },
149 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
150 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
151 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
152 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
153 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
154 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
155 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
156 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
157 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
158 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
159 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
160 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
161 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
162 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
163 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
164 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
165 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
166 /* Actual RAM size depends on initial RAM and device memory settings */
167 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
171 * Highmem IO Regions: This memory map is floating, located after the RAM.
172 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
173 * top of the RAM, so that its base get the same alignment as the size,
174 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
175 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
176 * Note the extended_memmap is sized so that it eventually also includes the
177 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
178 * index of base_memmap).
180 * The memory map for these Highmem IO Regions can be in legacy or compact
181 * layout, depending on 'compact-highmem' property. With legacy layout, the
182 * PA space for one specific region is always reserved, even if the region
183 * has been disabled or doesn't fit into the PA space. However, the PA space
184 * for the region won't be reserved in these circumstances with compact layout.
186 static MemMapEntry extended_memmap
[] = {
187 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
188 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
189 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
190 /* Second PCIe window */
191 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
194 static const int a15irqmap
[] = {
197 [VIRT_PCIE
] = 3, /* ... to 6 */
199 [VIRT_SECURE_UART
] = 8,
201 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
202 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
203 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
204 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
207 static void create_randomness(MachineState
*ms
, const char *node
)
214 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
217 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
.kaslr
);
218 qemu_fdt_setprop(ms
->fdt
, node
, "rng-seed", seed
.rng
, sizeof(seed
.rng
));
221 static void create_fdt(VirtMachineState
*vms
)
223 MachineState
*ms
= MACHINE(vms
);
224 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
225 void *fdt
= create_device_tree(&vms
->fdt_size
);
228 error_report("create_device_tree() failed");
235 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
236 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
237 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
238 qemu_fdt_setprop_string(fdt
, "/", "model", "linux,dummy-virt");
240 /* /chosen must exist for load_dtb to fill in necessary properties later */
241 qemu_fdt_add_subnode(fdt
, "/chosen");
242 if (vms
->dtb_randomness
) {
243 create_randomness(ms
, "/chosen");
247 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
248 if (vms
->dtb_randomness
) {
249 create_randomness(ms
, "/secure-chosen");
253 /* Clock node, for the benefit of the UART. The kernel device tree
254 * binding documentation claims the PL011 node clock properties are
255 * optional but in practice if you omit them the kernel refuses to
256 * probe for the device.
258 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
259 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
260 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
261 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
262 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
263 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
265 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
267 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
268 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
269 uint32_t *matrix
= g_malloc0(size
);
272 for (i
= 0; i
< nb_numa_nodes
; i
++) {
273 for (j
= 0; j
< nb_numa_nodes
; j
++) {
274 idx
= (i
* nb_numa_nodes
+ j
) * 3;
275 matrix
[idx
+ 0] = cpu_to_be32(i
);
276 matrix
[idx
+ 1] = cpu_to_be32(j
);
278 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
282 qemu_fdt_add_subnode(fdt
, "/distance-map");
283 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
284 "numa-distance-map-v1");
285 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
291 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
293 /* On real hardware these interrupts are level-triggered.
294 * On KVM they were edge-triggered before host kernel version 4.4,
295 * and level-triggered afterwards.
296 * On emulated QEMU they are level-triggered.
298 * Getting the DTB info about them wrong is awkward for some
300 * pre-4.8 ignore the DT and leave the interrupt configured
301 * with whatever the GIC reset value (or the bootloader) left it at
302 * 4.8 before rc6 honour the incorrect data by programming it back
303 * into the GIC, causing problems
304 * 4.8rc6 and later ignore the DT and always write "level triggered"
307 * For backwards-compatibility, virt-2.8 and earlier will continue
308 * to say these are edge-triggered, but later machines will report
309 * the correct information.
312 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
313 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
314 MachineState
*ms
= MACHINE(vms
);
316 if (vmc
->claim_edge_triggered_timers
) {
317 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
320 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
321 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
322 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
323 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
326 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
328 armcpu
= ARM_CPU(qemu_get_cpu(0));
329 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
330 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
331 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
332 compat
, sizeof(compat
));
334 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
337 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
338 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
339 GIC_FDT_IRQ_TYPE_PPI
,
340 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ
), irqflags
,
341 GIC_FDT_IRQ_TYPE_PPI
,
342 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ
), irqflags
,
343 GIC_FDT_IRQ_TYPE_PPI
,
344 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ
), irqflags
,
345 GIC_FDT_IRQ_TYPE_PPI
,
346 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ
), irqflags
);
349 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
353 const MachineState
*ms
= MACHINE(vms
);
354 const VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
355 int smp_cpus
= ms
->smp
.cpus
;
358 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
359 * On ARM v8 64-bit systems value should be set to 2,
360 * that corresponds to the MPIDR_EL1 register size.
361 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
362 * in the system, #address-cells can be set to 1, since
363 * MPIDR_EL1[63:32] bits are not used for CPUs
366 * Here we actually don't know whether our system is 32- or 64-bit one.
367 * The simplest way to go is to examine affinity IDs of all our CPUs. If
368 * at least one of them has Aff3 populated, we set #address-cells to 2.
370 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
371 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
373 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
379 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
380 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
381 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
383 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
384 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
385 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
386 CPUState
*cs
= CPU(armcpu
);
388 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
389 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
390 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
391 armcpu
->dtb_compatible
);
393 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
394 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
395 "enable-method", "psci");
398 if (addr_cells
== 2) {
399 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
400 armcpu
->mp_affinity
);
402 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
403 armcpu
->mp_affinity
);
406 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
407 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
408 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
411 if (!vmc
->no_cpu_topology
) {
412 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle",
413 qemu_fdt_alloc_phandle(ms
->fdt
));
419 if (!vmc
->no_cpu_topology
) {
421 * Add vCPU topology description through fdt node cpu-map.
423 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
424 * In a SMP system, the hierarchy of CPUs can be defined through
425 * four entities that are used to describe the layout of CPUs in
426 * the system: socket/cluster/core/thread.
428 * A socket node represents the boundary of system physical package
429 * and its child nodes must be one or more cluster nodes. A system
430 * can contain several layers of clustering within a single physical
431 * package and cluster nodes can be contained in parent cluster nodes.
433 * Note: currently we only support one layer of clustering within
434 * each physical package.
436 qemu_fdt_add_subnode(ms
->fdt
, "/cpus/cpu-map");
438 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
439 char *cpu_path
= g_strdup_printf("/cpus/cpu@%d", cpu
);
442 if (ms
->smp
.threads
> 1) {
443 map_path
= g_strdup_printf(
444 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
445 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
),
446 (cpu
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
,
447 (cpu
/ ms
->smp
.threads
) % ms
->smp
.cores
,
448 cpu
% ms
->smp
.threads
);
450 map_path
= g_strdup_printf(
451 "/cpus/cpu-map/socket%d/cluster%d/core%d",
452 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
),
453 (cpu
/ ms
->smp
.cores
) % ms
->smp
.clusters
,
454 cpu
% ms
->smp
.cores
);
456 qemu_fdt_add_path(ms
->fdt
, map_path
);
457 qemu_fdt_setprop_phandle(ms
->fdt
, map_path
, "cpu", cpu_path
);
465 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
468 MachineState
*ms
= MACHINE(vms
);
470 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
471 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
472 vms
->memmap
[VIRT_GIC_ITS
].base
);
473 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
474 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
476 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
477 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#msi-cells", 1);
478 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
479 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
480 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
481 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
485 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
487 MachineState
*ms
= MACHINE(vms
);
490 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
491 vms
->memmap
[VIRT_GIC_V2M
].base
);
492 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
493 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
494 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
495 "arm,gic-v2m-frame");
496 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
497 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
498 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
499 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
500 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
504 static void fdt_add_gic_node(VirtMachineState
*vms
)
506 MachineState
*ms
= MACHINE(vms
);
509 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
510 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
512 nodename
= g_strdup_printf("/intc@%" PRIx64
,
513 vms
->memmap
[VIRT_GIC_DIST
].base
);
514 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
515 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
516 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
517 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
518 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
519 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
520 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
521 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
523 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
526 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
527 "#redistributor-regions", nb_redist_regions
);
529 if (nb_redist_regions
== 1) {
530 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
531 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
532 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
533 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
534 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
536 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
537 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
538 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
539 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
540 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
541 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
542 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
546 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
547 GIC_FDT_IRQ_TYPE_PPI
,
548 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ
),
549 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
552 /* 'cortex-a15-gic' means 'GIC v2' */
553 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
554 "arm,cortex-a15-gic");
556 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
557 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
558 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
559 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
560 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
562 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
563 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
564 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
565 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
566 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
567 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
568 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
569 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
570 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
571 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
572 GIC_FDT_IRQ_TYPE_PPI
,
573 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ
),
574 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
578 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
582 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
584 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
585 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
586 MachineState
*ms
= MACHINE(vms
);
588 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
589 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
593 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
594 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
595 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
596 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
599 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
600 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
601 const char compat
[] = "arm,armv8-pmuv3";
602 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
603 compat
, sizeof(compat
));
604 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
605 GIC_FDT_IRQ_TYPE_PPI
,
606 INTID_TO_PPI(VIRTUAL_PMU_IRQ
), irqflags
);
610 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
613 MachineState
*ms
= MACHINE(vms
);
614 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
615 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
618 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
621 if (ms
->nvdimms_state
->is_enabled
) {
622 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
625 dev
= qdev_new(TYPE_ACPI_GED
);
626 qdev_prop_set_uint32(dev
, "ged-event", event
);
627 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
629 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
630 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
631 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
636 static void create_its(VirtMachineState
*vms
)
638 const char *itsclass
= its_class_name();
641 if (!strcmp(itsclass
, "arm-gicv3-its")) {
648 /* Do nothing if not supported */
652 dev
= qdev_new(itsclass
);
654 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
656 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
657 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
659 fdt_add_its_gic_node(vms
);
660 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
663 static void create_v2m(VirtMachineState
*vms
)
666 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
669 dev
= qdev_new("arm-gicv2m");
670 qdev_prop_set_uint32(dev
, "base-spi", irq
);
671 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
672 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
673 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
675 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
676 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
677 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
680 fdt_add_v2m_gic_node(vms
);
681 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
684 static void create_gic(VirtMachineState
*vms
, MemoryRegion
*mem
)
686 MachineState
*ms
= MACHINE(vms
);
687 /* We create a standalone GIC */
688 SysBusDevice
*gicbusdev
;
691 unsigned int smp_cpus
= ms
->smp
.cpus
;
692 uint32_t nb_redist_regions
= 0;
695 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
696 gictype
= gic_class_name();
698 gictype
= gicv3_class_name();
701 switch (vms
->gic_version
) {
702 case VIRT_GIC_VERSION_2
:
705 case VIRT_GIC_VERSION_3
:
708 case VIRT_GIC_VERSION_4
:
712 g_assert_not_reached();
714 vms
->gic
= qdev_new(gictype
);
715 qdev_prop_set_uint32(vms
->gic
, "revision", revision
);
716 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
717 /* Note that the num-irq property counts both internal and external
718 * interrupts; there are always 32 of the former (mandated by GIC spec).
720 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
721 if (!kvm_irqchip_in_kernel()) {
722 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
725 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
726 QList
*redist_region_count
;
727 uint32_t redist0_capacity
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
728 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
730 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
732 redist_region_count
= qlist_new();
733 qlist_append_int(redist_region_count
, redist0_count
);
734 if (nb_redist_regions
== 2) {
735 uint32_t redist1_capacity
=
736 virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
738 qlist_append_int(redist_region_count
,
739 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
741 qdev_prop_set_array(vms
->gic
, "redist-region-count",
742 redist_region_count
);
744 if (!kvm_irqchip_in_kernel()) {
746 object_property_set_link(OBJECT(vms
->gic
), "sysmem",
747 OBJECT(mem
), &error_fatal
);
748 qdev_prop_set_bit(vms
->gic
, "has-lpi", true);
752 if (!kvm_irqchip_in_kernel()) {
753 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
757 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
758 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
759 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
760 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
761 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
762 if (nb_redist_regions
== 2) {
763 sysbus_mmio_map(gicbusdev
, 2,
764 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
767 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
769 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
770 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
774 /* Wire the outputs from each CPU's generic timer and the GICv3
775 * maintenance interrupt signal to the appropriate GIC PPI inputs,
776 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
778 for (i
= 0; i
< smp_cpus
; i
++) {
779 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
780 int intidbase
= NUM_IRQS
+ i
* GIC_INTERNAL
;
781 /* Mapping from the output timer irq lines from the CPU to the
782 * GIC PPI inputs we use for the virt board.
784 const int timer_irq
[] = {
785 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
786 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
787 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
788 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
791 for (unsigned irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
792 qdev_connect_gpio_out(cpudev
, irq
,
793 qdev_get_gpio_in(vms
->gic
,
794 intidbase
+ timer_irq
[irq
]));
797 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
798 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
799 intidbase
+ ARCH_GIC_MAINT_IRQ
);
800 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
802 } else if (vms
->virt
) {
803 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
804 intidbase
+ ARCH_GIC_MAINT_IRQ
);
805 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
808 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
809 qdev_get_gpio_in(vms
->gic
, intidbase
812 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
813 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
814 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
815 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
816 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
817 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
818 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
821 fdt_add_gic_node(vms
);
823 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& vms
->its
) {
825 } else if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
830 static void create_uart(const VirtMachineState
*vms
, int uart
,
831 MemoryRegion
*mem
, Chardev
*chr
)
834 hwaddr base
= vms
->memmap
[uart
].base
;
835 hwaddr size
= vms
->memmap
[uart
].size
;
836 int irq
= vms
->irqmap
[uart
];
837 const char compat
[] = "arm,pl011\0arm,primecell";
838 const char clocknames
[] = "uartclk\0apb_pclk";
839 DeviceState
*dev
= qdev_new(TYPE_PL011
);
840 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
841 MachineState
*ms
= MACHINE(vms
);
843 qdev_prop_set_chr(dev
, "chardev", chr
);
844 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
845 memory_region_add_subregion(mem
, base
,
846 sysbus_mmio_get_region(s
, 0));
847 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
849 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
850 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
851 /* Note that we can't use setprop_string because of the embedded NUL */
852 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
853 compat
, sizeof(compat
));
854 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
856 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
857 GIC_FDT_IRQ_TYPE_SPI
, irq
,
858 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
859 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
860 vms
->clock_phandle
, vms
->clock_phandle
);
861 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
862 clocknames
, sizeof(clocknames
));
864 if (uart
== VIRT_UART
) {
865 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
867 /* Mark as not usable by the normal world */
868 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
869 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
871 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
878 static void create_rtc(const VirtMachineState
*vms
)
881 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
882 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
883 int irq
= vms
->irqmap
[VIRT_RTC
];
884 const char compat
[] = "arm,pl031\0arm,primecell";
885 MachineState
*ms
= MACHINE(vms
);
887 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
889 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
890 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
891 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
892 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
894 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
895 GIC_FDT_IRQ_TYPE_SPI
, irq
,
896 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
897 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
898 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
902 static DeviceState
*gpio_key_dev
;
903 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
905 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
908 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
910 /* use gpio Pin 3 for power button event */
911 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
915 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
918 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
919 qdev_get_gpio_in(pl061_dev
, 3));
921 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
922 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
924 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
925 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
926 "label", "GPIO Key Poweroff");
927 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
929 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
930 "gpios", phandle
, 3, 0);
933 #define SECURE_GPIO_POWEROFF 0
934 #define SECURE_GPIO_RESET 1
936 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
939 DeviceState
*gpio_pwr_dev
;
942 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
944 /* connect secure pl061 to gpio-pwr */
945 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
946 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
947 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
948 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
950 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
951 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
953 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
954 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
955 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
956 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
959 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
960 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
962 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
963 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
964 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
965 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
969 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
973 DeviceState
*pl061_dev
;
974 hwaddr base
= vms
->memmap
[gpio
].base
;
975 hwaddr size
= vms
->memmap
[gpio
].size
;
976 int irq
= vms
->irqmap
[gpio
];
977 const char compat
[] = "arm,pl061\0arm,primecell";
979 MachineState
*ms
= MACHINE(vms
);
981 pl061_dev
= qdev_new("pl061");
982 /* Pull lines down to 0 if not driven by the PL061 */
983 qdev_prop_set_uint32(pl061_dev
, "pullups", 0);
984 qdev_prop_set_uint32(pl061_dev
, "pulldowns", 0xff);
985 s
= SYS_BUS_DEVICE(pl061_dev
);
986 sysbus_realize_and_unref(s
, &error_fatal
);
987 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
988 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
990 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
991 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
992 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
993 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
995 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
996 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
997 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
998 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
999 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1000 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
1001 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
1002 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
1003 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
1005 if (gpio
!= VIRT_GPIO
) {
1006 /* Mark as not usable by the normal world */
1007 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1008 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1012 /* Child gpio devices */
1013 if (gpio
== VIRT_GPIO
) {
1014 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
1016 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
1020 static void create_virtio_devices(const VirtMachineState
*vms
)
1023 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
1024 MachineState
*ms
= MACHINE(vms
);
1026 /* We create the transports in forwards order. Since qbus_realize()
1027 * prepends (not appends) new child buses, the incrementing loop below will
1028 * create a list of virtio-mmio buses with decreasing base addresses.
1030 * When a -device option is processed from the command line,
1031 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1032 * order. The upshot is that -device options in increasing command line
1033 * order are mapped to virtio-mmio buses with decreasing base addresses.
1035 * When this code was originally written, that arrangement ensured that the
1036 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1037 * the first -device on the command line. (The end-to-end order is a
1038 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1039 * guest kernel's name-to-address assignment strategy.)
1041 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1042 * the message, if not necessarily the code, of commit 70161ff336.
1043 * Therefore the loop now establishes the inverse of the original intent.
1045 * Unfortunately, we can't counteract the kernel change by reversing the
1046 * loop; it would break existing command lines.
1048 * In any case, the kernel makes no guarantee about the stability of
1049 * enumeration order of virtio devices (as demonstrated by it changing
1050 * between kernel versions). For reliable and stable identification
1051 * of disks users must use UUIDs or similar mechanisms.
1053 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
1054 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1055 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1057 sysbus_create_simple("virtio-mmio", base
,
1058 qdev_get_gpio_in(vms
->gic
, irq
));
1061 /* We add dtb nodes in reverse order so that they appear in the finished
1062 * device tree lowest address first.
1064 * Note that this mapping is independent of the loop above. The previous
1065 * loop influences virtio device to virtio transport assignment, whereas
1066 * this loop controls how virtio transports are laid out in the dtb.
1068 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
1070 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1071 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1073 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
1074 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1075 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1076 "compatible", "virtio,mmio");
1077 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1079 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1080 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1081 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1082 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1087 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1089 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1091 const char *alias_prop_name
)
1094 * Create a single flash device. We use the same parameters as
1095 * the flash devices on the Versatile Express board.
1097 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1099 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1100 qdev_prop_set_uint8(dev
, "width", 4);
1101 qdev_prop_set_uint8(dev
, "device-width", 2);
1102 qdev_prop_set_bit(dev
, "big-endian", false);
1103 qdev_prop_set_uint16(dev
, "id0", 0x89);
1104 qdev_prop_set_uint16(dev
, "id1", 0x18);
1105 qdev_prop_set_uint16(dev
, "id2", 0x00);
1106 qdev_prop_set_uint16(dev
, "id3", 0x00);
1107 qdev_prop_set_string(dev
, "name", name
);
1108 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1109 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1110 OBJECT(dev
), "drive");
1111 return PFLASH_CFI01(dev
);
1114 static void virt_flash_create(VirtMachineState
*vms
)
1116 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1117 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1120 static void virt_flash_map1(PFlashCFI01
*flash
,
1121 hwaddr base
, hwaddr size
,
1122 MemoryRegion
*sysmem
)
1124 DeviceState
*dev
= DEVICE(flash
);
1126 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1127 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1128 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1129 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1131 memory_region_add_subregion(sysmem
, base
,
1132 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1136 static void virt_flash_map(VirtMachineState
*vms
,
1137 MemoryRegion
*sysmem
,
1138 MemoryRegion
*secure_sysmem
)
1141 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1142 * sysmem is the system memory space. secure_sysmem is the secure view
1143 * of the system, and the first flash device should be made visible only
1144 * there. The second flash device is visible to both secure and nonsecure.
1145 * If sysmem == secure_sysmem this means there is no separate Secure
1146 * address space and both flash devices are generally visible.
1148 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1149 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1151 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1153 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1157 static void virt_flash_fdt(VirtMachineState
*vms
,
1158 MemoryRegion
*sysmem
,
1159 MemoryRegion
*secure_sysmem
)
1161 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1162 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1163 MachineState
*ms
= MACHINE(vms
);
1166 if (sysmem
== secure_sysmem
) {
1167 /* Report both flash devices as a single node in the DT */
1168 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1169 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1170 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1171 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1172 2, flashbase
, 2, flashsize
,
1173 2, flashbase
+ flashsize
, 2, flashsize
);
1174 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1178 * Report the devices as separate nodes so we can mark one as
1179 * only visible to the secure world.
1181 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1182 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1183 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1184 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1185 2, flashbase
, 2, flashsize
);
1186 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1187 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1188 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1191 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
+ flashsize
);
1192 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1193 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1194 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1195 2, flashbase
+ flashsize
, 2, flashsize
);
1196 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1201 static bool virt_firmware_init(VirtMachineState
*vms
,
1202 MemoryRegion
*sysmem
,
1203 MemoryRegion
*secure_sysmem
)
1206 const char *bios_name
;
1207 BlockBackend
*pflash_blk0
;
1209 /* Map legacy -drive if=pflash to machine properties */
1210 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1211 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1212 drive_get(IF_PFLASH
, 0, i
));
1215 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1217 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1219 bios_name
= MACHINE(vms
)->firmware
;
1226 error_report("The contents of the first flash device may be "
1227 "specified with -bios or with -drive if=pflash... "
1228 "but you cannot use both options at once");
1232 /* Fall back to -bios */
1234 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1236 error_report("Could not find ROM image '%s'", bios_name
);
1239 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1240 image_size
= load_image_mr(fname
, mr
);
1242 if (image_size
< 0) {
1243 error_report("Could not load ROM image '%s'", bios_name
);
1248 return pflash_blk0
|| bios_name
;
1251 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1253 MachineState
*ms
= MACHINE(vms
);
1254 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1255 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1259 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1260 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1262 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1263 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1264 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1265 "compatible", "qemu,fw-cfg-mmio");
1266 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1268 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1273 static void create_pcie_irq_map(const MachineState
*ms
,
1274 uint32_t gic_phandle
,
1275 int first_irq
, const char *nodename
)
1278 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1279 uint32_t *irq_map
= full_irq_map
;
1281 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1282 for (pin
= 0; pin
< 4; pin
++) {
1283 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1284 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1285 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1289 devfn
<< 8, 0, 0, /* devfn */
1290 pin
+ 1, /* PCI pin */
1291 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1293 /* Convert map to big endian */
1294 for (i
= 0; i
< 10; i
++) {
1295 irq_map
[i
] = cpu_to_be32(map
[i
]);
1301 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1302 full_irq_map
, sizeof(full_irq_map
));
1304 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1305 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1310 static void create_smmu(const VirtMachineState
*vms
,
1314 const char compat
[] = "arm,smmu-v3";
1315 int irq
= vms
->irqmap
[VIRT_SMMU
];
1317 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1318 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1319 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1321 MachineState
*ms
= MACHINE(vms
);
1323 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1327 dev
= qdev_new(TYPE_ARM_SMMUV3
);
1329 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1331 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1332 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1333 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1334 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1335 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1338 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1339 qemu_fdt_add_subnode(ms
->fdt
, node
);
1340 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1341 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1343 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1344 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1345 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1346 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1347 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1349 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1352 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1354 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1356 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1360 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1362 const char compat
[] = "virtio,pci-iommu\0pci1af4,1057";
1363 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1364 MachineState
*ms
= MACHINE(vms
);
1367 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1369 node
= g_strdup_printf("%s/virtio_iommu@%x,%x", vms
->pciehb_nodename
,
1370 PCI_SLOT(bdf
), PCI_FUNC(bdf
));
1371 qemu_fdt_add_subnode(ms
->fdt
, node
);
1372 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1373 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1374 1, bdf
<< 8, 1, 0, 1, 0,
1377 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1378 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1381 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1382 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1383 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1386 static void create_pcie(VirtMachineState
*vms
)
1388 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1389 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1390 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1391 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1392 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1393 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1394 hwaddr base_ecam
, size_ecam
;
1395 hwaddr base
= base_mmio
;
1397 int irq
= vms
->irqmap
[VIRT_PCIE
];
1398 MemoryRegion
*mmio_alias
;
1399 MemoryRegion
*mmio_reg
;
1400 MemoryRegion
*ecam_alias
;
1401 MemoryRegion
*ecam_reg
;
1406 MachineState
*ms
= MACHINE(vms
);
1407 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
1409 dev
= qdev_new(TYPE_GPEX_HOST
);
1410 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1412 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1413 base_ecam
= vms
->memmap
[ecam_id
].base
;
1414 size_ecam
= vms
->memmap
[ecam_id
].size
;
1415 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1416 /* Map only the first size_ecam bytes of ECAM space */
1417 ecam_alias
= g_new0(MemoryRegion
, 1);
1418 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1419 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1420 ecam_reg
, 0, size_ecam
);
1421 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1423 /* Map the MMIO window into system address space so as to expose
1424 * the section of PCI MMIO space which starts at the same base address
1425 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1428 mmio_alias
= g_new0(MemoryRegion
, 1);
1429 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1430 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1431 mmio_reg
, base_mmio
, size_mmio
);
1432 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1434 if (vms
->highmem_mmio
) {
1435 /* Map high MMIO space */
1436 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1438 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1439 mmio_reg
, base_mmio_high
, size_mmio_high
);
1440 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1444 /* Map IO port space */
1445 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1447 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1448 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1449 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1450 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1453 pci
= PCI_HOST_BRIDGE(dev
);
1454 pci
->bypass_iommu
= vms
->default_bus_bypass_iommu
;
1455 vms
->bus
= pci
->bus
;
1457 for (i
= 0; i
< nb_nics
; i
++) {
1458 pci_nic_init_nofail(&nd_table
[i
], pci
->bus
, mc
->default_nic
, NULL
);
1462 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1463 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1464 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1465 "compatible", "pci-host-ecam-generic");
1466 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1467 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1468 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1469 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1470 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1472 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1474 if (vms
->msi_phandle
) {
1475 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-map",
1476 0, vms
->msi_phandle
, 0, 0x10000);
1479 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1480 2, base_ecam
, 2, size_ecam
);
1482 if (vms
->highmem_mmio
) {
1483 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1484 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1485 2, base_pio
, 2, size_pio
,
1486 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1487 2, base_mmio
, 2, size_mmio
,
1488 1, FDT_PCI_RANGE_MMIO_64BIT
,
1490 2, base_mmio_high
, 2, size_mmio_high
);
1492 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1493 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1494 2, base_pio
, 2, size_pio
,
1495 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1496 2, base_mmio
, 2, size_mmio
);
1499 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1500 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1503 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1505 switch (vms
->iommu
) {
1506 case VIRT_IOMMU_SMMUV3
:
1507 create_smmu(vms
, vms
->bus
);
1508 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1509 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1512 g_assert_not_reached();
1517 static void create_platform_bus(VirtMachineState
*vms
)
1522 MemoryRegion
*sysmem
= get_system_memory();
1524 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1525 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1526 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1527 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1528 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1529 vms
->platform_bus_dev
= dev
;
1531 s
= SYS_BUS_DEVICE(dev
);
1532 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1533 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1534 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1537 memory_region_add_subregion(sysmem
,
1538 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1539 sysbus_mmio_get_region(s
, 0));
1542 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1543 hwaddr base
, hwaddr size
,
1546 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1548 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1549 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1552 static void create_secure_ram(VirtMachineState
*vms
,
1553 MemoryRegion
*secure_sysmem
,
1554 MemoryRegion
*secure_tag_sysmem
)
1556 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1558 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1559 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1560 MachineState
*ms
= MACHINE(vms
);
1562 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1564 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1566 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1567 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1568 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1569 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1570 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1571 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1573 if (secure_tag_sysmem
) {
1574 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1580 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1582 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1584 MachineState
*ms
= MACHINE(board
);
1587 *fdt_size
= board
->fdt_size
;
1591 static void virt_build_smbios(VirtMachineState
*vms
)
1593 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1594 MachineState
*ms
= MACHINE(vms
);
1595 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1596 uint8_t *smbios_tables
, *smbios_anchor
;
1597 size_t smbios_tables_len
, smbios_anchor_len
;
1598 struct smbios_phys_mem_area mem_array
;
1599 const char *product
= "QEMU Virtual Machine";
1601 if (kvm_enabled()) {
1602 product
= "KVM Virtual Machine";
1605 smbios_set_defaults("QEMU", product
,
1606 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1607 true, SMBIOS_ENTRY_POINT_TYPE_64
);
1609 /* build the array of physical mem area from base_memmap */
1610 mem_array
.address
= vms
->memmap
[VIRT_MEM
].base
;
1611 mem_array
.length
= ms
->ram_size
;
1613 smbios_get_tables(ms
, &mem_array
, 1,
1614 &smbios_tables
, &smbios_tables_len
,
1615 &smbios_anchor
, &smbios_anchor_len
,
1618 if (smbios_anchor
) {
1619 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1620 smbios_tables
, smbios_tables_len
);
1621 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1622 smbios_anchor
, smbios_anchor_len
);
1627 void virt_machine_done(Notifier
*notifier
, void *data
)
1629 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1631 MachineState
*ms
= MACHINE(vms
);
1632 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1633 struct arm_boot_info
*info
= &vms
->bootinfo
;
1634 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1637 * If the user provided a dtb, we assume the dynamic sysbus nodes
1638 * already are integrated there. This corresponds to a use case where
1639 * the dynamic sysbus nodes are complex and their generation is not yet
1640 * supported. In that case the user can take charge of the guest dt
1641 * while qemu takes charge of the qom stuff.
1643 if (info
->dtb_filename
== NULL
) {
1644 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1645 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1646 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1647 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1649 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1653 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1655 virt_acpi_setup(vms
);
1656 virt_build_smbios(vms
);
1659 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1661 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1662 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1664 if (!vmc
->disallow_affinity_adjustment
) {
1665 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1666 * GIC's target-list limitations. 32-bit KVM hosts currently
1667 * always create clusters of 4 CPUs, but that is expected to
1668 * change when they gain support for gicv3. When KVM is enabled
1669 * it will override the changes we make here, therefore our
1670 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1671 * and to improve SGI efficiency.
1673 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
1674 clustersz
= GIC_TARGETLIST_BITS
;
1676 clustersz
= GICV3_TARGETLIST_BITS
;
1679 return arm_cpu_mp_affinity(idx
, clustersz
);
1682 static inline bool *virt_get_high_memmap_enabled(VirtMachineState
*vms
,
1685 bool *enabled_array
[] = {
1686 &vms
->highmem_redists
,
1691 assert(ARRAY_SIZE(extended_memmap
) - VIRT_LOWMEMMAP_LAST
==
1692 ARRAY_SIZE(enabled_array
));
1693 assert(index
- VIRT_LOWMEMMAP_LAST
< ARRAY_SIZE(enabled_array
));
1695 return enabled_array
[index
- VIRT_LOWMEMMAP_LAST
];
1698 static void virt_set_high_memmap(VirtMachineState
*vms
,
1699 hwaddr base
, int pa_bits
)
1701 hwaddr region_base
, region_size
;
1702 bool *region_enabled
, fits
;
1705 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1706 region_enabled
= virt_get_high_memmap_enabled(vms
, i
);
1707 region_base
= ROUND_UP(base
, extended_memmap
[i
].size
);
1708 region_size
= extended_memmap
[i
].size
;
1710 vms
->memmap
[i
].base
= region_base
;
1711 vms
->memmap
[i
].size
= region_size
;
1714 * Check each device to see if it fits in the PA space,
1715 * moving highest_gpa as we go. For compatibility, move
1716 * highest_gpa for disabled fitting devices as well, if
1717 * the compact layout has been disabled.
1719 * For each device that doesn't fit, disable it.
1721 fits
= (region_base
+ region_size
) <= BIT_ULL(pa_bits
);
1722 *region_enabled
&= fits
;
1723 if (vms
->highmem_compact
&& !*region_enabled
) {
1727 base
= region_base
+ region_size
;
1729 vms
->highest_gpa
= base
- 1;
1734 static void virt_set_memmap(VirtMachineState
*vms
, int pa_bits
)
1736 MachineState
*ms
= MACHINE(vms
);
1737 hwaddr base
, device_memory_base
, device_memory_size
, memtop
;
1740 vms
->memmap
= extended_memmap
;
1742 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1743 vms
->memmap
[i
] = base_memmap
[i
];
1746 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1747 error_report("unsupported number of memory slots: %"PRIu64
,
1753 * !highmem is exactly the same as limiting the PA space to 32bit,
1754 * irrespective of the underlying capabilities of the HW.
1756 if (!vms
->highmem
) {
1761 * We compute the base of the high IO region depending on the
1762 * amount of initial and device memory. The device memory start/size
1763 * is aligned on 1GiB. We never put the high IO region below 256GiB
1764 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1765 * The device region size assumes 1GiB page max alignment per slot.
1767 device_memory_base
=
1768 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1769 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1771 /* Base address of the high IO region */
1772 memtop
= base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1773 if (memtop
> BIT_ULL(pa_bits
)) {
1774 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
1775 pa_bits
, memtop
- BIT_ULL(pa_bits
));
1778 if (base
< device_memory_base
) {
1779 error_report("maxmem/slots too huge");
1782 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1783 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1786 /* We know for sure that at least the memory fits in the PA space */
1787 vms
->highest_gpa
= memtop
- 1;
1789 virt_set_high_memmap(vms
, base
, pa_bits
);
1791 if (device_memory_size
> 0) {
1792 machine_memory_devices_init(ms
, device_memory_base
, device_memory_size
);
1796 static VirtGICType
finalize_gic_version_do(const char *accel_name
,
1797 VirtGICType gic_version
,
1799 unsigned int max_cpus
)
1801 /* Convert host/max/nosel to GIC version number */
1802 switch (gic_version
) {
1803 case VIRT_GIC_VERSION_HOST
:
1804 if (!kvm_enabled()) {
1805 error_report("gic-version=host requires KVM");
1809 /* For KVM, gic-version=host means gic-version=max */
1810 return finalize_gic_version_do(accel_name
, VIRT_GIC_VERSION_MAX
,
1811 gics_supported
, max_cpus
);
1812 case VIRT_GIC_VERSION_MAX
:
1813 if (gics_supported
& VIRT_GIC_VERSION_4_MASK
) {
1814 gic_version
= VIRT_GIC_VERSION_4
;
1815 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1816 gic_version
= VIRT_GIC_VERSION_3
;
1818 gic_version
= VIRT_GIC_VERSION_2
;
1821 case VIRT_GIC_VERSION_NOSEL
:
1822 if ((gics_supported
& VIRT_GIC_VERSION_2_MASK
) &&
1823 max_cpus
<= GIC_NCPU
) {
1824 gic_version
= VIRT_GIC_VERSION_2
;
1825 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1827 * in case the host does not support v2 emulation or
1828 * the end-user requested more than 8 VCPUs we now default
1829 * to v3. In any case defaulting to v2 would be broken.
1831 gic_version
= VIRT_GIC_VERSION_3
;
1832 } else if (max_cpus
> GIC_NCPU
) {
1833 error_report("%s only supports GICv2 emulation but more than 8 "
1834 "vcpus are requested", accel_name
);
1838 case VIRT_GIC_VERSION_2
:
1839 case VIRT_GIC_VERSION_3
:
1840 case VIRT_GIC_VERSION_4
:
1844 /* Check chosen version is effectively supported */
1845 switch (gic_version
) {
1846 case VIRT_GIC_VERSION_2
:
1847 if (!(gics_supported
& VIRT_GIC_VERSION_2_MASK
)) {
1848 error_report("%s does not support GICv2 emulation", accel_name
);
1852 case VIRT_GIC_VERSION_3
:
1853 if (!(gics_supported
& VIRT_GIC_VERSION_3_MASK
)) {
1854 error_report("%s does not support GICv3 emulation", accel_name
);
1858 case VIRT_GIC_VERSION_4
:
1859 if (!(gics_supported
& VIRT_GIC_VERSION_4_MASK
)) {
1860 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1866 error_report("logic error in finalize_gic_version");
1875 * finalize_gic_version - Determines the final gic_version
1876 * according to the gic-version property
1878 * Default GIC type is v2
1880 static void finalize_gic_version(VirtMachineState
*vms
)
1882 const char *accel_name
= current_accel_name();
1883 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1884 int gics_supported
= 0;
1886 /* Determine which GIC versions the current environment supports */
1887 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1888 int probe_bitmap
= kvm_arm_vgic_probe();
1890 if (!probe_bitmap
) {
1891 error_report("Unable to determine GIC version supported by host");
1895 if (probe_bitmap
& KVM_ARM_VGIC_V2
) {
1896 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1898 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1899 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1901 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
1902 /* KVM w/o kernel irqchip can only deal with GICv2 */
1903 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1904 accel_name
= "KVM with kernel-irqchip=off";
1905 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
1906 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1907 if (module_object_class_by_name("arm-gicv3")) {
1908 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1910 /* GICv4 only makes sense if CPU has EL2 */
1911 gics_supported
|= VIRT_GIC_VERSION_4_MASK
;
1915 error_report("Unsupported accelerator, can not determine GIC support");
1920 * Then convert helpers like host/max to concrete GIC versions and ensure
1921 * the desired version is supported
1923 vms
->gic_version
= finalize_gic_version_do(accel_name
, vms
->gic_version
,
1924 gics_supported
, max_cpus
);
1928 * virt_cpu_post_init() must be called after the CPUs have
1929 * been realized and the GIC has been created.
1931 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
1933 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1934 bool aarch64
, pmu
, steal_time
;
1937 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
1938 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
1939 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
1940 "kvm-steal-time", NULL
);
1942 if (kvm_enabled()) {
1943 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
1944 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
1947 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
1948 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
1950 /* The memory region size must be a multiple of host page size. */
1951 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
1953 if (pvtime_size
> pvtime_reg_size
) {
1954 error_report("pvtime requires a %" HWADDR_PRId
1955 " byte memory region for %d CPUs,"
1956 " but only %" HWADDR_PRId
" has been reserved",
1957 pvtime_size
, max_cpus
, pvtime_reg_size
);
1961 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
1962 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
1967 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
1968 if (kvm_irqchip_in_kernel()) {
1969 kvm_arm_pmu_set_irq(ARM_CPU(cpu
), VIRTUAL_PMU_IRQ
);
1971 kvm_arm_pmu_init(ARM_CPU(cpu
));
1974 kvm_arm_pvtime_init(ARM_CPU(cpu
), pvtime_reg_base
1976 * PVTIME_SIZE_PER_CPU
);
1980 if (aarch64
&& vms
->highmem
) {
1981 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1982 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
1984 if (pamax
< requested_pa_size
) {
1985 error_report("VCPU supports less PA bits (%d) than "
1986 "requested by the memory map (%d)",
1987 pamax
, requested_pa_size
);
1994 static void machvirt_init(MachineState
*machine
)
1996 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1997 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1998 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1999 const CPUArchIdList
*possible_cpus
;
2000 MemoryRegion
*sysmem
= get_system_memory();
2001 MemoryRegion
*secure_sysmem
= NULL
;
2002 MemoryRegion
*tag_sysmem
= NULL
;
2003 MemoryRegion
*secure_tag_sysmem
= NULL
;
2004 int n
, virt_max_cpus
;
2005 bool firmware_loaded
;
2006 bool aarch64
= true;
2007 bool has_ged
= !vmc
->no_ged
;
2008 unsigned int smp_cpus
= machine
->smp
.cpus
;
2009 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2011 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2014 * In accelerated mode, the memory map is computed earlier in kvm_type()
2015 * to create a VM with the right number of IPA bits.
2023 * Instantiate a temporary CPU object to find out about what
2024 * we are about to deal with. Once this is done, get rid of
2027 cpuobj
= object_new(possible_cpus
->cpus
[0].type
);
2028 armcpu
= ARM_CPU(cpuobj
);
2030 pa_bits
= arm_pamax(armcpu
);
2032 object_unref(cpuobj
);
2034 virt_set_memmap(vms
, pa_bits
);
2037 /* We can probe only here because during property set
2038 * KVM is not available yet
2040 finalize_gic_version(vms
);
2044 * The Secure view of the world is the same as the NonSecure,
2045 * but with a few extra devices. Create it as a container region
2046 * containing the system memory at low priority; any secure-only
2047 * devices go in at higher priority and take precedence.
2049 secure_sysmem
= g_new(MemoryRegion
, 1);
2050 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
2052 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
2055 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
2056 secure_sysmem
?: sysmem
);
2058 /* If we have an EL3 boot ROM then the assumption is that it will
2059 * implement PSCI itself, so disable QEMU's internal implementation
2060 * so it doesn't get in the way. Instead of starting secondary
2061 * CPUs in PSCI powerdown state we will start them all running and
2062 * let the boot ROM sort them out.
2063 * The usual case is that we do use QEMU's PSCI implementation;
2064 * if the guest has EL2 then we will use SMC as the conduit,
2065 * and otherwise we will use HVC (for backwards compatibility and
2066 * because if we're using KVM then we must use HVC).
2068 if (vms
->secure
&& firmware_loaded
) {
2069 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
2070 } else if (vms
->virt
) {
2071 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
2073 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
2077 * The maximum number of CPUs depends on the GIC version, or on how
2078 * many redistributors we can fit into the memory map (which in turn
2079 * depends on whether this is a GICv3 or v4).
2081 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
2082 virt_max_cpus
= GIC_NCPU
;
2084 virt_max_cpus
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
2085 if (vms
->highmem_redists
) {
2086 virt_max_cpus
+= virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
2090 if (max_cpus
> virt_max_cpus
) {
2091 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2092 "supported by machine 'mach-virt' (%d)",
2093 max_cpus
, virt_max_cpus
);
2094 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& !vms
->highmem_redists
) {
2095 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2101 if (vms
->secure
&& (kvm_enabled() || hvf_enabled())) {
2102 error_report("mach-virt: %s does not support providing "
2103 "Security extensions (TrustZone) to the guest CPU",
2104 current_accel_name());
2108 if (vms
->virt
&& (kvm_enabled() || hvf_enabled())) {
2109 error_report("mach-virt: %s does not support providing "
2110 "Virtualization extensions to the guest CPU",
2111 current_accel_name());
2115 if (vms
->mte
&& (kvm_enabled() || hvf_enabled())) {
2116 error_report("mach-virt: %s does not support providing "
2117 "MTE to the guest CPU",
2118 current_accel_name());
2124 assert(possible_cpus
->len
== max_cpus
);
2125 for (n
= 0; n
< possible_cpus
->len
; n
++) {
2129 if (n
>= smp_cpus
) {
2133 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
2134 object_property_set_int(cpuobj
, "mp-affinity",
2135 possible_cpus
->cpus
[n
].arch_id
, NULL
);
2140 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
2143 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
2146 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
2149 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
2150 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
2153 if (vmc
->kvm_no_adjvtime
&&
2154 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
2155 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
2158 if (vmc
->no_kvm_steal_time
&&
2159 object_property_find(cpuobj
, "kvm-steal-time")) {
2160 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
2163 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
2164 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
2167 if (vmc
->no_tcg_lpa2
&& object_property_find(cpuobj
, "lpa2")) {
2168 object_property_set_bool(cpuobj
, "lpa2", false, NULL
);
2171 if (object_property_find(cpuobj
, "reset-cbar")) {
2172 object_property_set_int(cpuobj
, "reset-cbar",
2173 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
2177 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
2180 object_property_set_link(cpuobj
, "secure-memory",
2181 OBJECT(secure_sysmem
), &error_abort
);
2185 /* Create the memory region only once, but link to all cpus. */
2188 * The property exists only if MemTag is supported.
2189 * If it is, we must allocate the ram to back that up.
2191 if (!object_property_find(cpuobj
, "tag-memory")) {
2192 error_report("MTE requested, but not supported "
2193 "by the guest CPU");
2197 tag_sysmem
= g_new(MemoryRegion
, 1);
2198 memory_region_init(tag_sysmem
, OBJECT(machine
),
2199 "tag-memory", UINT64_MAX
/ 32);
2202 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2203 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2204 "secure-tag-memory", UINT64_MAX
/ 32);
2206 /* As with ram, secure-tag takes precedence over tag. */
2207 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2212 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2215 object_property_set_link(cpuobj
, "secure-tag-memory",
2216 OBJECT(secure_tag_sysmem
),
2221 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2222 object_unref(cpuobj
);
2224 fdt_add_timer_nodes(vms
);
2225 fdt_add_cpu_nodes(vms
);
2227 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2230 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2232 create_gic(vms
, sysmem
);
2234 virt_cpu_post_init(vms
, sysmem
);
2236 fdt_add_pmu_nodes(vms
);
2238 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2241 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2242 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2246 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2247 machine
->ram_size
, "mach-virt.tag");
2250 vms
->highmem_ecam
&= (!firmware_loaded
|| aarch64
);
2256 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2257 vms
->acpi_dev
= create_acpi_ged(vms
);
2259 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2262 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2263 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2266 /* connect powerdown request */
2267 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2268 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2270 /* Create mmio transports, so the user can create virtio backends
2271 * (which will be automatically plugged in to the transports). If
2272 * no backend is created the transport will just sit harmlessly idle.
2274 create_virtio_devices(vms
);
2276 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2277 rom_set_fw(vms
->fw_cfg
);
2279 create_platform_bus(vms
);
2281 if (machine
->nvdimms_state
->is_enabled
) {
2282 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2283 .space_id
= AML_AS_SYSTEM_MEMORY
,
2284 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2285 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2288 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2289 arm_virt_nvdimm_acpi_dsmio
,
2290 vms
->fw_cfg
, OBJECT(vms
));
2293 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2294 vms
->bootinfo
.board_id
= -1;
2295 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2296 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2297 vms
->bootinfo
.skip_dtb_autoload
= true;
2298 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2299 vms
->bootinfo
.psci_conduit
= vms
->psci_conduit
;
2300 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2302 vms
->machine_done
.notify
= virt_machine_done
;
2303 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2306 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2308 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2313 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2315 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2317 vms
->secure
= value
;
2320 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2322 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2327 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2329 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2334 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2336 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2338 return vms
->highmem
;
2341 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2343 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2345 vms
->highmem
= value
;
2348 static bool virt_get_compact_highmem(Object
*obj
, Error
**errp
)
2350 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2352 return vms
->highmem_compact
;
2355 static void virt_set_compact_highmem(Object
*obj
, bool value
, Error
**errp
)
2357 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2359 vms
->highmem_compact
= value
;
2362 static bool virt_get_highmem_redists(Object
*obj
, Error
**errp
)
2364 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2366 return vms
->highmem_redists
;
2369 static void virt_set_highmem_redists(Object
*obj
, bool value
, Error
**errp
)
2371 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2373 vms
->highmem_redists
= value
;
2376 static bool virt_get_highmem_ecam(Object
*obj
, Error
**errp
)
2378 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2380 return vms
->highmem_ecam
;
2383 static void virt_set_highmem_ecam(Object
*obj
, bool value
, Error
**errp
)
2385 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2387 vms
->highmem_ecam
= value
;
2390 static bool virt_get_highmem_mmio(Object
*obj
, Error
**errp
)
2392 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2394 return vms
->highmem_mmio
;
2397 static void virt_set_highmem_mmio(Object
*obj
, bool value
, Error
**errp
)
2399 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2401 vms
->highmem_mmio
= value
;
2405 static bool virt_get_its(Object
*obj
, Error
**errp
)
2407 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2412 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2414 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2419 static bool virt_get_dtb_randomness(Object
*obj
, Error
**errp
)
2421 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2423 return vms
->dtb_randomness
;
2426 static void virt_set_dtb_randomness(Object
*obj
, bool value
, Error
**errp
)
2428 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2430 vms
->dtb_randomness
= value
;
2433 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2435 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2437 return g_strdup(vms
->oem_id
);
2440 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2442 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2443 size_t len
= strlen(value
);
2447 "User specified oem-id value is bigger than 6 bytes in size");
2451 strncpy(vms
->oem_id
, value
, 6);
2454 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2456 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2458 return g_strdup(vms
->oem_table_id
);
2461 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2464 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2465 size_t len
= strlen(value
);
2469 "User specified oem-table-id value is bigger than 8 bytes in size");
2472 strncpy(vms
->oem_table_id
, value
, 8);
2476 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2478 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2484 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2485 void *opaque
, Error
**errp
)
2487 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2488 OnOffAuto acpi
= vms
->acpi
;
2490 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2493 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2494 void *opaque
, Error
**errp
)
2496 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2498 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2501 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2503 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2508 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2510 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2515 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2517 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2522 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2524 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2529 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2531 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2534 switch (vms
->gic_version
) {
2535 case VIRT_GIC_VERSION_4
:
2538 case VIRT_GIC_VERSION_3
:
2545 return g_strdup(val
);
2548 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2550 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2552 if (!strcmp(value
, "4")) {
2553 vms
->gic_version
= VIRT_GIC_VERSION_4
;
2554 } else if (!strcmp(value
, "3")) {
2555 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2556 } else if (!strcmp(value
, "2")) {
2557 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2558 } else if (!strcmp(value
, "host")) {
2559 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2560 } else if (!strcmp(value
, "max")) {
2561 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2563 error_setg(errp
, "Invalid gic-version value");
2564 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2568 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2570 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2572 switch (vms
->iommu
) {
2573 case VIRT_IOMMU_NONE
:
2574 return g_strdup("none");
2575 case VIRT_IOMMU_SMMUV3
:
2576 return g_strdup("smmuv3");
2578 g_assert_not_reached();
2582 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2584 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2586 if (!strcmp(value
, "smmuv3")) {
2587 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2588 } else if (!strcmp(value
, "none")) {
2589 vms
->iommu
= VIRT_IOMMU_NONE
;
2591 error_setg(errp
, "Invalid iommu value");
2592 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2596 static bool virt_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
2598 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2600 return vms
->default_bus_bypass_iommu
;
2603 static void virt_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
2606 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2608 vms
->default_bus_bypass_iommu
= value
;
2611 static CpuInstanceProperties
2612 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2614 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2615 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2617 assert(cpu_index
< possible_cpus
->len
);
2618 return possible_cpus
->cpus
[cpu_index
].props
;
2621 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2623 int64_t socket_id
= ms
->possible_cpus
->cpus
[idx
].props
.socket_id
;
2625 return socket_id
% ms
->numa_state
->num_nodes
;
2628 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2631 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2632 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2633 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2635 if (ms
->possible_cpus
) {
2636 assert(ms
->possible_cpus
->len
== max_cpus
);
2637 return ms
->possible_cpus
;
2640 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2641 sizeof(CPUArchId
) * max_cpus
);
2642 ms
->possible_cpus
->len
= max_cpus
;
2643 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2644 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2645 ms
->possible_cpus
->cpus
[n
].arch_id
=
2646 virt_cpu_mp_affinity(vms
, n
);
2648 assert(!mc
->smp_props
.dies_supported
);
2649 ms
->possible_cpus
->cpus
[n
].props
.has_socket_id
= true;
2650 ms
->possible_cpus
->cpus
[n
].props
.socket_id
=
2651 n
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
);
2652 ms
->possible_cpus
->cpus
[n
].props
.has_cluster_id
= true;
2653 ms
->possible_cpus
->cpus
[n
].props
.cluster_id
=
2654 (n
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
;
2655 ms
->possible_cpus
->cpus
[n
].props
.has_core_id
= true;
2656 ms
->possible_cpus
->cpus
[n
].props
.core_id
=
2657 (n
/ ms
->smp
.threads
) % ms
->smp
.cores
;
2658 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2659 ms
->possible_cpus
->cpus
[n
].props
.thread_id
=
2660 n
% ms
->smp
.threads
;
2662 return ms
->possible_cpus
;
2665 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2668 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2669 const MachineState
*ms
= MACHINE(hotplug_dev
);
2670 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2672 if (!vms
->acpi_dev
) {
2674 "memory hotplug is not enabled: missing acpi-ged device");
2679 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2683 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2684 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2688 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2691 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2692 DeviceState
*dev
, Error
**errp
)
2694 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2695 MachineState
*ms
= MACHINE(hotplug_dev
);
2696 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2698 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2701 nvdimm_plug(ms
->nvdimms_state
);
2704 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2708 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2709 DeviceState
*dev
, Error
**errp
)
2711 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2713 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2714 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2715 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2716 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2717 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2718 hwaddr db_start
= 0, db_end
= 0;
2719 QList
*reserved_regions
;
2720 char *resv_prop_str
;
2722 if (vms
->iommu
!= VIRT_IOMMU_NONE
) {
2723 error_setg(errp
, "virt machine does not support multiple IOMMUs");
2727 switch (vms
->msi_controller
) {
2728 case VIRT_MSI_CTRL_NONE
:
2730 case VIRT_MSI_CTRL_ITS
:
2731 /* GITS_TRANSLATER page */
2732 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2733 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2734 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2736 case VIRT_MSI_CTRL_GICV2M
:
2737 /* MSI_SETSPI_NS page */
2738 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2739 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2742 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2744 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2746 reserved_regions
= qlist_new();
2747 qlist_append_str(reserved_regions
, resv_prop_str
);
2748 qdev_prop_set_array(dev
, "reserved-regions", reserved_regions
);
2749 g_free(resv_prop_str
);
2753 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2754 DeviceState
*dev
, Error
**errp
)
2756 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2758 if (vms
->platform_bus_dev
) {
2759 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2761 if (device_is_dynamic_sysbus(mc
, dev
)) {
2762 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2763 SYS_BUS_DEVICE(dev
));
2767 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2768 virt_memory_plug(hotplug_dev
, dev
, errp
);
2769 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2770 virtio_md_pci_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2773 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2774 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2776 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2777 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2778 create_virtio_iommu_dt_bindings(vms
);
2782 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2783 DeviceState
*dev
, Error
**errp
)
2785 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2787 if (!vms
->acpi_dev
) {
2789 "memory hotplug is not enabled: missing acpi-ged device");
2793 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2794 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
2798 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2802 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2803 DeviceState
*dev
, Error
**errp
)
2805 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2806 Error
*local_err
= NULL
;
2808 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2813 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2814 qdev_unrealize(dev
);
2817 error_propagate(errp
, local_err
);
2820 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2821 DeviceState
*dev
, Error
**errp
)
2823 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2824 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2825 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2826 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
),
2829 error_setg(errp
, "device unplug request for unsupported device"
2830 " type: %s", object_get_typename(OBJECT(dev
)));
2834 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2835 DeviceState
*dev
, Error
**errp
)
2837 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2838 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2839 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2840 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2842 error_setg(errp
, "virt: device unplug for unsupported device"
2843 " type: %s", object_get_typename(OBJECT(dev
)));
2847 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2850 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2852 if (device_is_dynamic_sysbus(mc
, dev
) ||
2853 object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2854 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
) ||
2855 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2856 return HOTPLUG_HANDLER(machine
);
2862 * for arm64 kvm_type [7-0] encodes the requested number of bits
2863 * in the IPA address space
2865 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2867 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2868 int max_vm_pa_size
, requested_pa_size
;
2871 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
2873 /* we freeze the memory map to compute the highest gpa */
2874 virt_set_memmap(vms
, max_vm_pa_size
);
2876 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2879 * KVM requires the IPA size to be at least 32 bits.
2881 if (requested_pa_size
< 32) {
2882 requested_pa_size
= 32;
2885 if (requested_pa_size
> max_vm_pa_size
) {
2886 error_report("-m and ,maxmem option values "
2887 "require an IPA range (%d bits) larger than "
2888 "the one supported by the host (%d bits)",
2889 requested_pa_size
, max_vm_pa_size
);
2893 * We return the requested PA log size, unless KVM only supports
2894 * the implicit legacy 40b IPA setting, in which case the kvm_type
2897 return fixed_ipa
? 0 : requested_pa_size
;
2900 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2902 MachineClass
*mc
= MACHINE_CLASS(oc
);
2903 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2904 static const char * const valid_cpu_types
[] = {
2906 ARM_CPU_TYPE_NAME("cortex-a7"),
2907 ARM_CPU_TYPE_NAME("cortex-a15"),
2908 #ifdef TARGET_AARCH64
2909 ARM_CPU_TYPE_NAME("cortex-a35"),
2910 ARM_CPU_TYPE_NAME("cortex-a55"),
2911 ARM_CPU_TYPE_NAME("cortex-a72"),
2912 ARM_CPU_TYPE_NAME("cortex-a76"),
2913 ARM_CPU_TYPE_NAME("cortex-a710"),
2914 ARM_CPU_TYPE_NAME("a64fx"),
2915 ARM_CPU_TYPE_NAME("neoverse-n1"),
2916 ARM_CPU_TYPE_NAME("neoverse-v1"),
2917 ARM_CPU_TYPE_NAME("neoverse-n2"),
2918 #endif /* TARGET_AARCH64 */
2919 #endif /* CONFIG_TCG */
2920 #ifdef TARGET_AARCH64
2921 ARM_CPU_TYPE_NAME("cortex-a53"),
2922 ARM_CPU_TYPE_NAME("cortex-a57"),
2923 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
2924 ARM_CPU_TYPE_NAME("host"),
2925 #endif /* CONFIG_KVM || CONFIG_HVF */
2926 #endif /* TARGET_AARCH64 */
2927 ARM_CPU_TYPE_NAME("max"),
2931 mc
->init
= machvirt_init
;
2932 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2933 * The value may be reduced later when we have more information about the
2934 * configuration of the particular instance.
2937 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2938 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2939 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2940 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2942 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2944 mc
->block_default_type
= IF_VIRTIO
;
2946 mc
->pci_allow_0_address
= true;
2947 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2948 mc
->minimum_page_bits
= 12;
2949 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
2950 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
2952 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
2954 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("max");
2956 mc
->valid_cpu_types
= valid_cpu_types
;
2957 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
2958 mc
->kvm_type
= virt_kvm_type
;
2959 assert(!mc
->get_hotplug_handler
);
2960 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
2961 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
2962 hc
->plug
= virt_machine_device_plug_cb
;
2963 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
2964 hc
->unplug
= virt_machine_device_unplug_cb
;
2965 mc
->nvdimm_supported
= true;
2966 mc
->smp_props
.clusters_supported
= true;
2967 mc
->auto_enable_numa_with_memhp
= true;
2968 mc
->auto_enable_numa_with_memdev
= true;
2969 /* platform instead of architectural choice */
2970 mc
->cpu_cluster_has_numa_boundary
= true;
2971 mc
->default_ram_id
= "mach-virt.ram";
2972 mc
->default_nic
= "virtio-net-pci";
2974 object_class_property_add(oc
, "acpi", "OnOffAuto",
2975 virt_get_acpi
, virt_set_acpi
,
2977 object_class_property_set_description(oc
, "acpi",
2979 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
2981 object_class_property_set_description(oc
, "secure",
2982 "Set on/off to enable/disable the ARM "
2983 "Security Extensions (TrustZone)");
2985 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
2987 object_class_property_set_description(oc
, "virtualization",
2988 "Set on/off to enable/disable emulating a "
2989 "guest CPU which implements the ARM "
2990 "Virtualization Extensions");
2992 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
2994 object_class_property_set_description(oc
, "highmem",
2995 "Set on/off to enable/disable using "
2996 "physical address space above 32 bits");
2998 object_class_property_add_bool(oc
, "compact-highmem",
2999 virt_get_compact_highmem
,
3000 virt_set_compact_highmem
);
3001 object_class_property_set_description(oc
, "compact-highmem",
3002 "Set on/off to enable/disable compact "
3003 "layout for high memory regions");
3005 object_class_property_add_bool(oc
, "highmem-redists",
3006 virt_get_highmem_redists
,
3007 virt_set_highmem_redists
);
3008 object_class_property_set_description(oc
, "highmem-redists",
3009 "Set on/off to enable/disable high "
3010 "memory region for GICv3 or GICv4 "
3013 object_class_property_add_bool(oc
, "highmem-ecam",
3014 virt_get_highmem_ecam
,
3015 virt_set_highmem_ecam
);
3016 object_class_property_set_description(oc
, "highmem-ecam",
3017 "Set on/off to enable/disable high "
3018 "memory region for PCI ECAM");
3020 object_class_property_add_bool(oc
, "highmem-mmio",
3021 virt_get_highmem_mmio
,
3022 virt_set_highmem_mmio
);
3023 object_class_property_set_description(oc
, "highmem-mmio",
3024 "Set on/off to enable/disable high "
3025 "memory region for PCI MMIO");
3027 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
3028 virt_set_gic_version
);
3029 object_class_property_set_description(oc
, "gic-version",
3031 "Valid values are 2, 3, 4, host and max");
3033 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
3034 object_class_property_set_description(oc
, "iommu",
3035 "Set the IOMMU type. "
3036 "Valid values are none and smmuv3");
3038 object_class_property_add_bool(oc
, "default-bus-bypass-iommu",
3039 virt_get_default_bus_bypass_iommu
,
3040 virt_set_default_bus_bypass_iommu
);
3041 object_class_property_set_description(oc
, "default-bus-bypass-iommu",
3042 "Set on/off to enable/disable "
3043 "bypass_iommu for default root bus");
3045 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
3047 object_class_property_set_description(oc
, "ras",
3048 "Set on/off to enable/disable reporting host memory errors "
3049 "to a KVM guest using ACPI and guest external abort exceptions");
3051 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
3052 object_class_property_set_description(oc
, "mte",
3053 "Set on/off to enable/disable emulating a "
3054 "guest CPU which implements the ARM "
3055 "Memory Tagging Extension");
3057 object_class_property_add_bool(oc
, "its", virt_get_its
,
3059 object_class_property_set_description(oc
, "its",
3060 "Set on/off to enable/disable "
3061 "ITS instantiation");
3063 object_class_property_add_bool(oc
, "dtb-randomness",
3064 virt_get_dtb_randomness
,
3065 virt_set_dtb_randomness
);
3066 object_class_property_set_description(oc
, "dtb-randomness",
3067 "Set off to disable passing random or "
3068 "non-deterministic dtb nodes to guest");
3070 object_class_property_add_bool(oc
, "dtb-kaslr-seed",
3071 virt_get_dtb_randomness
,
3072 virt_set_dtb_randomness
);
3073 object_class_property_set_description(oc
, "dtb-kaslr-seed",
3074 "Deprecated synonym of dtb-randomness");
3076 object_class_property_add_str(oc
, "x-oem-id",
3079 object_class_property_set_description(oc
, "x-oem-id",
3080 "Override the default value of field OEMID "
3081 "in ACPI table header."
3082 "The string may be up to 6 bytes in size");
3085 object_class_property_add_str(oc
, "x-oem-table-id",
3086 virt_get_oem_table_id
,
3087 virt_set_oem_table_id
);
3088 object_class_property_set_description(oc
, "x-oem-table-id",
3089 "Override the default value of field OEM Table ID "
3090 "in ACPI table header."
3091 "The string may be up to 8 bytes in size");
3095 static void virt_instance_init(Object
*obj
)
3097 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
3098 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
3100 /* EL3 is disabled by default on virt: this makes us consistent
3101 * between KVM and TCG for this board, and it also allows us to
3102 * boot UEFI blobs which assume no TrustZone support.
3104 vms
->secure
= false;
3106 /* EL2 is also disabled by default, for similar reasons */
3109 /* High memory is enabled by default */
3110 vms
->highmem
= true;
3111 vms
->highmem_compact
= !vmc
->no_highmem_compact
;
3112 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
3114 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
3115 vms
->highmem_mmio
= true;
3116 vms
->highmem_redists
= true;
3121 /* Default allows ITS instantiation */
3124 if (vmc
->no_tcg_its
) {
3125 vms
->tcg_its
= false;
3127 vms
->tcg_its
= true;
3131 /* Default disallows iommu instantiation */
3132 vms
->iommu
= VIRT_IOMMU_NONE
;
3134 /* The default root bus is attached to iommu by default */
3135 vms
->default_bus_bypass_iommu
= false;
3137 /* Default disallows RAS instantiation */
3140 /* MTE is disabled by default. */
3143 /* Supply kaslr-seed and rng-seed by default */
3144 vms
->dtb_randomness
= true;
3146 vms
->irqmap
= a15irqmap
;
3148 virt_flash_create(vms
);
3150 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
3151 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
3154 static const TypeInfo virt_machine_info
= {
3155 .name
= TYPE_VIRT_MACHINE
,
3156 .parent
= TYPE_MACHINE
,
3158 .instance_size
= sizeof(VirtMachineState
),
3159 .class_size
= sizeof(VirtMachineClass
),
3160 .class_init
= virt_machine_class_init
,
3161 .instance_init
= virt_instance_init
,
3162 .interfaces
= (InterfaceInfo
[]) {
3163 { TYPE_HOTPLUG_HANDLER
},
3168 static void machvirt_machine_init(void)
3170 type_register_static(&virt_machine_info
);
3172 type_init(machvirt_machine_init
);
3174 static void virt_machine_9_0_options(MachineClass
*mc
)
3177 DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
3179 static void virt_machine_8_2_options(MachineClass
*mc
)
3181 virt_machine_9_0_options(mc
);
3182 compat_props_add(mc
->compat_props
, hw_compat_8_2
, hw_compat_8_2_len
);
3184 DEFINE_VIRT_MACHINE(8, 2)
3186 static void virt_machine_8_1_options(MachineClass
*mc
)
3188 virt_machine_8_2_options(mc
);
3189 compat_props_add(mc
->compat_props
, hw_compat_8_1
, hw_compat_8_1_len
);
3191 DEFINE_VIRT_MACHINE(8, 1)
3193 static void virt_machine_8_0_options(MachineClass
*mc
)
3195 virt_machine_8_1_options(mc
);
3196 compat_props_add(mc
->compat_props
, hw_compat_8_0
, hw_compat_8_0_len
);
3198 DEFINE_VIRT_MACHINE(8, 0)
3200 static void virt_machine_7_2_options(MachineClass
*mc
)
3202 virt_machine_8_0_options(mc
);
3203 compat_props_add(mc
->compat_props
, hw_compat_7_2
, hw_compat_7_2_len
);
3205 DEFINE_VIRT_MACHINE(7, 2)
3207 static void virt_machine_7_1_options(MachineClass
*mc
)
3209 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3211 virt_machine_7_2_options(mc
);
3212 compat_props_add(mc
->compat_props
, hw_compat_7_1
, hw_compat_7_1_len
);
3213 /* Compact layout for high memory regions was introduced with 7.2 */
3214 vmc
->no_highmem_compact
= true;
3216 DEFINE_VIRT_MACHINE(7, 1)
3218 static void virt_machine_7_0_options(MachineClass
*mc
)
3220 virt_machine_7_1_options(mc
);
3221 compat_props_add(mc
->compat_props
, hw_compat_7_0
, hw_compat_7_0_len
);
3223 DEFINE_VIRT_MACHINE(7, 0)
3225 static void virt_machine_6_2_options(MachineClass
*mc
)
3227 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3229 virt_machine_7_0_options(mc
);
3230 compat_props_add(mc
->compat_props
, hw_compat_6_2
, hw_compat_6_2_len
);
3231 vmc
->no_tcg_lpa2
= true;
3233 DEFINE_VIRT_MACHINE(6, 2)
3235 static void virt_machine_6_1_options(MachineClass
*mc
)
3237 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3239 virt_machine_6_2_options(mc
);
3240 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
3241 mc
->smp_props
.prefer_sockets
= true;
3242 vmc
->no_cpu_topology
= true;
3244 /* qemu ITS was introduced with 6.2 */
3245 vmc
->no_tcg_its
= true;
3247 DEFINE_VIRT_MACHINE(6, 1)
3249 static void virt_machine_6_0_options(MachineClass
*mc
)
3251 virt_machine_6_1_options(mc
);
3252 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
3254 DEFINE_VIRT_MACHINE(6, 0)
3256 static void virt_machine_5_2_options(MachineClass
*mc
)
3258 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3260 virt_machine_6_0_options(mc
);
3261 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
3262 vmc
->no_secure_gpio
= true;
3264 DEFINE_VIRT_MACHINE(5, 2)
3266 static void virt_machine_5_1_options(MachineClass
*mc
)
3268 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3270 virt_machine_5_2_options(mc
);
3271 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
3272 vmc
->no_kvm_steal_time
= true;
3274 DEFINE_VIRT_MACHINE(5, 1)
3276 static void virt_machine_5_0_options(MachineClass
*mc
)
3278 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3280 virt_machine_5_1_options(mc
);
3281 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
3282 mc
->numa_mem_supported
= true;
3283 vmc
->acpi_expose_flash
= true;
3284 mc
->auto_enable_numa_with_memdev
= false;
3286 DEFINE_VIRT_MACHINE(5, 0)
3288 static void virt_machine_4_2_options(MachineClass
*mc
)
3290 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3292 virt_machine_5_0_options(mc
);
3293 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
3294 vmc
->kvm_no_adjvtime
= true;
3296 DEFINE_VIRT_MACHINE(4, 2)
3298 static void virt_machine_4_1_options(MachineClass
*mc
)
3300 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3302 virt_machine_4_2_options(mc
);
3303 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
3305 mc
->auto_enable_numa_with_memhp
= false;
3307 DEFINE_VIRT_MACHINE(4, 1)
3309 static void virt_machine_4_0_options(MachineClass
*mc
)
3311 virt_machine_4_1_options(mc
);
3312 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
3314 DEFINE_VIRT_MACHINE(4, 0)
3316 static void virt_machine_3_1_options(MachineClass
*mc
)
3318 virt_machine_4_0_options(mc
);
3319 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
3321 DEFINE_VIRT_MACHINE(3, 1)
3323 static void virt_machine_3_0_options(MachineClass
*mc
)
3325 virt_machine_3_1_options(mc
);
3326 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
3328 DEFINE_VIRT_MACHINE(3, 0)
3330 static void virt_machine_2_12_options(MachineClass
*mc
)
3332 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3334 virt_machine_3_0_options(mc
);
3335 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
3336 vmc
->no_highmem_ecam
= true;
3339 DEFINE_VIRT_MACHINE(2, 12)
3341 static void virt_machine_2_11_options(MachineClass
*mc
)
3343 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3345 virt_machine_2_12_options(mc
);
3346 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
3347 vmc
->smbios_old_sys_ver
= true;
3349 DEFINE_VIRT_MACHINE(2, 11)
3351 static void virt_machine_2_10_options(MachineClass
*mc
)
3353 virt_machine_2_11_options(mc
);
3354 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
3355 /* before 2.11 we never faulted accesses to bad addresses */
3356 mc
->ignore_memory_transaction_failures
= true;
3358 DEFINE_VIRT_MACHINE(2, 10)
3360 static void virt_machine_2_9_options(MachineClass
*mc
)
3362 virt_machine_2_10_options(mc
);
3363 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
3365 DEFINE_VIRT_MACHINE(2, 9)
3367 static void virt_machine_2_8_options(MachineClass
*mc
)
3369 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3371 virt_machine_2_9_options(mc
);
3372 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
3373 /* For 2.8 and earlier we falsely claimed in the DT that
3374 * our timers were edge-triggered, not level-triggered.
3376 vmc
->claim_edge_triggered_timers
= true;
3378 DEFINE_VIRT_MACHINE(2, 8)
3380 static void virt_machine_2_7_options(MachineClass
*mc
)
3382 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3384 virt_machine_2_8_options(mc
);
3385 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
3386 /* ITS was introduced with 2.8 */
3388 /* Stick with 1K pages for migration compatibility */
3389 mc
->minimum_page_bits
= 0;
3391 DEFINE_VIRT_MACHINE(2, 7)
3393 static void virt_machine_2_6_options(MachineClass
*mc
)
3395 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3397 virt_machine_2_7_options(mc
);
3398 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
3399 vmc
->disallow_affinity_adjustment
= true;
3400 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3403 DEFINE_VIRT_MACHINE(2, 6)