2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "qapi/error.h"
37 #include "hw/sysbus.h"
38 #include "hw/arm/boot.h"
39 #include "hw/arm/primecell.h"
40 #include "hw/arm/virt.h"
41 #include "hw/block/flash.h"
42 #include "hw/vfio/vfio-calxeda-xgmac.h"
43 #include "hw/vfio/vfio-amd-xgbe.h"
44 #include "hw/display/ramfb.h"
46 #include "sysemu/device_tree.h"
47 #include "sysemu/numa.h"
48 #include "sysemu/runstate.h"
49 #include "sysemu/tpm.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "hw/loader.h"
53 #include "qapi/error.h"
54 #include "qemu/bitops.h"
55 #include "qemu/error-report.h"
56 #include "qemu/module.h"
57 #include "hw/pci-host/gpex.h"
58 #include "hw/virtio/virtio-pci.h"
59 #include "hw/core/sysbus-fdt.h"
60 #include "hw/platform-bus.h"
61 #include "hw/qdev-properties.h"
62 #include "hw/arm/fdt.h"
63 #include "hw/intc/arm_gic.h"
64 #include "hw/intc/arm_gicv3_common.h"
67 #include "hw/firmware/smbios.h"
68 #include "qapi/visitor.h"
69 #include "qapi/qapi-visit-common.h"
70 #include "standard-headers/linux/input.h"
71 #include "hw/arm/smmuv3.h"
72 #include "hw/acpi/acpi.h"
73 #include "target/arm/internals.h"
74 #include "hw/mem/memory-device.h"
75 #include "hw/mem/pc-dimm.h"
76 #include "hw/mem/nvdimm.h"
77 #include "hw/acpi/generic_event_device.h"
78 #include "hw/virtio/virtio-mem-pci.h"
79 #include "hw/virtio/virtio-iommu.h"
80 #include "hw/char/pl011.h"
81 #include "qemu/guest-random.h"
83 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
84 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
87 MachineClass *mc = MACHINE_CLASS(oc); \
88 virt_machine_##major##_##minor##_options(mc); \
89 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
94 static const TypeInfo machvirt_##major##_##minor##_info = { \
95 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
96 .parent = TYPE_VIRT_MACHINE, \
97 .class_init = virt_##major##_##minor##_class_init, \
99 static void machvirt_machine_##major##_##minor##_init(void) \
101 type_register_static(&machvirt_##major##_##minor##_info); \
103 type_init(machvirt_machine_##major##_##minor##_init);
105 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
106 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
107 #define DEFINE_VIRT_MACHINE(major, minor) \
108 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
111 /* Number of external interrupt lines to configure the GIC with */
114 #define PLATFORM_BUS_NUM_IRQS 64
116 /* Legacy RAM limit in GB (< version 4.0) */
117 #define LEGACY_RAMLIMIT_GB 255
118 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
120 /* Addresses and sizes of our components.
121 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
122 * 128MB..256MB is used for miscellaneous device I/O.
123 * 256MB..1GB is reserved for possible future PCI support (ie where the
124 * PCI memory window will go if we add a PCI host controller).
125 * 1GB and up is RAM (which may happily spill over into the
126 * high memory region beyond 4GB).
127 * This represents a compromise between how much RAM can be given to
128 * a 32 bit VM and leaving space for expansion and in particular for PCI.
129 * Note that devices should generally be placed at multiples of 0x10000,
130 * to accommodate guests using 64K pages.
132 static const MemMapEntry base_memmap
[] = {
133 /* Space up to 0x8000000 is reserved for a boot ROM */
134 [VIRT_FLASH
] = { 0, 0x08000000 },
135 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
136 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
137 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
138 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
139 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
140 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
141 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
142 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
143 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
144 /* This redistributor space allows up to 2*64kB*123 CPUs */
145 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
146 [VIRT_UART
] = { 0x09000000, 0x00001000 },
147 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
148 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
149 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
150 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
151 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
152 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
153 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
154 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
155 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
156 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
157 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
158 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
159 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
160 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
161 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
162 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
163 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
164 /* Actual RAM size depends on initial RAM and device memory settings */
165 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
169 * Highmem IO Regions: This memory map is floating, located after the RAM.
170 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
171 * top of the RAM, so that its base get the same alignment as the size,
172 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
173 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
174 * Note the extended_memmap is sized so that it eventually also includes the
175 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
176 * index of base_memmap).
178 static MemMapEntry extended_memmap
[] = {
179 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
180 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
181 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
182 /* Second PCIe window */
183 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
186 static const int a15irqmap
[] = {
189 [VIRT_PCIE
] = 3, /* ... to 6 */
191 [VIRT_SECURE_UART
] = 8,
193 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
194 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
195 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
196 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
199 static const char *valid_cpus
[] = {
200 ARM_CPU_TYPE_NAME("cortex-a7"),
201 ARM_CPU_TYPE_NAME("cortex-a15"),
202 ARM_CPU_TYPE_NAME("cortex-a35"),
203 ARM_CPU_TYPE_NAME("cortex-a53"),
204 ARM_CPU_TYPE_NAME("cortex-a57"),
205 ARM_CPU_TYPE_NAME("cortex-a72"),
206 ARM_CPU_TYPE_NAME("cortex-a76"),
207 ARM_CPU_TYPE_NAME("a64fx"),
208 ARM_CPU_TYPE_NAME("neoverse-n1"),
209 ARM_CPU_TYPE_NAME("host"),
210 ARM_CPU_TYPE_NAME("max"),
213 static bool cpu_type_valid(const char *cpu
)
217 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
218 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
225 static void create_randomness(MachineState
*ms
, const char *node
)
232 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
235 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
.kaslr
);
236 qemu_fdt_setprop(ms
->fdt
, node
, "rng-seed", seed
.rng
, sizeof(seed
.rng
));
239 static void create_fdt(VirtMachineState
*vms
)
241 MachineState
*ms
= MACHINE(vms
);
242 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
243 void *fdt
= create_device_tree(&vms
->fdt_size
);
246 error_report("create_device_tree() failed");
253 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
254 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
255 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
256 qemu_fdt_setprop_string(fdt
, "/", "model", "linux,dummy-virt");
258 /* /chosen must exist for load_dtb to fill in necessary properties later */
259 qemu_fdt_add_subnode(fdt
, "/chosen");
260 if (vms
->dtb_randomness
) {
261 create_randomness(ms
, "/chosen");
265 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
266 if (vms
->dtb_randomness
) {
267 create_randomness(ms
, "/secure-chosen");
271 /* Clock node, for the benefit of the UART. The kernel device tree
272 * binding documentation claims the PL011 node clock properties are
273 * optional but in practice if you omit them the kernel refuses to
274 * probe for the device.
276 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
277 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
278 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
279 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
280 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
281 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
283 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
285 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
286 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
287 uint32_t *matrix
= g_malloc0(size
);
290 for (i
= 0; i
< nb_numa_nodes
; i
++) {
291 for (j
= 0; j
< nb_numa_nodes
; j
++) {
292 idx
= (i
* nb_numa_nodes
+ j
) * 3;
293 matrix
[idx
+ 0] = cpu_to_be32(i
);
294 matrix
[idx
+ 1] = cpu_to_be32(j
);
296 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
300 qemu_fdt_add_subnode(fdt
, "/distance-map");
301 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
302 "numa-distance-map-v1");
303 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
309 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
311 /* On real hardware these interrupts are level-triggered.
312 * On KVM they were edge-triggered before host kernel version 4.4,
313 * and level-triggered afterwards.
314 * On emulated QEMU they are level-triggered.
316 * Getting the DTB info about them wrong is awkward for some
318 * pre-4.8 ignore the DT and leave the interrupt configured
319 * with whatever the GIC reset value (or the bootloader) left it at
320 * 4.8 before rc6 honour the incorrect data by programming it back
321 * into the GIC, causing problems
322 * 4.8rc6 and later ignore the DT and always write "level triggered"
325 * For backwards-compatibility, virt-2.8 and earlier will continue
326 * to say these are edge-triggered, but later machines will report
327 * the correct information.
330 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
331 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
332 MachineState
*ms
= MACHINE(vms
);
334 if (vmc
->claim_edge_triggered_timers
) {
335 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
338 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
339 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
340 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
341 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
344 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
346 armcpu
= ARM_CPU(qemu_get_cpu(0));
347 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
348 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
349 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
350 compat
, sizeof(compat
));
352 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
355 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
356 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
357 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
358 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
359 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
360 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
363 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
367 const MachineState
*ms
= MACHINE(vms
);
368 const VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
369 int smp_cpus
= ms
->smp
.cpus
;
372 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
373 * On ARM v8 64-bit systems value should be set to 2,
374 * that corresponds to the MPIDR_EL1 register size.
375 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
376 * in the system, #address-cells can be set to 1, since
377 * MPIDR_EL1[63:32] bits are not used for CPUs
380 * Here we actually don't know whether our system is 32- or 64-bit one.
381 * The simplest way to go is to examine affinity IDs of all our CPUs. If
382 * at least one of them has Aff3 populated, we set #address-cells to 2.
384 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
385 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
387 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
393 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
394 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
395 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
397 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
398 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
399 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
400 CPUState
*cs
= CPU(armcpu
);
402 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
403 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
404 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
405 armcpu
->dtb_compatible
);
407 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
408 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
409 "enable-method", "psci");
412 if (addr_cells
== 2) {
413 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
414 armcpu
->mp_affinity
);
416 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
417 armcpu
->mp_affinity
);
420 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
421 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
422 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
425 if (!vmc
->no_cpu_topology
) {
426 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle",
427 qemu_fdt_alloc_phandle(ms
->fdt
));
433 if (!vmc
->no_cpu_topology
) {
435 * Add vCPU topology description through fdt node cpu-map.
437 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
438 * In a SMP system, the hierarchy of CPUs can be defined through
439 * four entities that are used to describe the layout of CPUs in
440 * the system: socket/cluster/core/thread.
442 * A socket node represents the boundary of system physical package
443 * and its child nodes must be one or more cluster nodes. A system
444 * can contain several layers of clustering within a single physical
445 * package and cluster nodes can be contained in parent cluster nodes.
447 * Note: currently we only support one layer of clustering within
448 * each physical package.
450 qemu_fdt_add_subnode(ms
->fdt
, "/cpus/cpu-map");
452 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
453 char *cpu_path
= g_strdup_printf("/cpus/cpu@%d", cpu
);
456 if (ms
->smp
.threads
> 1) {
457 map_path
= g_strdup_printf(
458 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
459 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
),
460 (cpu
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
,
461 (cpu
/ ms
->smp
.threads
) % ms
->smp
.cores
,
462 cpu
% ms
->smp
.threads
);
464 map_path
= g_strdup_printf(
465 "/cpus/cpu-map/socket%d/cluster%d/core%d",
466 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
),
467 (cpu
/ ms
->smp
.cores
) % ms
->smp
.clusters
,
468 cpu
% ms
->smp
.cores
);
470 qemu_fdt_add_path(ms
->fdt
, map_path
);
471 qemu_fdt_setprop_phandle(ms
->fdt
, map_path
, "cpu", cpu_path
);
479 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
482 MachineState
*ms
= MACHINE(vms
);
484 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
485 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
486 vms
->memmap
[VIRT_GIC_ITS
].base
);
487 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
488 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
490 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
491 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#msi-cells", 1);
492 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
493 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
494 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
495 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
499 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
501 MachineState
*ms
= MACHINE(vms
);
504 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
505 vms
->memmap
[VIRT_GIC_V2M
].base
);
506 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
507 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
508 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
509 "arm,gic-v2m-frame");
510 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
511 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
512 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
513 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
514 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
518 static void fdt_add_gic_node(VirtMachineState
*vms
)
520 MachineState
*ms
= MACHINE(vms
);
523 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
524 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
526 nodename
= g_strdup_printf("/intc@%" PRIx64
,
527 vms
->memmap
[VIRT_GIC_DIST
].base
);
528 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
529 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
530 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
531 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
532 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
533 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
534 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
535 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
537 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
540 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
541 "#redistributor-regions", nb_redist_regions
);
543 if (nb_redist_regions
== 1) {
544 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
545 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
546 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
547 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
548 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
550 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
551 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
552 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
553 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
554 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
555 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
556 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
560 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
561 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
562 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
565 /* 'cortex-a15-gic' means 'GIC v2' */
566 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
567 "arm,cortex-a15-gic");
569 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
570 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
571 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
572 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
573 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
575 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
576 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
577 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
578 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
579 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
580 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
581 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
582 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
583 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
584 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
585 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
586 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
590 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
594 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
596 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
597 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
598 MachineState
*ms
= MACHINE(vms
);
600 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
601 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
605 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
606 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
607 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
608 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
611 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
612 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
613 const char compat
[] = "arm,armv8-pmuv3";
614 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
615 compat
, sizeof(compat
));
616 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
617 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
621 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
624 MachineState
*ms
= MACHINE(vms
);
625 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
626 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
629 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
632 if (ms
->nvdimms_state
->is_enabled
) {
633 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
636 dev
= qdev_new(TYPE_ACPI_GED
);
637 qdev_prop_set_uint32(dev
, "ged-event", event
);
639 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
640 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
641 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
643 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
648 static void create_its(VirtMachineState
*vms
)
650 const char *itsclass
= its_class_name();
653 if (!strcmp(itsclass
, "arm-gicv3-its")) {
660 /* Do nothing if not supported */
664 dev
= qdev_new(itsclass
);
666 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
668 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
669 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
671 fdt_add_its_gic_node(vms
);
672 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
675 static void create_v2m(VirtMachineState
*vms
)
678 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
681 dev
= qdev_new("arm-gicv2m");
682 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
683 qdev_prop_set_uint32(dev
, "base-spi", irq
);
684 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
685 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
687 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
688 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
689 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
692 fdt_add_v2m_gic_node(vms
);
693 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
696 static void create_gic(VirtMachineState
*vms
, MemoryRegion
*mem
)
698 MachineState
*ms
= MACHINE(vms
);
699 /* We create a standalone GIC */
700 SysBusDevice
*gicbusdev
;
703 unsigned int smp_cpus
= ms
->smp
.cpus
;
704 uint32_t nb_redist_regions
= 0;
707 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
708 gictype
= gic_class_name();
710 gictype
= gicv3_class_name();
713 switch (vms
->gic_version
) {
714 case VIRT_GIC_VERSION_2
:
717 case VIRT_GIC_VERSION_3
:
720 case VIRT_GIC_VERSION_4
:
724 g_assert_not_reached();
726 vms
->gic
= qdev_new(gictype
);
727 qdev_prop_set_uint32(vms
->gic
, "revision", revision
);
728 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
729 /* Note that the num-irq property counts both internal and external
730 * interrupts; there are always 32 of the former (mandated by GIC spec).
732 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
733 if (!kvm_irqchip_in_kernel()) {
734 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
737 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
738 uint32_t redist0_capacity
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
739 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
741 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
743 qdev_prop_set_uint32(vms
->gic
, "len-redist-region-count",
745 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[0]", redist0_count
);
747 if (!kvm_irqchip_in_kernel()) {
749 object_property_set_link(OBJECT(vms
->gic
), "sysmem",
750 OBJECT(mem
), &error_fatal
);
751 qdev_prop_set_bit(vms
->gic
, "has-lpi", true);
755 if (nb_redist_regions
== 2) {
756 uint32_t redist1_capacity
=
757 virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
759 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[1]",
760 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
763 if (!kvm_irqchip_in_kernel()) {
764 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
768 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
769 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
770 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
771 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
772 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
773 if (nb_redist_regions
== 2) {
774 sysbus_mmio_map(gicbusdev
, 2,
775 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
778 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
780 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
781 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
785 /* Wire the outputs from each CPU's generic timer and the GICv3
786 * maintenance interrupt signal to the appropriate GIC PPI inputs,
787 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
789 for (i
= 0; i
< smp_cpus
; i
++) {
790 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
791 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
793 /* Mapping from the output timer irq lines from the CPU to the
794 * GIC PPI inputs we use for the virt board.
796 const int timer_irq
[] = {
797 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
798 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
799 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
800 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
803 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
804 qdev_connect_gpio_out(cpudev
, irq
,
805 qdev_get_gpio_in(vms
->gic
,
806 ppibase
+ timer_irq
[irq
]));
809 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
810 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
811 ppibase
+ ARCH_GIC_MAINT_IRQ
);
812 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
814 } else if (vms
->virt
) {
815 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
816 ppibase
+ ARCH_GIC_MAINT_IRQ
);
817 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
820 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
821 qdev_get_gpio_in(vms
->gic
, ppibase
824 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
825 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
826 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
827 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
828 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
829 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
830 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
833 fdt_add_gic_node(vms
);
835 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& vms
->its
) {
837 } else if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
842 static void create_uart(const VirtMachineState
*vms
, int uart
,
843 MemoryRegion
*mem
, Chardev
*chr
)
846 hwaddr base
= vms
->memmap
[uart
].base
;
847 hwaddr size
= vms
->memmap
[uart
].size
;
848 int irq
= vms
->irqmap
[uart
];
849 const char compat
[] = "arm,pl011\0arm,primecell";
850 const char clocknames
[] = "uartclk\0apb_pclk";
851 DeviceState
*dev
= qdev_new(TYPE_PL011
);
852 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
853 MachineState
*ms
= MACHINE(vms
);
855 qdev_prop_set_chr(dev
, "chardev", chr
);
856 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
857 memory_region_add_subregion(mem
, base
,
858 sysbus_mmio_get_region(s
, 0));
859 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
861 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
862 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
863 /* Note that we can't use setprop_string because of the embedded NUL */
864 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
865 compat
, sizeof(compat
));
866 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
868 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
869 GIC_FDT_IRQ_TYPE_SPI
, irq
,
870 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
871 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
872 vms
->clock_phandle
, vms
->clock_phandle
);
873 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
874 clocknames
, sizeof(clocknames
));
876 if (uart
== VIRT_UART
) {
877 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
879 /* Mark as not usable by the normal world */
880 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
881 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
883 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
890 static void create_rtc(const VirtMachineState
*vms
)
893 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
894 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
895 int irq
= vms
->irqmap
[VIRT_RTC
];
896 const char compat
[] = "arm,pl031\0arm,primecell";
897 MachineState
*ms
= MACHINE(vms
);
899 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
901 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
902 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
903 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
904 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
906 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
907 GIC_FDT_IRQ_TYPE_SPI
, irq
,
908 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
909 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
910 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
914 static DeviceState
*gpio_key_dev
;
915 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
917 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
920 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
922 /* use gpio Pin 3 for power button event */
923 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
927 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
930 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
931 qdev_get_gpio_in(pl061_dev
, 3));
933 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
934 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
936 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
937 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
938 "label", "GPIO Key Poweroff");
939 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
941 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
942 "gpios", phandle
, 3, 0);
945 #define SECURE_GPIO_POWEROFF 0
946 #define SECURE_GPIO_RESET 1
948 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
951 DeviceState
*gpio_pwr_dev
;
954 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
956 /* connect secure pl061 to gpio-pwr */
957 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
958 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
959 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
960 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
962 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
963 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
965 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
966 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
967 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
968 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
971 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
972 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
974 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
975 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
976 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
977 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
981 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
985 DeviceState
*pl061_dev
;
986 hwaddr base
= vms
->memmap
[gpio
].base
;
987 hwaddr size
= vms
->memmap
[gpio
].size
;
988 int irq
= vms
->irqmap
[gpio
];
989 const char compat
[] = "arm,pl061\0arm,primecell";
991 MachineState
*ms
= MACHINE(vms
);
993 pl061_dev
= qdev_new("pl061");
994 /* Pull lines down to 0 if not driven by the PL061 */
995 qdev_prop_set_uint32(pl061_dev
, "pullups", 0);
996 qdev_prop_set_uint32(pl061_dev
, "pulldowns", 0xff);
997 s
= SYS_BUS_DEVICE(pl061_dev
);
998 sysbus_realize_and_unref(s
, &error_fatal
);
999 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
1000 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
1002 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1003 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
1004 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1005 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1007 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
1008 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
1009 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
1010 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1011 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1012 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
1013 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
1014 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
1015 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
1017 if (gpio
!= VIRT_GPIO
) {
1018 /* Mark as not usable by the normal world */
1019 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1020 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1024 /* Child gpio devices */
1025 if (gpio
== VIRT_GPIO
) {
1026 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
1028 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
1032 static void create_virtio_devices(const VirtMachineState
*vms
)
1035 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
1036 MachineState
*ms
= MACHINE(vms
);
1038 /* We create the transports in forwards order. Since qbus_realize()
1039 * prepends (not appends) new child buses, the incrementing loop below will
1040 * create a list of virtio-mmio buses with decreasing base addresses.
1042 * When a -device option is processed from the command line,
1043 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1044 * order. The upshot is that -device options in increasing command line
1045 * order are mapped to virtio-mmio buses with decreasing base addresses.
1047 * When this code was originally written, that arrangement ensured that the
1048 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1049 * the first -device on the command line. (The end-to-end order is a
1050 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1051 * guest kernel's name-to-address assignment strategy.)
1053 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1054 * the message, if not necessarily the code, of commit 70161ff336.
1055 * Therefore the loop now establishes the inverse of the original intent.
1057 * Unfortunately, we can't counteract the kernel change by reversing the
1058 * loop; it would break existing command lines.
1060 * In any case, the kernel makes no guarantee about the stability of
1061 * enumeration order of virtio devices (as demonstrated by it changing
1062 * between kernel versions). For reliable and stable identification
1063 * of disks users must use UUIDs or similar mechanisms.
1065 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
1066 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1067 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1069 sysbus_create_simple("virtio-mmio", base
,
1070 qdev_get_gpio_in(vms
->gic
, irq
));
1073 /* We add dtb nodes in reverse order so that they appear in the finished
1074 * device tree lowest address first.
1076 * Note that this mapping is independent of the loop above. The previous
1077 * loop influences virtio device to virtio transport assignment, whereas
1078 * this loop controls how virtio transports are laid out in the dtb.
1080 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
1082 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1083 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1085 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
1086 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1087 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1088 "compatible", "virtio,mmio");
1089 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1091 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1092 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1093 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1094 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1099 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1101 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1103 const char *alias_prop_name
)
1106 * Create a single flash device. We use the same parameters as
1107 * the flash devices on the Versatile Express board.
1109 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1111 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1112 qdev_prop_set_uint8(dev
, "width", 4);
1113 qdev_prop_set_uint8(dev
, "device-width", 2);
1114 qdev_prop_set_bit(dev
, "big-endian", false);
1115 qdev_prop_set_uint16(dev
, "id0", 0x89);
1116 qdev_prop_set_uint16(dev
, "id1", 0x18);
1117 qdev_prop_set_uint16(dev
, "id2", 0x00);
1118 qdev_prop_set_uint16(dev
, "id3", 0x00);
1119 qdev_prop_set_string(dev
, "name", name
);
1120 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1121 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1122 OBJECT(dev
), "drive");
1123 return PFLASH_CFI01(dev
);
1126 static void virt_flash_create(VirtMachineState
*vms
)
1128 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1129 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1132 static void virt_flash_map1(PFlashCFI01
*flash
,
1133 hwaddr base
, hwaddr size
,
1134 MemoryRegion
*sysmem
)
1136 DeviceState
*dev
= DEVICE(flash
);
1138 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1139 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1140 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1141 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1143 memory_region_add_subregion(sysmem
, base
,
1144 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1148 static void virt_flash_map(VirtMachineState
*vms
,
1149 MemoryRegion
*sysmem
,
1150 MemoryRegion
*secure_sysmem
)
1153 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1154 * sysmem is the system memory space. secure_sysmem is the secure view
1155 * of the system, and the first flash device should be made visible only
1156 * there. The second flash device is visible to both secure and nonsecure.
1157 * If sysmem == secure_sysmem this means there is no separate Secure
1158 * address space and both flash devices are generally visible.
1160 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1161 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1163 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1165 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1169 static void virt_flash_fdt(VirtMachineState
*vms
,
1170 MemoryRegion
*sysmem
,
1171 MemoryRegion
*secure_sysmem
)
1173 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1174 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1175 MachineState
*ms
= MACHINE(vms
);
1178 if (sysmem
== secure_sysmem
) {
1179 /* Report both flash devices as a single node in the DT */
1180 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1181 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1182 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1183 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1184 2, flashbase
, 2, flashsize
,
1185 2, flashbase
+ flashsize
, 2, flashsize
);
1186 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1190 * Report the devices as separate nodes so we can mark one as
1191 * only visible to the secure world.
1193 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1194 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1195 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1196 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1197 2, flashbase
, 2, flashsize
);
1198 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1199 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1200 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1203 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
+ flashsize
);
1204 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1205 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1206 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1207 2, flashbase
+ flashsize
, 2, flashsize
);
1208 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1213 static bool virt_firmware_init(VirtMachineState
*vms
,
1214 MemoryRegion
*sysmem
,
1215 MemoryRegion
*secure_sysmem
)
1218 const char *bios_name
;
1219 BlockBackend
*pflash_blk0
;
1221 /* Map legacy -drive if=pflash to machine properties */
1222 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1223 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1224 drive_get(IF_PFLASH
, 0, i
));
1227 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1229 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1231 bios_name
= MACHINE(vms
)->firmware
;
1238 error_report("The contents of the first flash device may be "
1239 "specified with -bios or with -drive if=pflash... "
1240 "but you cannot use both options at once");
1244 /* Fall back to -bios */
1246 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1248 error_report("Could not find ROM image '%s'", bios_name
);
1251 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1252 image_size
= load_image_mr(fname
, mr
);
1254 if (image_size
< 0) {
1255 error_report("Could not load ROM image '%s'", bios_name
);
1260 return pflash_blk0
|| bios_name
;
1263 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1265 MachineState
*ms
= MACHINE(vms
);
1266 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1267 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1271 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1272 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1274 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1275 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1276 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1277 "compatible", "qemu,fw-cfg-mmio");
1278 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1280 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1285 static void create_pcie_irq_map(const MachineState
*ms
,
1286 uint32_t gic_phandle
,
1287 int first_irq
, const char *nodename
)
1290 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1291 uint32_t *irq_map
= full_irq_map
;
1293 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1294 for (pin
= 0; pin
< 4; pin
++) {
1295 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1296 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1297 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1301 devfn
<< 8, 0, 0, /* devfn */
1302 pin
+ 1, /* PCI pin */
1303 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1305 /* Convert map to big endian */
1306 for (i
= 0; i
< 10; i
++) {
1307 irq_map
[i
] = cpu_to_be32(map
[i
]);
1313 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1314 full_irq_map
, sizeof(full_irq_map
));
1316 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1317 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1322 static void create_smmu(const VirtMachineState
*vms
,
1326 const char compat
[] = "arm,smmu-v3";
1327 int irq
= vms
->irqmap
[VIRT_SMMU
];
1329 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1330 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1331 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1333 MachineState
*ms
= MACHINE(vms
);
1335 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1339 dev
= qdev_new("arm-smmuv3");
1341 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1343 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1344 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1345 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1346 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1347 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1350 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1351 qemu_fdt_add_subnode(ms
->fdt
, node
);
1352 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1353 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1355 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1356 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1357 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1358 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1359 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1361 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1364 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1366 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1368 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1372 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1374 const char compat
[] = "virtio,pci-iommu\0pci1af4,1057";
1375 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1376 MachineState
*ms
= MACHINE(vms
);
1379 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1381 node
= g_strdup_printf("%s/virtio_iommu@%x,%x", vms
->pciehb_nodename
,
1382 PCI_SLOT(bdf
), PCI_FUNC(bdf
));
1383 qemu_fdt_add_subnode(ms
->fdt
, node
);
1384 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1385 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1386 1, bdf
<< 8, 1, 0, 1, 0,
1389 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1390 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1393 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1394 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1395 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1398 static void create_pcie(VirtMachineState
*vms
)
1400 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1401 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1402 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1403 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1404 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1405 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1406 hwaddr base_ecam
, size_ecam
;
1407 hwaddr base
= base_mmio
;
1409 int irq
= vms
->irqmap
[VIRT_PCIE
];
1410 MemoryRegion
*mmio_alias
;
1411 MemoryRegion
*mmio_reg
;
1412 MemoryRegion
*ecam_alias
;
1413 MemoryRegion
*ecam_reg
;
1418 MachineState
*ms
= MACHINE(vms
);
1420 dev
= qdev_new(TYPE_GPEX_HOST
);
1421 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1423 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1424 base_ecam
= vms
->memmap
[ecam_id
].base
;
1425 size_ecam
= vms
->memmap
[ecam_id
].size
;
1426 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1427 /* Map only the first size_ecam bytes of ECAM space */
1428 ecam_alias
= g_new0(MemoryRegion
, 1);
1429 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1430 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1431 ecam_reg
, 0, size_ecam
);
1432 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1434 /* Map the MMIO window into system address space so as to expose
1435 * the section of PCI MMIO space which starts at the same base address
1436 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1439 mmio_alias
= g_new0(MemoryRegion
, 1);
1440 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1441 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1442 mmio_reg
, base_mmio
, size_mmio
);
1443 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1445 if (vms
->highmem_mmio
) {
1446 /* Map high MMIO space */
1447 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1449 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1450 mmio_reg
, base_mmio_high
, size_mmio_high
);
1451 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1455 /* Map IO port space */
1456 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1458 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1459 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1460 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1461 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1464 pci
= PCI_HOST_BRIDGE(dev
);
1465 pci
->bypass_iommu
= vms
->default_bus_bypass_iommu
;
1466 vms
->bus
= pci
->bus
;
1468 for (i
= 0; i
< nb_nics
; i
++) {
1469 NICInfo
*nd
= &nd_table
[i
];
1472 nd
->model
= g_strdup("virtio");
1475 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1479 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1480 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1481 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1482 "compatible", "pci-host-ecam-generic");
1483 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1484 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1485 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1486 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1487 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1489 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1491 if (vms
->msi_phandle
) {
1492 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-map",
1493 0, vms
->msi_phandle
, 0, 0x10000);
1496 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1497 2, base_ecam
, 2, size_ecam
);
1499 if (vms
->highmem_mmio
) {
1500 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1501 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1502 2, base_pio
, 2, size_pio
,
1503 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1504 2, base_mmio
, 2, size_mmio
,
1505 1, FDT_PCI_RANGE_MMIO_64BIT
,
1507 2, base_mmio_high
, 2, size_mmio_high
);
1509 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1510 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1511 2, base_pio
, 2, size_pio
,
1512 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1513 2, base_mmio
, 2, size_mmio
);
1516 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1517 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1520 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1522 switch (vms
->iommu
) {
1523 case VIRT_IOMMU_SMMUV3
:
1524 create_smmu(vms
, vms
->bus
);
1525 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1526 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1529 g_assert_not_reached();
1534 static void create_platform_bus(VirtMachineState
*vms
)
1539 MemoryRegion
*sysmem
= get_system_memory();
1541 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1542 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1543 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1544 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1545 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1546 vms
->platform_bus_dev
= dev
;
1548 s
= SYS_BUS_DEVICE(dev
);
1549 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1550 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1551 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1554 memory_region_add_subregion(sysmem
,
1555 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1556 sysbus_mmio_get_region(s
, 0));
1559 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1560 hwaddr base
, hwaddr size
,
1563 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1565 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1566 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1569 static void create_secure_ram(VirtMachineState
*vms
,
1570 MemoryRegion
*secure_sysmem
,
1571 MemoryRegion
*secure_tag_sysmem
)
1573 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1575 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1576 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1577 MachineState
*ms
= MACHINE(vms
);
1579 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1581 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1583 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1584 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1585 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1586 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1587 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1588 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1590 if (secure_tag_sysmem
) {
1591 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1597 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1599 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1601 MachineState
*ms
= MACHINE(board
);
1604 *fdt_size
= board
->fdt_size
;
1608 static void virt_build_smbios(VirtMachineState
*vms
)
1610 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1611 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1612 uint8_t *smbios_tables
, *smbios_anchor
;
1613 size_t smbios_tables_len
, smbios_anchor_len
;
1614 const char *product
= "QEMU Virtual Machine";
1616 if (kvm_enabled()) {
1617 product
= "KVM Virtual Machine";
1620 smbios_set_defaults("QEMU", product
,
1621 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1622 true, SMBIOS_ENTRY_POINT_TYPE_64
);
1624 smbios_get_tables(MACHINE(vms
), NULL
, 0,
1625 &smbios_tables
, &smbios_tables_len
,
1626 &smbios_anchor
, &smbios_anchor_len
,
1629 if (smbios_anchor
) {
1630 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1631 smbios_tables
, smbios_tables_len
);
1632 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1633 smbios_anchor
, smbios_anchor_len
);
1638 void virt_machine_done(Notifier
*notifier
, void *data
)
1640 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1642 MachineState
*ms
= MACHINE(vms
);
1643 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1644 struct arm_boot_info
*info
= &vms
->bootinfo
;
1645 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1648 * If the user provided a dtb, we assume the dynamic sysbus nodes
1649 * already are integrated there. This corresponds to a use case where
1650 * the dynamic sysbus nodes are complex and their generation is not yet
1651 * supported. In that case the user can take charge of the guest dt
1652 * while qemu takes charge of the qom stuff.
1654 if (info
->dtb_filename
== NULL
) {
1655 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1656 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1657 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1658 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1660 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1664 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1666 virt_acpi_setup(vms
);
1667 virt_build_smbios(vms
);
1670 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1672 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1673 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1675 if (!vmc
->disallow_affinity_adjustment
) {
1676 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1677 * GIC's target-list limitations. 32-bit KVM hosts currently
1678 * always create clusters of 4 CPUs, but that is expected to
1679 * change when they gain support for gicv3. When KVM is enabled
1680 * it will override the changes we make here, therefore our
1681 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1682 * and to improve SGI efficiency.
1684 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
1685 clustersz
= GIC_TARGETLIST_BITS
;
1687 clustersz
= GICV3_TARGETLIST_BITS
;
1690 return arm_cpu_mp_affinity(idx
, clustersz
);
1693 static void virt_set_memmap(VirtMachineState
*vms
, int pa_bits
)
1695 MachineState
*ms
= MACHINE(vms
);
1696 hwaddr base
, device_memory_base
, device_memory_size
, memtop
;
1699 vms
->memmap
= extended_memmap
;
1701 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1702 vms
->memmap
[i
] = base_memmap
[i
];
1705 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1706 error_report("unsupported number of memory slots: %"PRIu64
,
1712 * !highmem is exactly the same as limiting the PA space to 32bit,
1713 * irrespective of the underlying capabilities of the HW.
1715 if (!vms
->highmem
) {
1720 * We compute the base of the high IO region depending on the
1721 * amount of initial and device memory. The device memory start/size
1722 * is aligned on 1GiB. We never put the high IO region below 256GiB
1723 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1724 * The device region size assumes 1GiB page max alignment per slot.
1726 device_memory_base
=
1727 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1728 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1730 /* Base address of the high IO region */
1731 memtop
= base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1732 if (memtop
> BIT_ULL(pa_bits
)) {
1733 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
1734 pa_bits
, memtop
- BIT_ULL(pa_bits
));
1737 if (base
< device_memory_base
) {
1738 error_report("maxmem/slots too huge");
1741 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1742 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1745 /* We know for sure that at least the memory fits in the PA space */
1746 vms
->highest_gpa
= memtop
- 1;
1748 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1749 hwaddr size
= extended_memmap
[i
].size
;
1752 base
= ROUND_UP(base
, size
);
1753 vms
->memmap
[i
].base
= base
;
1754 vms
->memmap
[i
].size
= size
;
1757 * Check each device to see if they fit in the PA space,
1758 * moving highest_gpa as we go.
1760 * For each device that doesn't fit, disable it.
1762 fits
= (base
+ size
) <= BIT_ULL(pa_bits
);
1764 vms
->highest_gpa
= base
+ size
- 1;
1768 case VIRT_HIGH_GIC_REDIST2
:
1769 vms
->highmem_redists
&= fits
;
1771 case VIRT_HIGH_PCIE_ECAM
:
1772 vms
->highmem_ecam
&= fits
;
1774 case VIRT_HIGH_PCIE_MMIO
:
1775 vms
->highmem_mmio
&= fits
;
1782 if (device_memory_size
> 0) {
1783 ms
->device_memory
= g_malloc0(sizeof(*ms
->device_memory
));
1784 ms
->device_memory
->base
= device_memory_base
;
1785 memory_region_init(&ms
->device_memory
->mr
, OBJECT(vms
),
1786 "device-memory", device_memory_size
);
1791 * finalize_gic_version - Determines the final gic_version
1792 * according to the gic-version property
1794 * Default GIC type is v2
1796 static void finalize_gic_version(VirtMachineState
*vms
)
1798 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1800 if (kvm_enabled()) {
1803 if (!kvm_irqchip_in_kernel()) {
1804 switch (vms
->gic_version
) {
1805 case VIRT_GIC_VERSION_HOST
:
1807 "gic-version=host not relevant with kernel-irqchip=off "
1808 "as only userspace GICv2 is supported. Using v2 ...");
1810 case VIRT_GIC_VERSION_MAX
:
1811 case VIRT_GIC_VERSION_NOSEL
:
1812 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1814 case VIRT_GIC_VERSION_2
:
1816 case VIRT_GIC_VERSION_3
:
1818 "gic-version=3 is not supported with kernel-irqchip=off");
1820 case VIRT_GIC_VERSION_4
:
1822 "gic-version=4 is not supported with kernel-irqchip=off");
1827 probe_bitmap
= kvm_arm_vgic_probe();
1828 if (!probe_bitmap
) {
1829 error_report("Unable to determine GIC version supported by host");
1833 switch (vms
->gic_version
) {
1834 case VIRT_GIC_VERSION_HOST
:
1835 case VIRT_GIC_VERSION_MAX
:
1836 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1837 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1839 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1842 case VIRT_GIC_VERSION_NOSEL
:
1843 if ((probe_bitmap
& KVM_ARM_VGIC_V2
) && max_cpus
<= GIC_NCPU
) {
1844 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1845 } else if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1847 * in case the host does not support v2 in-kernel emulation or
1848 * the end-user requested more than 8 VCPUs we now default
1849 * to v3. In any case defaulting to v2 would be broken.
1851 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1852 } else if (max_cpus
> GIC_NCPU
) {
1853 error_report("host only supports in-kernel GICv2 emulation "
1854 "but more than 8 vcpus are requested");
1858 case VIRT_GIC_VERSION_2
:
1859 case VIRT_GIC_VERSION_3
:
1861 case VIRT_GIC_VERSION_4
:
1862 error_report("gic-version=4 is not supported with KVM");
1866 /* Check chosen version is effectively supported by the host */
1867 if (vms
->gic_version
== VIRT_GIC_VERSION_2
&&
1868 !(probe_bitmap
& KVM_ARM_VGIC_V2
)) {
1869 error_report("host does not support in-kernel GICv2 emulation");
1871 } else if (vms
->gic_version
== VIRT_GIC_VERSION_3
&&
1872 !(probe_bitmap
& KVM_ARM_VGIC_V3
)) {
1873 error_report("host does not support in-kernel GICv3 emulation");
1880 switch (vms
->gic_version
) {
1881 case VIRT_GIC_VERSION_NOSEL
:
1882 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1884 case VIRT_GIC_VERSION_MAX
:
1885 if (module_object_class_by_name("arm-gicv3")) {
1886 /* CONFIG_ARM_GICV3_TCG was set */
1888 /* GICv4 only makes sense if CPU has EL2 */
1889 vms
->gic_version
= VIRT_GIC_VERSION_4
;
1891 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1894 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1897 case VIRT_GIC_VERSION_HOST
:
1898 error_report("gic-version=host requires KVM");
1900 case VIRT_GIC_VERSION_4
:
1902 error_report("gic-version=4 requires virtualization enabled");
1906 case VIRT_GIC_VERSION_2
:
1907 case VIRT_GIC_VERSION_3
:
1913 * virt_cpu_post_init() must be called after the CPUs have
1914 * been realized and the GIC has been created.
1916 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
1918 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1919 bool aarch64
, pmu
, steal_time
;
1922 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
1923 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
1924 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
1925 "kvm-steal-time", NULL
);
1927 if (kvm_enabled()) {
1928 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
1929 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
1932 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
1933 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
1935 /* The memory region size must be a multiple of host page size. */
1936 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
1938 if (pvtime_size
> pvtime_reg_size
) {
1939 error_report("pvtime requires a %" HWADDR_PRId
1940 " byte memory region for %d CPUs,"
1941 " but only %" HWADDR_PRId
" has been reserved",
1942 pvtime_size
, max_cpus
, pvtime_reg_size
);
1946 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
1947 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
1952 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
1953 if (kvm_irqchip_in_kernel()) {
1954 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
1956 kvm_arm_pmu_init(cpu
);
1959 kvm_arm_pvtime_init(cpu
, pvtime_reg_base
+
1960 cpu
->cpu_index
* PVTIME_SIZE_PER_CPU
);
1964 if (aarch64
&& vms
->highmem
) {
1965 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1966 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
1968 if (pamax
< requested_pa_size
) {
1969 error_report("VCPU supports less PA bits (%d) than "
1970 "requested by the memory map (%d)",
1971 pamax
, requested_pa_size
);
1978 static void machvirt_init(MachineState
*machine
)
1980 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1981 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1982 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1983 const CPUArchIdList
*possible_cpus
;
1984 MemoryRegion
*sysmem
= get_system_memory();
1985 MemoryRegion
*secure_sysmem
= NULL
;
1986 MemoryRegion
*tag_sysmem
= NULL
;
1987 MemoryRegion
*secure_tag_sysmem
= NULL
;
1988 int n
, virt_max_cpus
;
1989 bool firmware_loaded
;
1990 bool aarch64
= true;
1991 bool has_ged
= !vmc
->no_ged
;
1992 unsigned int smp_cpus
= machine
->smp
.cpus
;
1993 unsigned int max_cpus
= machine
->smp
.max_cpus
;
1995 if (!cpu_type_valid(machine
->cpu_type
)) {
1996 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
2000 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2003 * In accelerated mode, the memory map is computed earlier in kvm_type()
2004 * to create a VM with the right number of IPA bits.
2012 * Instanciate a temporary CPU object to find out about what
2013 * we are about to deal with. Once this is done, get rid of
2016 cpuobj
= object_new(possible_cpus
->cpus
[0].type
);
2017 armcpu
= ARM_CPU(cpuobj
);
2019 pa_bits
= arm_pamax(armcpu
);
2021 object_unref(cpuobj
);
2023 virt_set_memmap(vms
, pa_bits
);
2026 /* We can probe only here because during property set
2027 * KVM is not available yet
2029 finalize_gic_version(vms
);
2033 * The Secure view of the world is the same as the NonSecure,
2034 * but with a few extra devices. Create it as a container region
2035 * containing the system memory at low priority; any secure-only
2036 * devices go in at higher priority and take precedence.
2038 secure_sysmem
= g_new(MemoryRegion
, 1);
2039 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
2041 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
2044 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
2045 secure_sysmem
?: sysmem
);
2047 /* If we have an EL3 boot ROM then the assumption is that it will
2048 * implement PSCI itself, so disable QEMU's internal implementation
2049 * so it doesn't get in the way. Instead of starting secondary
2050 * CPUs in PSCI powerdown state we will start them all running and
2051 * let the boot ROM sort them out.
2052 * The usual case is that we do use QEMU's PSCI implementation;
2053 * if the guest has EL2 then we will use SMC as the conduit,
2054 * and otherwise we will use HVC (for backwards compatibility and
2055 * because if we're using KVM then we must use HVC).
2057 if (vms
->secure
&& firmware_loaded
) {
2058 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
2059 } else if (vms
->virt
) {
2060 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
2062 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
2066 * The maximum number of CPUs depends on the GIC version, or on how
2067 * many redistributors we can fit into the memory map (which in turn
2068 * depends on whether this is a GICv3 or v4).
2070 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
2071 virt_max_cpus
= GIC_NCPU
;
2073 virt_max_cpus
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
) +
2074 virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
2077 if (max_cpus
> virt_max_cpus
) {
2078 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2079 "supported by machine 'mach-virt' (%d)",
2080 max_cpus
, virt_max_cpus
);
2084 if (vms
->secure
&& (kvm_enabled() || hvf_enabled())) {
2085 error_report("mach-virt: %s does not support providing "
2086 "Security extensions (TrustZone) to the guest CPU",
2087 kvm_enabled() ? "KVM" : "HVF");
2091 if (vms
->virt
&& (kvm_enabled() || hvf_enabled())) {
2092 error_report("mach-virt: %s does not support providing "
2093 "Virtualization extensions to the guest CPU",
2094 kvm_enabled() ? "KVM" : "HVF");
2098 if (vms
->mte
&& (kvm_enabled() || hvf_enabled())) {
2099 error_report("mach-virt: %s does not support providing "
2100 "MTE to the guest CPU",
2101 kvm_enabled() ? "KVM" : "HVF");
2107 assert(possible_cpus
->len
== max_cpus
);
2108 for (n
= 0; n
< possible_cpus
->len
; n
++) {
2112 if (n
>= smp_cpus
) {
2116 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
2117 object_property_set_int(cpuobj
, "mp-affinity",
2118 possible_cpus
->cpus
[n
].arch_id
, NULL
);
2123 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
2126 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
2129 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
2132 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
2133 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
2136 if (vmc
->kvm_no_adjvtime
&&
2137 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
2138 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
2141 if (vmc
->no_kvm_steal_time
&&
2142 object_property_find(cpuobj
, "kvm-steal-time")) {
2143 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
2146 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
2147 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
2150 if (vmc
->no_tcg_lpa2
&& object_property_find(cpuobj
, "lpa2")) {
2151 object_property_set_bool(cpuobj
, "lpa2", false, NULL
);
2154 if (object_property_find(cpuobj
, "reset-cbar")) {
2155 object_property_set_int(cpuobj
, "reset-cbar",
2156 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
2160 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
2163 object_property_set_link(cpuobj
, "secure-memory",
2164 OBJECT(secure_sysmem
), &error_abort
);
2168 /* Create the memory region only once, but link to all cpus. */
2171 * The property exists only if MemTag is supported.
2172 * If it is, we must allocate the ram to back that up.
2174 if (!object_property_find(cpuobj
, "tag-memory")) {
2175 error_report("MTE requested, but not supported "
2176 "by the guest CPU");
2180 tag_sysmem
= g_new(MemoryRegion
, 1);
2181 memory_region_init(tag_sysmem
, OBJECT(machine
),
2182 "tag-memory", UINT64_MAX
/ 32);
2185 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2186 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2187 "secure-tag-memory", UINT64_MAX
/ 32);
2189 /* As with ram, secure-tag takes precedence over tag. */
2190 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2195 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2198 object_property_set_link(cpuobj
, "secure-tag-memory",
2199 OBJECT(secure_tag_sysmem
),
2204 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2205 object_unref(cpuobj
);
2207 fdt_add_timer_nodes(vms
);
2208 fdt_add_cpu_nodes(vms
);
2210 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2212 if (machine
->device_memory
) {
2213 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2214 &machine
->device_memory
->mr
);
2217 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2219 create_gic(vms
, sysmem
);
2221 virt_cpu_post_init(vms
, sysmem
);
2223 fdt_add_pmu_nodes(vms
);
2225 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2228 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2229 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2233 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2234 machine
->ram_size
, "mach-virt.tag");
2237 vms
->highmem_ecam
&= (!firmware_loaded
|| aarch64
);
2243 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2244 vms
->acpi_dev
= create_acpi_ged(vms
);
2246 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2249 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2250 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2253 /* connect powerdown request */
2254 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2255 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2257 /* Create mmio transports, so the user can create virtio backends
2258 * (which will be automatically plugged in to the transports). If
2259 * no backend is created the transport will just sit harmlessly idle.
2261 create_virtio_devices(vms
);
2263 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2264 rom_set_fw(vms
->fw_cfg
);
2266 create_platform_bus(vms
);
2268 if (machine
->nvdimms_state
->is_enabled
) {
2269 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2270 .space_id
= AML_AS_SYSTEM_MEMORY
,
2271 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2272 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2275 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2276 arm_virt_nvdimm_acpi_dsmio
,
2277 vms
->fw_cfg
, OBJECT(vms
));
2280 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2281 vms
->bootinfo
.board_id
= -1;
2282 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2283 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2284 vms
->bootinfo
.skip_dtb_autoload
= true;
2285 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2286 vms
->bootinfo
.psci_conduit
= vms
->psci_conduit
;
2287 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2289 vms
->machine_done
.notify
= virt_machine_done
;
2290 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2293 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2295 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2300 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2302 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2304 vms
->secure
= value
;
2307 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2309 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2314 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2316 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2321 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2323 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2325 return vms
->highmem
;
2328 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2330 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2332 vms
->highmem
= value
;
2335 static bool virt_get_its(Object
*obj
, Error
**errp
)
2337 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2342 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2344 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2349 static bool virt_get_dtb_randomness(Object
*obj
, Error
**errp
)
2351 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2353 return vms
->dtb_randomness
;
2356 static void virt_set_dtb_randomness(Object
*obj
, bool value
, Error
**errp
)
2358 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2360 vms
->dtb_randomness
= value
;
2363 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2365 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2367 return g_strdup(vms
->oem_id
);
2370 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2372 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2373 size_t len
= strlen(value
);
2377 "User specified oem-id value is bigger than 6 bytes in size");
2381 strncpy(vms
->oem_id
, value
, 6);
2384 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2386 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2388 return g_strdup(vms
->oem_table_id
);
2391 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2394 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2395 size_t len
= strlen(value
);
2399 "User specified oem-table-id value is bigger than 8 bytes in size");
2402 strncpy(vms
->oem_table_id
, value
, 8);
2406 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2408 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2414 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2415 void *opaque
, Error
**errp
)
2417 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2418 OnOffAuto acpi
= vms
->acpi
;
2420 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2423 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2424 void *opaque
, Error
**errp
)
2426 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2428 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2431 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2433 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2438 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2440 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2445 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2447 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2452 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2454 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2459 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2461 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2464 switch (vms
->gic_version
) {
2465 case VIRT_GIC_VERSION_4
:
2468 case VIRT_GIC_VERSION_3
:
2475 return g_strdup(val
);
2478 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2480 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2482 if (!strcmp(value
, "4")) {
2483 vms
->gic_version
= VIRT_GIC_VERSION_4
;
2484 } else if (!strcmp(value
, "3")) {
2485 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2486 } else if (!strcmp(value
, "2")) {
2487 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2488 } else if (!strcmp(value
, "host")) {
2489 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2490 } else if (!strcmp(value
, "max")) {
2491 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2493 error_setg(errp
, "Invalid gic-version value");
2494 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2498 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2500 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2502 switch (vms
->iommu
) {
2503 case VIRT_IOMMU_NONE
:
2504 return g_strdup("none");
2505 case VIRT_IOMMU_SMMUV3
:
2506 return g_strdup("smmuv3");
2508 g_assert_not_reached();
2512 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2514 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2516 if (!strcmp(value
, "smmuv3")) {
2517 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2518 } else if (!strcmp(value
, "none")) {
2519 vms
->iommu
= VIRT_IOMMU_NONE
;
2521 error_setg(errp
, "Invalid iommu value");
2522 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2526 static bool virt_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
2528 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2530 return vms
->default_bus_bypass_iommu
;
2533 static void virt_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
2536 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2538 vms
->default_bus_bypass_iommu
= value
;
2541 static CpuInstanceProperties
2542 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2544 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2545 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2547 assert(cpu_index
< possible_cpus
->len
);
2548 return possible_cpus
->cpus
[cpu_index
].props
;
2551 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2553 int64_t socket_id
= ms
->possible_cpus
->cpus
[idx
].props
.socket_id
;
2555 return socket_id
% ms
->numa_state
->num_nodes
;
2558 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2561 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2562 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2563 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2565 if (ms
->possible_cpus
) {
2566 assert(ms
->possible_cpus
->len
== max_cpus
);
2567 return ms
->possible_cpus
;
2570 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2571 sizeof(CPUArchId
) * max_cpus
);
2572 ms
->possible_cpus
->len
= max_cpus
;
2573 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2574 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2575 ms
->possible_cpus
->cpus
[n
].arch_id
=
2576 virt_cpu_mp_affinity(vms
, n
);
2578 assert(!mc
->smp_props
.dies_supported
);
2579 ms
->possible_cpus
->cpus
[n
].props
.has_socket_id
= true;
2580 ms
->possible_cpus
->cpus
[n
].props
.socket_id
=
2581 n
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
);
2582 ms
->possible_cpus
->cpus
[n
].props
.has_cluster_id
= true;
2583 ms
->possible_cpus
->cpus
[n
].props
.cluster_id
=
2584 (n
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
;
2585 ms
->possible_cpus
->cpus
[n
].props
.has_core_id
= true;
2586 ms
->possible_cpus
->cpus
[n
].props
.core_id
=
2587 (n
/ ms
->smp
.threads
) % ms
->smp
.cores
;
2588 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2589 ms
->possible_cpus
->cpus
[n
].props
.thread_id
=
2590 n
% ms
->smp
.threads
;
2592 return ms
->possible_cpus
;
2595 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2598 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2599 const MachineState
*ms
= MACHINE(hotplug_dev
);
2600 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2602 if (!vms
->acpi_dev
) {
2604 "memory hotplug is not enabled: missing acpi-ged device");
2609 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2613 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2614 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2618 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2621 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2622 DeviceState
*dev
, Error
**errp
)
2624 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2625 MachineState
*ms
= MACHINE(hotplug_dev
);
2626 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2628 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2631 nvdimm_plug(ms
->nvdimms_state
);
2634 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2638 static void virt_virtio_md_pci_pre_plug(HotplugHandler
*hotplug_dev
,
2639 DeviceState
*dev
, Error
**errp
)
2641 HotplugHandler
*hotplug_dev2
= qdev_get_bus_hotplug_handler(dev
);
2642 Error
*local_err
= NULL
;
2644 if (!hotplug_dev2
&& dev
->hotplugged
) {
2646 * Without a bus hotplug handler, we cannot control the plug/unplug
2647 * order. We should never reach this point when hotplugging on ARM.
2648 * However, it's nice to add a safety net, similar to what we have
2651 error_setg(errp
, "hotplug of virtio based memory devices not supported"
2656 * First, see if we can plug this memory device at all. If that
2657 * succeeds, branch of to the actual hotplug handler.
2659 memory_device_pre_plug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
), NULL
,
2661 if (!local_err
&& hotplug_dev2
) {
2662 hotplug_handler_pre_plug(hotplug_dev2
, dev
, &local_err
);
2664 error_propagate(errp
, local_err
);
2667 static void virt_virtio_md_pci_plug(HotplugHandler
*hotplug_dev
,
2668 DeviceState
*dev
, Error
**errp
)
2670 HotplugHandler
*hotplug_dev2
= qdev_get_bus_hotplug_handler(dev
);
2671 Error
*local_err
= NULL
;
2674 * Plug the memory device first and then branch off to the actual
2675 * hotplug handler. If that one fails, we can easily undo the memory
2678 memory_device_plug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
));
2680 hotplug_handler_plug(hotplug_dev2
, dev
, &local_err
);
2682 memory_device_unplug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
));
2685 error_propagate(errp
, local_err
);
2688 static void virt_virtio_md_pci_unplug_request(HotplugHandler
*hotplug_dev
,
2689 DeviceState
*dev
, Error
**errp
)
2691 /* We don't support hot unplug of virtio based memory devices */
2692 error_setg(errp
, "virtio based memory devices cannot be unplugged.");
2696 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2697 DeviceState
*dev
, Error
**errp
)
2699 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2701 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2702 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2703 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
2704 virt_virtio_md_pci_pre_plug(hotplug_dev
, dev
, errp
);
2705 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2706 hwaddr db_start
= 0, db_end
= 0;
2707 char *resv_prop_str
;
2709 if (vms
->iommu
!= VIRT_IOMMU_NONE
) {
2710 error_setg(errp
, "virt machine does not support multiple IOMMUs");
2714 switch (vms
->msi_controller
) {
2715 case VIRT_MSI_CTRL_NONE
:
2717 case VIRT_MSI_CTRL_ITS
:
2718 /* GITS_TRANSLATER page */
2719 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2720 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2721 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2723 case VIRT_MSI_CTRL_GICV2M
:
2724 /* MSI_SETSPI_NS page */
2725 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2726 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2729 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2731 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2733 object_property_set_uint(OBJECT(dev
), "len-reserved-regions", 1, errp
);
2734 object_property_set_str(OBJECT(dev
), "reserved-regions[0]",
2735 resv_prop_str
, errp
);
2736 g_free(resv_prop_str
);
2740 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2741 DeviceState
*dev
, Error
**errp
)
2743 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2745 if (vms
->platform_bus_dev
) {
2746 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2748 if (device_is_dynamic_sysbus(mc
, dev
)) {
2749 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2750 SYS_BUS_DEVICE(dev
));
2753 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2754 virt_memory_plug(hotplug_dev
, dev
, errp
);
2757 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
2758 virt_virtio_md_pci_plug(hotplug_dev
, dev
, errp
);
2761 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2762 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2764 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2765 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2766 create_virtio_iommu_dt_bindings(vms
);
2770 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2771 DeviceState
*dev
, Error
**errp
)
2773 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2774 Error
*local_err
= NULL
;
2776 if (!vms
->acpi_dev
) {
2777 error_setg(&local_err
,
2778 "memory hotplug is not enabled: missing acpi-ged device");
2782 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2783 error_setg(&local_err
,
2784 "nvdimm device hot unplug is not supported yet.");
2788 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2791 error_propagate(errp
, local_err
);
2794 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2795 DeviceState
*dev
, Error
**errp
)
2797 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2798 Error
*local_err
= NULL
;
2800 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2805 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2806 qdev_unrealize(dev
);
2809 error_propagate(errp
, local_err
);
2812 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2813 DeviceState
*dev
, Error
**errp
)
2815 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2816 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2817 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
2818 virt_virtio_md_pci_unplug_request(hotplug_dev
, dev
, errp
);
2820 error_setg(errp
, "device unplug request for unsupported device"
2821 " type: %s", object_get_typename(OBJECT(dev
)));
2825 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2826 DeviceState
*dev
, Error
**errp
)
2828 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2829 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2831 error_setg(errp
, "virt: device unplug for unsupported device"
2832 " type: %s", object_get_typename(OBJECT(dev
)));
2836 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2839 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2841 if (device_is_dynamic_sysbus(mc
, dev
) ||
2842 object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2843 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
) ||
2844 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2845 return HOTPLUG_HANDLER(machine
);
2851 * for arm64 kvm_type [7-0] encodes the requested number of bits
2852 * in the IPA address space
2854 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2856 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2857 int max_vm_pa_size
, requested_pa_size
;
2860 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
2862 /* we freeze the memory map to compute the highest gpa */
2863 virt_set_memmap(vms
, max_vm_pa_size
);
2865 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2868 * KVM requires the IPA size to be at least 32 bits.
2870 if (requested_pa_size
< 32) {
2871 requested_pa_size
= 32;
2874 if (requested_pa_size
> max_vm_pa_size
) {
2875 error_report("-m and ,maxmem option values "
2876 "require an IPA range (%d bits) larger than "
2877 "the one supported by the host (%d bits)",
2878 requested_pa_size
, max_vm_pa_size
);
2882 * We return the requested PA log size, unless KVM only supports
2883 * the implicit legacy 40b IPA setting, in which case the kvm_type
2886 return fixed_ipa
? 0 : requested_pa_size
;
2889 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2891 MachineClass
*mc
= MACHINE_CLASS(oc
);
2892 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2894 mc
->init
= machvirt_init
;
2895 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2896 * The value may be reduced later when we have more information about the
2897 * configuration of the particular instance.
2900 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2901 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2902 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2903 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2905 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2907 mc
->block_default_type
= IF_VIRTIO
;
2909 mc
->pci_allow_0_address
= true;
2910 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2911 mc
->minimum_page_bits
= 12;
2912 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
2913 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
2914 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
2915 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
2916 mc
->kvm_type
= virt_kvm_type
;
2917 assert(!mc
->get_hotplug_handler
);
2918 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
2919 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
2920 hc
->plug
= virt_machine_device_plug_cb
;
2921 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
2922 hc
->unplug
= virt_machine_device_unplug_cb
;
2923 mc
->nvdimm_supported
= true;
2924 mc
->smp_props
.clusters_supported
= true;
2925 mc
->auto_enable_numa_with_memhp
= true;
2926 mc
->auto_enable_numa_with_memdev
= true;
2927 mc
->default_ram_id
= "mach-virt.ram";
2929 object_class_property_add(oc
, "acpi", "OnOffAuto",
2930 virt_get_acpi
, virt_set_acpi
,
2932 object_class_property_set_description(oc
, "acpi",
2934 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
2936 object_class_property_set_description(oc
, "secure",
2937 "Set on/off to enable/disable the ARM "
2938 "Security Extensions (TrustZone)");
2940 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
2942 object_class_property_set_description(oc
, "virtualization",
2943 "Set on/off to enable/disable emulating a "
2944 "guest CPU which implements the ARM "
2945 "Virtualization Extensions");
2947 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
2949 object_class_property_set_description(oc
, "highmem",
2950 "Set on/off to enable/disable using "
2951 "physical address space above 32 bits");
2953 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
2954 virt_set_gic_version
);
2955 object_class_property_set_description(oc
, "gic-version",
2957 "Valid values are 2, 3, 4, host and max");
2959 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
2960 object_class_property_set_description(oc
, "iommu",
2961 "Set the IOMMU type. "
2962 "Valid values are none and smmuv3");
2964 object_class_property_add_bool(oc
, "default-bus-bypass-iommu",
2965 virt_get_default_bus_bypass_iommu
,
2966 virt_set_default_bus_bypass_iommu
);
2967 object_class_property_set_description(oc
, "default-bus-bypass-iommu",
2968 "Set on/off to enable/disable "
2969 "bypass_iommu for default root bus");
2971 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
2973 object_class_property_set_description(oc
, "ras",
2974 "Set on/off to enable/disable reporting host memory errors "
2975 "to a KVM guest using ACPI and guest external abort exceptions");
2977 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
2978 object_class_property_set_description(oc
, "mte",
2979 "Set on/off to enable/disable emulating a "
2980 "guest CPU which implements the ARM "
2981 "Memory Tagging Extension");
2983 object_class_property_add_bool(oc
, "its", virt_get_its
,
2985 object_class_property_set_description(oc
, "its",
2986 "Set on/off to enable/disable "
2987 "ITS instantiation");
2989 object_class_property_add_bool(oc
, "dtb-randomness",
2990 virt_get_dtb_randomness
,
2991 virt_set_dtb_randomness
);
2992 object_class_property_set_description(oc
, "dtb-randomness",
2993 "Set off to disable passing random or "
2994 "non-deterministic dtb nodes to guest");
2996 object_class_property_add_bool(oc
, "dtb-kaslr-seed",
2997 virt_get_dtb_randomness
,
2998 virt_set_dtb_randomness
);
2999 object_class_property_set_description(oc
, "dtb-kaslr-seed",
3000 "Deprecated synonym of dtb-randomness");
3002 object_class_property_add_str(oc
, "x-oem-id",
3005 object_class_property_set_description(oc
, "x-oem-id",
3006 "Override the default value of field OEMID "
3007 "in ACPI table header."
3008 "The string may be up to 6 bytes in size");
3011 object_class_property_add_str(oc
, "x-oem-table-id",
3012 virt_get_oem_table_id
,
3013 virt_set_oem_table_id
);
3014 object_class_property_set_description(oc
, "x-oem-table-id",
3015 "Override the default value of field OEM Table ID "
3016 "in ACPI table header."
3017 "The string may be up to 8 bytes in size");
3021 static void virt_instance_init(Object
*obj
)
3023 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
3024 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
3026 /* EL3 is disabled by default on virt: this makes us consistent
3027 * between KVM and TCG for this board, and it also allows us to
3028 * boot UEFI blobs which assume no TrustZone support.
3030 vms
->secure
= false;
3032 /* EL2 is also disabled by default, for similar reasons */
3035 /* High memory is enabled by default */
3036 vms
->highmem
= true;
3037 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
3039 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
3040 vms
->highmem_mmio
= true;
3041 vms
->highmem_redists
= true;
3046 /* Default allows ITS instantiation */
3049 if (vmc
->no_tcg_its
) {
3050 vms
->tcg_its
= false;
3052 vms
->tcg_its
= true;
3056 /* Default disallows iommu instantiation */
3057 vms
->iommu
= VIRT_IOMMU_NONE
;
3059 /* The default root bus is attached to iommu by default */
3060 vms
->default_bus_bypass_iommu
= false;
3062 /* Default disallows RAS instantiation */
3065 /* MTE is disabled by default. */
3068 /* Supply kaslr-seed and rng-seed by default */
3069 vms
->dtb_randomness
= true;
3071 vms
->irqmap
= a15irqmap
;
3073 virt_flash_create(vms
);
3075 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
3076 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
3079 static const TypeInfo virt_machine_info
= {
3080 .name
= TYPE_VIRT_MACHINE
,
3081 .parent
= TYPE_MACHINE
,
3083 .instance_size
= sizeof(VirtMachineState
),
3084 .class_size
= sizeof(VirtMachineClass
),
3085 .class_init
= virt_machine_class_init
,
3086 .instance_init
= virt_instance_init
,
3087 .interfaces
= (InterfaceInfo
[]) {
3088 { TYPE_HOTPLUG_HANDLER
},
3093 static void machvirt_machine_init(void)
3095 type_register_static(&virt_machine_info
);
3097 type_init(machvirt_machine_init
);
3099 static void virt_machine_7_2_options(MachineClass
*mc
)
3102 DEFINE_VIRT_MACHINE_AS_LATEST(7, 2)
3104 static void virt_machine_7_1_options(MachineClass
*mc
)
3106 virt_machine_7_2_options(mc
);
3107 compat_props_add(mc
->compat_props
, hw_compat_7_1
, hw_compat_7_1_len
);
3109 DEFINE_VIRT_MACHINE(7, 1)
3111 static void virt_machine_7_0_options(MachineClass
*mc
)
3113 virt_machine_7_1_options(mc
);
3114 compat_props_add(mc
->compat_props
, hw_compat_7_0
, hw_compat_7_0_len
);
3116 DEFINE_VIRT_MACHINE(7, 0)
3118 static void virt_machine_6_2_options(MachineClass
*mc
)
3120 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3122 virt_machine_7_0_options(mc
);
3123 compat_props_add(mc
->compat_props
, hw_compat_6_2
, hw_compat_6_2_len
);
3124 vmc
->no_tcg_lpa2
= true;
3126 DEFINE_VIRT_MACHINE(6, 2)
3128 static void virt_machine_6_1_options(MachineClass
*mc
)
3130 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3132 virt_machine_6_2_options(mc
);
3133 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
3134 mc
->smp_props
.prefer_sockets
= true;
3135 vmc
->no_cpu_topology
= true;
3137 /* qemu ITS was introduced with 6.2 */
3138 vmc
->no_tcg_its
= true;
3140 DEFINE_VIRT_MACHINE(6, 1)
3142 static void virt_machine_6_0_options(MachineClass
*mc
)
3144 virt_machine_6_1_options(mc
);
3145 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
3147 DEFINE_VIRT_MACHINE(6, 0)
3149 static void virt_machine_5_2_options(MachineClass
*mc
)
3151 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3153 virt_machine_6_0_options(mc
);
3154 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
3155 vmc
->no_secure_gpio
= true;
3157 DEFINE_VIRT_MACHINE(5, 2)
3159 static void virt_machine_5_1_options(MachineClass
*mc
)
3161 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3163 virt_machine_5_2_options(mc
);
3164 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
3165 vmc
->no_kvm_steal_time
= true;
3167 DEFINE_VIRT_MACHINE(5, 1)
3169 static void virt_machine_5_0_options(MachineClass
*mc
)
3171 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3173 virt_machine_5_1_options(mc
);
3174 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
3175 mc
->numa_mem_supported
= true;
3176 vmc
->acpi_expose_flash
= true;
3177 mc
->auto_enable_numa_with_memdev
= false;
3179 DEFINE_VIRT_MACHINE(5, 0)
3181 static void virt_machine_4_2_options(MachineClass
*mc
)
3183 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3185 virt_machine_5_0_options(mc
);
3186 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
3187 vmc
->kvm_no_adjvtime
= true;
3189 DEFINE_VIRT_MACHINE(4, 2)
3191 static void virt_machine_4_1_options(MachineClass
*mc
)
3193 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3195 virt_machine_4_2_options(mc
);
3196 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
3198 mc
->auto_enable_numa_with_memhp
= false;
3200 DEFINE_VIRT_MACHINE(4, 1)
3202 static void virt_machine_4_0_options(MachineClass
*mc
)
3204 virt_machine_4_1_options(mc
);
3205 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
3207 DEFINE_VIRT_MACHINE(4, 0)
3209 static void virt_machine_3_1_options(MachineClass
*mc
)
3211 virt_machine_4_0_options(mc
);
3212 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
3214 DEFINE_VIRT_MACHINE(3, 1)
3216 static void virt_machine_3_0_options(MachineClass
*mc
)
3218 virt_machine_3_1_options(mc
);
3219 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
3221 DEFINE_VIRT_MACHINE(3, 0)
3223 static void virt_machine_2_12_options(MachineClass
*mc
)
3225 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3227 virt_machine_3_0_options(mc
);
3228 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
3229 vmc
->no_highmem_ecam
= true;
3232 DEFINE_VIRT_MACHINE(2, 12)
3234 static void virt_machine_2_11_options(MachineClass
*mc
)
3236 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3238 virt_machine_2_12_options(mc
);
3239 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
3240 vmc
->smbios_old_sys_ver
= true;
3242 DEFINE_VIRT_MACHINE(2, 11)
3244 static void virt_machine_2_10_options(MachineClass
*mc
)
3246 virt_machine_2_11_options(mc
);
3247 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
3248 /* before 2.11 we never faulted accesses to bad addresses */
3249 mc
->ignore_memory_transaction_failures
= true;
3251 DEFINE_VIRT_MACHINE(2, 10)
3253 static void virt_machine_2_9_options(MachineClass
*mc
)
3255 virt_machine_2_10_options(mc
);
3256 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
3258 DEFINE_VIRT_MACHINE(2, 9)
3260 static void virt_machine_2_8_options(MachineClass
*mc
)
3262 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3264 virt_machine_2_9_options(mc
);
3265 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
3266 /* For 2.8 and earlier we falsely claimed in the DT that
3267 * our timers were edge-triggered, not level-triggered.
3269 vmc
->claim_edge_triggered_timers
= true;
3271 DEFINE_VIRT_MACHINE(2, 8)
3273 static void virt_machine_2_7_options(MachineClass
*mc
)
3275 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3277 virt_machine_2_8_options(mc
);
3278 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
3279 /* ITS was introduced with 2.8 */
3281 /* Stick with 1K pages for migration compatibility */
3282 mc
->minimum_page_bits
= 0;
3284 DEFINE_VIRT_MACHINE(2, 7)
3286 static void virt_machine_2_6_options(MachineClass
*mc
)
3288 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3290 virt_machine_2_7_options(mc
);
3291 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
3292 vmc
->disallow_affinity_adjustment
= true;
3293 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3296 DEFINE_VIRT_MACHINE(2, 6)