2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "qapi/error.h"
37 #include "hw/sysbus.h"
38 #include "hw/arm/boot.h"
39 #include "hw/arm/primecell.h"
40 #include "hw/arm/virt.h"
41 #include "hw/block/flash.h"
42 #include "hw/vfio/vfio-calxeda-xgmac.h"
43 #include "hw/vfio/vfio-amd-xgbe.h"
44 #include "hw/display/ramfb.h"
46 #include "sysemu/device_tree.h"
47 #include "sysemu/numa.h"
48 #include "sysemu/runstate.h"
49 #include "sysemu/tpm.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "hw/loader.h"
53 #include "qapi/error.h"
54 #include "qemu/bitops.h"
55 #include "qemu/error-report.h"
56 #include "qemu/module.h"
57 #include "hw/pci-host/gpex.h"
58 #include "hw/virtio/virtio-pci.h"
59 #include "hw/core/sysbus-fdt.h"
60 #include "hw/platform-bus.h"
61 #include "hw/qdev-properties.h"
62 #include "hw/arm/fdt.h"
63 #include "hw/intc/arm_gic.h"
64 #include "hw/intc/arm_gicv3_common.h"
67 #include "hw/firmware/smbios.h"
68 #include "qapi/visitor.h"
69 #include "qapi/qapi-visit-common.h"
70 #include "standard-headers/linux/input.h"
71 #include "hw/arm/smmuv3.h"
72 #include "hw/acpi/acpi.h"
73 #include "target/arm/internals.h"
74 #include "hw/mem/memory-device.h"
75 #include "hw/mem/pc-dimm.h"
76 #include "hw/mem/nvdimm.h"
77 #include "hw/acpi/generic_event_device.h"
78 #include "hw/virtio/virtio-mem-pci.h"
79 #include "hw/virtio/virtio-iommu.h"
80 #include "hw/char/pl011.h"
81 #include "qemu/guest-random.h"
83 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
84 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
87 MachineClass *mc = MACHINE_CLASS(oc); \
88 virt_machine_##major##_##minor##_options(mc); \
89 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
94 static const TypeInfo machvirt_##major##_##minor##_info = { \
95 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
96 .parent = TYPE_VIRT_MACHINE, \
97 .class_init = virt_##major##_##minor##_class_init, \
99 static void machvirt_machine_##major##_##minor##_init(void) \
101 type_register_static(&machvirt_##major##_##minor##_info); \
103 type_init(machvirt_machine_##major##_##minor##_init);
105 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
106 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
107 #define DEFINE_VIRT_MACHINE(major, minor) \
108 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
111 /* Number of external interrupt lines to configure the GIC with */
114 #define PLATFORM_BUS_NUM_IRQS 64
116 /* Legacy RAM limit in GB (< version 4.0) */
117 #define LEGACY_RAMLIMIT_GB 255
118 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
120 /* Addresses and sizes of our components.
121 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
122 * 128MB..256MB is used for miscellaneous device I/O.
123 * 256MB..1GB is reserved for possible future PCI support (ie where the
124 * PCI memory window will go if we add a PCI host controller).
125 * 1GB and up is RAM (which may happily spill over into the
126 * high memory region beyond 4GB).
127 * This represents a compromise between how much RAM can be given to
128 * a 32 bit VM and leaving space for expansion and in particular for PCI.
129 * Note that devices should generally be placed at multiples of 0x10000,
130 * to accommodate guests using 64K pages.
132 static const MemMapEntry base_memmap
[] = {
133 /* Space up to 0x8000000 is reserved for a boot ROM */
134 [VIRT_FLASH
] = { 0, 0x08000000 },
135 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
136 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
137 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
138 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
139 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
140 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
141 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
142 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
143 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
144 /* This redistributor space allows up to 2*64kB*123 CPUs */
145 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
146 [VIRT_UART
] = { 0x09000000, 0x00001000 },
147 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
148 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
149 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
150 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
151 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
152 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
153 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
154 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
155 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
156 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
157 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
158 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
159 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
160 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
161 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
162 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
163 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
164 /* Actual RAM size depends on initial RAM and device memory settings */
165 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
169 * Highmem IO Regions: This memory map is floating, located after the RAM.
170 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
171 * top of the RAM, so that its base get the same alignment as the size,
172 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
173 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
174 * Note the extended_memmap is sized so that it eventually also includes the
175 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
176 * index of base_memmap).
178 * The memory map for these Highmem IO Regions can be in legacy or compact
179 * layout, depending on 'compact-highmem' property. With legacy layout, the
180 * PA space for one specific region is always reserved, even if the region
181 * has been disabled or doesn't fit into the PA space. However, the PA space
182 * for the region won't be reserved in these circumstances with compact layout.
184 static MemMapEntry extended_memmap
[] = {
185 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
186 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
187 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
188 /* Second PCIe window */
189 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
192 static const int a15irqmap
[] = {
195 [VIRT_PCIE
] = 3, /* ... to 6 */
197 [VIRT_SECURE_UART
] = 8,
199 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
200 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
201 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
202 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
205 static const char *valid_cpus
[] = {
206 ARM_CPU_TYPE_NAME("cortex-a7"),
207 ARM_CPU_TYPE_NAME("cortex-a15"),
208 ARM_CPU_TYPE_NAME("cortex-a35"),
209 ARM_CPU_TYPE_NAME("cortex-a53"),
210 ARM_CPU_TYPE_NAME("cortex-a55"),
211 ARM_CPU_TYPE_NAME("cortex-a57"),
212 ARM_CPU_TYPE_NAME("cortex-a72"),
213 ARM_CPU_TYPE_NAME("cortex-a76"),
214 ARM_CPU_TYPE_NAME("a64fx"),
215 ARM_CPU_TYPE_NAME("neoverse-n1"),
216 ARM_CPU_TYPE_NAME("host"),
217 ARM_CPU_TYPE_NAME("max"),
220 static bool cpu_type_valid(const char *cpu
)
224 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
225 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
232 static void create_randomness(MachineState
*ms
, const char *node
)
239 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
242 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
.kaslr
);
243 qemu_fdt_setprop(ms
->fdt
, node
, "rng-seed", seed
.rng
, sizeof(seed
.rng
));
246 static void create_fdt(VirtMachineState
*vms
)
248 MachineState
*ms
= MACHINE(vms
);
249 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
250 void *fdt
= create_device_tree(&vms
->fdt_size
);
253 error_report("create_device_tree() failed");
260 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
261 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
262 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
263 qemu_fdt_setprop_string(fdt
, "/", "model", "linux,dummy-virt");
265 /* /chosen must exist for load_dtb to fill in necessary properties later */
266 qemu_fdt_add_subnode(fdt
, "/chosen");
267 if (vms
->dtb_randomness
) {
268 create_randomness(ms
, "/chosen");
272 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
273 if (vms
->dtb_randomness
) {
274 create_randomness(ms
, "/secure-chosen");
278 /* Clock node, for the benefit of the UART. The kernel device tree
279 * binding documentation claims the PL011 node clock properties are
280 * optional but in practice if you omit them the kernel refuses to
281 * probe for the device.
283 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
284 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
285 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
286 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
287 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
288 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
290 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
292 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
293 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
294 uint32_t *matrix
= g_malloc0(size
);
297 for (i
= 0; i
< nb_numa_nodes
; i
++) {
298 for (j
= 0; j
< nb_numa_nodes
; j
++) {
299 idx
= (i
* nb_numa_nodes
+ j
) * 3;
300 matrix
[idx
+ 0] = cpu_to_be32(i
);
301 matrix
[idx
+ 1] = cpu_to_be32(j
);
303 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
307 qemu_fdt_add_subnode(fdt
, "/distance-map");
308 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
309 "numa-distance-map-v1");
310 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
316 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
318 /* On real hardware these interrupts are level-triggered.
319 * On KVM they were edge-triggered before host kernel version 4.4,
320 * and level-triggered afterwards.
321 * On emulated QEMU they are level-triggered.
323 * Getting the DTB info about them wrong is awkward for some
325 * pre-4.8 ignore the DT and leave the interrupt configured
326 * with whatever the GIC reset value (or the bootloader) left it at
327 * 4.8 before rc6 honour the incorrect data by programming it back
328 * into the GIC, causing problems
329 * 4.8rc6 and later ignore the DT and always write "level triggered"
332 * For backwards-compatibility, virt-2.8 and earlier will continue
333 * to say these are edge-triggered, but later machines will report
334 * the correct information.
337 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
338 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
339 MachineState
*ms
= MACHINE(vms
);
341 if (vmc
->claim_edge_triggered_timers
) {
342 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
345 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
346 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
347 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
348 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
351 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
353 armcpu
= ARM_CPU(qemu_get_cpu(0));
354 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
355 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
356 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
357 compat
, sizeof(compat
));
359 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
362 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
363 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
364 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
365 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
366 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
367 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
370 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
374 const MachineState
*ms
= MACHINE(vms
);
375 const VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
376 int smp_cpus
= ms
->smp
.cpus
;
379 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
380 * On ARM v8 64-bit systems value should be set to 2,
381 * that corresponds to the MPIDR_EL1 register size.
382 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
383 * in the system, #address-cells can be set to 1, since
384 * MPIDR_EL1[63:32] bits are not used for CPUs
387 * Here we actually don't know whether our system is 32- or 64-bit one.
388 * The simplest way to go is to examine affinity IDs of all our CPUs. If
389 * at least one of them has Aff3 populated, we set #address-cells to 2.
391 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
392 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
394 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
400 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
401 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
402 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
404 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
405 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
406 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
407 CPUState
*cs
= CPU(armcpu
);
409 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
410 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
411 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
412 armcpu
->dtb_compatible
);
414 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
415 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
416 "enable-method", "psci");
419 if (addr_cells
== 2) {
420 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
421 armcpu
->mp_affinity
);
423 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
424 armcpu
->mp_affinity
);
427 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
428 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
429 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
432 if (!vmc
->no_cpu_topology
) {
433 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle",
434 qemu_fdt_alloc_phandle(ms
->fdt
));
440 if (!vmc
->no_cpu_topology
) {
442 * Add vCPU topology description through fdt node cpu-map.
444 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
445 * In a SMP system, the hierarchy of CPUs can be defined through
446 * four entities that are used to describe the layout of CPUs in
447 * the system: socket/cluster/core/thread.
449 * A socket node represents the boundary of system physical package
450 * and its child nodes must be one or more cluster nodes. A system
451 * can contain several layers of clustering within a single physical
452 * package and cluster nodes can be contained in parent cluster nodes.
454 * Note: currently we only support one layer of clustering within
455 * each physical package.
457 qemu_fdt_add_subnode(ms
->fdt
, "/cpus/cpu-map");
459 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
460 char *cpu_path
= g_strdup_printf("/cpus/cpu@%d", cpu
);
463 if (ms
->smp
.threads
> 1) {
464 map_path
= g_strdup_printf(
465 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
466 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
),
467 (cpu
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
,
468 (cpu
/ ms
->smp
.threads
) % ms
->smp
.cores
,
469 cpu
% ms
->smp
.threads
);
471 map_path
= g_strdup_printf(
472 "/cpus/cpu-map/socket%d/cluster%d/core%d",
473 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
),
474 (cpu
/ ms
->smp
.cores
) % ms
->smp
.clusters
,
475 cpu
% ms
->smp
.cores
);
477 qemu_fdt_add_path(ms
->fdt
, map_path
);
478 qemu_fdt_setprop_phandle(ms
->fdt
, map_path
, "cpu", cpu_path
);
486 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
489 MachineState
*ms
= MACHINE(vms
);
491 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
492 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
493 vms
->memmap
[VIRT_GIC_ITS
].base
);
494 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
495 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
497 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
498 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#msi-cells", 1);
499 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
500 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
501 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
502 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
506 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
508 MachineState
*ms
= MACHINE(vms
);
511 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
512 vms
->memmap
[VIRT_GIC_V2M
].base
);
513 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
514 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
515 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
516 "arm,gic-v2m-frame");
517 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
518 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
519 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
520 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
521 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
525 static void fdt_add_gic_node(VirtMachineState
*vms
)
527 MachineState
*ms
= MACHINE(vms
);
530 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
531 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
533 nodename
= g_strdup_printf("/intc@%" PRIx64
,
534 vms
->memmap
[VIRT_GIC_DIST
].base
);
535 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
536 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
537 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
538 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
539 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
540 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
541 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
542 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
544 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
547 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
548 "#redistributor-regions", nb_redist_regions
);
550 if (nb_redist_regions
== 1) {
551 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
552 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
553 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
554 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
555 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
557 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
558 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
559 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
560 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
561 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
562 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
563 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
567 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
568 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
569 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
572 /* 'cortex-a15-gic' means 'GIC v2' */
573 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
574 "arm,cortex-a15-gic");
576 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
577 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
578 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
579 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
580 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
582 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
583 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
584 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
585 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
586 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
587 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
588 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
589 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
590 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
591 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
592 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
593 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
597 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
601 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
603 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
604 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
605 MachineState
*ms
= MACHINE(vms
);
607 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
608 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
612 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
613 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
614 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
615 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
618 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
619 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
620 const char compat
[] = "arm,armv8-pmuv3";
621 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
622 compat
, sizeof(compat
));
623 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
624 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
628 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
631 MachineState
*ms
= MACHINE(vms
);
632 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
633 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
636 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
639 if (ms
->nvdimms_state
->is_enabled
) {
640 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
643 dev
= qdev_new(TYPE_ACPI_GED
);
644 qdev_prop_set_uint32(dev
, "ged-event", event
);
646 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
647 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
648 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
650 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
655 static void create_its(VirtMachineState
*vms
)
657 const char *itsclass
= its_class_name();
660 if (!strcmp(itsclass
, "arm-gicv3-its")) {
667 /* Do nothing if not supported */
671 dev
= qdev_new(itsclass
);
673 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
675 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
676 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
678 fdt_add_its_gic_node(vms
);
679 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
682 static void create_v2m(VirtMachineState
*vms
)
685 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
688 dev
= qdev_new("arm-gicv2m");
689 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
690 qdev_prop_set_uint32(dev
, "base-spi", irq
);
691 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
692 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
694 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
695 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
696 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
699 fdt_add_v2m_gic_node(vms
);
700 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
703 static void create_gic(VirtMachineState
*vms
, MemoryRegion
*mem
)
705 MachineState
*ms
= MACHINE(vms
);
706 /* We create a standalone GIC */
707 SysBusDevice
*gicbusdev
;
710 unsigned int smp_cpus
= ms
->smp
.cpus
;
711 uint32_t nb_redist_regions
= 0;
714 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
715 gictype
= gic_class_name();
717 gictype
= gicv3_class_name();
720 switch (vms
->gic_version
) {
721 case VIRT_GIC_VERSION_2
:
724 case VIRT_GIC_VERSION_3
:
727 case VIRT_GIC_VERSION_4
:
731 g_assert_not_reached();
733 vms
->gic
= qdev_new(gictype
);
734 qdev_prop_set_uint32(vms
->gic
, "revision", revision
);
735 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
736 /* Note that the num-irq property counts both internal and external
737 * interrupts; there are always 32 of the former (mandated by GIC spec).
739 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
740 if (!kvm_irqchip_in_kernel()) {
741 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
744 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
745 uint32_t redist0_capacity
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
746 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
748 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
750 qdev_prop_set_uint32(vms
->gic
, "len-redist-region-count",
752 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[0]", redist0_count
);
754 if (!kvm_irqchip_in_kernel()) {
756 object_property_set_link(OBJECT(vms
->gic
), "sysmem",
757 OBJECT(mem
), &error_fatal
);
758 qdev_prop_set_bit(vms
->gic
, "has-lpi", true);
762 if (nb_redist_regions
== 2) {
763 uint32_t redist1_capacity
=
764 virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
766 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[1]",
767 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
770 if (!kvm_irqchip_in_kernel()) {
771 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
775 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
776 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
777 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
778 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
779 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
780 if (nb_redist_regions
== 2) {
781 sysbus_mmio_map(gicbusdev
, 2,
782 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
785 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
787 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
788 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
792 /* Wire the outputs from each CPU's generic timer and the GICv3
793 * maintenance interrupt signal to the appropriate GIC PPI inputs,
794 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
796 for (i
= 0; i
< smp_cpus
; i
++) {
797 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
798 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
800 /* Mapping from the output timer irq lines from the CPU to the
801 * GIC PPI inputs we use for the virt board.
803 const int timer_irq
[] = {
804 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
805 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
806 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
807 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
810 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
811 qdev_connect_gpio_out(cpudev
, irq
,
812 qdev_get_gpio_in(vms
->gic
,
813 ppibase
+ timer_irq
[irq
]));
816 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
817 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
818 ppibase
+ ARCH_GIC_MAINT_IRQ
);
819 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
821 } else if (vms
->virt
) {
822 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
823 ppibase
+ ARCH_GIC_MAINT_IRQ
);
824 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
827 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
828 qdev_get_gpio_in(vms
->gic
, ppibase
831 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
832 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
833 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
834 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
835 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
836 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
837 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
840 fdt_add_gic_node(vms
);
842 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& vms
->its
) {
844 } else if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
849 static void create_uart(const VirtMachineState
*vms
, int uart
,
850 MemoryRegion
*mem
, Chardev
*chr
)
853 hwaddr base
= vms
->memmap
[uart
].base
;
854 hwaddr size
= vms
->memmap
[uart
].size
;
855 int irq
= vms
->irqmap
[uart
];
856 const char compat
[] = "arm,pl011\0arm,primecell";
857 const char clocknames
[] = "uartclk\0apb_pclk";
858 DeviceState
*dev
= qdev_new(TYPE_PL011
);
859 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
860 MachineState
*ms
= MACHINE(vms
);
862 qdev_prop_set_chr(dev
, "chardev", chr
);
863 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
864 memory_region_add_subregion(mem
, base
,
865 sysbus_mmio_get_region(s
, 0));
866 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
868 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
869 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
870 /* Note that we can't use setprop_string because of the embedded NUL */
871 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
872 compat
, sizeof(compat
));
873 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
875 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
876 GIC_FDT_IRQ_TYPE_SPI
, irq
,
877 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
878 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
879 vms
->clock_phandle
, vms
->clock_phandle
);
880 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
881 clocknames
, sizeof(clocknames
));
883 if (uart
== VIRT_UART
) {
884 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
886 /* Mark as not usable by the normal world */
887 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
888 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
890 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
897 static void create_rtc(const VirtMachineState
*vms
)
900 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
901 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
902 int irq
= vms
->irqmap
[VIRT_RTC
];
903 const char compat
[] = "arm,pl031\0arm,primecell";
904 MachineState
*ms
= MACHINE(vms
);
906 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
908 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
909 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
910 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
911 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
913 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
914 GIC_FDT_IRQ_TYPE_SPI
, irq
,
915 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
916 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
917 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
921 static DeviceState
*gpio_key_dev
;
922 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
924 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
927 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
929 /* use gpio Pin 3 for power button event */
930 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
934 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
937 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
938 qdev_get_gpio_in(pl061_dev
, 3));
940 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
941 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
943 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
944 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
945 "label", "GPIO Key Poweroff");
946 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
948 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
949 "gpios", phandle
, 3, 0);
952 #define SECURE_GPIO_POWEROFF 0
953 #define SECURE_GPIO_RESET 1
955 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
958 DeviceState
*gpio_pwr_dev
;
961 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
963 /* connect secure pl061 to gpio-pwr */
964 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
965 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
966 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
967 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
969 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
970 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
972 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
973 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
974 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
975 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
978 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
979 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
981 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
982 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
983 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
984 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
988 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
992 DeviceState
*pl061_dev
;
993 hwaddr base
= vms
->memmap
[gpio
].base
;
994 hwaddr size
= vms
->memmap
[gpio
].size
;
995 int irq
= vms
->irqmap
[gpio
];
996 const char compat
[] = "arm,pl061\0arm,primecell";
998 MachineState
*ms
= MACHINE(vms
);
1000 pl061_dev
= qdev_new("pl061");
1001 /* Pull lines down to 0 if not driven by the PL061 */
1002 qdev_prop_set_uint32(pl061_dev
, "pullups", 0);
1003 qdev_prop_set_uint32(pl061_dev
, "pulldowns", 0xff);
1004 s
= SYS_BUS_DEVICE(pl061_dev
);
1005 sysbus_realize_and_unref(s
, &error_fatal
);
1006 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
1007 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
1009 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1010 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
1011 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1012 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1014 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
1015 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
1016 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
1017 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1018 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1019 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
1020 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
1021 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
1022 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
1024 if (gpio
!= VIRT_GPIO
) {
1025 /* Mark as not usable by the normal world */
1026 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1027 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1031 /* Child gpio devices */
1032 if (gpio
== VIRT_GPIO
) {
1033 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
1035 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
1039 static void create_virtio_devices(const VirtMachineState
*vms
)
1042 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
1043 MachineState
*ms
= MACHINE(vms
);
1045 /* We create the transports in forwards order. Since qbus_realize()
1046 * prepends (not appends) new child buses, the incrementing loop below will
1047 * create a list of virtio-mmio buses with decreasing base addresses.
1049 * When a -device option is processed from the command line,
1050 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1051 * order. The upshot is that -device options in increasing command line
1052 * order are mapped to virtio-mmio buses with decreasing base addresses.
1054 * When this code was originally written, that arrangement ensured that the
1055 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1056 * the first -device on the command line. (The end-to-end order is a
1057 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1058 * guest kernel's name-to-address assignment strategy.)
1060 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1061 * the message, if not necessarily the code, of commit 70161ff336.
1062 * Therefore the loop now establishes the inverse of the original intent.
1064 * Unfortunately, we can't counteract the kernel change by reversing the
1065 * loop; it would break existing command lines.
1067 * In any case, the kernel makes no guarantee about the stability of
1068 * enumeration order of virtio devices (as demonstrated by it changing
1069 * between kernel versions). For reliable and stable identification
1070 * of disks users must use UUIDs or similar mechanisms.
1072 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
1073 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1074 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1076 sysbus_create_simple("virtio-mmio", base
,
1077 qdev_get_gpio_in(vms
->gic
, irq
));
1080 /* We add dtb nodes in reverse order so that they appear in the finished
1081 * device tree lowest address first.
1083 * Note that this mapping is independent of the loop above. The previous
1084 * loop influences virtio device to virtio transport assignment, whereas
1085 * this loop controls how virtio transports are laid out in the dtb.
1087 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
1089 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1090 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1092 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
1093 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1094 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1095 "compatible", "virtio,mmio");
1096 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1098 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1099 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1100 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1101 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1106 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1108 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1110 const char *alias_prop_name
)
1113 * Create a single flash device. We use the same parameters as
1114 * the flash devices on the Versatile Express board.
1116 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1118 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1119 qdev_prop_set_uint8(dev
, "width", 4);
1120 qdev_prop_set_uint8(dev
, "device-width", 2);
1121 qdev_prop_set_bit(dev
, "big-endian", false);
1122 qdev_prop_set_uint16(dev
, "id0", 0x89);
1123 qdev_prop_set_uint16(dev
, "id1", 0x18);
1124 qdev_prop_set_uint16(dev
, "id2", 0x00);
1125 qdev_prop_set_uint16(dev
, "id3", 0x00);
1126 qdev_prop_set_string(dev
, "name", name
);
1127 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1128 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1129 OBJECT(dev
), "drive");
1130 return PFLASH_CFI01(dev
);
1133 static void virt_flash_create(VirtMachineState
*vms
)
1135 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1136 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1139 static void virt_flash_map1(PFlashCFI01
*flash
,
1140 hwaddr base
, hwaddr size
,
1141 MemoryRegion
*sysmem
)
1143 DeviceState
*dev
= DEVICE(flash
);
1145 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1146 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1147 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1148 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1150 memory_region_add_subregion(sysmem
, base
,
1151 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1155 static void virt_flash_map(VirtMachineState
*vms
,
1156 MemoryRegion
*sysmem
,
1157 MemoryRegion
*secure_sysmem
)
1160 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1161 * sysmem is the system memory space. secure_sysmem is the secure view
1162 * of the system, and the first flash device should be made visible only
1163 * there. The second flash device is visible to both secure and nonsecure.
1164 * If sysmem == secure_sysmem this means there is no separate Secure
1165 * address space and both flash devices are generally visible.
1167 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1168 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1170 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1172 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1176 static void virt_flash_fdt(VirtMachineState
*vms
,
1177 MemoryRegion
*sysmem
,
1178 MemoryRegion
*secure_sysmem
)
1180 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1181 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1182 MachineState
*ms
= MACHINE(vms
);
1185 if (sysmem
== secure_sysmem
) {
1186 /* Report both flash devices as a single node in the DT */
1187 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1188 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1189 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1190 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1191 2, flashbase
, 2, flashsize
,
1192 2, flashbase
+ flashsize
, 2, flashsize
);
1193 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1197 * Report the devices as separate nodes so we can mark one as
1198 * only visible to the secure world.
1200 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1201 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1202 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1203 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1204 2, flashbase
, 2, flashsize
);
1205 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1206 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1207 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1210 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
+ flashsize
);
1211 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1212 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1213 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1214 2, flashbase
+ flashsize
, 2, flashsize
);
1215 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1220 static bool virt_firmware_init(VirtMachineState
*vms
,
1221 MemoryRegion
*sysmem
,
1222 MemoryRegion
*secure_sysmem
)
1225 const char *bios_name
;
1226 BlockBackend
*pflash_blk0
;
1228 /* Map legacy -drive if=pflash to machine properties */
1229 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1230 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1231 drive_get(IF_PFLASH
, 0, i
));
1234 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1236 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1238 bios_name
= MACHINE(vms
)->firmware
;
1245 error_report("The contents of the first flash device may be "
1246 "specified with -bios or with -drive if=pflash... "
1247 "but you cannot use both options at once");
1251 /* Fall back to -bios */
1253 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1255 error_report("Could not find ROM image '%s'", bios_name
);
1258 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1259 image_size
= load_image_mr(fname
, mr
);
1261 if (image_size
< 0) {
1262 error_report("Could not load ROM image '%s'", bios_name
);
1267 return pflash_blk0
|| bios_name
;
1270 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1272 MachineState
*ms
= MACHINE(vms
);
1273 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1274 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1278 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1279 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1281 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1282 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1283 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1284 "compatible", "qemu,fw-cfg-mmio");
1285 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1287 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1292 static void create_pcie_irq_map(const MachineState
*ms
,
1293 uint32_t gic_phandle
,
1294 int first_irq
, const char *nodename
)
1297 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1298 uint32_t *irq_map
= full_irq_map
;
1300 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1301 for (pin
= 0; pin
< 4; pin
++) {
1302 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1303 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1304 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1308 devfn
<< 8, 0, 0, /* devfn */
1309 pin
+ 1, /* PCI pin */
1310 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1312 /* Convert map to big endian */
1313 for (i
= 0; i
< 10; i
++) {
1314 irq_map
[i
] = cpu_to_be32(map
[i
]);
1320 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1321 full_irq_map
, sizeof(full_irq_map
));
1323 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1324 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1329 static void create_smmu(const VirtMachineState
*vms
,
1333 const char compat
[] = "arm,smmu-v3";
1334 int irq
= vms
->irqmap
[VIRT_SMMU
];
1336 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1337 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1338 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1340 MachineState
*ms
= MACHINE(vms
);
1342 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1346 dev
= qdev_new("arm-smmuv3");
1348 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1350 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1351 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1352 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1353 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1354 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1357 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1358 qemu_fdt_add_subnode(ms
->fdt
, node
);
1359 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1360 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1362 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1363 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1364 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1365 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1366 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1368 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1371 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1373 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1375 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1379 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1381 const char compat
[] = "virtio,pci-iommu\0pci1af4,1057";
1382 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1383 MachineState
*ms
= MACHINE(vms
);
1386 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1388 node
= g_strdup_printf("%s/virtio_iommu@%x,%x", vms
->pciehb_nodename
,
1389 PCI_SLOT(bdf
), PCI_FUNC(bdf
));
1390 qemu_fdt_add_subnode(ms
->fdt
, node
);
1391 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1392 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1393 1, bdf
<< 8, 1, 0, 1, 0,
1396 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1397 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1400 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1401 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1402 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1405 static void create_pcie(VirtMachineState
*vms
)
1407 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1408 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1409 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1410 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1411 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1412 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1413 hwaddr base_ecam
, size_ecam
;
1414 hwaddr base
= base_mmio
;
1416 int irq
= vms
->irqmap
[VIRT_PCIE
];
1417 MemoryRegion
*mmio_alias
;
1418 MemoryRegion
*mmio_reg
;
1419 MemoryRegion
*ecam_alias
;
1420 MemoryRegion
*ecam_reg
;
1425 MachineState
*ms
= MACHINE(vms
);
1427 dev
= qdev_new(TYPE_GPEX_HOST
);
1428 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1430 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1431 base_ecam
= vms
->memmap
[ecam_id
].base
;
1432 size_ecam
= vms
->memmap
[ecam_id
].size
;
1433 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1434 /* Map only the first size_ecam bytes of ECAM space */
1435 ecam_alias
= g_new0(MemoryRegion
, 1);
1436 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1437 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1438 ecam_reg
, 0, size_ecam
);
1439 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1441 /* Map the MMIO window into system address space so as to expose
1442 * the section of PCI MMIO space which starts at the same base address
1443 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1446 mmio_alias
= g_new0(MemoryRegion
, 1);
1447 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1448 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1449 mmio_reg
, base_mmio
, size_mmio
);
1450 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1452 if (vms
->highmem_mmio
) {
1453 /* Map high MMIO space */
1454 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1456 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1457 mmio_reg
, base_mmio_high
, size_mmio_high
);
1458 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1462 /* Map IO port space */
1463 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1465 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1466 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1467 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1468 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1471 pci
= PCI_HOST_BRIDGE(dev
);
1472 pci
->bypass_iommu
= vms
->default_bus_bypass_iommu
;
1473 vms
->bus
= pci
->bus
;
1475 for (i
= 0; i
< nb_nics
; i
++) {
1476 NICInfo
*nd
= &nd_table
[i
];
1479 nd
->model
= g_strdup("virtio");
1482 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1486 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1487 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1488 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1489 "compatible", "pci-host-ecam-generic");
1490 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1491 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1492 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1493 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1494 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1496 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1498 if (vms
->msi_phandle
) {
1499 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-map",
1500 0, vms
->msi_phandle
, 0, 0x10000);
1503 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1504 2, base_ecam
, 2, size_ecam
);
1506 if (vms
->highmem_mmio
) {
1507 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1508 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1509 2, base_pio
, 2, size_pio
,
1510 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1511 2, base_mmio
, 2, size_mmio
,
1512 1, FDT_PCI_RANGE_MMIO_64BIT
,
1514 2, base_mmio_high
, 2, size_mmio_high
);
1516 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1517 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1518 2, base_pio
, 2, size_pio
,
1519 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1520 2, base_mmio
, 2, size_mmio
);
1523 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1524 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1527 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1529 switch (vms
->iommu
) {
1530 case VIRT_IOMMU_SMMUV3
:
1531 create_smmu(vms
, vms
->bus
);
1532 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1533 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1536 g_assert_not_reached();
1541 static void create_platform_bus(VirtMachineState
*vms
)
1546 MemoryRegion
*sysmem
= get_system_memory();
1548 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1549 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1550 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1551 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1552 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1553 vms
->platform_bus_dev
= dev
;
1555 s
= SYS_BUS_DEVICE(dev
);
1556 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1557 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1558 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1561 memory_region_add_subregion(sysmem
,
1562 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1563 sysbus_mmio_get_region(s
, 0));
1566 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1567 hwaddr base
, hwaddr size
,
1570 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1572 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1573 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1576 static void create_secure_ram(VirtMachineState
*vms
,
1577 MemoryRegion
*secure_sysmem
,
1578 MemoryRegion
*secure_tag_sysmem
)
1580 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1582 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1583 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1584 MachineState
*ms
= MACHINE(vms
);
1586 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1588 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1590 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1591 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1592 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1593 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1594 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1595 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1597 if (secure_tag_sysmem
) {
1598 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1604 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1606 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1608 MachineState
*ms
= MACHINE(board
);
1611 *fdt_size
= board
->fdt_size
;
1615 static void virt_build_smbios(VirtMachineState
*vms
)
1617 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1618 MachineState
*ms
= MACHINE(vms
);
1619 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1620 uint8_t *smbios_tables
, *smbios_anchor
;
1621 size_t smbios_tables_len
, smbios_anchor_len
;
1622 struct smbios_phys_mem_area mem_array
;
1623 const char *product
= "QEMU Virtual Machine";
1625 if (kvm_enabled()) {
1626 product
= "KVM Virtual Machine";
1629 smbios_set_defaults("QEMU", product
,
1630 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1631 true, SMBIOS_ENTRY_POINT_TYPE_64
);
1633 /* build the array of physical mem area from base_memmap */
1634 mem_array
.address
= vms
->memmap
[VIRT_MEM
].base
;
1635 mem_array
.length
= ms
->ram_size
;
1637 smbios_get_tables(ms
, &mem_array
, 1,
1638 &smbios_tables
, &smbios_tables_len
,
1639 &smbios_anchor
, &smbios_anchor_len
,
1642 if (smbios_anchor
) {
1643 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1644 smbios_tables
, smbios_tables_len
);
1645 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1646 smbios_anchor
, smbios_anchor_len
);
1651 void virt_machine_done(Notifier
*notifier
, void *data
)
1653 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1655 MachineState
*ms
= MACHINE(vms
);
1656 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1657 struct arm_boot_info
*info
= &vms
->bootinfo
;
1658 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1661 * If the user provided a dtb, we assume the dynamic sysbus nodes
1662 * already are integrated there. This corresponds to a use case where
1663 * the dynamic sysbus nodes are complex and their generation is not yet
1664 * supported. In that case the user can take charge of the guest dt
1665 * while qemu takes charge of the qom stuff.
1667 if (info
->dtb_filename
== NULL
) {
1668 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1669 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1670 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1671 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1673 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1677 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1679 virt_acpi_setup(vms
);
1680 virt_build_smbios(vms
);
1683 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1685 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1686 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1688 if (!vmc
->disallow_affinity_adjustment
) {
1689 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1690 * GIC's target-list limitations. 32-bit KVM hosts currently
1691 * always create clusters of 4 CPUs, but that is expected to
1692 * change when they gain support for gicv3. When KVM is enabled
1693 * it will override the changes we make here, therefore our
1694 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1695 * and to improve SGI efficiency.
1697 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
1698 clustersz
= GIC_TARGETLIST_BITS
;
1700 clustersz
= GICV3_TARGETLIST_BITS
;
1703 return arm_cpu_mp_affinity(idx
, clustersz
);
1706 static inline bool *virt_get_high_memmap_enabled(VirtMachineState
*vms
,
1709 bool *enabled_array
[] = {
1710 &vms
->highmem_redists
,
1715 assert(ARRAY_SIZE(extended_memmap
) - VIRT_LOWMEMMAP_LAST
==
1716 ARRAY_SIZE(enabled_array
));
1717 assert(index
- VIRT_LOWMEMMAP_LAST
< ARRAY_SIZE(enabled_array
));
1719 return enabled_array
[index
- VIRT_LOWMEMMAP_LAST
];
1722 static void virt_set_high_memmap(VirtMachineState
*vms
,
1723 hwaddr base
, int pa_bits
)
1725 hwaddr region_base
, region_size
;
1726 bool *region_enabled
, fits
;
1729 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1730 region_enabled
= virt_get_high_memmap_enabled(vms
, i
);
1731 region_base
= ROUND_UP(base
, extended_memmap
[i
].size
);
1732 region_size
= extended_memmap
[i
].size
;
1734 vms
->memmap
[i
].base
= region_base
;
1735 vms
->memmap
[i
].size
= region_size
;
1738 * Check each device to see if it fits in the PA space,
1739 * moving highest_gpa as we go. For compatibility, move
1740 * highest_gpa for disabled fitting devices as well, if
1741 * the compact layout has been disabled.
1743 * For each device that doesn't fit, disable it.
1745 fits
= (region_base
+ region_size
) <= BIT_ULL(pa_bits
);
1746 *region_enabled
&= fits
;
1747 if (vms
->highmem_compact
&& !*region_enabled
) {
1751 base
= region_base
+ region_size
;
1753 vms
->highest_gpa
= base
- 1;
1758 static void virt_set_memmap(VirtMachineState
*vms
, int pa_bits
)
1760 MachineState
*ms
= MACHINE(vms
);
1761 hwaddr base
, device_memory_base
, device_memory_size
, memtop
;
1764 vms
->memmap
= extended_memmap
;
1766 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1767 vms
->memmap
[i
] = base_memmap
[i
];
1770 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1771 error_report("unsupported number of memory slots: %"PRIu64
,
1777 * !highmem is exactly the same as limiting the PA space to 32bit,
1778 * irrespective of the underlying capabilities of the HW.
1780 if (!vms
->highmem
) {
1785 * We compute the base of the high IO region depending on the
1786 * amount of initial and device memory. The device memory start/size
1787 * is aligned on 1GiB. We never put the high IO region below 256GiB
1788 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1789 * The device region size assumes 1GiB page max alignment per slot.
1791 device_memory_base
=
1792 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1793 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1795 /* Base address of the high IO region */
1796 memtop
= base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1797 if (memtop
> BIT_ULL(pa_bits
)) {
1798 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
1799 pa_bits
, memtop
- BIT_ULL(pa_bits
));
1802 if (base
< device_memory_base
) {
1803 error_report("maxmem/slots too huge");
1806 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1807 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1810 /* We know for sure that at least the memory fits in the PA space */
1811 vms
->highest_gpa
= memtop
- 1;
1813 virt_set_high_memmap(vms
, base
, pa_bits
);
1815 if (device_memory_size
> 0) {
1816 ms
->device_memory
= g_malloc0(sizeof(*ms
->device_memory
));
1817 ms
->device_memory
->base
= device_memory_base
;
1818 memory_region_init(&ms
->device_memory
->mr
, OBJECT(vms
),
1819 "device-memory", device_memory_size
);
1824 * finalize_gic_version - Determines the final gic_version
1825 * according to the gic-version property
1827 * Default GIC type is v2
1829 static void finalize_gic_version(VirtMachineState
*vms
)
1831 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1833 if (kvm_enabled()) {
1836 if (!kvm_irqchip_in_kernel()) {
1837 switch (vms
->gic_version
) {
1838 case VIRT_GIC_VERSION_HOST
:
1840 "gic-version=host not relevant with kernel-irqchip=off "
1841 "as only userspace GICv2 is supported. Using v2 ...");
1843 case VIRT_GIC_VERSION_MAX
:
1844 case VIRT_GIC_VERSION_NOSEL
:
1845 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1847 case VIRT_GIC_VERSION_2
:
1849 case VIRT_GIC_VERSION_3
:
1851 "gic-version=3 is not supported with kernel-irqchip=off");
1853 case VIRT_GIC_VERSION_4
:
1855 "gic-version=4 is not supported with kernel-irqchip=off");
1860 probe_bitmap
= kvm_arm_vgic_probe();
1861 if (!probe_bitmap
) {
1862 error_report("Unable to determine GIC version supported by host");
1866 switch (vms
->gic_version
) {
1867 case VIRT_GIC_VERSION_HOST
:
1868 case VIRT_GIC_VERSION_MAX
:
1869 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1870 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1872 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1875 case VIRT_GIC_VERSION_NOSEL
:
1876 if ((probe_bitmap
& KVM_ARM_VGIC_V2
) && max_cpus
<= GIC_NCPU
) {
1877 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1878 } else if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1880 * in case the host does not support v2 in-kernel emulation or
1881 * the end-user requested more than 8 VCPUs we now default
1882 * to v3. In any case defaulting to v2 would be broken.
1884 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1885 } else if (max_cpus
> GIC_NCPU
) {
1886 error_report("host only supports in-kernel GICv2 emulation "
1887 "but more than 8 vcpus are requested");
1891 case VIRT_GIC_VERSION_2
:
1892 case VIRT_GIC_VERSION_3
:
1894 case VIRT_GIC_VERSION_4
:
1895 error_report("gic-version=4 is not supported with KVM");
1899 /* Check chosen version is effectively supported by the host */
1900 if (vms
->gic_version
== VIRT_GIC_VERSION_2
&&
1901 !(probe_bitmap
& KVM_ARM_VGIC_V2
)) {
1902 error_report("host does not support in-kernel GICv2 emulation");
1904 } else if (vms
->gic_version
== VIRT_GIC_VERSION_3
&&
1905 !(probe_bitmap
& KVM_ARM_VGIC_V3
)) {
1906 error_report("host does not support in-kernel GICv3 emulation");
1913 switch (vms
->gic_version
) {
1914 case VIRT_GIC_VERSION_NOSEL
:
1915 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1917 case VIRT_GIC_VERSION_MAX
:
1918 if (module_object_class_by_name("arm-gicv3")) {
1919 /* CONFIG_ARM_GICV3_TCG was set */
1921 /* GICv4 only makes sense if CPU has EL2 */
1922 vms
->gic_version
= VIRT_GIC_VERSION_4
;
1924 vms
->gic_version
= VIRT_GIC_VERSION_3
;
1927 vms
->gic_version
= VIRT_GIC_VERSION_2
;
1930 case VIRT_GIC_VERSION_HOST
:
1931 error_report("gic-version=host requires KVM");
1933 case VIRT_GIC_VERSION_4
:
1935 error_report("gic-version=4 requires virtualization enabled");
1939 case VIRT_GIC_VERSION_2
:
1940 case VIRT_GIC_VERSION_3
:
1946 * virt_cpu_post_init() must be called after the CPUs have
1947 * been realized and the GIC has been created.
1949 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
1951 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1952 bool aarch64
, pmu
, steal_time
;
1955 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
1956 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
1957 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
1958 "kvm-steal-time", NULL
);
1960 if (kvm_enabled()) {
1961 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
1962 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
1965 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
1966 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
1968 /* The memory region size must be a multiple of host page size. */
1969 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
1971 if (pvtime_size
> pvtime_reg_size
) {
1972 error_report("pvtime requires a %" HWADDR_PRId
1973 " byte memory region for %d CPUs,"
1974 " but only %" HWADDR_PRId
" has been reserved",
1975 pvtime_size
, max_cpus
, pvtime_reg_size
);
1979 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
1980 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
1985 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
1986 if (kvm_irqchip_in_kernel()) {
1987 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
1989 kvm_arm_pmu_init(cpu
);
1992 kvm_arm_pvtime_init(cpu
, pvtime_reg_base
+
1993 cpu
->cpu_index
* PVTIME_SIZE_PER_CPU
);
1997 if (aarch64
&& vms
->highmem
) {
1998 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1999 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
2001 if (pamax
< requested_pa_size
) {
2002 error_report("VCPU supports less PA bits (%d) than "
2003 "requested by the memory map (%d)",
2004 pamax
, requested_pa_size
);
2011 static void machvirt_init(MachineState
*machine
)
2013 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
2014 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
2015 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2016 const CPUArchIdList
*possible_cpus
;
2017 MemoryRegion
*sysmem
= get_system_memory();
2018 MemoryRegion
*secure_sysmem
= NULL
;
2019 MemoryRegion
*tag_sysmem
= NULL
;
2020 MemoryRegion
*secure_tag_sysmem
= NULL
;
2021 int n
, virt_max_cpus
;
2022 bool firmware_loaded
;
2023 bool aarch64
= true;
2024 bool has_ged
= !vmc
->no_ged
;
2025 unsigned int smp_cpus
= machine
->smp
.cpus
;
2026 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2028 if (!cpu_type_valid(machine
->cpu_type
)) {
2029 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
2033 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2036 * In accelerated mode, the memory map is computed earlier in kvm_type()
2037 * to create a VM with the right number of IPA bits.
2045 * Instanciate a temporary CPU object to find out about what
2046 * we are about to deal with. Once this is done, get rid of
2049 cpuobj
= object_new(possible_cpus
->cpus
[0].type
);
2050 armcpu
= ARM_CPU(cpuobj
);
2052 pa_bits
= arm_pamax(armcpu
);
2054 object_unref(cpuobj
);
2056 virt_set_memmap(vms
, pa_bits
);
2059 /* We can probe only here because during property set
2060 * KVM is not available yet
2062 finalize_gic_version(vms
);
2066 * The Secure view of the world is the same as the NonSecure,
2067 * but with a few extra devices. Create it as a container region
2068 * containing the system memory at low priority; any secure-only
2069 * devices go in at higher priority and take precedence.
2071 secure_sysmem
= g_new(MemoryRegion
, 1);
2072 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
2074 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
2077 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
2078 secure_sysmem
?: sysmem
);
2080 /* If we have an EL3 boot ROM then the assumption is that it will
2081 * implement PSCI itself, so disable QEMU's internal implementation
2082 * so it doesn't get in the way. Instead of starting secondary
2083 * CPUs in PSCI powerdown state we will start them all running and
2084 * let the boot ROM sort them out.
2085 * The usual case is that we do use QEMU's PSCI implementation;
2086 * if the guest has EL2 then we will use SMC as the conduit,
2087 * and otherwise we will use HVC (for backwards compatibility and
2088 * because if we're using KVM then we must use HVC).
2090 if (vms
->secure
&& firmware_loaded
) {
2091 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
2092 } else if (vms
->virt
) {
2093 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
2095 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
2099 * The maximum number of CPUs depends on the GIC version, or on how
2100 * many redistributors we can fit into the memory map (which in turn
2101 * depends on whether this is a GICv3 or v4).
2103 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
2104 virt_max_cpus
= GIC_NCPU
;
2106 virt_max_cpus
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
2107 if (vms
->highmem_redists
) {
2108 virt_max_cpus
+= virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
2112 if (max_cpus
> virt_max_cpus
) {
2113 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2114 "supported by machine 'mach-virt' (%d)",
2115 max_cpus
, virt_max_cpus
);
2116 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& !vms
->highmem_redists
) {
2117 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2123 if (vms
->secure
&& (kvm_enabled() || hvf_enabled())) {
2124 error_report("mach-virt: %s does not support providing "
2125 "Security extensions (TrustZone) to the guest CPU",
2126 kvm_enabled() ? "KVM" : "HVF");
2130 if (vms
->virt
&& (kvm_enabled() || hvf_enabled())) {
2131 error_report("mach-virt: %s does not support providing "
2132 "Virtualization extensions to the guest CPU",
2133 kvm_enabled() ? "KVM" : "HVF");
2137 if (vms
->mte
&& (kvm_enabled() || hvf_enabled())) {
2138 error_report("mach-virt: %s does not support providing "
2139 "MTE to the guest CPU",
2140 kvm_enabled() ? "KVM" : "HVF");
2146 assert(possible_cpus
->len
== max_cpus
);
2147 for (n
= 0; n
< possible_cpus
->len
; n
++) {
2151 if (n
>= smp_cpus
) {
2155 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
2156 object_property_set_int(cpuobj
, "mp-affinity",
2157 possible_cpus
->cpus
[n
].arch_id
, NULL
);
2162 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
2165 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
2168 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
2171 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
2172 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
2175 if (vmc
->kvm_no_adjvtime
&&
2176 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
2177 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
2180 if (vmc
->no_kvm_steal_time
&&
2181 object_property_find(cpuobj
, "kvm-steal-time")) {
2182 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
2185 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
2186 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
2189 if (vmc
->no_tcg_lpa2
&& object_property_find(cpuobj
, "lpa2")) {
2190 object_property_set_bool(cpuobj
, "lpa2", false, NULL
);
2193 if (object_property_find(cpuobj
, "reset-cbar")) {
2194 object_property_set_int(cpuobj
, "reset-cbar",
2195 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
2199 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
2202 object_property_set_link(cpuobj
, "secure-memory",
2203 OBJECT(secure_sysmem
), &error_abort
);
2207 /* Create the memory region only once, but link to all cpus. */
2210 * The property exists only if MemTag is supported.
2211 * If it is, we must allocate the ram to back that up.
2213 if (!object_property_find(cpuobj
, "tag-memory")) {
2214 error_report("MTE requested, but not supported "
2215 "by the guest CPU");
2219 tag_sysmem
= g_new(MemoryRegion
, 1);
2220 memory_region_init(tag_sysmem
, OBJECT(machine
),
2221 "tag-memory", UINT64_MAX
/ 32);
2224 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2225 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2226 "secure-tag-memory", UINT64_MAX
/ 32);
2228 /* As with ram, secure-tag takes precedence over tag. */
2229 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2234 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2237 object_property_set_link(cpuobj
, "secure-tag-memory",
2238 OBJECT(secure_tag_sysmem
),
2243 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2244 object_unref(cpuobj
);
2246 fdt_add_timer_nodes(vms
);
2247 fdt_add_cpu_nodes(vms
);
2249 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2251 if (machine
->device_memory
) {
2252 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2253 &machine
->device_memory
->mr
);
2256 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2258 create_gic(vms
, sysmem
);
2260 virt_cpu_post_init(vms
, sysmem
);
2262 fdt_add_pmu_nodes(vms
);
2264 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2267 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2268 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2272 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2273 machine
->ram_size
, "mach-virt.tag");
2276 vms
->highmem_ecam
&= (!firmware_loaded
|| aarch64
);
2282 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2283 vms
->acpi_dev
= create_acpi_ged(vms
);
2285 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2288 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2289 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2292 /* connect powerdown request */
2293 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2294 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2296 /* Create mmio transports, so the user can create virtio backends
2297 * (which will be automatically plugged in to the transports). If
2298 * no backend is created the transport will just sit harmlessly idle.
2300 create_virtio_devices(vms
);
2302 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2303 rom_set_fw(vms
->fw_cfg
);
2305 create_platform_bus(vms
);
2307 if (machine
->nvdimms_state
->is_enabled
) {
2308 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2309 .space_id
= AML_AS_SYSTEM_MEMORY
,
2310 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2311 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2314 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2315 arm_virt_nvdimm_acpi_dsmio
,
2316 vms
->fw_cfg
, OBJECT(vms
));
2319 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2320 vms
->bootinfo
.board_id
= -1;
2321 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2322 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2323 vms
->bootinfo
.skip_dtb_autoload
= true;
2324 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2325 vms
->bootinfo
.psci_conduit
= vms
->psci_conduit
;
2326 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2328 vms
->machine_done
.notify
= virt_machine_done
;
2329 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2332 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2334 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2339 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2341 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2343 vms
->secure
= value
;
2346 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2348 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2353 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2355 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2360 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2362 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2364 return vms
->highmem
;
2367 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2369 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2371 vms
->highmem
= value
;
2374 static bool virt_get_compact_highmem(Object
*obj
, Error
**errp
)
2376 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2378 return vms
->highmem_compact
;
2381 static void virt_set_compact_highmem(Object
*obj
, bool value
, Error
**errp
)
2383 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2385 vms
->highmem_compact
= value
;
2388 static bool virt_get_highmem_redists(Object
*obj
, Error
**errp
)
2390 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2392 return vms
->highmem_redists
;
2395 static void virt_set_highmem_redists(Object
*obj
, bool value
, Error
**errp
)
2397 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2399 vms
->highmem_redists
= value
;
2402 static bool virt_get_highmem_ecam(Object
*obj
, Error
**errp
)
2404 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2406 return vms
->highmem_ecam
;
2409 static void virt_set_highmem_ecam(Object
*obj
, bool value
, Error
**errp
)
2411 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2413 vms
->highmem_ecam
= value
;
2416 static bool virt_get_highmem_mmio(Object
*obj
, Error
**errp
)
2418 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2420 return vms
->highmem_mmio
;
2423 static void virt_set_highmem_mmio(Object
*obj
, bool value
, Error
**errp
)
2425 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2427 vms
->highmem_mmio
= value
;
2431 static bool virt_get_its(Object
*obj
, Error
**errp
)
2433 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2438 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2440 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2445 static bool virt_get_dtb_randomness(Object
*obj
, Error
**errp
)
2447 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2449 return vms
->dtb_randomness
;
2452 static void virt_set_dtb_randomness(Object
*obj
, bool value
, Error
**errp
)
2454 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2456 vms
->dtb_randomness
= value
;
2459 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2461 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2463 return g_strdup(vms
->oem_id
);
2466 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2468 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2469 size_t len
= strlen(value
);
2473 "User specified oem-id value is bigger than 6 bytes in size");
2477 strncpy(vms
->oem_id
, value
, 6);
2480 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2482 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2484 return g_strdup(vms
->oem_table_id
);
2487 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2490 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2491 size_t len
= strlen(value
);
2495 "User specified oem-table-id value is bigger than 8 bytes in size");
2498 strncpy(vms
->oem_table_id
, value
, 8);
2502 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2504 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2510 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2511 void *opaque
, Error
**errp
)
2513 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2514 OnOffAuto acpi
= vms
->acpi
;
2516 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2519 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2520 void *opaque
, Error
**errp
)
2522 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2524 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2527 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2529 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2534 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2536 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2541 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2543 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2548 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2550 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2555 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2557 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2560 switch (vms
->gic_version
) {
2561 case VIRT_GIC_VERSION_4
:
2564 case VIRT_GIC_VERSION_3
:
2571 return g_strdup(val
);
2574 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2576 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2578 if (!strcmp(value
, "4")) {
2579 vms
->gic_version
= VIRT_GIC_VERSION_4
;
2580 } else if (!strcmp(value
, "3")) {
2581 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2582 } else if (!strcmp(value
, "2")) {
2583 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2584 } else if (!strcmp(value
, "host")) {
2585 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2586 } else if (!strcmp(value
, "max")) {
2587 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2589 error_setg(errp
, "Invalid gic-version value");
2590 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2594 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2596 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2598 switch (vms
->iommu
) {
2599 case VIRT_IOMMU_NONE
:
2600 return g_strdup("none");
2601 case VIRT_IOMMU_SMMUV3
:
2602 return g_strdup("smmuv3");
2604 g_assert_not_reached();
2608 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2610 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2612 if (!strcmp(value
, "smmuv3")) {
2613 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2614 } else if (!strcmp(value
, "none")) {
2615 vms
->iommu
= VIRT_IOMMU_NONE
;
2617 error_setg(errp
, "Invalid iommu value");
2618 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2622 static bool virt_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
2624 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2626 return vms
->default_bus_bypass_iommu
;
2629 static void virt_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
2632 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2634 vms
->default_bus_bypass_iommu
= value
;
2637 static CpuInstanceProperties
2638 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2640 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2641 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2643 assert(cpu_index
< possible_cpus
->len
);
2644 return possible_cpus
->cpus
[cpu_index
].props
;
2647 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2649 int64_t socket_id
= ms
->possible_cpus
->cpus
[idx
].props
.socket_id
;
2651 return socket_id
% ms
->numa_state
->num_nodes
;
2654 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2657 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2658 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2659 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2661 if (ms
->possible_cpus
) {
2662 assert(ms
->possible_cpus
->len
== max_cpus
);
2663 return ms
->possible_cpus
;
2666 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2667 sizeof(CPUArchId
) * max_cpus
);
2668 ms
->possible_cpus
->len
= max_cpus
;
2669 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2670 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2671 ms
->possible_cpus
->cpus
[n
].arch_id
=
2672 virt_cpu_mp_affinity(vms
, n
);
2674 assert(!mc
->smp_props
.dies_supported
);
2675 ms
->possible_cpus
->cpus
[n
].props
.has_socket_id
= true;
2676 ms
->possible_cpus
->cpus
[n
].props
.socket_id
=
2677 n
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
);
2678 ms
->possible_cpus
->cpus
[n
].props
.has_cluster_id
= true;
2679 ms
->possible_cpus
->cpus
[n
].props
.cluster_id
=
2680 (n
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
;
2681 ms
->possible_cpus
->cpus
[n
].props
.has_core_id
= true;
2682 ms
->possible_cpus
->cpus
[n
].props
.core_id
=
2683 (n
/ ms
->smp
.threads
) % ms
->smp
.cores
;
2684 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2685 ms
->possible_cpus
->cpus
[n
].props
.thread_id
=
2686 n
% ms
->smp
.threads
;
2688 return ms
->possible_cpus
;
2691 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2694 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2695 const MachineState
*ms
= MACHINE(hotplug_dev
);
2696 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2698 if (!vms
->acpi_dev
) {
2700 "memory hotplug is not enabled: missing acpi-ged device");
2705 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2709 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2710 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2714 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2717 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2718 DeviceState
*dev
, Error
**errp
)
2720 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2721 MachineState
*ms
= MACHINE(hotplug_dev
);
2722 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2724 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2727 nvdimm_plug(ms
->nvdimms_state
);
2730 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2734 static void virt_virtio_md_pci_pre_plug(HotplugHandler
*hotplug_dev
,
2735 DeviceState
*dev
, Error
**errp
)
2737 HotplugHandler
*hotplug_dev2
= qdev_get_bus_hotplug_handler(dev
);
2738 Error
*local_err
= NULL
;
2740 if (!hotplug_dev2
&& dev
->hotplugged
) {
2742 * Without a bus hotplug handler, we cannot control the plug/unplug
2743 * order. We should never reach this point when hotplugging on ARM.
2744 * However, it's nice to add a safety net, similar to what we have
2747 error_setg(errp
, "hotplug of virtio based memory devices not supported"
2752 * First, see if we can plug this memory device at all. If that
2753 * succeeds, branch of to the actual hotplug handler.
2755 memory_device_pre_plug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
), NULL
,
2757 if (!local_err
&& hotplug_dev2
) {
2758 hotplug_handler_pre_plug(hotplug_dev2
, dev
, &local_err
);
2760 error_propagate(errp
, local_err
);
2763 static void virt_virtio_md_pci_plug(HotplugHandler
*hotplug_dev
,
2764 DeviceState
*dev
, Error
**errp
)
2766 HotplugHandler
*hotplug_dev2
= qdev_get_bus_hotplug_handler(dev
);
2767 Error
*local_err
= NULL
;
2770 * Plug the memory device first and then branch off to the actual
2771 * hotplug handler. If that one fails, we can easily undo the memory
2774 memory_device_plug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
));
2776 hotplug_handler_plug(hotplug_dev2
, dev
, &local_err
);
2778 memory_device_unplug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
));
2781 error_propagate(errp
, local_err
);
2784 static void virt_virtio_md_pci_unplug_request(HotplugHandler
*hotplug_dev
,
2785 DeviceState
*dev
, Error
**errp
)
2787 /* We don't support hot unplug of virtio based memory devices */
2788 error_setg(errp
, "virtio based memory devices cannot be unplugged.");
2792 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2793 DeviceState
*dev
, Error
**errp
)
2795 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2797 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2798 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2799 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
2800 virt_virtio_md_pci_pre_plug(hotplug_dev
, dev
, errp
);
2801 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2802 hwaddr db_start
= 0, db_end
= 0;
2803 char *resv_prop_str
;
2805 if (vms
->iommu
!= VIRT_IOMMU_NONE
) {
2806 error_setg(errp
, "virt machine does not support multiple IOMMUs");
2810 switch (vms
->msi_controller
) {
2811 case VIRT_MSI_CTRL_NONE
:
2813 case VIRT_MSI_CTRL_ITS
:
2814 /* GITS_TRANSLATER page */
2815 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2816 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2817 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2819 case VIRT_MSI_CTRL_GICV2M
:
2820 /* MSI_SETSPI_NS page */
2821 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2822 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2825 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2827 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2829 object_property_set_uint(OBJECT(dev
), "len-reserved-regions", 1, errp
);
2830 object_property_set_str(OBJECT(dev
), "reserved-regions[0]",
2831 resv_prop_str
, errp
);
2832 g_free(resv_prop_str
);
2836 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2837 DeviceState
*dev
, Error
**errp
)
2839 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2841 if (vms
->platform_bus_dev
) {
2842 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2844 if (device_is_dynamic_sysbus(mc
, dev
)) {
2845 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2846 SYS_BUS_DEVICE(dev
));
2849 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2850 virt_memory_plug(hotplug_dev
, dev
, errp
);
2853 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
2854 virt_virtio_md_pci_plug(hotplug_dev
, dev
, errp
);
2857 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2858 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2860 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2861 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2862 create_virtio_iommu_dt_bindings(vms
);
2866 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2867 DeviceState
*dev
, Error
**errp
)
2869 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2871 if (!vms
->acpi_dev
) {
2873 "memory hotplug is not enabled: missing acpi-ged device");
2877 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2878 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
2882 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2886 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2887 DeviceState
*dev
, Error
**errp
)
2889 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2890 Error
*local_err
= NULL
;
2892 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2897 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2898 qdev_unrealize(dev
);
2901 error_propagate(errp
, local_err
);
2904 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2905 DeviceState
*dev
, Error
**errp
)
2907 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2908 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2909 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
)) {
2910 virt_virtio_md_pci_unplug_request(hotplug_dev
, dev
, errp
);
2912 error_setg(errp
, "device unplug request for unsupported device"
2913 " type: %s", object_get_typename(OBJECT(dev
)));
2917 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2918 DeviceState
*dev
, Error
**errp
)
2920 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2921 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2923 error_setg(errp
, "virt: device unplug for unsupported device"
2924 " type: %s", object_get_typename(OBJECT(dev
)));
2928 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2931 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2933 if (device_is_dynamic_sysbus(mc
, dev
) ||
2934 object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2935 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MEM_PCI
) ||
2936 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2937 return HOTPLUG_HANDLER(machine
);
2943 * for arm64 kvm_type [7-0] encodes the requested number of bits
2944 * in the IPA address space
2946 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2948 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2949 int max_vm_pa_size
, requested_pa_size
;
2952 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
2954 /* we freeze the memory map to compute the highest gpa */
2955 virt_set_memmap(vms
, max_vm_pa_size
);
2957 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2960 * KVM requires the IPA size to be at least 32 bits.
2962 if (requested_pa_size
< 32) {
2963 requested_pa_size
= 32;
2966 if (requested_pa_size
> max_vm_pa_size
) {
2967 error_report("-m and ,maxmem option values "
2968 "require an IPA range (%d bits) larger than "
2969 "the one supported by the host (%d bits)",
2970 requested_pa_size
, max_vm_pa_size
);
2974 * We return the requested PA log size, unless KVM only supports
2975 * the implicit legacy 40b IPA setting, in which case the kvm_type
2978 return fixed_ipa
? 0 : requested_pa_size
;
2981 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2983 MachineClass
*mc
= MACHINE_CLASS(oc
);
2984 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2986 mc
->init
= machvirt_init
;
2987 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2988 * The value may be reduced later when we have more information about the
2989 * configuration of the particular instance.
2992 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2993 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2994 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2995 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2997 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2999 mc
->block_default_type
= IF_VIRTIO
;
3001 mc
->pci_allow_0_address
= true;
3002 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
3003 mc
->minimum_page_bits
= 12;
3004 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
3005 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
3006 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
3007 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
3008 mc
->kvm_type
= virt_kvm_type
;
3009 assert(!mc
->get_hotplug_handler
);
3010 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
3011 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
3012 hc
->plug
= virt_machine_device_plug_cb
;
3013 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
3014 hc
->unplug
= virt_machine_device_unplug_cb
;
3015 mc
->nvdimm_supported
= true;
3016 mc
->smp_props
.clusters_supported
= true;
3017 mc
->auto_enable_numa_with_memhp
= true;
3018 mc
->auto_enable_numa_with_memdev
= true;
3019 mc
->default_ram_id
= "mach-virt.ram";
3021 object_class_property_add(oc
, "acpi", "OnOffAuto",
3022 virt_get_acpi
, virt_set_acpi
,
3024 object_class_property_set_description(oc
, "acpi",
3026 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
3028 object_class_property_set_description(oc
, "secure",
3029 "Set on/off to enable/disable the ARM "
3030 "Security Extensions (TrustZone)");
3032 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
3034 object_class_property_set_description(oc
, "virtualization",
3035 "Set on/off to enable/disable emulating a "
3036 "guest CPU which implements the ARM "
3037 "Virtualization Extensions");
3039 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
3041 object_class_property_set_description(oc
, "highmem",
3042 "Set on/off to enable/disable using "
3043 "physical address space above 32 bits");
3045 object_class_property_add_bool(oc
, "compact-highmem",
3046 virt_get_compact_highmem
,
3047 virt_set_compact_highmem
);
3048 object_class_property_set_description(oc
, "compact-highmem",
3049 "Set on/off to enable/disable compact "
3050 "layout for high memory regions");
3052 object_class_property_add_bool(oc
, "highmem-redists",
3053 virt_get_highmem_redists
,
3054 virt_set_highmem_redists
);
3055 object_class_property_set_description(oc
, "highmem-redists",
3056 "Set on/off to enable/disable high "
3057 "memory region for GICv3 or GICv4 "
3060 object_class_property_add_bool(oc
, "highmem-ecam",
3061 virt_get_highmem_ecam
,
3062 virt_set_highmem_ecam
);
3063 object_class_property_set_description(oc
, "highmem-ecam",
3064 "Set on/off to enable/disable high "
3065 "memory region for PCI ECAM");
3067 object_class_property_add_bool(oc
, "highmem-mmio",
3068 virt_get_highmem_mmio
,
3069 virt_set_highmem_mmio
);
3070 object_class_property_set_description(oc
, "highmem-mmio",
3071 "Set on/off to enable/disable high "
3072 "memory region for PCI MMIO");
3074 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
3075 virt_set_gic_version
);
3076 object_class_property_set_description(oc
, "gic-version",
3078 "Valid values are 2, 3, 4, host and max");
3080 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
3081 object_class_property_set_description(oc
, "iommu",
3082 "Set the IOMMU type. "
3083 "Valid values are none and smmuv3");
3085 object_class_property_add_bool(oc
, "default-bus-bypass-iommu",
3086 virt_get_default_bus_bypass_iommu
,
3087 virt_set_default_bus_bypass_iommu
);
3088 object_class_property_set_description(oc
, "default-bus-bypass-iommu",
3089 "Set on/off to enable/disable "
3090 "bypass_iommu for default root bus");
3092 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
3094 object_class_property_set_description(oc
, "ras",
3095 "Set on/off to enable/disable reporting host memory errors "
3096 "to a KVM guest using ACPI and guest external abort exceptions");
3098 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
3099 object_class_property_set_description(oc
, "mte",
3100 "Set on/off to enable/disable emulating a "
3101 "guest CPU which implements the ARM "
3102 "Memory Tagging Extension");
3104 object_class_property_add_bool(oc
, "its", virt_get_its
,
3106 object_class_property_set_description(oc
, "its",
3107 "Set on/off to enable/disable "
3108 "ITS instantiation");
3110 object_class_property_add_bool(oc
, "dtb-randomness",
3111 virt_get_dtb_randomness
,
3112 virt_set_dtb_randomness
);
3113 object_class_property_set_description(oc
, "dtb-randomness",
3114 "Set off to disable passing random or "
3115 "non-deterministic dtb nodes to guest");
3117 object_class_property_add_bool(oc
, "dtb-kaslr-seed",
3118 virt_get_dtb_randomness
,
3119 virt_set_dtb_randomness
);
3120 object_class_property_set_description(oc
, "dtb-kaslr-seed",
3121 "Deprecated synonym of dtb-randomness");
3123 object_class_property_add_str(oc
, "x-oem-id",
3126 object_class_property_set_description(oc
, "x-oem-id",
3127 "Override the default value of field OEMID "
3128 "in ACPI table header."
3129 "The string may be up to 6 bytes in size");
3132 object_class_property_add_str(oc
, "x-oem-table-id",
3133 virt_get_oem_table_id
,
3134 virt_set_oem_table_id
);
3135 object_class_property_set_description(oc
, "x-oem-table-id",
3136 "Override the default value of field OEM Table ID "
3137 "in ACPI table header."
3138 "The string may be up to 8 bytes in size");
3142 static void virt_instance_init(Object
*obj
)
3144 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
3145 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
3147 /* EL3 is disabled by default on virt: this makes us consistent
3148 * between KVM and TCG for this board, and it also allows us to
3149 * boot UEFI blobs which assume no TrustZone support.
3151 vms
->secure
= false;
3153 /* EL2 is also disabled by default, for similar reasons */
3156 /* High memory is enabled by default */
3157 vms
->highmem
= true;
3158 vms
->highmem_compact
= !vmc
->no_highmem_compact
;
3159 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
3161 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
3162 vms
->highmem_mmio
= true;
3163 vms
->highmem_redists
= true;
3168 /* Default allows ITS instantiation */
3171 if (vmc
->no_tcg_its
) {
3172 vms
->tcg_its
= false;
3174 vms
->tcg_its
= true;
3178 /* Default disallows iommu instantiation */
3179 vms
->iommu
= VIRT_IOMMU_NONE
;
3181 /* The default root bus is attached to iommu by default */
3182 vms
->default_bus_bypass_iommu
= false;
3184 /* Default disallows RAS instantiation */
3187 /* MTE is disabled by default. */
3190 /* Supply kaslr-seed and rng-seed by default */
3191 vms
->dtb_randomness
= true;
3193 vms
->irqmap
= a15irqmap
;
3195 virt_flash_create(vms
);
3197 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
3198 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
3201 static const TypeInfo virt_machine_info
= {
3202 .name
= TYPE_VIRT_MACHINE
,
3203 .parent
= TYPE_MACHINE
,
3205 .instance_size
= sizeof(VirtMachineState
),
3206 .class_size
= sizeof(VirtMachineClass
),
3207 .class_init
= virt_machine_class_init
,
3208 .instance_init
= virt_instance_init
,
3209 .interfaces
= (InterfaceInfo
[]) {
3210 { TYPE_HOTPLUG_HANDLER
},
3215 static void machvirt_machine_init(void)
3217 type_register_static(&virt_machine_info
);
3219 type_init(machvirt_machine_init
);
3221 static void virt_machine_8_0_options(MachineClass
*mc
)
3224 DEFINE_VIRT_MACHINE_AS_LATEST(8, 0)
3226 static void virt_machine_7_2_options(MachineClass
*mc
)
3228 virt_machine_8_0_options(mc
);
3229 compat_props_add(mc
->compat_props
, hw_compat_7_2
, hw_compat_7_2_len
);
3231 DEFINE_VIRT_MACHINE(7, 2)
3233 static void virt_machine_7_1_options(MachineClass
*mc
)
3235 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3237 virt_machine_7_2_options(mc
);
3238 compat_props_add(mc
->compat_props
, hw_compat_7_1
, hw_compat_7_1_len
);
3239 /* Compact layout for high memory regions was introduced with 7.2 */
3240 vmc
->no_highmem_compact
= true;
3242 DEFINE_VIRT_MACHINE(7, 1)
3244 static void virt_machine_7_0_options(MachineClass
*mc
)
3246 virt_machine_7_1_options(mc
);
3247 compat_props_add(mc
->compat_props
, hw_compat_7_0
, hw_compat_7_0_len
);
3249 DEFINE_VIRT_MACHINE(7, 0)
3251 static void virt_machine_6_2_options(MachineClass
*mc
)
3253 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3255 virt_machine_7_0_options(mc
);
3256 compat_props_add(mc
->compat_props
, hw_compat_6_2
, hw_compat_6_2_len
);
3257 vmc
->no_tcg_lpa2
= true;
3259 DEFINE_VIRT_MACHINE(6, 2)
3261 static void virt_machine_6_1_options(MachineClass
*mc
)
3263 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3265 virt_machine_6_2_options(mc
);
3266 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
3267 mc
->smp_props
.prefer_sockets
= true;
3268 vmc
->no_cpu_topology
= true;
3270 /* qemu ITS was introduced with 6.2 */
3271 vmc
->no_tcg_its
= true;
3273 DEFINE_VIRT_MACHINE(6, 1)
3275 static void virt_machine_6_0_options(MachineClass
*mc
)
3277 virt_machine_6_1_options(mc
);
3278 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
3280 DEFINE_VIRT_MACHINE(6, 0)
3282 static void virt_machine_5_2_options(MachineClass
*mc
)
3284 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3286 virt_machine_6_0_options(mc
);
3287 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
3288 vmc
->no_secure_gpio
= true;
3290 DEFINE_VIRT_MACHINE(5, 2)
3292 static void virt_machine_5_1_options(MachineClass
*mc
)
3294 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3296 virt_machine_5_2_options(mc
);
3297 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
3298 vmc
->no_kvm_steal_time
= true;
3300 DEFINE_VIRT_MACHINE(5, 1)
3302 static void virt_machine_5_0_options(MachineClass
*mc
)
3304 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3306 virt_machine_5_1_options(mc
);
3307 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
3308 mc
->numa_mem_supported
= true;
3309 vmc
->acpi_expose_flash
= true;
3310 mc
->auto_enable_numa_with_memdev
= false;
3312 DEFINE_VIRT_MACHINE(5, 0)
3314 static void virt_machine_4_2_options(MachineClass
*mc
)
3316 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3318 virt_machine_5_0_options(mc
);
3319 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
3320 vmc
->kvm_no_adjvtime
= true;
3322 DEFINE_VIRT_MACHINE(4, 2)
3324 static void virt_machine_4_1_options(MachineClass
*mc
)
3326 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3328 virt_machine_4_2_options(mc
);
3329 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
3331 mc
->auto_enable_numa_with_memhp
= false;
3333 DEFINE_VIRT_MACHINE(4, 1)
3335 static void virt_machine_4_0_options(MachineClass
*mc
)
3337 virt_machine_4_1_options(mc
);
3338 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
3340 DEFINE_VIRT_MACHINE(4, 0)
3342 static void virt_machine_3_1_options(MachineClass
*mc
)
3344 virt_machine_4_0_options(mc
);
3345 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
3347 DEFINE_VIRT_MACHINE(3, 1)
3349 static void virt_machine_3_0_options(MachineClass
*mc
)
3351 virt_machine_3_1_options(mc
);
3352 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
3354 DEFINE_VIRT_MACHINE(3, 0)
3356 static void virt_machine_2_12_options(MachineClass
*mc
)
3358 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3360 virt_machine_3_0_options(mc
);
3361 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
3362 vmc
->no_highmem_ecam
= true;
3365 DEFINE_VIRT_MACHINE(2, 12)
3367 static void virt_machine_2_11_options(MachineClass
*mc
)
3369 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3371 virt_machine_2_12_options(mc
);
3372 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
3373 vmc
->smbios_old_sys_ver
= true;
3375 DEFINE_VIRT_MACHINE(2, 11)
3377 static void virt_machine_2_10_options(MachineClass
*mc
)
3379 virt_machine_2_11_options(mc
);
3380 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
3381 /* before 2.11 we never faulted accesses to bad addresses */
3382 mc
->ignore_memory_transaction_failures
= true;
3384 DEFINE_VIRT_MACHINE(2, 10)
3386 static void virt_machine_2_9_options(MachineClass
*mc
)
3388 virt_machine_2_10_options(mc
);
3389 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
3391 DEFINE_VIRT_MACHINE(2, 9)
3393 static void virt_machine_2_8_options(MachineClass
*mc
)
3395 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3397 virt_machine_2_9_options(mc
);
3398 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
3399 /* For 2.8 and earlier we falsely claimed in the DT that
3400 * our timers were edge-triggered, not level-triggered.
3402 vmc
->claim_edge_triggered_timers
= true;
3404 DEFINE_VIRT_MACHINE(2, 8)
3406 static void virt_machine_2_7_options(MachineClass
*mc
)
3408 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3410 virt_machine_2_8_options(mc
);
3411 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
3412 /* ITS was introduced with 2.8 */
3414 /* Stick with 1K pages for migration compatibility */
3415 mc
->minimum_page_bits
= 0;
3417 DEFINE_VIRT_MACHINE(2, 7)
3419 static void virt_machine_2_6_options(MachineClass
*mc
)
3421 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3423 virt_machine_2_7_options(mc
);
3424 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
3425 vmc
->disallow_affinity_adjustment
= true;
3426 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3429 DEFINE_VIRT_MACHINE(2, 6)