2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "hw/sysbus.h"
33 #include "hw/arm/arm.h"
34 #include "hw/arm/primecell.h"
35 #include "hw/arm/virt.h"
36 #include "hw/devices.h"
38 #include "sysemu/block-backend.h"
39 #include "sysemu/device_tree.h"
40 #include "sysemu/sysemu.h"
41 #include "sysemu/kvm.h"
42 #include "hw/boards.h"
43 #include "hw/loader.h"
44 #include "exec/address-spaces.h"
45 #include "qemu/bitops.h"
46 #include "qemu/error-report.h"
47 #include "hw/pci-host/gpex.h"
48 #include "hw/arm/virt-acpi-build.h"
49 #include "hw/arm/sysbus-fdt.h"
50 #include "hw/platform-bus.h"
51 #include "hw/arm/fdt.h"
52 #include "hw/intc/arm_gic_common.h"
54 #include "hw/smbios/smbios.h"
55 #include "qapi/visitor.h"
56 #include "standard-headers/linux/input.h"
58 /* Number of external interrupt lines to configure the GIC with */
61 #define PLATFORM_BUS_NUM_IRQS 64
63 static ARMPlatformBusSystemParams platform_bus_params
;
65 typedef struct VirtBoardInfo
{
66 struct arm_boot_info bootinfo
;
67 const char *cpu_model
;
68 const MemMapEntry
*memmap
;
73 uint32_t clock_phandle
;
80 VirtBoardInfo
*daughterboard
;
90 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
91 #define VIRT_MACHINE(obj) \
92 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
93 #define VIRT_MACHINE_GET_CLASS(obj) \
94 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
95 #define VIRT_MACHINE_CLASS(klass) \
96 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
98 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
99 * RAM can go up to the 256GB mark, leaving 256GB of the physical
100 * address space unallocated and free for future use between 256G and 512G.
101 * If we need to provide more RAM to VMs in the future then we need to:
102 * * allocate a second bank of RAM starting at 2TB and working up
103 * * fix the DT and ACPI table generation code in QEMU to correctly
104 * report two split lumps of RAM to the guest
105 * * fix KVM in the host kernel to allow guests with >40 bit address spaces
106 * (We don't want to fill all the way up to 512GB with RAM because
107 * we might want it for non-RAM purposes later. Conversely it seems
108 * reasonable to assume that anybody configuring a VM with a quarter
109 * of a terabyte of RAM will be doing it on a host with more than a
110 * terabyte of physical address space.)
112 #define RAMLIMIT_GB 255
113 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
115 /* Addresses and sizes of our components.
116 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
117 * 128MB..256MB is used for miscellaneous device I/O.
118 * 256MB..1GB is reserved for possible future PCI support (ie where the
119 * PCI memory window will go if we add a PCI host controller).
120 * 1GB and up is RAM (which may happily spill over into the
121 * high memory region beyond 4GB).
122 * This represents a compromise between how much RAM can be given to
123 * a 32 bit VM and leaving space for expansion and in particular for PCI.
124 * Note that devices should generally be placed at multiples of 0x10000,
125 * to accommodate guests using 64K pages.
127 static const MemMapEntry a15memmap
[] = {
128 /* Space up to 0x8000000 is reserved for a boot ROM */
129 [VIRT_FLASH
] = { 0, 0x08000000 },
130 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
131 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
132 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
133 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
134 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
135 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
136 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
137 /* This redistributor space allows up to 2*64kB*123 CPUs */
138 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
139 [VIRT_UART
] = { 0x09000000, 0x00001000 },
140 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
141 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
142 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
143 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
144 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
145 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
146 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
147 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
148 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
149 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
150 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
151 [VIRT_MEM
] = { 0x40000000, RAMLIMIT_BYTES
},
152 /* Second PCIe window, 512GB wide at the 512GB boundary */
153 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
156 static const int a15irqmap
[] = {
159 [VIRT_PCIE
] = 3, /* ... to 6 */
161 [VIRT_SECURE_UART
] = 8,
162 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
163 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
164 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
167 static VirtBoardInfo machines
[] = {
169 .cpu_model
= "cortex-a15",
174 .cpu_model
= "cortex-a53",
179 .cpu_model
= "cortex-a57",
190 static VirtBoardInfo
*find_machine_info(const char *cpu
)
194 for (i
= 0; i
< ARRAY_SIZE(machines
); i
++) {
195 if (strcmp(cpu
, machines
[i
].cpu_model
) == 0) {
202 static void create_fdt(VirtBoardInfo
*vbi
)
204 void *fdt
= create_device_tree(&vbi
->fdt_size
);
207 error_report("create_device_tree() failed");
214 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
215 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
216 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
219 * /chosen and /memory nodes must exist for load_dtb
220 * to fill in necessary properties later
222 qemu_fdt_add_subnode(fdt
, "/chosen");
223 qemu_fdt_add_subnode(fdt
, "/memory");
224 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
226 /* Clock node, for the benefit of the UART. The kernel device tree
227 * binding documentation claims the PL011 node clock properties are
228 * optional but in practice if you omit them the kernel refuses to
229 * probe for the device.
231 vbi
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
232 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
233 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
234 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
235 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
236 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
238 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vbi
->clock_phandle
);
242 static void fdt_add_psci_node(const VirtBoardInfo
*vbi
)
244 uint32_t cpu_suspend_fn
;
248 void *fdt
= vbi
->fdt
;
249 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
251 qemu_fdt_add_subnode(fdt
, "/psci");
252 if (armcpu
->psci_version
== 2) {
253 const char comp
[] = "arm,psci-0.2\0arm,psci";
254 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
256 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
257 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
258 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
259 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
260 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
262 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
263 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
264 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
267 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
269 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
270 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
271 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
272 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
275 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
276 * to the instruction that should be used to invoke PSCI functions.
277 * However, the device tree binding uses 'method' instead, so that is
278 * what we should use here.
280 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
282 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
283 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
284 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
285 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
288 static void fdt_add_timer_nodes(const VirtBoardInfo
*vbi
, int gictype
)
290 /* Note that on A15 h/w these interrupts are level-triggered,
291 * but for the GIC implementation provided by both QEMU and KVM
292 * they are edge-triggered.
295 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
298 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
299 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
300 (1 << vbi
->smp_cpus
) - 1);
303 qemu_fdt_add_subnode(vbi
->fdt
, "/timer");
305 armcpu
= ARM_CPU(qemu_get_cpu(0));
306 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
307 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
308 qemu_fdt_setprop(vbi
->fdt
, "/timer", "compatible",
309 compat
, sizeof(compat
));
311 qemu_fdt_setprop_string(vbi
->fdt
, "/timer", "compatible",
314 qemu_fdt_setprop(vbi
->fdt
, "/timer", "always-on", NULL
, 0);
315 qemu_fdt_setprop_cells(vbi
->fdt
, "/timer", "interrupts",
316 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
317 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
318 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
319 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
322 static void fdt_add_cpu_nodes(const VirtBoardInfo
*vbi
)
328 * From Documentation/devicetree/bindings/arm/cpus.txt
329 * On ARM v8 64-bit systems value should be set to 2,
330 * that corresponds to the MPIDR_EL1 register size.
331 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
332 * in the system, #address-cells can be set to 1, since
333 * MPIDR_EL1[63:32] bits are not used for CPUs
336 * Here we actually don't know whether our system is 32- or 64-bit one.
337 * The simplest way to go is to examine affinity IDs of all our CPUs. If
338 * at least one of them has Aff3 populated, we set #address-cells to 2.
340 for (cpu
= 0; cpu
< vbi
->smp_cpus
; cpu
++) {
341 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
343 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
349 qemu_fdt_add_subnode(vbi
->fdt
, "/cpus");
350 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#address-cells", addr_cells
);
351 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#size-cells", 0x0);
353 for (cpu
= vbi
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
354 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
355 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
357 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
358 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "cpu");
359 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible",
360 armcpu
->dtb_compatible
);
362 if (vbi
->smp_cpus
> 1) {
363 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
364 "enable-method", "psci");
367 if (addr_cells
== 2) {
368 qemu_fdt_setprop_u64(vbi
->fdt
, nodename
, "reg",
369 armcpu
->mp_affinity
);
371 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "reg",
372 armcpu
->mp_affinity
);
379 static void fdt_add_v2m_gic_node(VirtBoardInfo
*vbi
)
381 vbi
->v2m_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
382 qemu_fdt_add_subnode(vbi
->fdt
, "/intc/v2m");
383 qemu_fdt_setprop_string(vbi
->fdt
, "/intc/v2m", "compatible",
384 "arm,gic-v2m-frame");
385 qemu_fdt_setprop(vbi
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
386 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc/v2m", "reg",
387 2, vbi
->memmap
[VIRT_GIC_V2M
].base
,
388 2, vbi
->memmap
[VIRT_GIC_V2M
].size
);
389 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc/v2m", "phandle", vbi
->v2m_phandle
);
392 static void fdt_add_gic_node(VirtBoardInfo
*vbi
, int type
)
394 vbi
->gic_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
395 qemu_fdt_setprop_cell(vbi
->fdt
, "/", "interrupt-parent", vbi
->gic_phandle
);
397 qemu_fdt_add_subnode(vbi
->fdt
, "/intc");
398 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#interrupt-cells", 3);
399 qemu_fdt_setprop(vbi
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
400 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#address-cells", 0x2);
401 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#size-cells", 0x2);
402 qemu_fdt_setprop(vbi
->fdt
, "/intc", "ranges", NULL
, 0);
404 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
406 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
407 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
408 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
409 2, vbi
->memmap
[VIRT_GIC_REDIST
].base
,
410 2, vbi
->memmap
[VIRT_GIC_REDIST
].size
);
412 /* 'cortex-a15-gic' means 'GIC v2' */
413 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
414 "arm,cortex-a15-gic");
415 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
416 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
417 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
418 2, vbi
->memmap
[VIRT_GIC_CPU
].base
,
419 2, vbi
->memmap
[VIRT_GIC_CPU
].size
);
422 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "phandle", vbi
->gic_phandle
);
425 static void create_v2m(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
428 int irq
= vbi
->irqmap
[VIRT_GIC_V2M
];
431 dev
= qdev_create(NULL
, "arm-gicv2m");
432 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vbi
->memmap
[VIRT_GIC_V2M
].base
);
433 qdev_prop_set_uint32(dev
, "base-spi", irq
);
434 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
435 qdev_init_nofail(dev
);
437 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
438 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
441 fdt_add_v2m_gic_node(vbi
);
444 static void create_gic(VirtBoardInfo
*vbi
, qemu_irq
*pic
, int type
, bool secure
)
446 /* We create a standalone GIC */
448 SysBusDevice
*gicbusdev
;
452 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
454 gicdev
= qdev_create(NULL
, gictype
);
455 qdev_prop_set_uint32(gicdev
, "revision", type
);
456 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
457 /* Note that the num-irq property counts both internal and external
458 * interrupts; there are always 32 of the former (mandated by GIC spec).
460 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
461 if (!kvm_irqchip_in_kernel()) {
462 qdev_prop_set_bit(gicdev
, "has-security-extensions", secure
);
464 qdev_init_nofail(gicdev
);
465 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
466 sysbus_mmio_map(gicbusdev
, 0, vbi
->memmap
[VIRT_GIC_DIST
].base
);
468 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_REDIST
].base
);
470 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_CPU
].base
);
473 /* Wire the outputs from each CPU's generic timer to the
474 * appropriate GIC PPI inputs, and the GIC's IRQ output to
475 * the CPU's IRQ input.
477 for (i
= 0; i
< smp_cpus
; i
++) {
478 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
479 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
481 /* Mapping from the output timer irq lines from the CPU to the
482 * GIC PPI inputs we use for the virt board.
484 const int timer_irq
[] = {
485 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
486 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
487 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
488 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
491 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
492 qdev_connect_gpio_out(cpudev
, irq
,
493 qdev_get_gpio_in(gicdev
,
494 ppibase
+ timer_irq
[irq
]));
497 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
498 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
499 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
502 for (i
= 0; i
< NUM_IRQS
; i
++) {
503 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
506 fdt_add_gic_node(vbi
, type
);
509 create_v2m(vbi
, pic
);
513 static void create_uart(const VirtBoardInfo
*vbi
, qemu_irq
*pic
, int uart
,
517 hwaddr base
= vbi
->memmap
[uart
].base
;
518 hwaddr size
= vbi
->memmap
[uart
].size
;
519 int irq
= vbi
->irqmap
[uart
];
520 const char compat
[] = "arm,pl011\0arm,primecell";
521 const char clocknames
[] = "uartclk\0apb_pclk";
522 DeviceState
*dev
= qdev_create(NULL
, "pl011");
523 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
525 qdev_init_nofail(dev
);
526 memory_region_add_subregion(mem
, base
,
527 sysbus_mmio_get_region(s
, 0));
528 sysbus_connect_irq(s
, 0, pic
[irq
]);
530 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
531 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
532 /* Note that we can't use setprop_string because of the embedded NUL */
533 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible",
534 compat
, sizeof(compat
));
535 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
537 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
538 GIC_FDT_IRQ_TYPE_SPI
, irq
,
539 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
540 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "clocks",
541 vbi
->clock_phandle
, vbi
->clock_phandle
);
542 qemu_fdt_setprop(vbi
->fdt
, nodename
, "clock-names",
543 clocknames
, sizeof(clocknames
));
545 if (uart
== VIRT_UART
) {
546 qemu_fdt_setprop_string(vbi
->fdt
, "/chosen", "stdout-path", nodename
);
548 /* Mark as not usable by the normal world */
549 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "status", "disabled");
550 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "secure-status", "okay");
556 static void create_rtc(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
559 hwaddr base
= vbi
->memmap
[VIRT_RTC
].base
;
560 hwaddr size
= vbi
->memmap
[VIRT_RTC
].size
;
561 int irq
= vbi
->irqmap
[VIRT_RTC
];
562 const char compat
[] = "arm,pl031\0arm,primecell";
564 sysbus_create_simple("pl031", base
, pic
[irq
]);
566 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
567 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
568 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
569 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
571 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
572 GIC_FDT_IRQ_TYPE_SPI
, irq
,
573 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
574 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
575 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
579 static DeviceState
*pl061_dev
;
580 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
582 /* use gpio Pin 3 for power button event */
583 qemu_set_irq(qdev_get_gpio_in(pl061_dev
, 3), 1);
586 static Notifier virt_system_powerdown_notifier
= {
587 .notify
= virt_powerdown_req
590 static void create_gpio(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
593 hwaddr base
= vbi
->memmap
[VIRT_GPIO
].base
;
594 hwaddr size
= vbi
->memmap
[VIRT_GPIO
].size
;
595 int irq
= vbi
->irqmap
[VIRT_GPIO
];
596 const char compat
[] = "arm,pl061\0arm,primecell";
598 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
600 uint32_t phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
601 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
602 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
603 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
605 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
606 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#gpio-cells", 2);
607 qemu_fdt_setprop(vbi
->fdt
, nodename
, "gpio-controller", NULL
, 0);
608 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
609 GIC_FDT_IRQ_TYPE_SPI
, irq
,
610 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
611 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
612 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
613 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "phandle", phandle
);
615 qemu_fdt_add_subnode(vbi
->fdt
, "/gpio-keys");
616 qemu_fdt_setprop_string(vbi
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
617 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys", "#size-cells", 0);
618 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys", "#address-cells", 1);
620 qemu_fdt_add_subnode(vbi
->fdt
, "/gpio-keys/poweroff");
621 qemu_fdt_setprop_string(vbi
->fdt
, "/gpio-keys/poweroff",
622 "label", "GPIO Key Poweroff");
623 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys/poweroff", "linux,code",
625 qemu_fdt_setprop_cells(vbi
->fdt
, "/gpio-keys/poweroff",
626 "gpios", phandle
, 3, 0);
628 /* connect powerdown request */
629 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
634 static void create_virtio_devices(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
637 hwaddr size
= vbi
->memmap
[VIRT_MMIO
].size
;
639 /* We create the transports in forwards order. Since qbus_realize()
640 * prepends (not appends) new child buses, the incrementing loop below will
641 * create a list of virtio-mmio buses with decreasing base addresses.
643 * When a -device option is processed from the command line,
644 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
645 * order. The upshot is that -device options in increasing command line
646 * order are mapped to virtio-mmio buses with decreasing base addresses.
648 * When this code was originally written, that arrangement ensured that the
649 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
650 * the first -device on the command line. (The end-to-end order is a
651 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
652 * guest kernel's name-to-address assignment strategy.)
654 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
655 * the message, if not necessarily the code, of commit 70161ff336.
656 * Therefore the loop now establishes the inverse of the original intent.
658 * Unfortunately, we can't counteract the kernel change by reversing the
659 * loop; it would break existing command lines.
661 * In any case, the kernel makes no guarantee about the stability of
662 * enumeration order of virtio devices (as demonstrated by it changing
663 * between kernel versions). For reliable and stable identification
664 * of disks users must use UUIDs or similar mechanisms.
666 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
667 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
668 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
670 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
673 /* We add dtb nodes in reverse order so that they appear in the finished
674 * device tree lowest address first.
676 * Note that this mapping is independent of the loop above. The previous
677 * loop influences virtio device to virtio transport assignment, whereas
678 * this loop controls how virtio transports are laid out in the dtb.
680 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
682 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
683 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
685 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
686 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
687 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
688 "compatible", "virtio,mmio");
689 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
691 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
692 GIC_FDT_IRQ_TYPE_SPI
, irq
,
693 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
698 static void create_one_flash(const char *name
, hwaddr flashbase
,
699 hwaddr flashsize
, const char *file
)
701 /* Create and map a single flash device. We use the same
702 * parameters as the flash devices on the Versatile Express board.
704 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
705 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
706 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
707 const uint64_t sectorlength
= 256 * 1024;
710 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
714 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
715 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
716 qdev_prop_set_uint8(dev
, "width", 4);
717 qdev_prop_set_uint8(dev
, "device-width", 2);
718 qdev_prop_set_bit(dev
, "big-endian", false);
719 qdev_prop_set_uint16(dev
, "id0", 0x89);
720 qdev_prop_set_uint16(dev
, "id1", 0x18);
721 qdev_prop_set_uint16(dev
, "id2", 0x00);
722 qdev_prop_set_uint16(dev
, "id3", 0x00);
723 qdev_prop_set_string(dev
, "name", name
);
724 qdev_init_nofail(dev
);
726 sysbus_mmio_map(sbd
, 0, flashbase
);
732 if (drive_get(IF_PFLASH
, 0, 0)) {
733 error_report("The contents of the first flash device may be "
734 "specified with -bios or with -drive if=pflash... "
735 "but you cannot use both options at once");
738 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, file
);
740 error_report("Could not find ROM image '%s'", file
);
743 image_size
= load_image_mr(fn
, sysbus_mmio_get_region(sbd
, 0));
745 if (image_size
< 0) {
746 error_report("Could not load ROM image '%s'", file
);
752 static void create_flash(const VirtBoardInfo
*vbi
)
754 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
755 * Any file passed via -bios goes in the first of these.
757 hwaddr flashsize
= vbi
->memmap
[VIRT_FLASH
].size
/ 2;
758 hwaddr flashbase
= vbi
->memmap
[VIRT_FLASH
].base
;
761 create_one_flash("virt.flash0", flashbase
, flashsize
, bios_name
);
762 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
, NULL
);
764 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
765 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
766 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
767 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
768 2, flashbase
, 2, flashsize
,
769 2, flashbase
+ flashsize
, 2, flashsize
);
770 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
774 static void create_fw_cfg(const VirtBoardInfo
*vbi
, AddressSpace
*as
)
776 hwaddr base
= vbi
->memmap
[VIRT_FW_CFG
].base
;
777 hwaddr size
= vbi
->memmap
[VIRT_FW_CFG
].size
;
780 fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
782 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
783 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
784 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
785 "compatible", "qemu,fw-cfg-mmio");
786 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
791 static void create_pcie_irq_map(const VirtBoardInfo
*vbi
, uint32_t gic_phandle
,
792 int first_irq
, const char *nodename
)
795 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
796 uint32_t *irq_map
= full_irq_map
;
798 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
799 for (pin
= 0; pin
< 4; pin
++) {
800 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
801 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
802 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
806 devfn
<< 8, 0, 0, /* devfn */
807 pin
+ 1, /* PCI pin */
808 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
810 /* Convert map to big endian */
811 for (i
= 0; i
< 10; i
++) {
812 irq_map
[i
] = cpu_to_be32(map
[i
]);
818 qemu_fdt_setprop(vbi
->fdt
, nodename
, "interrupt-map",
819 full_irq_map
, sizeof(full_irq_map
));
821 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupt-map-mask",
822 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
826 static void create_pcie(const VirtBoardInfo
*vbi
, qemu_irq
*pic
,
829 hwaddr base_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].base
;
830 hwaddr size_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].size
;
831 hwaddr base_mmio_high
= vbi
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
832 hwaddr size_mmio_high
= vbi
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
833 hwaddr base_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].base
;
834 hwaddr size_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].size
;
835 hwaddr base_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].base
;
836 hwaddr size_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].size
;
837 hwaddr base
= base_mmio
;
838 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
839 int irq
= vbi
->irqmap
[VIRT_PCIE
];
840 MemoryRegion
*mmio_alias
;
841 MemoryRegion
*mmio_reg
;
842 MemoryRegion
*ecam_alias
;
843 MemoryRegion
*ecam_reg
;
849 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
850 qdev_init_nofail(dev
);
852 /* Map only the first size_ecam bytes of ECAM space */
853 ecam_alias
= g_new0(MemoryRegion
, 1);
854 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
855 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
856 ecam_reg
, 0, size_ecam
);
857 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
859 /* Map the MMIO window into system address space so as to expose
860 * the section of PCI MMIO space which starts at the same base address
861 * (ie 1:1 mapping for that part of PCI MMIO space visible through
864 mmio_alias
= g_new0(MemoryRegion
, 1);
865 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
866 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
867 mmio_reg
, base_mmio
, size_mmio
);
868 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
871 /* Map high MMIO space */
872 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
874 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
875 mmio_reg
, base_mmio_high
, size_mmio_high
);
876 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
880 /* Map IO port space */
881 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
883 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
884 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
887 pci
= PCI_HOST_BRIDGE(dev
);
889 for (i
= 0; i
< nb_nics
; i
++) {
890 NICInfo
*nd
= &nd_table
[i
];
893 nd
->model
= g_strdup("virtio");
896 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
900 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
901 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
902 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
903 "compatible", "pci-host-ecam-generic");
904 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "pci");
905 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#address-cells", 3);
906 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#size-cells", 2);
907 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "bus-range", 0,
910 if (vbi
->v2m_phandle
) {
911 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "msi-parent",
915 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
916 2, base_ecam
, 2, size_ecam
);
919 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
920 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
921 2, base_pio
, 2, size_pio
,
922 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
923 2, base_mmio
, 2, size_mmio
,
924 1, FDT_PCI_RANGE_MMIO_64BIT
,
926 2, base_mmio_high
, 2, size_mmio_high
);
928 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
929 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
930 2, base_pio
, 2, size_pio
,
931 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
932 2, base_mmio
, 2, size_mmio
);
935 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#interrupt-cells", 1);
936 create_pcie_irq_map(vbi
, vbi
->gic_phandle
, irq
, nodename
);
941 static void create_platform_bus(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
946 ARMPlatformBusFDTParams
*fdt_params
= g_new(ARMPlatformBusFDTParams
, 1);
947 MemoryRegion
*sysmem
= get_system_memory();
949 platform_bus_params
.platform_bus_base
= vbi
->memmap
[VIRT_PLATFORM_BUS
].base
;
950 platform_bus_params
.platform_bus_size
= vbi
->memmap
[VIRT_PLATFORM_BUS
].size
;
951 platform_bus_params
.platform_bus_first_irq
= vbi
->irqmap
[VIRT_PLATFORM_BUS
];
952 platform_bus_params
.platform_bus_num_irqs
= PLATFORM_BUS_NUM_IRQS
;
954 fdt_params
->system_params
= &platform_bus_params
;
955 fdt_params
->binfo
= &vbi
->bootinfo
;
956 fdt_params
->intc
= "/intc";
958 * register a machine init done notifier that creates the device tree
959 * nodes of the platform bus and its children dynamic sysbus devices
961 arm_register_platform_bus_fdt_creator(fdt_params
);
963 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
964 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
965 qdev_prop_set_uint32(dev
, "num_irqs",
966 platform_bus_params
.platform_bus_num_irqs
);
967 qdev_prop_set_uint32(dev
, "mmio_size",
968 platform_bus_params
.platform_bus_size
);
969 qdev_init_nofail(dev
);
970 s
= SYS_BUS_DEVICE(dev
);
972 for (i
= 0; i
< platform_bus_params
.platform_bus_num_irqs
; i
++) {
973 int irqn
= platform_bus_params
.platform_bus_first_irq
+ i
;
974 sysbus_connect_irq(s
, i
, pic
[irqn
]);
977 memory_region_add_subregion(sysmem
,
978 platform_bus_params
.platform_bus_base
,
979 sysbus_mmio_get_region(s
, 0));
982 static void create_secure_ram(VirtBoardInfo
*vbi
, MemoryRegion
*secure_sysmem
)
984 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
986 hwaddr base
= vbi
->memmap
[VIRT_SECURE_MEM
].base
;
987 hwaddr size
= vbi
->memmap
[VIRT_SECURE_MEM
].size
;
989 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
, &error_fatal
);
990 vmstate_register_ram_global(secram
);
991 memory_region_add_subregion(secure_sysmem
, base
, secram
);
993 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
994 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
995 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "memory");
996 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg", 2, base
, 2, size
);
997 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "status", "disabled");
998 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "secure-status", "okay");
1003 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1005 const VirtBoardInfo
*board
= (const VirtBoardInfo
*)binfo
;
1007 *fdt_size
= board
->fdt_size
;
1011 static void virt_build_smbios(VirtGuestInfo
*guest_info
)
1013 FWCfgState
*fw_cfg
= guest_info
->fw_cfg
;
1014 uint8_t *smbios_tables
, *smbios_anchor
;
1015 size_t smbios_tables_len
, smbios_anchor_len
;
1016 const char *product
= "QEMU Virtual Machine";
1022 if (kvm_enabled()) {
1023 product
= "KVM Virtual Machine";
1026 smbios_set_defaults("QEMU", product
,
1027 "1.0", false, true, SMBIOS_ENTRY_POINT_30
);
1029 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1030 &smbios_anchor
, &smbios_anchor_len
);
1032 if (smbios_anchor
) {
1033 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-tables",
1034 smbios_tables
, smbios_tables_len
);
1035 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-anchor",
1036 smbios_anchor
, smbios_anchor_len
);
1041 void virt_guest_info_machine_done(Notifier
*notifier
, void *data
)
1043 VirtGuestInfoState
*guest_info_state
= container_of(notifier
,
1044 VirtGuestInfoState
, machine_done
);
1045 virt_acpi_setup(&guest_info_state
->info
);
1046 virt_build_smbios(&guest_info_state
->info
);
1049 static void machvirt_init(MachineState
*machine
)
1051 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1052 qemu_irq pic
[NUM_IRQS
];
1053 MemoryRegion
*sysmem
= get_system_memory();
1054 MemoryRegion
*secure_sysmem
= NULL
;
1055 int gic_version
= vms
->gic_version
;
1056 int n
, virt_max_cpus
;
1057 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1058 const char *cpu_model
= machine
->cpu_model
;
1060 VirtGuestInfoState
*guest_info_state
= g_malloc0(sizeof *guest_info_state
);
1061 VirtGuestInfo
*guest_info
= &guest_info_state
->info
;
1065 cpu_model
= "cortex-a15";
1068 /* We can probe only here because during property set
1069 * KVM is not available yet
1072 gic_version
= kvm_arm_vgic_probe();
1074 error_report("Unable to determine GIC version supported by host");
1075 error_printf("KVM acceleration is probably not supported\n");
1080 /* Separate the actual CPU model name from any appended features */
1081 cpustr
= g_strsplit(cpu_model
, ",", 2);
1083 vbi
= find_machine_info(cpustr
[0]);
1086 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
1090 /* The maximum number of CPUs depends on the GIC version, or on how
1091 * many redistributors we can fit into the memory map.
1093 if (gic_version
== 3) {
1094 virt_max_cpus
= vbi
->memmap
[VIRT_GIC_REDIST
].size
/ 0x20000;
1096 virt_max_cpus
= GIC_NCPU
;
1099 if (max_cpus
> virt_max_cpus
) {
1100 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1101 "supported by machine 'mach-virt' (%d)",
1102 max_cpus
, virt_max_cpus
);
1106 vbi
->smp_cpus
= smp_cpus
;
1108 if (machine
->ram_size
> vbi
->memmap
[VIRT_MEM
].size
) {
1109 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB
);
1114 if (kvm_enabled()) {
1115 error_report("mach-virt: KVM does not support Security extensions");
1119 /* The Secure view of the world is the same as the NonSecure,
1120 * but with a few extra devices. Create it as a container region
1121 * containing the system memory at low priority; any secure-only
1122 * devices go in at higher priority and take precedence.
1124 secure_sysmem
= g_new(MemoryRegion
, 1);
1125 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1127 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1132 for (n
= 0; n
< smp_cpus
; n
++) {
1133 ObjectClass
*oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
1134 CPUClass
*cc
= CPU_CLASS(oc
);
1137 char *cpuopts
= g_strdup(cpustr
[1]);
1140 error_report("Unable to find CPU definition");
1143 cpuobj
= object_new(object_class_get_name(oc
));
1145 /* Handle any CPU options specified by the user */
1146 cc
->parse_features(CPU(cpuobj
), cpuopts
, &err
);
1149 error_report_err(err
);
1154 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1157 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_HVC
, "psci-conduit",
1160 /* Secondary CPUs start in PSCI powered-down state */
1162 object_property_set_bool(cpuobj
, true, "start-powered-off", NULL
);
1165 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1166 object_property_set_int(cpuobj
, vbi
->memmap
[VIRT_CPUPERIPHS
].base
,
1167 "reset-cbar", &error_abort
);
1170 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1173 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1174 "secure-memory", &error_abort
);
1177 object_property_set_bool(cpuobj
, true, "realized", NULL
);
1180 fdt_add_timer_nodes(vbi
, gic_version
);
1181 fdt_add_cpu_nodes(vbi
);
1182 fdt_add_psci_node(vbi
);
1184 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1186 memory_region_add_subregion(sysmem
, vbi
->memmap
[VIRT_MEM
].base
, ram
);
1190 create_gic(vbi
, pic
, gic_version
, vms
->secure
);
1192 create_uart(vbi
, pic
, VIRT_UART
, sysmem
);
1195 create_secure_ram(vbi
, secure_sysmem
);
1196 create_uart(vbi
, pic
, VIRT_SECURE_UART
, secure_sysmem
);
1199 create_rtc(vbi
, pic
);
1201 create_pcie(vbi
, pic
, vms
->highmem
);
1203 create_gpio(vbi
, pic
);
1205 /* Create mmio transports, so the user can create virtio backends
1206 * (which will be automatically plugged in to the transports). If
1207 * no backend is created the transport will just sit harmlessly idle.
1209 create_virtio_devices(vbi
, pic
);
1211 create_fw_cfg(vbi
, &address_space_memory
);
1212 rom_set_fw(fw_cfg_find());
1214 guest_info
->smp_cpus
= smp_cpus
;
1215 guest_info
->fw_cfg
= fw_cfg_find();
1216 guest_info
->memmap
= vbi
->memmap
;
1217 guest_info
->irqmap
= vbi
->irqmap
;
1218 guest_info
->use_highmem
= vms
->highmem
;
1219 guest_info
->gic_version
= gic_version
;
1220 guest_info_state
->machine_done
.notify
= virt_guest_info_machine_done
;
1221 qemu_add_machine_init_done_notifier(&guest_info_state
->machine_done
);
1223 vbi
->bootinfo
.ram_size
= machine
->ram_size
;
1224 vbi
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1225 vbi
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1226 vbi
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1227 vbi
->bootinfo
.nb_cpus
= smp_cpus
;
1228 vbi
->bootinfo
.board_id
= -1;
1229 vbi
->bootinfo
.loader_start
= vbi
->memmap
[VIRT_MEM
].base
;
1230 vbi
->bootinfo
.get_dtb
= machvirt_dtb
;
1231 vbi
->bootinfo
.firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1232 arm_load_kernel(ARM_CPU(first_cpu
), &vbi
->bootinfo
);
1235 * arm_load_kernel machine init done notifier registration must
1236 * happen before the platform_bus_create call. In this latter,
1237 * another notifier is registered which adds platform bus nodes.
1238 * Notifiers are executed in registration reverse order.
1240 create_platform_bus(vbi
, pic
);
1243 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1245 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1250 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1252 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1254 vms
->secure
= value
;
1257 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1259 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1261 return vms
->highmem
;
1264 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1266 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1268 vms
->highmem
= value
;
1271 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1273 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1274 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1276 return g_strdup(val
);
1279 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1281 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1283 if (!strcmp(value
, "3")) {
1284 vms
->gic_version
= 3;
1285 } else if (!strcmp(value
, "2")) {
1286 vms
->gic_version
= 2;
1287 } else if (!strcmp(value
, "host")) {
1288 vms
->gic_version
= 0; /* Will probe later */
1290 error_setg(errp
, "Invalid gic-version value");
1291 error_append_hint(errp
, "Valid values are 3, 2, host.\n");
1295 static void virt_instance_init(Object
*obj
)
1297 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1299 /* EL3 is disabled by default on virt: this makes us consistent
1300 * between KVM and TCG for this board, and it also allows us to
1301 * boot UEFI blobs which assume no TrustZone support.
1303 vms
->secure
= false;
1304 object_property_add_bool(obj
, "secure", virt_get_secure
,
1305 virt_set_secure
, NULL
);
1306 object_property_set_description(obj
, "secure",
1307 "Set on/off to enable/disable the ARM "
1308 "Security Extensions (TrustZone)",
1311 /* High memory is enabled by default */
1312 vms
->highmem
= true;
1313 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1314 virt_set_highmem
, NULL
);
1315 object_property_set_description(obj
, "highmem",
1316 "Set on/off to enable/disable using "
1317 "physical address space above 32 bits",
1319 /* Default GIC type is v2 */
1320 vms
->gic_version
= 2;
1321 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1322 virt_set_gic_version
, NULL
);
1323 object_property_set_description(obj
, "gic-version",
1325 "Valid values are 2, 3 and host", NULL
);
1328 static void virt_class_init(ObjectClass
*oc
, void *data
)
1330 MachineClass
*mc
= MACHINE_CLASS(oc
);
1332 mc
->desc
= "ARM Virtual Machine",
1333 mc
->init
= machvirt_init
;
1334 /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1335 * it later in machvirt_init, where we have more information about the
1336 * configuration of the particular instance.
1338 mc
->max_cpus
= MAX_CPUMASK_BITS
;
1339 mc
->has_dynamic_sysbus
= true;
1340 mc
->block_default_type
= IF_VIRTIO
;
1342 mc
->pci_allow_0_address
= true;
1345 static const TypeInfo machvirt_info
= {
1346 .name
= TYPE_VIRT_MACHINE
,
1347 .parent
= TYPE_MACHINE
,
1348 .instance_size
= sizeof(VirtMachineState
),
1349 .instance_init
= virt_instance_init
,
1350 .class_size
= sizeof(VirtMachineClass
),
1351 .class_init
= virt_class_init
,
1354 static void machvirt_machine_init(void)
1356 type_register_static(&machvirt_info
);
1359 machine_init(machvirt_machine_init
);