2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/runstate.h"
48 #include "sysemu/tpm.h"
49 #include "sysemu/tcg.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "sysemu/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/intc/arm_gicv3_its_common.h"
69 #include "hw/firmware/smbios.h"
70 #include "qapi/visitor.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "standard-headers/linux/input.h"
73 #include "hw/arm/smmuv3.h"
74 #include "hw/acpi/acpi.h"
75 #include "target/arm/internals.h"
76 #include "hw/mem/pc-dimm.h"
77 #include "hw/mem/nvdimm.h"
78 #include "hw/acpi/generic_event_device.h"
79 #include "hw/virtio/virtio-md-pci.h"
80 #include "hw/virtio/virtio-iommu.h"
81 #include "hw/char/pl011.h"
82 #include "qemu/guest-random.h"
84 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
85 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
88 MachineClass *mc = MACHINE_CLASS(oc); \
89 virt_machine_##major##_##minor##_options(mc); \
90 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
95 static const TypeInfo machvirt_##major##_##minor##_info = { \
96 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
97 .parent = TYPE_VIRT_MACHINE, \
98 .class_init = virt_##major##_##minor##_class_init, \
100 static void machvirt_machine_##major##_##minor##_init(void) \
102 type_register_static(&machvirt_##major##_##minor##_info); \
104 type_init(machvirt_machine_##major##_##minor##_init);
106 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
107 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
108 #define DEFINE_VIRT_MACHINE(major, minor) \
109 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
112 /* Number of external interrupt lines to configure the GIC with */
115 #define PLATFORM_BUS_NUM_IRQS 64
117 /* Legacy RAM limit in GB (< version 4.0) */
118 #define LEGACY_RAMLIMIT_GB 255
119 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
121 /* Addresses and sizes of our components.
122 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
123 * 128MB..256MB is used for miscellaneous device I/O.
124 * 256MB..1GB is reserved for possible future PCI support (ie where the
125 * PCI memory window will go if we add a PCI host controller).
126 * 1GB and up is RAM (which may happily spill over into the
127 * high memory region beyond 4GB).
128 * This represents a compromise between how much RAM can be given to
129 * a 32 bit VM and leaving space for expansion and in particular for PCI.
130 * Note that devices should generally be placed at multiples of 0x10000,
131 * to accommodate guests using 64K pages.
133 static const MemMapEntry base_memmap
[] = {
134 /* Space up to 0x8000000 is reserved for a boot ROM */
135 [VIRT_FLASH
] = { 0, 0x08000000 },
136 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
137 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
138 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
139 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
140 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
141 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
142 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
143 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
144 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
145 /* This redistributor space allows up to 2*64kB*123 CPUs */
146 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
147 [VIRT_UART
] = { 0x09000000, 0x00001000 },
148 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
149 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
150 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
151 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
152 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
153 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
154 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
155 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
156 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
157 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
158 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
159 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
160 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
161 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
162 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
163 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
164 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
165 /* Actual RAM size depends on initial RAM and device memory settings */
166 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
170 * Highmem IO Regions: This memory map is floating, located after the RAM.
171 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
172 * top of the RAM, so that its base get the same alignment as the size,
173 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
174 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
175 * Note the extended_memmap is sized so that it eventually also includes the
176 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
177 * index of base_memmap).
179 * The memory map for these Highmem IO Regions can be in legacy or compact
180 * layout, depending on 'compact-highmem' property. With legacy layout, the
181 * PA space for one specific region is always reserved, even if the region
182 * has been disabled or doesn't fit into the PA space. However, the PA space
183 * for the region won't be reserved in these circumstances with compact layout.
185 static MemMapEntry extended_memmap
[] = {
186 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
187 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
188 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
189 /* Second PCIe window */
190 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
193 static const int a15irqmap
[] = {
196 [VIRT_PCIE
] = 3, /* ... to 6 */
198 [VIRT_SECURE_UART
] = 8,
200 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
201 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
202 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
203 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
206 static const char *valid_cpus
[] = {
208 ARM_CPU_TYPE_NAME("cortex-a7"),
209 ARM_CPU_TYPE_NAME("cortex-a15"),
210 ARM_CPU_TYPE_NAME("cortex-a35"),
211 ARM_CPU_TYPE_NAME("cortex-a55"),
212 ARM_CPU_TYPE_NAME("cortex-a72"),
213 ARM_CPU_TYPE_NAME("cortex-a76"),
214 ARM_CPU_TYPE_NAME("cortex-a710"),
215 ARM_CPU_TYPE_NAME("a64fx"),
216 ARM_CPU_TYPE_NAME("neoverse-n1"),
217 ARM_CPU_TYPE_NAME("neoverse-v1"),
219 ARM_CPU_TYPE_NAME("cortex-a53"),
220 ARM_CPU_TYPE_NAME("cortex-a57"),
221 ARM_CPU_TYPE_NAME("host"),
222 ARM_CPU_TYPE_NAME("max"),
225 static bool cpu_type_valid(const char *cpu
)
229 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
230 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
237 static void create_randomness(MachineState
*ms
, const char *node
)
244 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
247 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
.kaslr
);
248 qemu_fdt_setprop(ms
->fdt
, node
, "rng-seed", seed
.rng
, sizeof(seed
.rng
));
251 static void create_fdt(VirtMachineState
*vms
)
253 MachineState
*ms
= MACHINE(vms
);
254 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
255 void *fdt
= create_device_tree(&vms
->fdt_size
);
258 error_report("create_device_tree() failed");
265 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
266 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
267 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
268 qemu_fdt_setprop_string(fdt
, "/", "model", "linux,dummy-virt");
270 /* /chosen must exist for load_dtb to fill in necessary properties later */
271 qemu_fdt_add_subnode(fdt
, "/chosen");
272 if (vms
->dtb_randomness
) {
273 create_randomness(ms
, "/chosen");
277 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
278 if (vms
->dtb_randomness
) {
279 create_randomness(ms
, "/secure-chosen");
283 /* Clock node, for the benefit of the UART. The kernel device tree
284 * binding documentation claims the PL011 node clock properties are
285 * optional but in practice if you omit them the kernel refuses to
286 * probe for the device.
288 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
289 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
290 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
291 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
292 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
293 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
295 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
297 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
298 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
299 uint32_t *matrix
= g_malloc0(size
);
302 for (i
= 0; i
< nb_numa_nodes
; i
++) {
303 for (j
= 0; j
< nb_numa_nodes
; j
++) {
304 idx
= (i
* nb_numa_nodes
+ j
) * 3;
305 matrix
[idx
+ 0] = cpu_to_be32(i
);
306 matrix
[idx
+ 1] = cpu_to_be32(j
);
308 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
312 qemu_fdt_add_subnode(fdt
, "/distance-map");
313 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
314 "numa-distance-map-v1");
315 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
321 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
323 /* On real hardware these interrupts are level-triggered.
324 * On KVM they were edge-triggered before host kernel version 4.4,
325 * and level-triggered afterwards.
326 * On emulated QEMU they are level-triggered.
328 * Getting the DTB info about them wrong is awkward for some
330 * pre-4.8 ignore the DT and leave the interrupt configured
331 * with whatever the GIC reset value (or the bootloader) left it at
332 * 4.8 before rc6 honour the incorrect data by programming it back
333 * into the GIC, causing problems
334 * 4.8rc6 and later ignore the DT and always write "level triggered"
337 * For backwards-compatibility, virt-2.8 and earlier will continue
338 * to say these are edge-triggered, but later machines will report
339 * the correct information.
342 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
343 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
344 MachineState
*ms
= MACHINE(vms
);
346 if (vmc
->claim_edge_triggered_timers
) {
347 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
350 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
351 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
352 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
353 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
356 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
358 armcpu
= ARM_CPU(qemu_get_cpu(0));
359 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
360 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
361 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
362 compat
, sizeof(compat
));
364 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
367 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
368 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
369 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
370 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
371 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
372 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
375 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
379 const MachineState
*ms
= MACHINE(vms
);
380 const VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
381 int smp_cpus
= ms
->smp
.cpus
;
384 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
385 * On ARM v8 64-bit systems value should be set to 2,
386 * that corresponds to the MPIDR_EL1 register size.
387 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
388 * in the system, #address-cells can be set to 1, since
389 * MPIDR_EL1[63:32] bits are not used for CPUs
392 * Here we actually don't know whether our system is 32- or 64-bit one.
393 * The simplest way to go is to examine affinity IDs of all our CPUs. If
394 * at least one of them has Aff3 populated, we set #address-cells to 2.
396 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
397 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
399 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
405 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
406 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
407 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
409 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
410 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
411 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
412 CPUState
*cs
= CPU(armcpu
);
414 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
415 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
416 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
417 armcpu
->dtb_compatible
);
419 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
420 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
421 "enable-method", "psci");
424 if (addr_cells
== 2) {
425 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
426 armcpu
->mp_affinity
);
428 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
429 armcpu
->mp_affinity
);
432 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
433 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
434 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
437 if (!vmc
->no_cpu_topology
) {
438 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle",
439 qemu_fdt_alloc_phandle(ms
->fdt
));
445 if (!vmc
->no_cpu_topology
) {
447 * Add vCPU topology description through fdt node cpu-map.
449 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
450 * In a SMP system, the hierarchy of CPUs can be defined through
451 * four entities that are used to describe the layout of CPUs in
452 * the system: socket/cluster/core/thread.
454 * A socket node represents the boundary of system physical package
455 * and its child nodes must be one or more cluster nodes. A system
456 * can contain several layers of clustering within a single physical
457 * package and cluster nodes can be contained in parent cluster nodes.
459 * Note: currently we only support one layer of clustering within
460 * each physical package.
462 qemu_fdt_add_subnode(ms
->fdt
, "/cpus/cpu-map");
464 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
465 char *cpu_path
= g_strdup_printf("/cpus/cpu@%d", cpu
);
468 if (ms
->smp
.threads
> 1) {
469 map_path
= g_strdup_printf(
470 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
471 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
),
472 (cpu
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
,
473 (cpu
/ ms
->smp
.threads
) % ms
->smp
.cores
,
474 cpu
% ms
->smp
.threads
);
476 map_path
= g_strdup_printf(
477 "/cpus/cpu-map/socket%d/cluster%d/core%d",
478 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
),
479 (cpu
/ ms
->smp
.cores
) % ms
->smp
.clusters
,
480 cpu
% ms
->smp
.cores
);
482 qemu_fdt_add_path(ms
->fdt
, map_path
);
483 qemu_fdt_setprop_phandle(ms
->fdt
, map_path
, "cpu", cpu_path
);
491 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
494 MachineState
*ms
= MACHINE(vms
);
496 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
497 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
498 vms
->memmap
[VIRT_GIC_ITS
].base
);
499 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
500 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
502 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
503 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#msi-cells", 1);
504 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
505 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
506 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
507 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
511 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
513 MachineState
*ms
= MACHINE(vms
);
516 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
517 vms
->memmap
[VIRT_GIC_V2M
].base
);
518 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
519 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
520 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
521 "arm,gic-v2m-frame");
522 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
523 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
524 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
525 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
526 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
530 static void fdt_add_gic_node(VirtMachineState
*vms
)
532 MachineState
*ms
= MACHINE(vms
);
535 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
536 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
538 nodename
= g_strdup_printf("/intc@%" PRIx64
,
539 vms
->memmap
[VIRT_GIC_DIST
].base
);
540 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
541 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
542 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
543 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
544 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
545 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
546 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
547 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
549 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
552 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
553 "#redistributor-regions", nb_redist_regions
);
555 if (nb_redist_regions
== 1) {
556 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
557 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
558 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
559 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
560 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
562 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
563 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
564 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
565 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
566 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
567 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
568 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
572 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
573 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
574 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
577 /* 'cortex-a15-gic' means 'GIC v2' */
578 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
579 "arm,cortex-a15-gic");
581 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
582 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
583 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
584 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
585 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
587 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
588 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
589 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
590 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
591 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
592 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
593 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
594 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
595 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
596 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
597 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
598 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
602 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
606 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
608 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
609 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
610 MachineState
*ms
= MACHINE(vms
);
612 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
613 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
617 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
618 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
619 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
620 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
623 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
624 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
625 const char compat
[] = "arm,armv8-pmuv3";
626 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
627 compat
, sizeof(compat
));
628 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
629 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
633 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
636 MachineState
*ms
= MACHINE(vms
);
637 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
638 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
641 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
644 if (ms
->nvdimms_state
->is_enabled
) {
645 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
648 dev
= qdev_new(TYPE_ACPI_GED
);
649 qdev_prop_set_uint32(dev
, "ged-event", event
);
651 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
652 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
653 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
655 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
660 static void create_its(VirtMachineState
*vms
)
662 const char *itsclass
= its_class_name();
665 if (!strcmp(itsclass
, "arm-gicv3-its")) {
672 /* Do nothing if not supported */
676 dev
= qdev_new(itsclass
);
678 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
680 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
681 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
683 fdt_add_its_gic_node(vms
);
684 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
687 static void create_v2m(VirtMachineState
*vms
)
690 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
693 dev
= qdev_new("arm-gicv2m");
694 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
695 qdev_prop_set_uint32(dev
, "base-spi", irq
);
696 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
697 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
699 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
700 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
701 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
704 fdt_add_v2m_gic_node(vms
);
705 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
708 static void create_gic(VirtMachineState
*vms
, MemoryRegion
*mem
)
710 MachineState
*ms
= MACHINE(vms
);
711 /* We create a standalone GIC */
712 SysBusDevice
*gicbusdev
;
715 unsigned int smp_cpus
= ms
->smp
.cpus
;
716 uint32_t nb_redist_regions
= 0;
719 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
720 gictype
= gic_class_name();
722 gictype
= gicv3_class_name();
725 switch (vms
->gic_version
) {
726 case VIRT_GIC_VERSION_2
:
729 case VIRT_GIC_VERSION_3
:
732 case VIRT_GIC_VERSION_4
:
736 g_assert_not_reached();
738 vms
->gic
= qdev_new(gictype
);
739 qdev_prop_set_uint32(vms
->gic
, "revision", revision
);
740 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
741 /* Note that the num-irq property counts both internal and external
742 * interrupts; there are always 32 of the former (mandated by GIC spec).
744 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
745 if (!kvm_irqchip_in_kernel()) {
746 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
749 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
750 uint32_t redist0_capacity
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
751 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
753 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
755 qdev_prop_set_uint32(vms
->gic
, "len-redist-region-count",
757 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[0]", redist0_count
);
759 if (!kvm_irqchip_in_kernel()) {
761 object_property_set_link(OBJECT(vms
->gic
), "sysmem",
762 OBJECT(mem
), &error_fatal
);
763 qdev_prop_set_bit(vms
->gic
, "has-lpi", true);
767 if (nb_redist_regions
== 2) {
768 uint32_t redist1_capacity
=
769 virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
771 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[1]",
772 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
775 if (!kvm_irqchip_in_kernel()) {
776 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
780 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
781 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
782 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
783 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
784 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
785 if (nb_redist_regions
== 2) {
786 sysbus_mmio_map(gicbusdev
, 2,
787 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
790 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
792 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
793 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
797 /* Wire the outputs from each CPU's generic timer and the GICv3
798 * maintenance interrupt signal to the appropriate GIC PPI inputs,
799 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
801 for (i
= 0; i
< smp_cpus
; i
++) {
802 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
803 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
804 /* Mapping from the output timer irq lines from the CPU to the
805 * GIC PPI inputs we use for the virt board.
807 const int timer_irq
[] = {
808 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
809 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
810 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
811 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
814 for (unsigned irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
815 qdev_connect_gpio_out(cpudev
, irq
,
816 qdev_get_gpio_in(vms
->gic
,
817 ppibase
+ timer_irq
[irq
]));
820 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
821 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
822 ppibase
+ ARCH_GIC_MAINT_IRQ
);
823 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
825 } else if (vms
->virt
) {
826 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
827 ppibase
+ ARCH_GIC_MAINT_IRQ
);
828 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
831 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
832 qdev_get_gpio_in(vms
->gic
, ppibase
835 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
836 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
837 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
838 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
839 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
840 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
841 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
844 fdt_add_gic_node(vms
);
846 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& vms
->its
) {
848 } else if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
853 static void create_uart(const VirtMachineState
*vms
, int uart
,
854 MemoryRegion
*mem
, Chardev
*chr
)
857 hwaddr base
= vms
->memmap
[uart
].base
;
858 hwaddr size
= vms
->memmap
[uart
].size
;
859 int irq
= vms
->irqmap
[uart
];
860 const char compat
[] = "arm,pl011\0arm,primecell";
861 const char clocknames
[] = "uartclk\0apb_pclk";
862 DeviceState
*dev
= qdev_new(TYPE_PL011
);
863 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
864 MachineState
*ms
= MACHINE(vms
);
866 qdev_prop_set_chr(dev
, "chardev", chr
);
867 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
868 memory_region_add_subregion(mem
, base
,
869 sysbus_mmio_get_region(s
, 0));
870 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
872 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
873 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
874 /* Note that we can't use setprop_string because of the embedded NUL */
875 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
876 compat
, sizeof(compat
));
877 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
879 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
880 GIC_FDT_IRQ_TYPE_SPI
, irq
,
881 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
882 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
883 vms
->clock_phandle
, vms
->clock_phandle
);
884 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
885 clocknames
, sizeof(clocknames
));
887 if (uart
== VIRT_UART
) {
888 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
890 /* Mark as not usable by the normal world */
891 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
892 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
894 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
901 static void create_rtc(const VirtMachineState
*vms
)
904 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
905 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
906 int irq
= vms
->irqmap
[VIRT_RTC
];
907 const char compat
[] = "arm,pl031\0arm,primecell";
908 MachineState
*ms
= MACHINE(vms
);
910 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
912 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
913 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
914 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
915 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
917 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
918 GIC_FDT_IRQ_TYPE_SPI
, irq
,
919 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
920 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
921 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
925 static DeviceState
*gpio_key_dev
;
926 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
928 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
931 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
933 /* use gpio Pin 3 for power button event */
934 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
938 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
941 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
942 qdev_get_gpio_in(pl061_dev
, 3));
944 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
945 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
947 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
948 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
949 "label", "GPIO Key Poweroff");
950 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
952 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
953 "gpios", phandle
, 3, 0);
956 #define SECURE_GPIO_POWEROFF 0
957 #define SECURE_GPIO_RESET 1
959 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
962 DeviceState
*gpio_pwr_dev
;
965 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
967 /* connect secure pl061 to gpio-pwr */
968 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
969 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
970 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
971 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
973 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
974 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
976 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
977 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
978 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
979 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
982 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
983 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
985 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
986 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
987 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
988 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
992 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
996 DeviceState
*pl061_dev
;
997 hwaddr base
= vms
->memmap
[gpio
].base
;
998 hwaddr size
= vms
->memmap
[gpio
].size
;
999 int irq
= vms
->irqmap
[gpio
];
1000 const char compat
[] = "arm,pl061\0arm,primecell";
1002 MachineState
*ms
= MACHINE(vms
);
1004 pl061_dev
= qdev_new("pl061");
1005 /* Pull lines down to 0 if not driven by the PL061 */
1006 qdev_prop_set_uint32(pl061_dev
, "pullups", 0);
1007 qdev_prop_set_uint32(pl061_dev
, "pulldowns", 0xff);
1008 s
= SYS_BUS_DEVICE(pl061_dev
);
1009 sysbus_realize_and_unref(s
, &error_fatal
);
1010 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
1011 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
1013 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1014 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
1015 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1016 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1018 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
1019 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
1020 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
1021 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1022 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1023 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
1024 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
1025 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
1026 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
1028 if (gpio
!= VIRT_GPIO
) {
1029 /* Mark as not usable by the normal world */
1030 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1031 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1035 /* Child gpio devices */
1036 if (gpio
== VIRT_GPIO
) {
1037 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
1039 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
1043 static void create_virtio_devices(const VirtMachineState
*vms
)
1046 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
1047 MachineState
*ms
= MACHINE(vms
);
1049 /* We create the transports in forwards order. Since qbus_realize()
1050 * prepends (not appends) new child buses, the incrementing loop below will
1051 * create a list of virtio-mmio buses with decreasing base addresses.
1053 * When a -device option is processed from the command line,
1054 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1055 * order. The upshot is that -device options in increasing command line
1056 * order are mapped to virtio-mmio buses with decreasing base addresses.
1058 * When this code was originally written, that arrangement ensured that the
1059 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1060 * the first -device on the command line. (The end-to-end order is a
1061 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1062 * guest kernel's name-to-address assignment strategy.)
1064 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1065 * the message, if not necessarily the code, of commit 70161ff336.
1066 * Therefore the loop now establishes the inverse of the original intent.
1068 * Unfortunately, we can't counteract the kernel change by reversing the
1069 * loop; it would break existing command lines.
1071 * In any case, the kernel makes no guarantee about the stability of
1072 * enumeration order of virtio devices (as demonstrated by it changing
1073 * between kernel versions). For reliable and stable identification
1074 * of disks users must use UUIDs or similar mechanisms.
1076 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
1077 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1078 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1080 sysbus_create_simple("virtio-mmio", base
,
1081 qdev_get_gpio_in(vms
->gic
, irq
));
1084 /* We add dtb nodes in reverse order so that they appear in the finished
1085 * device tree lowest address first.
1087 * Note that this mapping is independent of the loop above. The previous
1088 * loop influences virtio device to virtio transport assignment, whereas
1089 * this loop controls how virtio transports are laid out in the dtb.
1091 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
1093 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1094 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1096 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
1097 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1098 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1099 "compatible", "virtio,mmio");
1100 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1102 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1103 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1104 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1105 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1110 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1112 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1114 const char *alias_prop_name
)
1117 * Create a single flash device. We use the same parameters as
1118 * the flash devices on the Versatile Express board.
1120 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1122 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1123 qdev_prop_set_uint8(dev
, "width", 4);
1124 qdev_prop_set_uint8(dev
, "device-width", 2);
1125 qdev_prop_set_bit(dev
, "big-endian", false);
1126 qdev_prop_set_uint16(dev
, "id0", 0x89);
1127 qdev_prop_set_uint16(dev
, "id1", 0x18);
1128 qdev_prop_set_uint16(dev
, "id2", 0x00);
1129 qdev_prop_set_uint16(dev
, "id3", 0x00);
1130 qdev_prop_set_string(dev
, "name", name
);
1131 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1132 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1133 OBJECT(dev
), "drive");
1134 return PFLASH_CFI01(dev
);
1137 static void virt_flash_create(VirtMachineState
*vms
)
1139 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1140 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1143 static void virt_flash_map1(PFlashCFI01
*flash
,
1144 hwaddr base
, hwaddr size
,
1145 MemoryRegion
*sysmem
)
1147 DeviceState
*dev
= DEVICE(flash
);
1149 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1150 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1151 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1152 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1154 memory_region_add_subregion(sysmem
, base
,
1155 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1159 static void virt_flash_map(VirtMachineState
*vms
,
1160 MemoryRegion
*sysmem
,
1161 MemoryRegion
*secure_sysmem
)
1164 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1165 * sysmem is the system memory space. secure_sysmem is the secure view
1166 * of the system, and the first flash device should be made visible only
1167 * there. The second flash device is visible to both secure and nonsecure.
1168 * If sysmem == secure_sysmem this means there is no separate Secure
1169 * address space and both flash devices are generally visible.
1171 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1172 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1174 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1176 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1180 static void virt_flash_fdt(VirtMachineState
*vms
,
1181 MemoryRegion
*sysmem
,
1182 MemoryRegion
*secure_sysmem
)
1184 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1185 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1186 MachineState
*ms
= MACHINE(vms
);
1189 if (sysmem
== secure_sysmem
) {
1190 /* Report both flash devices as a single node in the DT */
1191 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1192 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1193 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1194 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1195 2, flashbase
, 2, flashsize
,
1196 2, flashbase
+ flashsize
, 2, flashsize
);
1197 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1201 * Report the devices as separate nodes so we can mark one as
1202 * only visible to the secure world.
1204 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1205 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1206 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1207 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1208 2, flashbase
, 2, flashsize
);
1209 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1210 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1211 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1214 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
+ flashsize
);
1215 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1216 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1217 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1218 2, flashbase
+ flashsize
, 2, flashsize
);
1219 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1224 static bool virt_firmware_init(VirtMachineState
*vms
,
1225 MemoryRegion
*sysmem
,
1226 MemoryRegion
*secure_sysmem
)
1229 const char *bios_name
;
1230 BlockBackend
*pflash_blk0
;
1232 /* Map legacy -drive if=pflash to machine properties */
1233 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1234 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1235 drive_get(IF_PFLASH
, 0, i
));
1238 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1240 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1242 bios_name
= MACHINE(vms
)->firmware
;
1249 error_report("The contents of the first flash device may be "
1250 "specified with -bios or with -drive if=pflash... "
1251 "but you cannot use both options at once");
1255 /* Fall back to -bios */
1257 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1259 error_report("Could not find ROM image '%s'", bios_name
);
1262 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1263 image_size
= load_image_mr(fname
, mr
);
1265 if (image_size
< 0) {
1266 error_report("Could not load ROM image '%s'", bios_name
);
1271 return pflash_blk0
|| bios_name
;
1274 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1276 MachineState
*ms
= MACHINE(vms
);
1277 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1278 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1282 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1283 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1285 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1286 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1287 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1288 "compatible", "qemu,fw-cfg-mmio");
1289 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1291 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1296 static void create_pcie_irq_map(const MachineState
*ms
,
1297 uint32_t gic_phandle
,
1298 int first_irq
, const char *nodename
)
1301 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1302 uint32_t *irq_map
= full_irq_map
;
1304 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1305 for (pin
= 0; pin
< 4; pin
++) {
1306 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1307 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1308 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1312 devfn
<< 8, 0, 0, /* devfn */
1313 pin
+ 1, /* PCI pin */
1314 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1316 /* Convert map to big endian */
1317 for (i
= 0; i
< 10; i
++) {
1318 irq_map
[i
] = cpu_to_be32(map
[i
]);
1324 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1325 full_irq_map
, sizeof(full_irq_map
));
1327 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1328 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1333 static void create_smmu(const VirtMachineState
*vms
,
1337 const char compat
[] = "arm,smmu-v3";
1338 int irq
= vms
->irqmap
[VIRT_SMMU
];
1340 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1341 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1342 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1344 MachineState
*ms
= MACHINE(vms
);
1346 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1350 dev
= qdev_new(TYPE_ARM_SMMUV3
);
1352 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1354 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1355 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1356 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1357 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1358 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1361 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1362 qemu_fdt_add_subnode(ms
->fdt
, node
);
1363 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1364 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1366 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1367 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1368 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1369 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1370 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1372 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1375 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1377 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1379 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1383 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1385 const char compat
[] = "virtio,pci-iommu\0pci1af4,1057";
1386 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1387 MachineState
*ms
= MACHINE(vms
);
1390 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1392 node
= g_strdup_printf("%s/virtio_iommu@%x,%x", vms
->pciehb_nodename
,
1393 PCI_SLOT(bdf
), PCI_FUNC(bdf
));
1394 qemu_fdt_add_subnode(ms
->fdt
, node
);
1395 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1396 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1397 1, bdf
<< 8, 1, 0, 1, 0,
1400 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1401 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1404 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1405 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1406 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1409 static void create_pcie(VirtMachineState
*vms
)
1411 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1412 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1413 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1414 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1415 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1416 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1417 hwaddr base_ecam
, size_ecam
;
1418 hwaddr base
= base_mmio
;
1420 int irq
= vms
->irqmap
[VIRT_PCIE
];
1421 MemoryRegion
*mmio_alias
;
1422 MemoryRegion
*mmio_reg
;
1423 MemoryRegion
*ecam_alias
;
1424 MemoryRegion
*ecam_reg
;
1429 MachineState
*ms
= MACHINE(vms
);
1430 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
1432 dev
= qdev_new(TYPE_GPEX_HOST
);
1433 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1435 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1436 base_ecam
= vms
->memmap
[ecam_id
].base
;
1437 size_ecam
= vms
->memmap
[ecam_id
].size
;
1438 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1439 /* Map only the first size_ecam bytes of ECAM space */
1440 ecam_alias
= g_new0(MemoryRegion
, 1);
1441 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1442 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1443 ecam_reg
, 0, size_ecam
);
1444 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1446 /* Map the MMIO window into system address space so as to expose
1447 * the section of PCI MMIO space which starts at the same base address
1448 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1451 mmio_alias
= g_new0(MemoryRegion
, 1);
1452 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1453 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1454 mmio_reg
, base_mmio
, size_mmio
);
1455 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1457 if (vms
->highmem_mmio
) {
1458 /* Map high MMIO space */
1459 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1461 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1462 mmio_reg
, base_mmio_high
, size_mmio_high
);
1463 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1467 /* Map IO port space */
1468 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1470 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1471 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1472 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1473 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1476 pci
= PCI_HOST_BRIDGE(dev
);
1477 pci
->bypass_iommu
= vms
->default_bus_bypass_iommu
;
1478 vms
->bus
= pci
->bus
;
1480 for (i
= 0; i
< nb_nics
; i
++) {
1481 pci_nic_init_nofail(&nd_table
[i
], pci
->bus
, mc
->default_nic
, NULL
);
1485 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1486 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1487 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1488 "compatible", "pci-host-ecam-generic");
1489 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1490 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1491 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1492 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1493 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1495 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1497 if (vms
->msi_phandle
) {
1498 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-map",
1499 0, vms
->msi_phandle
, 0, 0x10000);
1502 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1503 2, base_ecam
, 2, size_ecam
);
1505 if (vms
->highmem_mmio
) {
1506 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1507 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1508 2, base_pio
, 2, size_pio
,
1509 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1510 2, base_mmio
, 2, size_mmio
,
1511 1, FDT_PCI_RANGE_MMIO_64BIT
,
1513 2, base_mmio_high
, 2, size_mmio_high
);
1515 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1516 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1517 2, base_pio
, 2, size_pio
,
1518 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1519 2, base_mmio
, 2, size_mmio
);
1522 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1523 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1526 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1528 switch (vms
->iommu
) {
1529 case VIRT_IOMMU_SMMUV3
:
1530 create_smmu(vms
, vms
->bus
);
1531 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1532 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1535 g_assert_not_reached();
1540 static void create_platform_bus(VirtMachineState
*vms
)
1545 MemoryRegion
*sysmem
= get_system_memory();
1547 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1548 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1549 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1550 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1551 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1552 vms
->platform_bus_dev
= dev
;
1554 s
= SYS_BUS_DEVICE(dev
);
1555 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1556 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1557 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1560 memory_region_add_subregion(sysmem
,
1561 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1562 sysbus_mmio_get_region(s
, 0));
1565 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1566 hwaddr base
, hwaddr size
,
1569 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1571 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1572 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1575 static void create_secure_ram(VirtMachineState
*vms
,
1576 MemoryRegion
*secure_sysmem
,
1577 MemoryRegion
*secure_tag_sysmem
)
1579 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1581 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1582 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1583 MachineState
*ms
= MACHINE(vms
);
1585 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1587 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1589 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1590 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1591 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1592 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1593 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1594 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1596 if (secure_tag_sysmem
) {
1597 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1603 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1605 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1607 MachineState
*ms
= MACHINE(board
);
1610 *fdt_size
= board
->fdt_size
;
1614 static void virt_build_smbios(VirtMachineState
*vms
)
1616 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1617 MachineState
*ms
= MACHINE(vms
);
1618 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1619 uint8_t *smbios_tables
, *smbios_anchor
;
1620 size_t smbios_tables_len
, smbios_anchor_len
;
1621 struct smbios_phys_mem_area mem_array
;
1622 const char *product
= "QEMU Virtual Machine";
1624 if (kvm_enabled()) {
1625 product
= "KVM Virtual Machine";
1628 smbios_set_defaults("QEMU", product
,
1629 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1630 true, SMBIOS_ENTRY_POINT_TYPE_64
);
1632 /* build the array of physical mem area from base_memmap */
1633 mem_array
.address
= vms
->memmap
[VIRT_MEM
].base
;
1634 mem_array
.length
= ms
->ram_size
;
1636 smbios_get_tables(ms
, &mem_array
, 1,
1637 &smbios_tables
, &smbios_tables_len
,
1638 &smbios_anchor
, &smbios_anchor_len
,
1641 if (smbios_anchor
) {
1642 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1643 smbios_tables
, smbios_tables_len
);
1644 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1645 smbios_anchor
, smbios_anchor_len
);
1650 void virt_machine_done(Notifier
*notifier
, void *data
)
1652 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1654 MachineState
*ms
= MACHINE(vms
);
1655 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1656 struct arm_boot_info
*info
= &vms
->bootinfo
;
1657 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1660 * If the user provided a dtb, we assume the dynamic sysbus nodes
1661 * already are integrated there. This corresponds to a use case where
1662 * the dynamic sysbus nodes are complex and their generation is not yet
1663 * supported. In that case the user can take charge of the guest dt
1664 * while qemu takes charge of the qom stuff.
1666 if (info
->dtb_filename
== NULL
) {
1667 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1668 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1669 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1670 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1672 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1676 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1678 virt_acpi_setup(vms
);
1679 virt_build_smbios(vms
);
1682 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1684 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1685 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1687 if (!vmc
->disallow_affinity_adjustment
) {
1688 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1689 * GIC's target-list limitations. 32-bit KVM hosts currently
1690 * always create clusters of 4 CPUs, but that is expected to
1691 * change when they gain support for gicv3. When KVM is enabled
1692 * it will override the changes we make here, therefore our
1693 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1694 * and to improve SGI efficiency.
1696 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
1697 clustersz
= GIC_TARGETLIST_BITS
;
1699 clustersz
= GICV3_TARGETLIST_BITS
;
1702 return arm_cpu_mp_affinity(idx
, clustersz
);
1705 static inline bool *virt_get_high_memmap_enabled(VirtMachineState
*vms
,
1708 bool *enabled_array
[] = {
1709 &vms
->highmem_redists
,
1714 assert(ARRAY_SIZE(extended_memmap
) - VIRT_LOWMEMMAP_LAST
==
1715 ARRAY_SIZE(enabled_array
));
1716 assert(index
- VIRT_LOWMEMMAP_LAST
< ARRAY_SIZE(enabled_array
));
1718 return enabled_array
[index
- VIRT_LOWMEMMAP_LAST
];
1721 static void virt_set_high_memmap(VirtMachineState
*vms
,
1722 hwaddr base
, int pa_bits
)
1724 hwaddr region_base
, region_size
;
1725 bool *region_enabled
, fits
;
1728 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1729 region_enabled
= virt_get_high_memmap_enabled(vms
, i
);
1730 region_base
= ROUND_UP(base
, extended_memmap
[i
].size
);
1731 region_size
= extended_memmap
[i
].size
;
1733 vms
->memmap
[i
].base
= region_base
;
1734 vms
->memmap
[i
].size
= region_size
;
1737 * Check each device to see if it fits in the PA space,
1738 * moving highest_gpa as we go. For compatibility, move
1739 * highest_gpa for disabled fitting devices as well, if
1740 * the compact layout has been disabled.
1742 * For each device that doesn't fit, disable it.
1744 fits
= (region_base
+ region_size
) <= BIT_ULL(pa_bits
);
1745 *region_enabled
&= fits
;
1746 if (vms
->highmem_compact
&& !*region_enabled
) {
1750 base
= region_base
+ region_size
;
1752 vms
->highest_gpa
= base
- 1;
1757 static void virt_set_memmap(VirtMachineState
*vms
, int pa_bits
)
1759 MachineState
*ms
= MACHINE(vms
);
1760 hwaddr base
, device_memory_base
, device_memory_size
, memtop
;
1763 vms
->memmap
= extended_memmap
;
1765 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1766 vms
->memmap
[i
] = base_memmap
[i
];
1769 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1770 error_report("unsupported number of memory slots: %"PRIu64
,
1776 * !highmem is exactly the same as limiting the PA space to 32bit,
1777 * irrespective of the underlying capabilities of the HW.
1779 if (!vms
->highmem
) {
1784 * We compute the base of the high IO region depending on the
1785 * amount of initial and device memory. The device memory start/size
1786 * is aligned on 1GiB. We never put the high IO region below 256GiB
1787 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1788 * The device region size assumes 1GiB page max alignment per slot.
1790 device_memory_base
=
1791 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1792 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1794 /* Base address of the high IO region */
1795 memtop
= base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1796 if (memtop
> BIT_ULL(pa_bits
)) {
1797 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
1798 pa_bits
, memtop
- BIT_ULL(pa_bits
));
1801 if (base
< device_memory_base
) {
1802 error_report("maxmem/slots too huge");
1805 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1806 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1809 /* We know for sure that at least the memory fits in the PA space */
1810 vms
->highest_gpa
= memtop
- 1;
1812 virt_set_high_memmap(vms
, base
, pa_bits
);
1814 if (device_memory_size
> 0) {
1815 machine_memory_devices_init(ms
, device_memory_base
, device_memory_size
);
1819 static VirtGICType
finalize_gic_version_do(const char *accel_name
,
1820 VirtGICType gic_version
,
1822 unsigned int max_cpus
)
1824 /* Convert host/max/nosel to GIC version number */
1825 switch (gic_version
) {
1826 case VIRT_GIC_VERSION_HOST
:
1827 if (!kvm_enabled()) {
1828 error_report("gic-version=host requires KVM");
1832 /* For KVM, gic-version=host means gic-version=max */
1833 return finalize_gic_version_do(accel_name
, VIRT_GIC_VERSION_MAX
,
1834 gics_supported
, max_cpus
);
1835 case VIRT_GIC_VERSION_MAX
:
1836 if (gics_supported
& VIRT_GIC_VERSION_4_MASK
) {
1837 gic_version
= VIRT_GIC_VERSION_4
;
1838 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1839 gic_version
= VIRT_GIC_VERSION_3
;
1841 gic_version
= VIRT_GIC_VERSION_2
;
1844 case VIRT_GIC_VERSION_NOSEL
:
1845 if ((gics_supported
& VIRT_GIC_VERSION_2_MASK
) &&
1846 max_cpus
<= GIC_NCPU
) {
1847 gic_version
= VIRT_GIC_VERSION_2
;
1848 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1850 * in case the host does not support v2 emulation or
1851 * the end-user requested more than 8 VCPUs we now default
1852 * to v3. In any case defaulting to v2 would be broken.
1854 gic_version
= VIRT_GIC_VERSION_3
;
1855 } else if (max_cpus
> GIC_NCPU
) {
1856 error_report("%s only supports GICv2 emulation but more than 8 "
1857 "vcpus are requested", accel_name
);
1861 case VIRT_GIC_VERSION_2
:
1862 case VIRT_GIC_VERSION_3
:
1863 case VIRT_GIC_VERSION_4
:
1867 /* Check chosen version is effectively supported */
1868 switch (gic_version
) {
1869 case VIRT_GIC_VERSION_2
:
1870 if (!(gics_supported
& VIRT_GIC_VERSION_2_MASK
)) {
1871 error_report("%s does not support GICv2 emulation", accel_name
);
1875 case VIRT_GIC_VERSION_3
:
1876 if (!(gics_supported
& VIRT_GIC_VERSION_3_MASK
)) {
1877 error_report("%s does not support GICv3 emulation", accel_name
);
1881 case VIRT_GIC_VERSION_4
:
1882 if (!(gics_supported
& VIRT_GIC_VERSION_4_MASK
)) {
1883 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1889 error_report("logic error in finalize_gic_version");
1898 * finalize_gic_version - Determines the final gic_version
1899 * according to the gic-version property
1901 * Default GIC type is v2
1903 static void finalize_gic_version(VirtMachineState
*vms
)
1905 const char *accel_name
= current_accel_name();
1906 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1907 int gics_supported
= 0;
1909 /* Determine which GIC versions the current environment supports */
1910 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1911 int probe_bitmap
= kvm_arm_vgic_probe();
1913 if (!probe_bitmap
) {
1914 error_report("Unable to determine GIC version supported by host");
1918 if (probe_bitmap
& KVM_ARM_VGIC_V2
) {
1919 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1921 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1922 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1924 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
1925 /* KVM w/o kernel irqchip can only deal with GICv2 */
1926 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1927 accel_name
= "KVM with kernel-irqchip=off";
1928 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
1929 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1930 if (module_object_class_by_name("arm-gicv3")) {
1931 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1933 /* GICv4 only makes sense if CPU has EL2 */
1934 gics_supported
|= VIRT_GIC_VERSION_4_MASK
;
1938 error_report("Unsupported accelerator, can not determine GIC support");
1943 * Then convert helpers like host/max to concrete GIC versions and ensure
1944 * the desired version is supported
1946 vms
->gic_version
= finalize_gic_version_do(accel_name
, vms
->gic_version
,
1947 gics_supported
, max_cpus
);
1951 * virt_cpu_post_init() must be called after the CPUs have
1952 * been realized and the GIC has been created.
1954 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
1956 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1957 bool aarch64
, pmu
, steal_time
;
1960 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
1961 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
1962 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
1963 "kvm-steal-time", NULL
);
1965 if (kvm_enabled()) {
1966 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
1967 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
1970 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
1971 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
1973 /* The memory region size must be a multiple of host page size. */
1974 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
1976 if (pvtime_size
> pvtime_reg_size
) {
1977 error_report("pvtime requires a %" HWADDR_PRId
1978 " byte memory region for %d CPUs,"
1979 " but only %" HWADDR_PRId
" has been reserved",
1980 pvtime_size
, max_cpus
, pvtime_reg_size
);
1984 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
1985 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
1990 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
1991 if (kvm_irqchip_in_kernel()) {
1992 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
1994 kvm_arm_pmu_init(cpu
);
1997 kvm_arm_pvtime_init(cpu
, pvtime_reg_base
+
1998 cpu
->cpu_index
* PVTIME_SIZE_PER_CPU
);
2002 if (aarch64
&& vms
->highmem
) {
2003 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2004 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
2006 if (pamax
< requested_pa_size
) {
2007 error_report("VCPU supports less PA bits (%d) than "
2008 "requested by the memory map (%d)",
2009 pamax
, requested_pa_size
);
2016 static void machvirt_init(MachineState
*machine
)
2018 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
2019 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
2020 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2021 const CPUArchIdList
*possible_cpus
;
2022 MemoryRegion
*sysmem
= get_system_memory();
2023 MemoryRegion
*secure_sysmem
= NULL
;
2024 MemoryRegion
*tag_sysmem
= NULL
;
2025 MemoryRegion
*secure_tag_sysmem
= NULL
;
2026 int n
, virt_max_cpus
;
2027 bool firmware_loaded
;
2028 bool aarch64
= true;
2029 bool has_ged
= !vmc
->no_ged
;
2030 unsigned int smp_cpus
= machine
->smp
.cpus
;
2031 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2033 if (!cpu_type_valid(machine
->cpu_type
)) {
2034 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
2038 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2041 * In accelerated mode, the memory map is computed earlier in kvm_type()
2042 * to create a VM with the right number of IPA bits.
2050 * Instantiate a temporary CPU object to find out about what
2051 * we are about to deal with. Once this is done, get rid of
2054 cpuobj
= object_new(possible_cpus
->cpus
[0].type
);
2055 armcpu
= ARM_CPU(cpuobj
);
2057 pa_bits
= arm_pamax(armcpu
);
2059 object_unref(cpuobj
);
2061 virt_set_memmap(vms
, pa_bits
);
2064 /* We can probe only here because during property set
2065 * KVM is not available yet
2067 finalize_gic_version(vms
);
2071 * The Secure view of the world is the same as the NonSecure,
2072 * but with a few extra devices. Create it as a container region
2073 * containing the system memory at low priority; any secure-only
2074 * devices go in at higher priority and take precedence.
2076 secure_sysmem
= g_new(MemoryRegion
, 1);
2077 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
2079 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
2082 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
2083 secure_sysmem
?: sysmem
);
2085 /* If we have an EL3 boot ROM then the assumption is that it will
2086 * implement PSCI itself, so disable QEMU's internal implementation
2087 * so it doesn't get in the way. Instead of starting secondary
2088 * CPUs in PSCI powerdown state we will start them all running and
2089 * let the boot ROM sort them out.
2090 * The usual case is that we do use QEMU's PSCI implementation;
2091 * if the guest has EL2 then we will use SMC as the conduit,
2092 * and otherwise we will use HVC (for backwards compatibility and
2093 * because if we're using KVM then we must use HVC).
2095 if (vms
->secure
&& firmware_loaded
) {
2096 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
2097 } else if (vms
->virt
) {
2098 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
2100 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
2104 * The maximum number of CPUs depends on the GIC version, or on how
2105 * many redistributors we can fit into the memory map (which in turn
2106 * depends on whether this is a GICv3 or v4).
2108 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
2109 virt_max_cpus
= GIC_NCPU
;
2111 virt_max_cpus
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
2112 if (vms
->highmem_redists
) {
2113 virt_max_cpus
+= virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
2117 if (max_cpus
> virt_max_cpus
) {
2118 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2119 "supported by machine 'mach-virt' (%d)",
2120 max_cpus
, virt_max_cpus
);
2121 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& !vms
->highmem_redists
) {
2122 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2128 if (vms
->secure
&& (kvm_enabled() || hvf_enabled())) {
2129 error_report("mach-virt: %s does not support providing "
2130 "Security extensions (TrustZone) to the guest CPU",
2131 current_accel_name());
2135 if (vms
->virt
&& (kvm_enabled() || hvf_enabled())) {
2136 error_report("mach-virt: %s does not support providing "
2137 "Virtualization extensions to the guest CPU",
2138 current_accel_name());
2142 if (vms
->mte
&& (kvm_enabled() || hvf_enabled())) {
2143 error_report("mach-virt: %s does not support providing "
2144 "MTE to the guest CPU",
2145 current_accel_name());
2151 assert(possible_cpus
->len
== max_cpus
);
2152 for (n
= 0; n
< possible_cpus
->len
; n
++) {
2156 if (n
>= smp_cpus
) {
2160 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
2161 object_property_set_int(cpuobj
, "mp-affinity",
2162 possible_cpus
->cpus
[n
].arch_id
, NULL
);
2167 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
2170 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
2173 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
2176 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
2177 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
2180 if (vmc
->kvm_no_adjvtime
&&
2181 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
2182 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
2185 if (vmc
->no_kvm_steal_time
&&
2186 object_property_find(cpuobj
, "kvm-steal-time")) {
2187 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
2190 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
2191 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
2194 if (vmc
->no_tcg_lpa2
&& object_property_find(cpuobj
, "lpa2")) {
2195 object_property_set_bool(cpuobj
, "lpa2", false, NULL
);
2198 if (object_property_find(cpuobj
, "reset-cbar")) {
2199 object_property_set_int(cpuobj
, "reset-cbar",
2200 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
2204 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
2207 object_property_set_link(cpuobj
, "secure-memory",
2208 OBJECT(secure_sysmem
), &error_abort
);
2212 /* Create the memory region only once, but link to all cpus. */
2215 * The property exists only if MemTag is supported.
2216 * If it is, we must allocate the ram to back that up.
2218 if (!object_property_find(cpuobj
, "tag-memory")) {
2219 error_report("MTE requested, but not supported "
2220 "by the guest CPU");
2224 tag_sysmem
= g_new(MemoryRegion
, 1);
2225 memory_region_init(tag_sysmem
, OBJECT(machine
),
2226 "tag-memory", UINT64_MAX
/ 32);
2229 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2230 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2231 "secure-tag-memory", UINT64_MAX
/ 32);
2233 /* As with ram, secure-tag takes precedence over tag. */
2234 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2239 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2242 object_property_set_link(cpuobj
, "secure-tag-memory",
2243 OBJECT(secure_tag_sysmem
),
2248 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2249 object_unref(cpuobj
);
2251 fdt_add_timer_nodes(vms
);
2252 fdt_add_cpu_nodes(vms
);
2254 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2257 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2259 create_gic(vms
, sysmem
);
2261 virt_cpu_post_init(vms
, sysmem
);
2263 fdt_add_pmu_nodes(vms
);
2265 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2268 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2269 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2273 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2274 machine
->ram_size
, "mach-virt.tag");
2277 vms
->highmem_ecam
&= (!firmware_loaded
|| aarch64
);
2283 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2284 vms
->acpi_dev
= create_acpi_ged(vms
);
2286 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2289 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2290 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2293 /* connect powerdown request */
2294 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2295 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2297 /* Create mmio transports, so the user can create virtio backends
2298 * (which will be automatically plugged in to the transports). If
2299 * no backend is created the transport will just sit harmlessly idle.
2301 create_virtio_devices(vms
);
2303 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2304 rom_set_fw(vms
->fw_cfg
);
2306 create_platform_bus(vms
);
2308 if (machine
->nvdimms_state
->is_enabled
) {
2309 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2310 .space_id
= AML_AS_SYSTEM_MEMORY
,
2311 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2312 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2315 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2316 arm_virt_nvdimm_acpi_dsmio
,
2317 vms
->fw_cfg
, OBJECT(vms
));
2320 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2321 vms
->bootinfo
.board_id
= -1;
2322 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2323 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2324 vms
->bootinfo
.skip_dtb_autoload
= true;
2325 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2326 vms
->bootinfo
.psci_conduit
= vms
->psci_conduit
;
2327 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2329 vms
->machine_done
.notify
= virt_machine_done
;
2330 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2333 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2335 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2340 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2342 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2344 vms
->secure
= value
;
2347 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2349 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2354 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2356 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2361 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2363 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2365 return vms
->highmem
;
2368 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2370 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2372 vms
->highmem
= value
;
2375 static bool virt_get_compact_highmem(Object
*obj
, Error
**errp
)
2377 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2379 return vms
->highmem_compact
;
2382 static void virt_set_compact_highmem(Object
*obj
, bool value
, Error
**errp
)
2384 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2386 vms
->highmem_compact
= value
;
2389 static bool virt_get_highmem_redists(Object
*obj
, Error
**errp
)
2391 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2393 return vms
->highmem_redists
;
2396 static void virt_set_highmem_redists(Object
*obj
, bool value
, Error
**errp
)
2398 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2400 vms
->highmem_redists
= value
;
2403 static bool virt_get_highmem_ecam(Object
*obj
, Error
**errp
)
2405 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2407 return vms
->highmem_ecam
;
2410 static void virt_set_highmem_ecam(Object
*obj
, bool value
, Error
**errp
)
2412 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2414 vms
->highmem_ecam
= value
;
2417 static bool virt_get_highmem_mmio(Object
*obj
, Error
**errp
)
2419 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2421 return vms
->highmem_mmio
;
2424 static void virt_set_highmem_mmio(Object
*obj
, bool value
, Error
**errp
)
2426 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2428 vms
->highmem_mmio
= value
;
2432 static bool virt_get_its(Object
*obj
, Error
**errp
)
2434 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2439 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2441 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2446 static bool virt_get_dtb_randomness(Object
*obj
, Error
**errp
)
2448 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2450 return vms
->dtb_randomness
;
2453 static void virt_set_dtb_randomness(Object
*obj
, bool value
, Error
**errp
)
2455 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2457 vms
->dtb_randomness
= value
;
2460 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2462 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2464 return g_strdup(vms
->oem_id
);
2467 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2469 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2470 size_t len
= strlen(value
);
2474 "User specified oem-id value is bigger than 6 bytes in size");
2478 strncpy(vms
->oem_id
, value
, 6);
2481 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2483 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2485 return g_strdup(vms
->oem_table_id
);
2488 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2491 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2492 size_t len
= strlen(value
);
2496 "User specified oem-table-id value is bigger than 8 bytes in size");
2499 strncpy(vms
->oem_table_id
, value
, 8);
2503 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2505 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2511 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2512 void *opaque
, Error
**errp
)
2514 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2515 OnOffAuto acpi
= vms
->acpi
;
2517 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2520 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2521 void *opaque
, Error
**errp
)
2523 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2525 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2528 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2530 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2535 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2537 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2542 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2544 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2549 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2551 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2556 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2558 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2561 switch (vms
->gic_version
) {
2562 case VIRT_GIC_VERSION_4
:
2565 case VIRT_GIC_VERSION_3
:
2572 return g_strdup(val
);
2575 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2577 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2579 if (!strcmp(value
, "4")) {
2580 vms
->gic_version
= VIRT_GIC_VERSION_4
;
2581 } else if (!strcmp(value
, "3")) {
2582 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2583 } else if (!strcmp(value
, "2")) {
2584 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2585 } else if (!strcmp(value
, "host")) {
2586 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2587 } else if (!strcmp(value
, "max")) {
2588 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2590 error_setg(errp
, "Invalid gic-version value");
2591 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2595 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2597 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2599 switch (vms
->iommu
) {
2600 case VIRT_IOMMU_NONE
:
2601 return g_strdup("none");
2602 case VIRT_IOMMU_SMMUV3
:
2603 return g_strdup("smmuv3");
2605 g_assert_not_reached();
2609 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2611 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2613 if (!strcmp(value
, "smmuv3")) {
2614 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2615 } else if (!strcmp(value
, "none")) {
2616 vms
->iommu
= VIRT_IOMMU_NONE
;
2618 error_setg(errp
, "Invalid iommu value");
2619 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2623 static bool virt_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
2625 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2627 return vms
->default_bus_bypass_iommu
;
2630 static void virt_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
2633 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2635 vms
->default_bus_bypass_iommu
= value
;
2638 static CpuInstanceProperties
2639 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2641 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2642 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2644 assert(cpu_index
< possible_cpus
->len
);
2645 return possible_cpus
->cpus
[cpu_index
].props
;
2648 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2650 int64_t socket_id
= ms
->possible_cpus
->cpus
[idx
].props
.socket_id
;
2652 return socket_id
% ms
->numa_state
->num_nodes
;
2655 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2658 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2659 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2660 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2662 if (ms
->possible_cpus
) {
2663 assert(ms
->possible_cpus
->len
== max_cpus
);
2664 return ms
->possible_cpus
;
2667 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2668 sizeof(CPUArchId
) * max_cpus
);
2669 ms
->possible_cpus
->len
= max_cpus
;
2670 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2671 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2672 ms
->possible_cpus
->cpus
[n
].arch_id
=
2673 virt_cpu_mp_affinity(vms
, n
);
2675 assert(!mc
->smp_props
.dies_supported
);
2676 ms
->possible_cpus
->cpus
[n
].props
.has_socket_id
= true;
2677 ms
->possible_cpus
->cpus
[n
].props
.socket_id
=
2678 n
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
);
2679 ms
->possible_cpus
->cpus
[n
].props
.has_cluster_id
= true;
2680 ms
->possible_cpus
->cpus
[n
].props
.cluster_id
=
2681 (n
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
;
2682 ms
->possible_cpus
->cpus
[n
].props
.has_core_id
= true;
2683 ms
->possible_cpus
->cpus
[n
].props
.core_id
=
2684 (n
/ ms
->smp
.threads
) % ms
->smp
.cores
;
2685 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2686 ms
->possible_cpus
->cpus
[n
].props
.thread_id
=
2687 n
% ms
->smp
.threads
;
2689 return ms
->possible_cpus
;
2692 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2695 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2696 const MachineState
*ms
= MACHINE(hotplug_dev
);
2697 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2699 if (!vms
->acpi_dev
) {
2701 "memory hotplug is not enabled: missing acpi-ged device");
2706 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2710 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2711 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2715 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2718 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2719 DeviceState
*dev
, Error
**errp
)
2721 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2722 MachineState
*ms
= MACHINE(hotplug_dev
);
2723 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2725 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2728 nvdimm_plug(ms
->nvdimms_state
);
2731 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2735 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2736 DeviceState
*dev
, Error
**errp
)
2738 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2740 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2741 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2742 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2743 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2744 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2745 hwaddr db_start
= 0, db_end
= 0;
2746 char *resv_prop_str
;
2748 if (vms
->iommu
!= VIRT_IOMMU_NONE
) {
2749 error_setg(errp
, "virt machine does not support multiple IOMMUs");
2753 switch (vms
->msi_controller
) {
2754 case VIRT_MSI_CTRL_NONE
:
2756 case VIRT_MSI_CTRL_ITS
:
2757 /* GITS_TRANSLATER page */
2758 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2759 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2760 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2762 case VIRT_MSI_CTRL_GICV2M
:
2763 /* MSI_SETSPI_NS page */
2764 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2765 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2768 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2770 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2772 object_property_set_uint(OBJECT(dev
), "len-reserved-regions", 1, errp
);
2773 object_property_set_str(OBJECT(dev
), "reserved-regions[0]",
2774 resv_prop_str
, errp
);
2775 g_free(resv_prop_str
);
2779 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2780 DeviceState
*dev
, Error
**errp
)
2782 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2784 if (vms
->platform_bus_dev
) {
2785 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2787 if (device_is_dynamic_sysbus(mc
, dev
)) {
2788 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2789 SYS_BUS_DEVICE(dev
));
2793 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2794 virt_memory_plug(hotplug_dev
, dev
, errp
);
2795 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2796 virtio_md_pci_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2799 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2800 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2802 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2803 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2804 create_virtio_iommu_dt_bindings(vms
);
2808 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2809 DeviceState
*dev
, Error
**errp
)
2811 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2813 if (!vms
->acpi_dev
) {
2815 "memory hotplug is not enabled: missing acpi-ged device");
2819 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2820 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
2824 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2828 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2829 DeviceState
*dev
, Error
**errp
)
2831 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2832 Error
*local_err
= NULL
;
2834 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2839 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2840 qdev_unrealize(dev
);
2843 error_propagate(errp
, local_err
);
2846 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2847 DeviceState
*dev
, Error
**errp
)
2849 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2850 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2851 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2852 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
),
2855 error_setg(errp
, "device unplug request for unsupported device"
2856 " type: %s", object_get_typename(OBJECT(dev
)));
2860 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2861 DeviceState
*dev
, Error
**errp
)
2863 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2864 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2865 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2866 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2868 error_setg(errp
, "virt: device unplug for unsupported device"
2869 " type: %s", object_get_typename(OBJECT(dev
)));
2873 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2876 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2878 if (device_is_dynamic_sysbus(mc
, dev
) ||
2879 object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2880 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
) ||
2881 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2882 return HOTPLUG_HANDLER(machine
);
2888 * for arm64 kvm_type [7-0] encodes the requested number of bits
2889 * in the IPA address space
2891 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2893 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2894 int max_vm_pa_size
, requested_pa_size
;
2897 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
2899 /* we freeze the memory map to compute the highest gpa */
2900 virt_set_memmap(vms
, max_vm_pa_size
);
2902 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2905 * KVM requires the IPA size to be at least 32 bits.
2907 if (requested_pa_size
< 32) {
2908 requested_pa_size
= 32;
2911 if (requested_pa_size
> max_vm_pa_size
) {
2912 error_report("-m and ,maxmem option values "
2913 "require an IPA range (%d bits) larger than "
2914 "the one supported by the host (%d bits)",
2915 requested_pa_size
, max_vm_pa_size
);
2919 * We return the requested PA log size, unless KVM only supports
2920 * the implicit legacy 40b IPA setting, in which case the kvm_type
2923 return fixed_ipa
? 0 : requested_pa_size
;
2926 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2928 MachineClass
*mc
= MACHINE_CLASS(oc
);
2929 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2931 mc
->init
= machvirt_init
;
2932 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2933 * The value may be reduced later when we have more information about the
2934 * configuration of the particular instance.
2937 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2938 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2939 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2940 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2942 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2944 mc
->block_default_type
= IF_VIRTIO
;
2946 mc
->pci_allow_0_address
= true;
2947 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2948 mc
->minimum_page_bits
= 12;
2949 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
2950 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
2952 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
2954 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("max");
2956 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
2957 mc
->kvm_type
= virt_kvm_type
;
2958 assert(!mc
->get_hotplug_handler
);
2959 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
2960 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
2961 hc
->plug
= virt_machine_device_plug_cb
;
2962 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
2963 hc
->unplug
= virt_machine_device_unplug_cb
;
2964 mc
->nvdimm_supported
= true;
2965 mc
->smp_props
.clusters_supported
= true;
2966 mc
->auto_enable_numa_with_memhp
= true;
2967 mc
->auto_enable_numa_with_memdev
= true;
2968 /* platform instead of architectural choice */
2969 mc
->cpu_cluster_has_numa_boundary
= true;
2970 mc
->default_ram_id
= "mach-virt.ram";
2971 mc
->default_nic
= "virtio-net-pci";
2973 object_class_property_add(oc
, "acpi", "OnOffAuto",
2974 virt_get_acpi
, virt_set_acpi
,
2976 object_class_property_set_description(oc
, "acpi",
2978 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
2980 object_class_property_set_description(oc
, "secure",
2981 "Set on/off to enable/disable the ARM "
2982 "Security Extensions (TrustZone)");
2984 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
2986 object_class_property_set_description(oc
, "virtualization",
2987 "Set on/off to enable/disable emulating a "
2988 "guest CPU which implements the ARM "
2989 "Virtualization Extensions");
2991 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
2993 object_class_property_set_description(oc
, "highmem",
2994 "Set on/off to enable/disable using "
2995 "physical address space above 32 bits");
2997 object_class_property_add_bool(oc
, "compact-highmem",
2998 virt_get_compact_highmem
,
2999 virt_set_compact_highmem
);
3000 object_class_property_set_description(oc
, "compact-highmem",
3001 "Set on/off to enable/disable compact "
3002 "layout for high memory regions");
3004 object_class_property_add_bool(oc
, "highmem-redists",
3005 virt_get_highmem_redists
,
3006 virt_set_highmem_redists
);
3007 object_class_property_set_description(oc
, "highmem-redists",
3008 "Set on/off to enable/disable high "
3009 "memory region for GICv3 or GICv4 "
3012 object_class_property_add_bool(oc
, "highmem-ecam",
3013 virt_get_highmem_ecam
,
3014 virt_set_highmem_ecam
);
3015 object_class_property_set_description(oc
, "highmem-ecam",
3016 "Set on/off to enable/disable high "
3017 "memory region for PCI ECAM");
3019 object_class_property_add_bool(oc
, "highmem-mmio",
3020 virt_get_highmem_mmio
,
3021 virt_set_highmem_mmio
);
3022 object_class_property_set_description(oc
, "highmem-mmio",
3023 "Set on/off to enable/disable high "
3024 "memory region for PCI MMIO");
3026 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
3027 virt_set_gic_version
);
3028 object_class_property_set_description(oc
, "gic-version",
3030 "Valid values are 2, 3, 4, host and max");
3032 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
3033 object_class_property_set_description(oc
, "iommu",
3034 "Set the IOMMU type. "
3035 "Valid values are none and smmuv3");
3037 object_class_property_add_bool(oc
, "default-bus-bypass-iommu",
3038 virt_get_default_bus_bypass_iommu
,
3039 virt_set_default_bus_bypass_iommu
);
3040 object_class_property_set_description(oc
, "default-bus-bypass-iommu",
3041 "Set on/off to enable/disable "
3042 "bypass_iommu for default root bus");
3044 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
3046 object_class_property_set_description(oc
, "ras",
3047 "Set on/off to enable/disable reporting host memory errors "
3048 "to a KVM guest using ACPI and guest external abort exceptions");
3050 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
3051 object_class_property_set_description(oc
, "mte",
3052 "Set on/off to enable/disable emulating a "
3053 "guest CPU which implements the ARM "
3054 "Memory Tagging Extension");
3056 object_class_property_add_bool(oc
, "its", virt_get_its
,
3058 object_class_property_set_description(oc
, "its",
3059 "Set on/off to enable/disable "
3060 "ITS instantiation");
3062 object_class_property_add_bool(oc
, "dtb-randomness",
3063 virt_get_dtb_randomness
,
3064 virt_set_dtb_randomness
);
3065 object_class_property_set_description(oc
, "dtb-randomness",
3066 "Set off to disable passing random or "
3067 "non-deterministic dtb nodes to guest");
3069 object_class_property_add_bool(oc
, "dtb-kaslr-seed",
3070 virt_get_dtb_randomness
,
3071 virt_set_dtb_randomness
);
3072 object_class_property_set_description(oc
, "dtb-kaslr-seed",
3073 "Deprecated synonym of dtb-randomness");
3075 object_class_property_add_str(oc
, "x-oem-id",
3078 object_class_property_set_description(oc
, "x-oem-id",
3079 "Override the default value of field OEMID "
3080 "in ACPI table header."
3081 "The string may be up to 6 bytes in size");
3084 object_class_property_add_str(oc
, "x-oem-table-id",
3085 virt_get_oem_table_id
,
3086 virt_set_oem_table_id
);
3087 object_class_property_set_description(oc
, "x-oem-table-id",
3088 "Override the default value of field OEM Table ID "
3089 "in ACPI table header."
3090 "The string may be up to 8 bytes in size");
3094 static void virt_instance_init(Object
*obj
)
3096 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
3097 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
3099 /* EL3 is disabled by default on virt: this makes us consistent
3100 * between KVM and TCG for this board, and it also allows us to
3101 * boot UEFI blobs which assume no TrustZone support.
3103 vms
->secure
= false;
3105 /* EL2 is also disabled by default, for similar reasons */
3108 /* High memory is enabled by default */
3109 vms
->highmem
= true;
3110 vms
->highmem_compact
= !vmc
->no_highmem_compact
;
3111 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
3113 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
3114 vms
->highmem_mmio
= true;
3115 vms
->highmem_redists
= true;
3120 /* Default allows ITS instantiation */
3123 if (vmc
->no_tcg_its
) {
3124 vms
->tcg_its
= false;
3126 vms
->tcg_its
= true;
3130 /* Default disallows iommu instantiation */
3131 vms
->iommu
= VIRT_IOMMU_NONE
;
3133 /* The default root bus is attached to iommu by default */
3134 vms
->default_bus_bypass_iommu
= false;
3136 /* Default disallows RAS instantiation */
3139 /* MTE is disabled by default. */
3142 /* Supply kaslr-seed and rng-seed by default */
3143 vms
->dtb_randomness
= true;
3145 vms
->irqmap
= a15irqmap
;
3147 virt_flash_create(vms
);
3149 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
3150 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
3153 static const TypeInfo virt_machine_info
= {
3154 .name
= TYPE_VIRT_MACHINE
,
3155 .parent
= TYPE_MACHINE
,
3157 .instance_size
= sizeof(VirtMachineState
),
3158 .class_size
= sizeof(VirtMachineClass
),
3159 .class_init
= virt_machine_class_init
,
3160 .instance_init
= virt_instance_init
,
3161 .interfaces
= (InterfaceInfo
[]) {
3162 { TYPE_HOTPLUG_HANDLER
},
3167 static void machvirt_machine_init(void)
3169 type_register_static(&virt_machine_info
);
3171 type_init(machvirt_machine_init
);
3173 static void virt_machine_8_2_options(MachineClass
*mc
)
3176 DEFINE_VIRT_MACHINE_AS_LATEST(8, 2)
3178 static void virt_machine_8_1_options(MachineClass
*mc
)
3180 virt_machine_8_2_options(mc
);
3181 compat_props_add(mc
->compat_props
, hw_compat_8_1
, hw_compat_8_1_len
);
3183 DEFINE_VIRT_MACHINE(8, 1)
3185 static void virt_machine_8_0_options(MachineClass
*mc
)
3187 virt_machine_8_1_options(mc
);
3188 compat_props_add(mc
->compat_props
, hw_compat_8_0
, hw_compat_8_0_len
);
3190 DEFINE_VIRT_MACHINE(8, 0)
3192 static void virt_machine_7_2_options(MachineClass
*mc
)
3194 virt_machine_8_0_options(mc
);
3195 compat_props_add(mc
->compat_props
, hw_compat_7_2
, hw_compat_7_2_len
);
3197 DEFINE_VIRT_MACHINE(7, 2)
3199 static void virt_machine_7_1_options(MachineClass
*mc
)
3201 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3203 virt_machine_7_2_options(mc
);
3204 compat_props_add(mc
->compat_props
, hw_compat_7_1
, hw_compat_7_1_len
);
3205 /* Compact layout for high memory regions was introduced with 7.2 */
3206 vmc
->no_highmem_compact
= true;
3208 DEFINE_VIRT_MACHINE(7, 1)
3210 static void virt_machine_7_0_options(MachineClass
*mc
)
3212 virt_machine_7_1_options(mc
);
3213 compat_props_add(mc
->compat_props
, hw_compat_7_0
, hw_compat_7_0_len
);
3215 DEFINE_VIRT_MACHINE(7, 0)
3217 static void virt_machine_6_2_options(MachineClass
*mc
)
3219 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3221 virt_machine_7_0_options(mc
);
3222 compat_props_add(mc
->compat_props
, hw_compat_6_2
, hw_compat_6_2_len
);
3223 vmc
->no_tcg_lpa2
= true;
3225 DEFINE_VIRT_MACHINE(6, 2)
3227 static void virt_machine_6_1_options(MachineClass
*mc
)
3229 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3231 virt_machine_6_2_options(mc
);
3232 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
3233 mc
->smp_props
.prefer_sockets
= true;
3234 vmc
->no_cpu_topology
= true;
3236 /* qemu ITS was introduced with 6.2 */
3237 vmc
->no_tcg_its
= true;
3239 DEFINE_VIRT_MACHINE(6, 1)
3241 static void virt_machine_6_0_options(MachineClass
*mc
)
3243 virt_machine_6_1_options(mc
);
3244 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
3246 DEFINE_VIRT_MACHINE(6, 0)
3248 static void virt_machine_5_2_options(MachineClass
*mc
)
3250 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3252 virt_machine_6_0_options(mc
);
3253 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
3254 vmc
->no_secure_gpio
= true;
3256 DEFINE_VIRT_MACHINE(5, 2)
3258 static void virt_machine_5_1_options(MachineClass
*mc
)
3260 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3262 virt_machine_5_2_options(mc
);
3263 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
3264 vmc
->no_kvm_steal_time
= true;
3266 DEFINE_VIRT_MACHINE(5, 1)
3268 static void virt_machine_5_0_options(MachineClass
*mc
)
3270 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3272 virt_machine_5_1_options(mc
);
3273 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
3274 mc
->numa_mem_supported
= true;
3275 vmc
->acpi_expose_flash
= true;
3276 mc
->auto_enable_numa_with_memdev
= false;
3278 DEFINE_VIRT_MACHINE(5, 0)
3280 static void virt_machine_4_2_options(MachineClass
*mc
)
3282 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3284 virt_machine_5_0_options(mc
);
3285 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
3286 vmc
->kvm_no_adjvtime
= true;
3288 DEFINE_VIRT_MACHINE(4, 2)
3290 static void virt_machine_4_1_options(MachineClass
*mc
)
3292 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3294 virt_machine_4_2_options(mc
);
3295 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
3297 mc
->auto_enable_numa_with_memhp
= false;
3299 DEFINE_VIRT_MACHINE(4, 1)
3301 static void virt_machine_4_0_options(MachineClass
*mc
)
3303 virt_machine_4_1_options(mc
);
3304 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
3306 DEFINE_VIRT_MACHINE(4, 0)
3308 static void virt_machine_3_1_options(MachineClass
*mc
)
3310 virt_machine_4_0_options(mc
);
3311 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
3313 DEFINE_VIRT_MACHINE(3, 1)
3315 static void virt_machine_3_0_options(MachineClass
*mc
)
3317 virt_machine_3_1_options(mc
);
3318 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
3320 DEFINE_VIRT_MACHINE(3, 0)
3322 static void virt_machine_2_12_options(MachineClass
*mc
)
3324 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3326 virt_machine_3_0_options(mc
);
3327 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
3328 vmc
->no_highmem_ecam
= true;
3331 DEFINE_VIRT_MACHINE(2, 12)
3333 static void virt_machine_2_11_options(MachineClass
*mc
)
3335 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3337 virt_machine_2_12_options(mc
);
3338 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
3339 vmc
->smbios_old_sys_ver
= true;
3341 DEFINE_VIRT_MACHINE(2, 11)
3343 static void virt_machine_2_10_options(MachineClass
*mc
)
3345 virt_machine_2_11_options(mc
);
3346 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
3347 /* before 2.11 we never faulted accesses to bad addresses */
3348 mc
->ignore_memory_transaction_failures
= true;
3350 DEFINE_VIRT_MACHINE(2, 10)
3352 static void virt_machine_2_9_options(MachineClass
*mc
)
3354 virt_machine_2_10_options(mc
);
3355 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
3357 DEFINE_VIRT_MACHINE(2, 9)
3359 static void virt_machine_2_8_options(MachineClass
*mc
)
3361 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3363 virt_machine_2_9_options(mc
);
3364 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
3365 /* For 2.8 and earlier we falsely claimed in the DT that
3366 * our timers were edge-triggered, not level-triggered.
3368 vmc
->claim_edge_triggered_timers
= true;
3370 DEFINE_VIRT_MACHINE(2, 8)
3372 static void virt_machine_2_7_options(MachineClass
*mc
)
3374 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3376 virt_machine_2_8_options(mc
);
3377 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
3378 /* ITS was introduced with 2.8 */
3380 /* Stick with 1K pages for migration compatibility */
3381 mc
->minimum_page_bits
= 0;
3383 DEFINE_VIRT_MACHINE(2, 7)
3385 static void virt_machine_2_6_options(MachineClass
*mc
)
3387 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3389 virt_machine_2_7_options(mc
);
3390 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
3391 vmc
->disallow_affinity_adjustment
= true;
3392 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3395 DEFINE_VIRT_MACHINE(2, 6)