2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "hw/sysbus.h"
34 #include "hw/arm/arm.h"
35 #include "hw/arm/primecell.h"
36 #include "hw/arm/virt.h"
37 #include "hw/vfio/vfio-calxeda-xgmac.h"
38 #include "hw/vfio/vfio-amd-xgbe.h"
39 #include "hw/devices.h"
41 #include "sysemu/block-backend.h"
42 #include "sysemu/device_tree.h"
43 #include "sysemu/numa.h"
44 #include "sysemu/sysemu.h"
45 #include "sysemu/kvm.h"
46 #include "hw/compat.h"
47 #include "hw/loader.h"
48 #include "exec/address-spaces.h"
49 #include "qemu/bitops.h"
50 #include "qemu/error-report.h"
51 #include "hw/pci-host/gpex.h"
52 #include "hw/arm/sysbus-fdt.h"
53 #include "hw/platform-bus.h"
54 #include "hw/arm/fdt.h"
55 #include "hw/intc/arm_gic.h"
56 #include "hw/intc/arm_gicv3_common.h"
58 #include "hw/smbios/smbios.h"
59 #include "qapi/visitor.h"
60 #include "standard-headers/linux/input.h"
61 #include "hw/arm/smmuv3.h"
63 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
64 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
67 MachineClass *mc = MACHINE_CLASS(oc); \
68 virt_machine_##major##_##minor##_options(mc); \
69 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
74 static const TypeInfo machvirt_##major##_##minor##_info = { \
75 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
76 .parent = TYPE_VIRT_MACHINE, \
77 .instance_init = virt_##major##_##minor##_instance_init, \
78 .class_init = virt_##major##_##minor##_class_init, \
80 static void machvirt_machine_##major##_##minor##_init(void) \
82 type_register_static(&machvirt_##major##_##minor##_info); \
84 type_init(machvirt_machine_##major##_##minor##_init);
86 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
87 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
88 #define DEFINE_VIRT_MACHINE(major, minor) \
89 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
92 /* Number of external interrupt lines to configure the GIC with */
95 #define PLATFORM_BUS_NUM_IRQS 64
97 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
98 * RAM can go up to the 256GB mark, leaving 256GB of the physical
99 * address space unallocated and free for future use between 256G and 512G.
100 * If we need to provide more RAM to VMs in the future then we need to:
101 * * allocate a second bank of RAM starting at 2TB and working up
102 * * fix the DT and ACPI table generation code in QEMU to correctly
103 * report two split lumps of RAM to the guest
104 * * fix KVM in the host kernel to allow guests with >40 bit address spaces
105 * (We don't want to fill all the way up to 512GB with RAM because
106 * we might want it for non-RAM purposes later. Conversely it seems
107 * reasonable to assume that anybody configuring a VM with a quarter
108 * of a terabyte of RAM will be doing it on a host with more than a
109 * terabyte of physical address space.)
111 #define RAMLIMIT_GB 255
112 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
114 /* Addresses and sizes of our components.
115 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
116 * 128MB..256MB is used for miscellaneous device I/O.
117 * 256MB..1GB is reserved for possible future PCI support (ie where the
118 * PCI memory window will go if we add a PCI host controller).
119 * 1GB and up is RAM (which may happily spill over into the
120 * high memory region beyond 4GB).
121 * This represents a compromise between how much RAM can be given to
122 * a 32 bit VM and leaving space for expansion and in particular for PCI.
123 * Note that devices should generally be placed at multiples of 0x10000,
124 * to accommodate guests using 64K pages.
126 static const MemMapEntry a15memmap
[] = {
127 /* Space up to 0x8000000 is reserved for a boot ROM */
128 [VIRT_FLASH
] = { 0, 0x08000000 },
129 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
130 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
131 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
132 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
133 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
134 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
135 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
136 /* This redistributor space allows up to 2*64kB*123 CPUs */
137 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
138 [VIRT_UART
] = { 0x09000000, 0x00001000 },
139 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
140 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
141 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
142 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
143 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
144 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
145 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
146 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
147 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
148 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
149 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
150 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
151 [VIRT_MEM
] = { 0x40000000, RAMLIMIT_BYTES
},
152 /* Second PCIe window, 512GB wide at the 512GB boundary */
153 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
156 static const int a15irqmap
[] = {
159 [VIRT_PCIE
] = 3, /* ... to 6 */
161 [VIRT_SECURE_UART
] = 8,
162 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
163 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
164 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
165 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
168 static const char *valid_cpus
[] = {
169 ARM_CPU_TYPE_NAME("cortex-a15"),
170 ARM_CPU_TYPE_NAME("cortex-a53"),
171 ARM_CPU_TYPE_NAME("cortex-a57"),
172 ARM_CPU_TYPE_NAME("host"),
173 ARM_CPU_TYPE_NAME("max"),
176 static bool cpu_type_valid(const char *cpu
)
180 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
181 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
188 static void create_fdt(VirtMachineState
*vms
)
190 void *fdt
= create_device_tree(&vms
->fdt_size
);
193 error_report("create_device_tree() failed");
200 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
201 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
202 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
205 * /chosen and /memory nodes must exist for load_dtb
206 * to fill in necessary properties later
208 qemu_fdt_add_subnode(fdt
, "/chosen");
209 qemu_fdt_add_subnode(fdt
, "/memory");
210 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
212 /* Clock node, for the benefit of the UART. The kernel device tree
213 * binding documentation claims the PL011 node clock properties are
214 * optional but in practice if you omit them the kernel refuses to
215 * probe for the device.
217 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
218 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
219 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
220 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
221 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
222 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
224 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
226 if (have_numa_distance
) {
227 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
228 uint32_t *matrix
= g_malloc0(size
);
231 for (i
= 0; i
< nb_numa_nodes
; i
++) {
232 for (j
= 0; j
< nb_numa_nodes
; j
++) {
233 idx
= (i
* nb_numa_nodes
+ j
) * 3;
234 matrix
[idx
+ 0] = cpu_to_be32(i
);
235 matrix
[idx
+ 1] = cpu_to_be32(j
);
236 matrix
[idx
+ 2] = cpu_to_be32(numa_info
[i
].distance
[j
]);
240 qemu_fdt_add_subnode(fdt
, "/distance-map");
241 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
242 "numa-distance-map-v1");
243 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
249 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
251 /* On real hardware these interrupts are level-triggered.
252 * On KVM they were edge-triggered before host kernel version 4.4,
253 * and level-triggered afterwards.
254 * On emulated QEMU they are level-triggered.
256 * Getting the DTB info about them wrong is awkward for some
258 * pre-4.8 ignore the DT and leave the interrupt configured
259 * with whatever the GIC reset value (or the bootloader) left it at
260 * 4.8 before rc6 honour the incorrect data by programming it back
261 * into the GIC, causing problems
262 * 4.8rc6 and later ignore the DT and always write "level triggered"
265 * For backwards-compatibility, virt-2.8 and earlier will continue
266 * to say these are edge-triggered, but later machines will report
267 * the correct information.
270 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
271 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
273 if (vmc
->claim_edge_triggered_timers
) {
274 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
277 if (vms
->gic_version
== 2) {
278 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
279 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
280 (1 << vms
->smp_cpus
) - 1);
283 qemu_fdt_add_subnode(vms
->fdt
, "/timer");
285 armcpu
= ARM_CPU(qemu_get_cpu(0));
286 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
287 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
288 qemu_fdt_setprop(vms
->fdt
, "/timer", "compatible",
289 compat
, sizeof(compat
));
291 qemu_fdt_setprop_string(vms
->fdt
, "/timer", "compatible",
294 qemu_fdt_setprop(vms
->fdt
, "/timer", "always-on", NULL
, 0);
295 qemu_fdt_setprop_cells(vms
->fdt
, "/timer", "interrupts",
296 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
297 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
298 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
299 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
302 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
306 const MachineState
*ms
= MACHINE(vms
);
309 * From Documentation/devicetree/bindings/arm/cpus.txt
310 * On ARM v8 64-bit systems value should be set to 2,
311 * that corresponds to the MPIDR_EL1 register size.
312 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
313 * in the system, #address-cells can be set to 1, since
314 * MPIDR_EL1[63:32] bits are not used for CPUs
317 * Here we actually don't know whether our system is 32- or 64-bit one.
318 * The simplest way to go is to examine affinity IDs of all our CPUs. If
319 * at least one of them has Aff3 populated, we set #address-cells to 2.
321 for (cpu
= 0; cpu
< vms
->smp_cpus
; cpu
++) {
322 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
324 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
330 qemu_fdt_add_subnode(vms
->fdt
, "/cpus");
331 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#address-cells", addr_cells
);
332 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#size-cells", 0x0);
334 for (cpu
= vms
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
335 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
336 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
337 CPUState
*cs
= CPU(armcpu
);
339 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
340 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "cpu");
341 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
342 armcpu
->dtb_compatible
);
344 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
345 && vms
->smp_cpus
> 1) {
346 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
347 "enable-method", "psci");
350 if (addr_cells
== 2) {
351 qemu_fdt_setprop_u64(vms
->fdt
, nodename
, "reg",
352 armcpu
->mp_affinity
);
354 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "reg",
355 armcpu
->mp_affinity
);
358 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
359 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "numa-node-id",
360 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
367 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
369 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
370 qemu_fdt_add_subnode(vms
->fdt
, "/intc/its");
371 qemu_fdt_setprop_string(vms
->fdt
, "/intc/its", "compatible",
373 qemu_fdt_setprop(vms
->fdt
, "/intc/its", "msi-controller", NULL
, 0);
374 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/its", "reg",
375 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
376 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
377 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/its", "phandle", vms
->msi_phandle
);
380 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
382 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
383 qemu_fdt_add_subnode(vms
->fdt
, "/intc/v2m");
384 qemu_fdt_setprop_string(vms
->fdt
, "/intc/v2m", "compatible",
385 "arm,gic-v2m-frame");
386 qemu_fdt_setprop(vms
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
387 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/v2m", "reg",
388 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
389 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
390 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/v2m", "phandle", vms
->msi_phandle
);
393 static void fdt_add_gic_node(VirtMachineState
*vms
)
395 vms
->gic_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
396 qemu_fdt_setprop_cell(vms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
398 qemu_fdt_add_subnode(vms
->fdt
, "/intc");
399 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#interrupt-cells", 3);
400 qemu_fdt_setprop(vms
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
401 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#address-cells", 0x2);
402 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#size-cells", 0x2);
403 qemu_fdt_setprop(vms
->fdt
, "/intc", "ranges", NULL
, 0);
404 if (vms
->gic_version
== 3) {
405 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
407 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
408 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
409 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
410 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
411 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
413 qemu_fdt_setprop_cells(vms
->fdt
, "/intc", "interrupts",
414 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GICV3_MAINT_IRQ
,
415 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
418 /* 'cortex-a15-gic' means 'GIC v2' */
419 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
420 "arm,cortex-a15-gic");
421 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
422 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
423 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
424 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
425 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
428 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "phandle", vms
->gic_phandle
);
431 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
435 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
438 armcpu
= ARM_CPU(cpu
);
439 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
443 if (kvm_irqchip_in_kernel()) {
444 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
446 kvm_arm_pmu_init(cpu
);
450 if (vms
->gic_version
== 2) {
451 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
452 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
453 (1 << vms
->smp_cpus
) - 1);
456 armcpu
= ARM_CPU(qemu_get_cpu(0));
457 qemu_fdt_add_subnode(vms
->fdt
, "/pmu");
458 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
459 const char compat
[] = "arm,armv8-pmuv3";
460 qemu_fdt_setprop(vms
->fdt
, "/pmu", "compatible",
461 compat
, sizeof(compat
));
462 qemu_fdt_setprop_cells(vms
->fdt
, "/pmu", "interrupts",
463 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
467 static void create_its(VirtMachineState
*vms
, DeviceState
*gicdev
)
469 const char *itsclass
= its_class_name();
473 /* Do nothing if not supported */
477 dev
= qdev_create(NULL
, itsclass
);
479 object_property_set_link(OBJECT(dev
), OBJECT(gicdev
), "parent-gicv3",
481 qdev_init_nofail(dev
);
482 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
484 fdt_add_its_gic_node(vms
);
487 static void create_v2m(VirtMachineState
*vms
, qemu_irq
*pic
)
490 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
493 dev
= qdev_create(NULL
, "arm-gicv2m");
494 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
495 qdev_prop_set_uint32(dev
, "base-spi", irq
);
496 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
497 qdev_init_nofail(dev
);
499 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
500 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
503 fdt_add_v2m_gic_node(vms
);
506 static void create_gic(VirtMachineState
*vms
, qemu_irq
*pic
)
508 /* We create a standalone GIC */
510 SysBusDevice
*gicbusdev
;
512 int type
= vms
->gic_version
, i
;
514 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
516 gicdev
= qdev_create(NULL
, gictype
);
517 qdev_prop_set_uint32(gicdev
, "revision", type
);
518 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
519 /* Note that the num-irq property counts both internal and external
520 * interrupts; there are always 32 of the former (mandated by GIC spec).
522 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
523 if (!kvm_irqchip_in_kernel()) {
524 qdev_prop_set_bit(gicdev
, "has-security-extensions", vms
->secure
);
526 qdev_init_nofail(gicdev
);
527 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
528 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
530 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
532 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
535 /* Wire the outputs from each CPU's generic timer and the GICv3
536 * maintenance interrupt signal to the appropriate GIC PPI inputs,
537 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
539 for (i
= 0; i
< smp_cpus
; i
++) {
540 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
541 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
543 /* Mapping from the output timer irq lines from the CPU to the
544 * GIC PPI inputs we use for the virt board.
546 const int timer_irq
[] = {
547 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
548 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
549 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
550 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
553 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
554 qdev_connect_gpio_out(cpudev
, irq
,
555 qdev_get_gpio_in(gicdev
,
556 ppibase
+ timer_irq
[irq
]));
559 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt", 0,
560 qdev_get_gpio_in(gicdev
, ppibase
561 + ARCH_GICV3_MAINT_IRQ
));
562 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
563 qdev_get_gpio_in(gicdev
, ppibase
566 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
567 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
568 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
569 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
570 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
571 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
572 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
575 for (i
= 0; i
< NUM_IRQS
; i
++) {
576 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
579 fdt_add_gic_node(vms
);
581 if (type
== 3 && vms
->its
) {
582 create_its(vms
, gicdev
);
583 } else if (type
== 2) {
584 create_v2m(vms
, pic
);
588 static void create_uart(const VirtMachineState
*vms
, qemu_irq
*pic
, int uart
,
589 MemoryRegion
*mem
, Chardev
*chr
)
592 hwaddr base
= vms
->memmap
[uart
].base
;
593 hwaddr size
= vms
->memmap
[uart
].size
;
594 int irq
= vms
->irqmap
[uart
];
595 const char compat
[] = "arm,pl011\0arm,primecell";
596 const char clocknames
[] = "uartclk\0apb_pclk";
597 DeviceState
*dev
= qdev_create(NULL
, "pl011");
598 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
600 qdev_prop_set_chr(dev
, "chardev", chr
);
601 qdev_init_nofail(dev
);
602 memory_region_add_subregion(mem
, base
,
603 sysbus_mmio_get_region(s
, 0));
604 sysbus_connect_irq(s
, 0, pic
[irq
]);
606 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
607 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
608 /* Note that we can't use setprop_string because of the embedded NUL */
609 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible",
610 compat
, sizeof(compat
));
611 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
613 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
614 GIC_FDT_IRQ_TYPE_SPI
, irq
,
615 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
616 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "clocks",
617 vms
->clock_phandle
, vms
->clock_phandle
);
618 qemu_fdt_setprop(vms
->fdt
, nodename
, "clock-names",
619 clocknames
, sizeof(clocknames
));
621 if (uart
== VIRT_UART
) {
622 qemu_fdt_setprop_string(vms
->fdt
, "/chosen", "stdout-path", nodename
);
624 /* Mark as not usable by the normal world */
625 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
626 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
632 static void create_rtc(const VirtMachineState
*vms
, qemu_irq
*pic
)
635 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
636 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
637 int irq
= vms
->irqmap
[VIRT_RTC
];
638 const char compat
[] = "arm,pl031\0arm,primecell";
640 sysbus_create_simple("pl031", base
, pic
[irq
]);
642 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
643 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
644 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
645 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
647 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
648 GIC_FDT_IRQ_TYPE_SPI
, irq
,
649 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
650 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
651 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
655 static DeviceState
*gpio_key_dev
;
656 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
658 /* use gpio Pin 3 for power button event */
659 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
662 static Notifier virt_system_powerdown_notifier
= {
663 .notify
= virt_powerdown_req
666 static void create_gpio(const VirtMachineState
*vms
, qemu_irq
*pic
)
669 DeviceState
*pl061_dev
;
670 hwaddr base
= vms
->memmap
[VIRT_GPIO
].base
;
671 hwaddr size
= vms
->memmap
[VIRT_GPIO
].size
;
672 int irq
= vms
->irqmap
[VIRT_GPIO
];
673 const char compat
[] = "arm,pl061\0arm,primecell";
675 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
677 uint32_t phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
678 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
679 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
680 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
682 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
683 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#gpio-cells", 2);
684 qemu_fdt_setprop(vms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
685 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
686 GIC_FDT_IRQ_TYPE_SPI
, irq
,
687 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
688 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
689 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
690 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", phandle
);
692 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
693 qdev_get_gpio_in(pl061_dev
, 3));
694 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys");
695 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
696 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#size-cells", 0);
697 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#address-cells", 1);
699 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys/poweroff");
700 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys/poweroff",
701 "label", "GPIO Key Poweroff");
702 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys/poweroff", "linux,code",
704 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-keys/poweroff",
705 "gpios", phandle
, 3, 0);
707 /* connect powerdown request */
708 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
713 static void create_virtio_devices(const VirtMachineState
*vms
, qemu_irq
*pic
)
716 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
718 /* We create the transports in forwards order. Since qbus_realize()
719 * prepends (not appends) new child buses, the incrementing loop below will
720 * create a list of virtio-mmio buses with decreasing base addresses.
722 * When a -device option is processed from the command line,
723 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
724 * order. The upshot is that -device options in increasing command line
725 * order are mapped to virtio-mmio buses with decreasing base addresses.
727 * When this code was originally written, that arrangement ensured that the
728 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
729 * the first -device on the command line. (The end-to-end order is a
730 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
731 * guest kernel's name-to-address assignment strategy.)
733 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
734 * the message, if not necessarily the code, of commit 70161ff336.
735 * Therefore the loop now establishes the inverse of the original intent.
737 * Unfortunately, we can't counteract the kernel change by reversing the
738 * loop; it would break existing command lines.
740 * In any case, the kernel makes no guarantee about the stability of
741 * enumeration order of virtio devices (as demonstrated by it changing
742 * between kernel versions). For reliable and stable identification
743 * of disks users must use UUIDs or similar mechanisms.
745 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
746 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
747 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
749 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
752 /* We add dtb nodes in reverse order so that they appear in the finished
753 * device tree lowest address first.
755 * Note that this mapping is independent of the loop above. The previous
756 * loop influences virtio device to virtio transport assignment, whereas
757 * this loop controls how virtio transports are laid out in the dtb.
759 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
761 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
762 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
764 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
765 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
766 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
767 "compatible", "virtio,mmio");
768 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
770 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
771 GIC_FDT_IRQ_TYPE_SPI
, irq
,
772 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
773 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
778 static void create_one_flash(const char *name
, hwaddr flashbase
,
779 hwaddr flashsize
, const char *file
,
780 MemoryRegion
*sysmem
)
782 /* Create and map a single flash device. We use the same
783 * parameters as the flash devices on the Versatile Express board.
785 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
786 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
787 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
788 const uint64_t sectorlength
= 256 * 1024;
791 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
795 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
796 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
797 qdev_prop_set_uint8(dev
, "width", 4);
798 qdev_prop_set_uint8(dev
, "device-width", 2);
799 qdev_prop_set_bit(dev
, "big-endian", false);
800 qdev_prop_set_uint16(dev
, "id0", 0x89);
801 qdev_prop_set_uint16(dev
, "id1", 0x18);
802 qdev_prop_set_uint16(dev
, "id2", 0x00);
803 qdev_prop_set_uint16(dev
, "id3", 0x00);
804 qdev_prop_set_string(dev
, "name", name
);
805 qdev_init_nofail(dev
);
807 memory_region_add_subregion(sysmem
, flashbase
,
808 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0));
814 if (drive_get(IF_PFLASH
, 0, 0)) {
815 error_report("The contents of the first flash device may be "
816 "specified with -bios or with -drive if=pflash... "
817 "but you cannot use both options at once");
820 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, file
);
822 error_report("Could not find ROM image '%s'", file
);
825 image_size
= load_image_mr(fn
, sysbus_mmio_get_region(sbd
, 0));
827 if (image_size
< 0) {
828 error_report("Could not load ROM image '%s'", file
);
834 static void create_flash(const VirtMachineState
*vms
,
835 MemoryRegion
*sysmem
,
836 MemoryRegion
*secure_sysmem
)
838 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
839 * Any file passed via -bios goes in the first of these.
840 * sysmem is the system memory space. secure_sysmem is the secure view
841 * of the system, and the first flash device should be made visible only
842 * there. The second flash device is visible to both secure and nonsecure.
843 * If sysmem == secure_sysmem this means there is no separate Secure
844 * address space and both flash devices are generally visible.
846 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
847 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
850 create_one_flash("virt.flash0", flashbase
, flashsize
,
851 bios_name
, secure_sysmem
);
852 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
,
855 if (sysmem
== secure_sysmem
) {
856 /* Report both flash devices as a single node in the DT */
857 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
858 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
859 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
860 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
861 2, flashbase
, 2, flashsize
,
862 2, flashbase
+ flashsize
, 2, flashsize
);
863 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
866 /* Report the devices as separate nodes so we can mark one as
867 * only visible to the secure world.
869 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
870 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
871 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
872 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
873 2, flashbase
, 2, flashsize
);
874 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
875 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
876 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
879 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
880 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
881 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
882 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
883 2, flashbase
+ flashsize
, 2, flashsize
);
884 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
889 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
891 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
892 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
896 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
897 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
899 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
900 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
901 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
902 "compatible", "qemu,fw-cfg-mmio");
903 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
905 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
910 static void create_pcie_irq_map(const VirtMachineState
*vms
,
911 uint32_t gic_phandle
,
912 int first_irq
, const char *nodename
)
915 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
916 uint32_t *irq_map
= full_irq_map
;
918 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
919 for (pin
= 0; pin
< 4; pin
++) {
920 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
921 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
922 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
926 devfn
<< 8, 0, 0, /* devfn */
927 pin
+ 1, /* PCI pin */
928 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
930 /* Convert map to big endian */
931 for (i
= 0; i
< 10; i
++) {
932 irq_map
[i
] = cpu_to_be32(map
[i
]);
938 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-map",
939 full_irq_map
, sizeof(full_irq_map
));
941 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupt-map-mask",
942 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
946 static void create_smmu(const VirtMachineState
*vms
, qemu_irq
*pic
,
950 const char compat
[] = "arm,smmu-v3";
951 int irq
= vms
->irqmap
[VIRT_SMMU
];
953 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
954 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
955 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
958 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
962 dev
= qdev_create(NULL
, "arm-smmuv3");
964 object_property_set_link(OBJECT(dev
), OBJECT(bus
), "primary-bus",
966 qdev_init_nofail(dev
);
967 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
968 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
969 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
972 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
973 qemu_fdt_add_subnode(vms
->fdt
, node
);
974 qemu_fdt_setprop(vms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
975 qemu_fdt_setprop_sized_cells(vms
->fdt
, node
, "reg", 2, base
, 2, size
);
977 qemu_fdt_setprop_cells(vms
->fdt
, node
, "interrupts",
978 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
979 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
980 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
981 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
983 qemu_fdt_setprop(vms
->fdt
, node
, "interrupt-names", irq_names
,
986 qemu_fdt_setprop_cell(vms
->fdt
, node
, "clocks", vms
->clock_phandle
);
987 qemu_fdt_setprop_string(vms
->fdt
, node
, "clock-names", "apb_pclk");
988 qemu_fdt_setprop(vms
->fdt
, node
, "dma-coherent", NULL
, 0);
990 qemu_fdt_setprop_cell(vms
->fdt
, node
, "#iommu-cells", 1);
992 qemu_fdt_setprop_cell(vms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
996 static void create_pcie(VirtMachineState
*vms
, qemu_irq
*pic
)
998 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
999 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1000 hwaddr base_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
1001 hwaddr size_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
1002 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1003 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1004 hwaddr base_ecam
= vms
->memmap
[VIRT_PCIE_ECAM
].base
;
1005 hwaddr size_ecam
= vms
->memmap
[VIRT_PCIE_ECAM
].size
;
1006 hwaddr base
= base_mmio
;
1007 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1008 int irq
= vms
->irqmap
[VIRT_PCIE
];
1009 MemoryRegion
*mmio_alias
;
1010 MemoryRegion
*mmio_reg
;
1011 MemoryRegion
*ecam_alias
;
1012 MemoryRegion
*ecam_reg
;
1018 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
1019 qdev_init_nofail(dev
);
1021 /* Map only the first size_ecam bytes of ECAM space */
1022 ecam_alias
= g_new0(MemoryRegion
, 1);
1023 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1024 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1025 ecam_reg
, 0, size_ecam
);
1026 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1028 /* Map the MMIO window into system address space so as to expose
1029 * the section of PCI MMIO space which starts at the same base address
1030 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1033 mmio_alias
= g_new0(MemoryRegion
, 1);
1034 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1035 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1036 mmio_reg
, base_mmio
, size_mmio
);
1037 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1040 /* Map high MMIO space */
1041 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1043 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1044 mmio_reg
, base_mmio_high
, size_mmio_high
);
1045 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1049 /* Map IO port space */
1050 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1052 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1053 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1054 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1057 pci
= PCI_HOST_BRIDGE(dev
);
1059 for (i
= 0; i
< nb_nics
; i
++) {
1060 NICInfo
*nd
= &nd_table
[i
];
1063 nd
->model
= g_strdup("virtio");
1066 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1070 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1071 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1072 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1073 "compatible", "pci-host-ecam-generic");
1074 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "pci");
1075 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 3);
1076 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 2);
1077 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "linux,pci-domain", 0);
1078 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "bus-range", 0,
1080 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1082 if (vms
->msi_phandle
) {
1083 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "msi-parent",
1087 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1088 2, base_ecam
, 2, size_ecam
);
1091 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1092 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1093 2, base_pio
, 2, size_pio
,
1094 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1095 2, base_mmio
, 2, size_mmio
,
1096 1, FDT_PCI_RANGE_MMIO_64BIT
,
1098 2, base_mmio_high
, 2, size_mmio_high
);
1100 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1101 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1102 2, base_pio
, 2, size_pio
,
1103 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1104 2, base_mmio
, 2, size_mmio
);
1107 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 1);
1108 create_pcie_irq_map(vms
, vms
->gic_phandle
, irq
, nodename
);
1111 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
1113 create_smmu(vms
, pic
, pci
->bus
);
1115 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "iommu-map",
1116 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1122 static void create_platform_bus(VirtMachineState
*vms
, qemu_irq
*pic
)
1127 MemoryRegion
*sysmem
= get_system_memory();
1129 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1130 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1131 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1132 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1133 qdev_init_nofail(dev
);
1134 vms
->platform_bus_dev
= dev
;
1136 s
= SYS_BUS_DEVICE(dev
);
1137 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1138 int irqn
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1139 sysbus_connect_irq(s
, i
, pic
[irqn
]);
1142 memory_region_add_subregion(sysmem
,
1143 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1144 sysbus_mmio_get_region(s
, 0));
1147 static void create_secure_ram(VirtMachineState
*vms
,
1148 MemoryRegion
*secure_sysmem
)
1150 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1152 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1153 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1155 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1157 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1159 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1160 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1161 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "memory");
1162 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1163 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1164 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1169 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1171 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1174 *fdt_size
= board
->fdt_size
;
1178 static void virt_build_smbios(VirtMachineState
*vms
)
1180 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1181 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1182 uint8_t *smbios_tables
, *smbios_anchor
;
1183 size_t smbios_tables_len
, smbios_anchor_len
;
1184 const char *product
= "QEMU Virtual Machine";
1190 if (kvm_enabled()) {
1191 product
= "KVM Virtual Machine";
1194 smbios_set_defaults("QEMU", product
,
1195 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1196 true, SMBIOS_ENTRY_POINT_30
);
1198 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1199 &smbios_anchor
, &smbios_anchor_len
);
1201 if (smbios_anchor
) {
1202 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1203 smbios_tables
, smbios_tables_len
);
1204 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1205 smbios_anchor
, smbios_anchor_len
);
1210 void virt_machine_done(Notifier
*notifier
, void *data
)
1212 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1214 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1215 struct arm_boot_info
*info
= &vms
->bootinfo
;
1216 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1219 * If the user provided a dtb, we assume the dynamic sysbus nodes
1220 * already are integrated there. This corresponds to a use case where
1221 * the dynamic sysbus nodes are complex and their generation is not yet
1222 * supported. In that case the user can take charge of the guest dt
1223 * while qemu takes charge of the qom stuff.
1225 if (info
->dtb_filename
== NULL
) {
1226 platform_bus_add_all_fdt_nodes(vms
->fdt
, "/intc",
1227 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1228 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1229 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1231 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
) < 0) {
1235 virt_acpi_setup(vms
);
1236 virt_build_smbios(vms
);
1239 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1241 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1242 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1244 if (!vmc
->disallow_affinity_adjustment
) {
1245 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1246 * GIC's target-list limitations. 32-bit KVM hosts currently
1247 * always create clusters of 4 CPUs, but that is expected to
1248 * change when they gain support for gicv3. When KVM is enabled
1249 * it will override the changes we make here, therefore our
1250 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1251 * and to improve SGI efficiency.
1253 if (vms
->gic_version
== 3) {
1254 clustersz
= GICV3_TARGETLIST_BITS
;
1256 clustersz
= GIC_TARGETLIST_BITS
;
1259 return arm_cpu_mp_affinity(idx
, clustersz
);
1262 static void machvirt_init(MachineState
*machine
)
1264 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1265 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1266 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1267 const CPUArchIdList
*possible_cpus
;
1268 qemu_irq pic
[NUM_IRQS
];
1269 MemoryRegion
*sysmem
= get_system_memory();
1270 MemoryRegion
*secure_sysmem
= NULL
;
1271 int n
, virt_max_cpus
;
1272 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1273 bool firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1275 /* We can probe only here because during property set
1276 * KVM is not available yet
1278 if (vms
->gic_version
<= 0) {
1279 /* "host" or "max" */
1280 if (!kvm_enabled()) {
1281 if (vms
->gic_version
== 0) {
1282 error_report("gic-version=host requires KVM");
1285 /* "max": currently means 3 for TCG */
1286 vms
->gic_version
= 3;
1289 vms
->gic_version
= kvm_arm_vgic_probe();
1290 if (!vms
->gic_version
) {
1292 "Unable to determine GIC version supported by host");
1298 if (!cpu_type_valid(machine
->cpu_type
)) {
1299 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
1303 /* If we have an EL3 boot ROM then the assumption is that it will
1304 * implement PSCI itself, so disable QEMU's internal implementation
1305 * so it doesn't get in the way. Instead of starting secondary
1306 * CPUs in PSCI powerdown state we will start them all running and
1307 * let the boot ROM sort them out.
1308 * The usual case is that we do use QEMU's PSCI implementation;
1309 * if the guest has EL2 then we will use SMC as the conduit,
1310 * and otherwise we will use HVC (for backwards compatibility and
1311 * because if we're using KVM then we must use HVC).
1313 if (vms
->secure
&& firmware_loaded
) {
1314 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
1315 } else if (vms
->virt
) {
1316 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
1318 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
1321 /* The maximum number of CPUs depends on the GIC version, or on how
1322 * many redistributors we can fit into the memory map.
1324 if (vms
->gic_version
== 3) {
1325 virt_max_cpus
= vms
->memmap
[VIRT_GIC_REDIST
].size
/ 0x20000;
1327 virt_max_cpus
= GIC_NCPU
;
1330 if (max_cpus
> virt_max_cpus
) {
1331 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1332 "supported by machine 'mach-virt' (%d)",
1333 max_cpus
, virt_max_cpus
);
1337 vms
->smp_cpus
= smp_cpus
;
1339 if (machine
->ram_size
> vms
->memmap
[VIRT_MEM
].size
) {
1340 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB
);
1344 if (vms
->virt
&& kvm_enabled()) {
1345 error_report("mach-virt: KVM does not support providing "
1346 "Virtualization extensions to the guest CPU");
1351 if (kvm_enabled()) {
1352 error_report("mach-virt: KVM does not support Security extensions");
1356 /* The Secure view of the world is the same as the NonSecure,
1357 * but with a few extra devices. Create it as a container region
1358 * containing the system memory at low priority; any secure-only
1359 * devices go in at higher priority and take precedence.
1361 secure_sysmem
= g_new(MemoryRegion
, 1);
1362 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1364 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1369 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1370 for (n
= 0; n
< possible_cpus
->len
; n
++) {
1374 if (n
>= smp_cpus
) {
1378 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
1379 object_property_set_int(cpuobj
, possible_cpus
->cpus
[n
].arch_id
,
1380 "mp-affinity", NULL
);
1385 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
1389 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1392 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2", NULL
)) {
1393 object_property_set_bool(cpuobj
, false, "has_el2", NULL
);
1396 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
) {
1397 object_property_set_int(cpuobj
, vms
->psci_conduit
,
1398 "psci-conduit", NULL
);
1400 /* Secondary CPUs start in PSCI powered-down state */
1402 object_property_set_bool(cpuobj
, true,
1403 "start-powered-off", NULL
);
1407 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu", NULL
)) {
1408 object_property_set_bool(cpuobj
, false, "pmu", NULL
);
1411 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1412 object_property_set_int(cpuobj
, vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1413 "reset-cbar", &error_abort
);
1416 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1419 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1420 "secure-memory", &error_abort
);
1423 object_property_set_bool(cpuobj
, true, "realized", &error_fatal
);
1424 object_unref(cpuobj
);
1426 fdt_add_timer_nodes(vms
);
1427 fdt_add_cpu_nodes(vms
);
1429 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1431 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
, ram
);
1433 create_flash(vms
, sysmem
, secure_sysmem
? secure_sysmem
: sysmem
);
1435 create_gic(vms
, pic
);
1437 fdt_add_pmu_nodes(vms
);
1439 create_uart(vms
, pic
, VIRT_UART
, sysmem
, serial_hd(0));
1442 create_secure_ram(vms
, secure_sysmem
);
1443 create_uart(vms
, pic
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
1446 create_rtc(vms
, pic
);
1448 create_pcie(vms
, pic
);
1450 create_gpio(vms
, pic
);
1452 /* Create mmio transports, so the user can create virtio backends
1453 * (which will be automatically plugged in to the transports). If
1454 * no backend is created the transport will just sit harmlessly idle.
1456 create_virtio_devices(vms
, pic
);
1458 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
1459 rom_set_fw(vms
->fw_cfg
);
1461 create_platform_bus(vms
, pic
);
1463 vms
->bootinfo
.ram_size
= machine
->ram_size
;
1464 vms
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1465 vms
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1466 vms
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1467 vms
->bootinfo
.nb_cpus
= smp_cpus
;
1468 vms
->bootinfo
.board_id
= -1;
1469 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
1470 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
1471 vms
->bootinfo
.skip_dtb_autoload
= true;
1472 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
1473 arm_load_kernel(ARM_CPU(first_cpu
), &vms
->bootinfo
);
1475 vms
->machine_done
.notify
= virt_machine_done
;
1476 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
1479 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1481 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1486 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1488 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1490 vms
->secure
= value
;
1493 static bool virt_get_virt(Object
*obj
, Error
**errp
)
1495 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1500 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
1502 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1507 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1509 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1511 return vms
->highmem
;
1514 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1516 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1518 vms
->highmem
= value
;
1521 static bool virt_get_its(Object
*obj
, Error
**errp
)
1523 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1528 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
1530 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1535 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1537 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1538 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1540 return g_strdup(val
);
1543 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1545 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1547 if (!strcmp(value
, "3")) {
1548 vms
->gic_version
= 3;
1549 } else if (!strcmp(value
, "2")) {
1550 vms
->gic_version
= 2;
1551 } else if (!strcmp(value
, "host")) {
1552 vms
->gic_version
= 0; /* Will probe later */
1553 } else if (!strcmp(value
, "max")) {
1554 vms
->gic_version
= -1; /* Will probe later */
1556 error_setg(errp
, "Invalid gic-version value");
1557 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
1561 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
1563 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1565 switch (vms
->iommu
) {
1566 case VIRT_IOMMU_NONE
:
1567 return g_strdup("none");
1568 case VIRT_IOMMU_SMMUV3
:
1569 return g_strdup("smmuv3");
1571 g_assert_not_reached();
1575 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
1577 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1579 if (!strcmp(value
, "smmuv3")) {
1580 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
1581 } else if (!strcmp(value
, "none")) {
1582 vms
->iommu
= VIRT_IOMMU_NONE
;
1584 error_setg(errp
, "Invalid iommu value");
1585 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
1589 static CpuInstanceProperties
1590 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
1592 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
1593 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1595 assert(cpu_index
< possible_cpus
->len
);
1596 return possible_cpus
->cpus
[cpu_index
].props
;
1599 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
1601 return idx
% nb_numa_nodes
;
1604 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
1607 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
1609 if (ms
->possible_cpus
) {
1610 assert(ms
->possible_cpus
->len
== max_cpus
);
1611 return ms
->possible_cpus
;
1614 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
1615 sizeof(CPUArchId
) * max_cpus
);
1616 ms
->possible_cpus
->len
= max_cpus
;
1617 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
1618 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
1619 ms
->possible_cpus
->cpus
[n
].arch_id
=
1620 virt_cpu_mp_affinity(vms
, n
);
1621 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
1622 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
1624 return ms
->possible_cpus
;
1627 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
1628 DeviceState
*dev
, Error
**errp
)
1630 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
1632 if (vms
->platform_bus_dev
) {
1633 if (object_dynamic_cast(OBJECT(dev
), TYPE_SYS_BUS_DEVICE
)) {
1634 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
1635 SYS_BUS_DEVICE(dev
));
1640 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
1643 if (object_dynamic_cast(OBJECT(dev
), TYPE_SYS_BUS_DEVICE
)) {
1644 return HOTPLUG_HANDLER(machine
);
1650 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1652 MachineClass
*mc
= MACHINE_CLASS(oc
);
1653 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
1655 mc
->init
= machvirt_init
;
1656 /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1657 * it later in machvirt_init, where we have more information about the
1658 * configuration of the particular instance.
1661 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
1662 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
1663 mc
->block_default_type
= IF_VIRTIO
;
1665 mc
->pci_allow_0_address
= true;
1666 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1667 mc
->minimum_page_bits
= 12;
1668 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
1669 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
1670 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
1671 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
1672 assert(!mc
->get_hotplug_handler
);
1673 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
1674 hc
->plug
= virt_machine_device_plug_cb
;
1677 static const TypeInfo virt_machine_info
= {
1678 .name
= TYPE_VIRT_MACHINE
,
1679 .parent
= TYPE_MACHINE
,
1681 .instance_size
= sizeof(VirtMachineState
),
1682 .class_size
= sizeof(VirtMachineClass
),
1683 .class_init
= virt_machine_class_init
,
1684 .interfaces
= (InterfaceInfo
[]) {
1685 { TYPE_HOTPLUG_HANDLER
},
1690 static void machvirt_machine_init(void)
1692 type_register_static(&virt_machine_info
);
1694 type_init(machvirt_machine_init
);
1696 static void virt_2_12_instance_init(Object
*obj
)
1698 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1699 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1701 /* EL3 is disabled by default on virt: this makes us consistent
1702 * between KVM and TCG for this board, and it also allows us to
1703 * boot UEFI blobs which assume no TrustZone support.
1705 vms
->secure
= false;
1706 object_property_add_bool(obj
, "secure", virt_get_secure
,
1707 virt_set_secure
, NULL
);
1708 object_property_set_description(obj
, "secure",
1709 "Set on/off to enable/disable the ARM "
1710 "Security Extensions (TrustZone)",
1713 /* EL2 is also disabled by default, for similar reasons */
1715 object_property_add_bool(obj
, "virtualization", virt_get_virt
,
1716 virt_set_virt
, NULL
);
1717 object_property_set_description(obj
, "virtualization",
1718 "Set on/off to enable/disable emulating a "
1719 "guest CPU which implements the ARM "
1720 "Virtualization Extensions",
1723 /* High memory is enabled by default */
1724 vms
->highmem
= true;
1725 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1726 virt_set_highmem
, NULL
);
1727 object_property_set_description(obj
, "highmem",
1728 "Set on/off to enable/disable using "
1729 "physical address space above 32 bits",
1731 /* Default GIC type is v2 */
1732 vms
->gic_version
= 2;
1733 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1734 virt_set_gic_version
, NULL
);
1735 object_property_set_description(obj
, "gic-version",
1737 "Valid values are 2, 3 and host", NULL
);
1742 /* Default allows ITS instantiation */
1744 object_property_add_bool(obj
, "its", virt_get_its
,
1745 virt_set_its
, NULL
);
1746 object_property_set_description(obj
, "its",
1747 "Set on/off to enable/disable "
1748 "ITS instantiation",
1752 /* Default disallows iommu instantiation */
1753 vms
->iommu
= VIRT_IOMMU_NONE
;
1754 object_property_add_str(obj
, "iommu", virt_get_iommu
, virt_set_iommu
, NULL
);
1755 object_property_set_description(obj
, "iommu",
1756 "Set the IOMMU type. "
1757 "Valid values are none and smmuv3",
1760 vms
->memmap
= a15memmap
;
1761 vms
->irqmap
= a15irqmap
;
1764 static void virt_machine_2_12_options(MachineClass
*mc
)
1767 DEFINE_VIRT_MACHINE_AS_LATEST(2, 12)
1769 #define VIRT_COMPAT_2_11 \
1772 static void virt_2_11_instance_init(Object
*obj
)
1774 virt_2_12_instance_init(obj
);
1777 static void virt_machine_2_11_options(MachineClass
*mc
)
1779 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1781 virt_machine_2_12_options(mc
);
1782 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_11
);
1783 vmc
->smbios_old_sys_ver
= true;
1785 DEFINE_VIRT_MACHINE(2, 11)
1787 #define VIRT_COMPAT_2_10 \
1790 static void virt_2_10_instance_init(Object
*obj
)
1792 virt_2_11_instance_init(obj
);
1795 static void virt_machine_2_10_options(MachineClass
*mc
)
1797 virt_machine_2_11_options(mc
);
1798 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_10
);
1800 DEFINE_VIRT_MACHINE(2, 10)
1802 #define VIRT_COMPAT_2_9 \
1805 static void virt_2_9_instance_init(Object
*obj
)
1807 virt_2_10_instance_init(obj
);
1810 static void virt_machine_2_9_options(MachineClass
*mc
)
1812 virt_machine_2_10_options(mc
);
1813 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_9
);
1815 DEFINE_VIRT_MACHINE(2, 9)
1817 #define VIRT_COMPAT_2_8 \
1820 static void virt_2_8_instance_init(Object
*obj
)
1822 virt_2_9_instance_init(obj
);
1825 static void virt_machine_2_8_options(MachineClass
*mc
)
1827 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1829 virt_machine_2_9_options(mc
);
1830 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_8
);
1831 /* For 2.8 and earlier we falsely claimed in the DT that
1832 * our timers were edge-triggered, not level-triggered.
1834 vmc
->claim_edge_triggered_timers
= true;
1836 DEFINE_VIRT_MACHINE(2, 8)
1838 #define VIRT_COMPAT_2_7 \
1841 static void virt_2_7_instance_init(Object
*obj
)
1843 virt_2_8_instance_init(obj
);
1846 static void virt_machine_2_7_options(MachineClass
*mc
)
1848 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1850 virt_machine_2_8_options(mc
);
1851 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_7
);
1852 /* ITS was introduced with 2.8 */
1854 /* Stick with 1K pages for migration compatibility */
1855 mc
->minimum_page_bits
= 0;
1857 DEFINE_VIRT_MACHINE(2, 7)
1859 #define VIRT_COMPAT_2_6 \
1862 static void virt_2_6_instance_init(Object
*obj
)
1864 virt_2_7_instance_init(obj
);
1867 static void virt_machine_2_6_options(MachineClass
*mc
)
1869 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1871 virt_machine_2_7_options(mc
);
1872 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_6
);
1873 vmc
->disallow_affinity_adjustment
= true;
1874 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
1877 DEFINE_VIRT_MACHINE(2, 6)