2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "hw/sysbus.h"
33 #include "hw/arm/arm.h"
34 #include "hw/arm/primecell.h"
35 #include "hw/arm/virt.h"
36 #include "hw/devices.h"
38 #include "sysemu/block-backend.h"
39 #include "sysemu/device_tree.h"
40 #include "sysemu/sysemu.h"
41 #include "sysemu/kvm.h"
42 #include "hw/boards.h"
43 #include "hw/loader.h"
44 #include "exec/address-spaces.h"
45 #include "qemu/bitops.h"
46 #include "qemu/error-report.h"
47 #include "hw/pci-host/gpex.h"
48 #include "hw/arm/virt-acpi-build.h"
49 #include "hw/arm/sysbus-fdt.h"
50 #include "hw/platform-bus.h"
51 #include "hw/arm/fdt.h"
52 #include "hw/intc/arm_gic_common.h"
54 #include "hw/smbios/smbios.h"
55 #include "qapi/visitor.h"
56 #include "standard-headers/linux/input.h"
58 /* Number of external interrupt lines to configure the GIC with */
61 #define PLATFORM_BUS_NUM_IRQS 64
63 static ARMPlatformBusSystemParams platform_bus_params
;
65 typedef struct VirtBoardInfo
{
66 struct arm_boot_info bootinfo
;
67 const char *cpu_model
;
68 const MemMapEntry
*memmap
;
73 uint32_t clock_phandle
;
81 VirtBoardInfo
*daughterboard
;
91 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
92 #define VIRT_MACHINE(obj) \
93 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
94 #define VIRT_MACHINE_GET_CLASS(obj) \
95 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
96 #define VIRT_MACHINE_CLASS(klass) \
97 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
99 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
100 * RAM can go up to the 256GB mark, leaving 256GB of the physical
101 * address space unallocated and free for future use between 256G and 512G.
102 * If we need to provide more RAM to VMs in the future then we need to:
103 * * allocate a second bank of RAM starting at 2TB and working up
104 * * fix the DT and ACPI table generation code in QEMU to correctly
105 * report two split lumps of RAM to the guest
106 * * fix KVM in the host kernel to allow guests with >40 bit address spaces
107 * (We don't want to fill all the way up to 512GB with RAM because
108 * we might want it for non-RAM purposes later. Conversely it seems
109 * reasonable to assume that anybody configuring a VM with a quarter
110 * of a terabyte of RAM will be doing it on a host with more than a
111 * terabyte of physical address space.)
113 #define RAMLIMIT_GB 255
114 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
116 /* Addresses and sizes of our components.
117 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
118 * 128MB..256MB is used for miscellaneous device I/O.
119 * 256MB..1GB is reserved for possible future PCI support (ie where the
120 * PCI memory window will go if we add a PCI host controller).
121 * 1GB and up is RAM (which may happily spill over into the
122 * high memory region beyond 4GB).
123 * This represents a compromise between how much RAM can be given to
124 * a 32 bit VM and leaving space for expansion and in particular for PCI.
125 * Note that devices should generally be placed at multiples of 0x10000,
126 * to accommodate guests using 64K pages.
128 static const MemMapEntry a15memmap
[] = {
129 /* Space up to 0x8000000 is reserved for a boot ROM */
130 [VIRT_FLASH
] = { 0, 0x08000000 },
131 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
132 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
133 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
134 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
135 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
136 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
137 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
138 /* This redistributor space allows up to 2*64kB*123 CPUs */
139 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
140 [VIRT_UART
] = { 0x09000000, 0x00001000 },
141 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
142 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
143 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
144 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
145 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
146 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
147 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
148 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
149 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
150 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
151 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
152 [VIRT_MEM
] = { 0x40000000, RAMLIMIT_BYTES
},
153 /* Second PCIe window, 512GB wide at the 512GB boundary */
154 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
157 static const int a15irqmap
[] = {
160 [VIRT_PCIE
] = 3, /* ... to 6 */
162 [VIRT_SECURE_UART
] = 8,
163 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
164 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
165 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
168 static VirtBoardInfo machines
[] = {
170 .cpu_model
= "cortex-a15",
175 .cpu_model
= "cortex-a53",
180 .cpu_model
= "cortex-a57",
191 static VirtBoardInfo
*find_machine_info(const char *cpu
)
195 for (i
= 0; i
< ARRAY_SIZE(machines
); i
++) {
196 if (strcmp(cpu
, machines
[i
].cpu_model
) == 0) {
203 static void create_fdt(VirtBoardInfo
*vbi
)
205 void *fdt
= create_device_tree(&vbi
->fdt_size
);
208 error_report("create_device_tree() failed");
215 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
216 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
217 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
220 * /chosen and /memory nodes must exist for load_dtb
221 * to fill in necessary properties later
223 qemu_fdt_add_subnode(fdt
, "/chosen");
224 qemu_fdt_add_subnode(fdt
, "/memory");
225 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
227 /* Clock node, for the benefit of the UART. The kernel device tree
228 * binding documentation claims the PL011 node clock properties are
229 * optional but in practice if you omit them the kernel refuses to
230 * probe for the device.
232 vbi
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
233 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
234 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
235 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
236 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
237 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
239 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vbi
->clock_phandle
);
243 static void fdt_add_psci_node(const VirtBoardInfo
*vbi
)
245 uint32_t cpu_suspend_fn
;
249 void *fdt
= vbi
->fdt
;
250 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
252 if (!vbi
->using_psci
) {
256 qemu_fdt_add_subnode(fdt
, "/psci");
257 if (armcpu
->psci_version
== 2) {
258 const char comp
[] = "arm,psci-0.2\0arm,psci";
259 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
261 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
262 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
263 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
264 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
265 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
267 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
268 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
269 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
272 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
274 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
275 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
276 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
277 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
280 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
281 * to the instruction that should be used to invoke PSCI functions.
282 * However, the device tree binding uses 'method' instead, so that is
283 * what we should use here.
285 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
287 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
288 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
289 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
290 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
293 static void fdt_add_timer_nodes(const VirtBoardInfo
*vbi
, int gictype
)
295 /* Note that on A15 h/w these interrupts are level-triggered,
296 * but for the GIC implementation provided by both QEMU and KVM
297 * they are edge-triggered.
300 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
303 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
304 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
305 (1 << vbi
->smp_cpus
) - 1);
308 qemu_fdt_add_subnode(vbi
->fdt
, "/timer");
310 armcpu
= ARM_CPU(qemu_get_cpu(0));
311 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
312 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
313 qemu_fdt_setprop(vbi
->fdt
, "/timer", "compatible",
314 compat
, sizeof(compat
));
316 qemu_fdt_setprop_string(vbi
->fdt
, "/timer", "compatible",
319 qemu_fdt_setprop(vbi
->fdt
, "/timer", "always-on", NULL
, 0);
320 qemu_fdt_setprop_cells(vbi
->fdt
, "/timer", "interrupts",
321 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
322 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
323 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
324 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
327 static void fdt_add_cpu_nodes(const VirtBoardInfo
*vbi
)
333 * From Documentation/devicetree/bindings/arm/cpus.txt
334 * On ARM v8 64-bit systems value should be set to 2,
335 * that corresponds to the MPIDR_EL1 register size.
336 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
337 * in the system, #address-cells can be set to 1, since
338 * MPIDR_EL1[63:32] bits are not used for CPUs
341 * Here we actually don't know whether our system is 32- or 64-bit one.
342 * The simplest way to go is to examine affinity IDs of all our CPUs. If
343 * at least one of them has Aff3 populated, we set #address-cells to 2.
345 for (cpu
= 0; cpu
< vbi
->smp_cpus
; cpu
++) {
346 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
348 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
354 qemu_fdt_add_subnode(vbi
->fdt
, "/cpus");
355 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#address-cells", addr_cells
);
356 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#size-cells", 0x0);
358 for (cpu
= vbi
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
359 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
360 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
362 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
363 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "cpu");
364 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible",
365 armcpu
->dtb_compatible
);
367 if (vbi
->using_psci
&& vbi
->smp_cpus
> 1) {
368 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
369 "enable-method", "psci");
372 if (addr_cells
== 2) {
373 qemu_fdt_setprop_u64(vbi
->fdt
, nodename
, "reg",
374 armcpu
->mp_affinity
);
376 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "reg",
377 armcpu
->mp_affinity
);
384 static void fdt_add_v2m_gic_node(VirtBoardInfo
*vbi
)
386 vbi
->v2m_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
387 qemu_fdt_add_subnode(vbi
->fdt
, "/intc/v2m");
388 qemu_fdt_setprop_string(vbi
->fdt
, "/intc/v2m", "compatible",
389 "arm,gic-v2m-frame");
390 qemu_fdt_setprop(vbi
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
391 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc/v2m", "reg",
392 2, vbi
->memmap
[VIRT_GIC_V2M
].base
,
393 2, vbi
->memmap
[VIRT_GIC_V2M
].size
);
394 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc/v2m", "phandle", vbi
->v2m_phandle
);
397 static void fdt_add_gic_node(VirtBoardInfo
*vbi
, int type
)
399 vbi
->gic_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
400 qemu_fdt_setprop_cell(vbi
->fdt
, "/", "interrupt-parent", vbi
->gic_phandle
);
402 qemu_fdt_add_subnode(vbi
->fdt
, "/intc");
403 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#interrupt-cells", 3);
404 qemu_fdt_setprop(vbi
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
405 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#address-cells", 0x2);
406 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#size-cells", 0x2);
407 qemu_fdt_setprop(vbi
->fdt
, "/intc", "ranges", NULL
, 0);
409 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
411 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
412 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
413 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
414 2, vbi
->memmap
[VIRT_GIC_REDIST
].base
,
415 2, vbi
->memmap
[VIRT_GIC_REDIST
].size
);
417 /* 'cortex-a15-gic' means 'GIC v2' */
418 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
419 "arm,cortex-a15-gic");
420 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
421 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
422 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
423 2, vbi
->memmap
[VIRT_GIC_CPU
].base
,
424 2, vbi
->memmap
[VIRT_GIC_CPU
].size
);
427 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "phandle", vbi
->gic_phandle
);
430 static void create_v2m(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
433 int irq
= vbi
->irqmap
[VIRT_GIC_V2M
];
436 dev
= qdev_create(NULL
, "arm-gicv2m");
437 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vbi
->memmap
[VIRT_GIC_V2M
].base
);
438 qdev_prop_set_uint32(dev
, "base-spi", irq
);
439 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
440 qdev_init_nofail(dev
);
442 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
443 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
446 fdt_add_v2m_gic_node(vbi
);
449 static void create_gic(VirtBoardInfo
*vbi
, qemu_irq
*pic
, int type
, bool secure
)
451 /* We create a standalone GIC */
453 SysBusDevice
*gicbusdev
;
457 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
459 gicdev
= qdev_create(NULL
, gictype
);
460 qdev_prop_set_uint32(gicdev
, "revision", type
);
461 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
462 /* Note that the num-irq property counts both internal and external
463 * interrupts; there are always 32 of the former (mandated by GIC spec).
465 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
466 if (!kvm_irqchip_in_kernel()) {
467 qdev_prop_set_bit(gicdev
, "has-security-extensions", secure
);
469 qdev_init_nofail(gicdev
);
470 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
471 sysbus_mmio_map(gicbusdev
, 0, vbi
->memmap
[VIRT_GIC_DIST
].base
);
473 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_REDIST
].base
);
475 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_CPU
].base
);
478 /* Wire the outputs from each CPU's generic timer to the
479 * appropriate GIC PPI inputs, and the GIC's IRQ output to
480 * the CPU's IRQ input.
482 for (i
= 0; i
< smp_cpus
; i
++) {
483 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
484 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
486 /* Mapping from the output timer irq lines from the CPU to the
487 * GIC PPI inputs we use for the virt board.
489 const int timer_irq
[] = {
490 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
491 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
492 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
493 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
496 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
497 qdev_connect_gpio_out(cpudev
, irq
,
498 qdev_get_gpio_in(gicdev
,
499 ppibase
+ timer_irq
[irq
]));
502 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
503 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
504 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
507 for (i
= 0; i
< NUM_IRQS
; i
++) {
508 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
511 fdt_add_gic_node(vbi
, type
);
514 create_v2m(vbi
, pic
);
518 static void create_uart(const VirtBoardInfo
*vbi
, qemu_irq
*pic
, int uart
,
522 hwaddr base
= vbi
->memmap
[uart
].base
;
523 hwaddr size
= vbi
->memmap
[uart
].size
;
524 int irq
= vbi
->irqmap
[uart
];
525 const char compat
[] = "arm,pl011\0arm,primecell";
526 const char clocknames
[] = "uartclk\0apb_pclk";
527 DeviceState
*dev
= qdev_create(NULL
, "pl011");
528 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
530 qdev_init_nofail(dev
);
531 memory_region_add_subregion(mem
, base
,
532 sysbus_mmio_get_region(s
, 0));
533 sysbus_connect_irq(s
, 0, pic
[irq
]);
535 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
536 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
537 /* Note that we can't use setprop_string because of the embedded NUL */
538 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible",
539 compat
, sizeof(compat
));
540 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
542 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
543 GIC_FDT_IRQ_TYPE_SPI
, irq
,
544 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
545 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "clocks",
546 vbi
->clock_phandle
, vbi
->clock_phandle
);
547 qemu_fdt_setprop(vbi
->fdt
, nodename
, "clock-names",
548 clocknames
, sizeof(clocknames
));
550 if (uart
== VIRT_UART
) {
551 qemu_fdt_setprop_string(vbi
->fdt
, "/chosen", "stdout-path", nodename
);
553 /* Mark as not usable by the normal world */
554 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "status", "disabled");
555 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "secure-status", "okay");
561 static void create_rtc(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
564 hwaddr base
= vbi
->memmap
[VIRT_RTC
].base
;
565 hwaddr size
= vbi
->memmap
[VIRT_RTC
].size
;
566 int irq
= vbi
->irqmap
[VIRT_RTC
];
567 const char compat
[] = "arm,pl031\0arm,primecell";
569 sysbus_create_simple("pl031", base
, pic
[irq
]);
571 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
572 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
573 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
574 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
576 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
577 GIC_FDT_IRQ_TYPE_SPI
, irq
,
578 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
579 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
580 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
584 static DeviceState
*pl061_dev
;
585 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
587 /* use gpio Pin 3 for power button event */
588 qemu_set_irq(qdev_get_gpio_in(pl061_dev
, 3), 1);
591 static Notifier virt_system_powerdown_notifier
= {
592 .notify
= virt_powerdown_req
595 static void create_gpio(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
598 hwaddr base
= vbi
->memmap
[VIRT_GPIO
].base
;
599 hwaddr size
= vbi
->memmap
[VIRT_GPIO
].size
;
600 int irq
= vbi
->irqmap
[VIRT_GPIO
];
601 const char compat
[] = "arm,pl061\0arm,primecell";
603 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
605 uint32_t phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
606 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
607 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
608 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
610 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
611 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#gpio-cells", 2);
612 qemu_fdt_setprop(vbi
->fdt
, nodename
, "gpio-controller", NULL
, 0);
613 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
614 GIC_FDT_IRQ_TYPE_SPI
, irq
,
615 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
616 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
617 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
618 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "phandle", phandle
);
620 qemu_fdt_add_subnode(vbi
->fdt
, "/gpio-keys");
621 qemu_fdt_setprop_string(vbi
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
622 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys", "#size-cells", 0);
623 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys", "#address-cells", 1);
625 qemu_fdt_add_subnode(vbi
->fdt
, "/gpio-keys/poweroff");
626 qemu_fdt_setprop_string(vbi
->fdt
, "/gpio-keys/poweroff",
627 "label", "GPIO Key Poweroff");
628 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys/poweroff", "linux,code",
630 qemu_fdt_setprop_cells(vbi
->fdt
, "/gpio-keys/poweroff",
631 "gpios", phandle
, 3, 0);
633 /* connect powerdown request */
634 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
639 static void create_virtio_devices(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
642 hwaddr size
= vbi
->memmap
[VIRT_MMIO
].size
;
644 /* We create the transports in forwards order. Since qbus_realize()
645 * prepends (not appends) new child buses, the incrementing loop below will
646 * create a list of virtio-mmio buses with decreasing base addresses.
648 * When a -device option is processed from the command line,
649 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
650 * order. The upshot is that -device options in increasing command line
651 * order are mapped to virtio-mmio buses with decreasing base addresses.
653 * When this code was originally written, that arrangement ensured that the
654 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
655 * the first -device on the command line. (The end-to-end order is a
656 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
657 * guest kernel's name-to-address assignment strategy.)
659 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
660 * the message, if not necessarily the code, of commit 70161ff336.
661 * Therefore the loop now establishes the inverse of the original intent.
663 * Unfortunately, we can't counteract the kernel change by reversing the
664 * loop; it would break existing command lines.
666 * In any case, the kernel makes no guarantee about the stability of
667 * enumeration order of virtio devices (as demonstrated by it changing
668 * between kernel versions). For reliable and stable identification
669 * of disks users must use UUIDs or similar mechanisms.
671 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
672 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
673 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
675 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
678 /* We add dtb nodes in reverse order so that they appear in the finished
679 * device tree lowest address first.
681 * Note that this mapping is independent of the loop above. The previous
682 * loop influences virtio device to virtio transport assignment, whereas
683 * this loop controls how virtio transports are laid out in the dtb.
685 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
687 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
688 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
690 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
691 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
692 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
693 "compatible", "virtio,mmio");
694 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
696 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
697 GIC_FDT_IRQ_TYPE_SPI
, irq
,
698 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
703 static void create_one_flash(const char *name
, hwaddr flashbase
,
704 hwaddr flashsize
, const char *file
,
705 MemoryRegion
*sysmem
)
707 /* Create and map a single flash device. We use the same
708 * parameters as the flash devices on the Versatile Express board.
710 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
711 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
712 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
713 const uint64_t sectorlength
= 256 * 1024;
716 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
720 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
721 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
722 qdev_prop_set_uint8(dev
, "width", 4);
723 qdev_prop_set_uint8(dev
, "device-width", 2);
724 qdev_prop_set_bit(dev
, "big-endian", false);
725 qdev_prop_set_uint16(dev
, "id0", 0x89);
726 qdev_prop_set_uint16(dev
, "id1", 0x18);
727 qdev_prop_set_uint16(dev
, "id2", 0x00);
728 qdev_prop_set_uint16(dev
, "id3", 0x00);
729 qdev_prop_set_string(dev
, "name", name
);
730 qdev_init_nofail(dev
);
732 memory_region_add_subregion(sysmem
, flashbase
,
733 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0));
739 if (drive_get(IF_PFLASH
, 0, 0)) {
740 error_report("The contents of the first flash device may be "
741 "specified with -bios or with -drive if=pflash... "
742 "but you cannot use both options at once");
745 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, file
);
747 error_report("Could not find ROM image '%s'", file
);
750 image_size
= load_image_mr(fn
, sysbus_mmio_get_region(sbd
, 0));
752 if (image_size
< 0) {
753 error_report("Could not load ROM image '%s'", file
);
759 static void create_flash(const VirtBoardInfo
*vbi
,
760 MemoryRegion
*sysmem
,
761 MemoryRegion
*secure_sysmem
)
763 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
764 * Any file passed via -bios goes in the first of these.
765 * sysmem is the system memory space. secure_sysmem is the secure view
766 * of the system, and the first flash device should be made visible only
767 * there. The second flash device is visible to both secure and nonsecure.
768 * If sysmem == secure_sysmem this means there is no separate Secure
769 * address space and both flash devices are generally visible.
771 hwaddr flashsize
= vbi
->memmap
[VIRT_FLASH
].size
/ 2;
772 hwaddr flashbase
= vbi
->memmap
[VIRT_FLASH
].base
;
775 create_one_flash("virt.flash0", flashbase
, flashsize
,
776 bios_name
, secure_sysmem
);
777 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
,
780 if (sysmem
== secure_sysmem
) {
781 /* Report both flash devices as a single node in the DT */
782 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
783 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
784 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
785 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
786 2, flashbase
, 2, flashsize
,
787 2, flashbase
+ flashsize
, 2, flashsize
);
788 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
791 /* Report the devices as separate nodes so we can mark one as
792 * only visible to the secure world.
794 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
795 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
796 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
797 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
798 2, flashbase
, 2, flashsize
);
799 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
800 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "status", "disabled");
801 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "secure-status", "okay");
804 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
805 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
806 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
807 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
808 2, flashbase
+ flashsize
, 2, flashsize
);
809 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
814 static void create_fw_cfg(const VirtBoardInfo
*vbi
, AddressSpace
*as
)
816 hwaddr base
= vbi
->memmap
[VIRT_FW_CFG
].base
;
817 hwaddr size
= vbi
->memmap
[VIRT_FW_CFG
].size
;
820 fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
822 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
823 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
824 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
825 "compatible", "qemu,fw-cfg-mmio");
826 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
831 static void create_pcie_irq_map(const VirtBoardInfo
*vbi
, uint32_t gic_phandle
,
832 int first_irq
, const char *nodename
)
835 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
836 uint32_t *irq_map
= full_irq_map
;
838 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
839 for (pin
= 0; pin
< 4; pin
++) {
840 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
841 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
842 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
846 devfn
<< 8, 0, 0, /* devfn */
847 pin
+ 1, /* PCI pin */
848 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
850 /* Convert map to big endian */
851 for (i
= 0; i
< 10; i
++) {
852 irq_map
[i
] = cpu_to_be32(map
[i
]);
858 qemu_fdt_setprop(vbi
->fdt
, nodename
, "interrupt-map",
859 full_irq_map
, sizeof(full_irq_map
));
861 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupt-map-mask",
862 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
866 static void create_pcie(const VirtBoardInfo
*vbi
, qemu_irq
*pic
,
869 hwaddr base_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].base
;
870 hwaddr size_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].size
;
871 hwaddr base_mmio_high
= vbi
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
872 hwaddr size_mmio_high
= vbi
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
873 hwaddr base_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].base
;
874 hwaddr size_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].size
;
875 hwaddr base_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].base
;
876 hwaddr size_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].size
;
877 hwaddr base
= base_mmio
;
878 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
879 int irq
= vbi
->irqmap
[VIRT_PCIE
];
880 MemoryRegion
*mmio_alias
;
881 MemoryRegion
*mmio_reg
;
882 MemoryRegion
*ecam_alias
;
883 MemoryRegion
*ecam_reg
;
889 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
890 qdev_init_nofail(dev
);
892 /* Map only the first size_ecam bytes of ECAM space */
893 ecam_alias
= g_new0(MemoryRegion
, 1);
894 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
895 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
896 ecam_reg
, 0, size_ecam
);
897 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
899 /* Map the MMIO window into system address space so as to expose
900 * the section of PCI MMIO space which starts at the same base address
901 * (ie 1:1 mapping for that part of PCI MMIO space visible through
904 mmio_alias
= g_new0(MemoryRegion
, 1);
905 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
906 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
907 mmio_reg
, base_mmio
, size_mmio
);
908 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
911 /* Map high MMIO space */
912 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
914 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
915 mmio_reg
, base_mmio_high
, size_mmio_high
);
916 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
920 /* Map IO port space */
921 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
923 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
924 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
927 pci
= PCI_HOST_BRIDGE(dev
);
929 for (i
= 0; i
< nb_nics
; i
++) {
930 NICInfo
*nd
= &nd_table
[i
];
933 nd
->model
= g_strdup("virtio");
936 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
940 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
941 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
942 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
943 "compatible", "pci-host-ecam-generic");
944 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "pci");
945 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#address-cells", 3);
946 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#size-cells", 2);
947 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "bus-range", 0,
950 if (vbi
->v2m_phandle
) {
951 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "msi-parent",
955 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
956 2, base_ecam
, 2, size_ecam
);
959 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
960 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
961 2, base_pio
, 2, size_pio
,
962 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
963 2, base_mmio
, 2, size_mmio
,
964 1, FDT_PCI_RANGE_MMIO_64BIT
,
966 2, base_mmio_high
, 2, size_mmio_high
);
968 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
969 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
970 2, base_pio
, 2, size_pio
,
971 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
972 2, base_mmio
, 2, size_mmio
);
975 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#interrupt-cells", 1);
976 create_pcie_irq_map(vbi
, vbi
->gic_phandle
, irq
, nodename
);
981 static void create_platform_bus(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
986 ARMPlatformBusFDTParams
*fdt_params
= g_new(ARMPlatformBusFDTParams
, 1);
987 MemoryRegion
*sysmem
= get_system_memory();
989 platform_bus_params
.platform_bus_base
= vbi
->memmap
[VIRT_PLATFORM_BUS
].base
;
990 platform_bus_params
.platform_bus_size
= vbi
->memmap
[VIRT_PLATFORM_BUS
].size
;
991 platform_bus_params
.platform_bus_first_irq
= vbi
->irqmap
[VIRT_PLATFORM_BUS
];
992 platform_bus_params
.platform_bus_num_irqs
= PLATFORM_BUS_NUM_IRQS
;
994 fdt_params
->system_params
= &platform_bus_params
;
995 fdt_params
->binfo
= &vbi
->bootinfo
;
996 fdt_params
->intc
= "/intc";
998 * register a machine init done notifier that creates the device tree
999 * nodes of the platform bus and its children dynamic sysbus devices
1001 arm_register_platform_bus_fdt_creator(fdt_params
);
1003 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1004 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1005 qdev_prop_set_uint32(dev
, "num_irqs",
1006 platform_bus_params
.platform_bus_num_irqs
);
1007 qdev_prop_set_uint32(dev
, "mmio_size",
1008 platform_bus_params
.platform_bus_size
);
1009 qdev_init_nofail(dev
);
1010 s
= SYS_BUS_DEVICE(dev
);
1012 for (i
= 0; i
< platform_bus_params
.platform_bus_num_irqs
; i
++) {
1013 int irqn
= platform_bus_params
.platform_bus_first_irq
+ i
;
1014 sysbus_connect_irq(s
, i
, pic
[irqn
]);
1017 memory_region_add_subregion(sysmem
,
1018 platform_bus_params
.platform_bus_base
,
1019 sysbus_mmio_get_region(s
, 0));
1022 static void create_secure_ram(VirtBoardInfo
*vbi
, MemoryRegion
*secure_sysmem
)
1024 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1026 hwaddr base
= vbi
->memmap
[VIRT_SECURE_MEM
].base
;
1027 hwaddr size
= vbi
->memmap
[VIRT_SECURE_MEM
].size
;
1029 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
, &error_fatal
);
1030 vmstate_register_ram_global(secram
);
1031 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1033 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1034 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
1035 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "memory");
1036 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1037 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "status", "disabled");
1038 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "secure-status", "okay");
1043 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1045 const VirtBoardInfo
*board
= (const VirtBoardInfo
*)binfo
;
1047 *fdt_size
= board
->fdt_size
;
1051 static void virt_build_smbios(VirtGuestInfo
*guest_info
)
1053 FWCfgState
*fw_cfg
= guest_info
->fw_cfg
;
1054 uint8_t *smbios_tables
, *smbios_anchor
;
1055 size_t smbios_tables_len
, smbios_anchor_len
;
1056 const char *product
= "QEMU Virtual Machine";
1062 if (kvm_enabled()) {
1063 product
= "KVM Virtual Machine";
1066 smbios_set_defaults("QEMU", product
,
1067 "1.0", false, true, SMBIOS_ENTRY_POINT_30
);
1069 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1070 &smbios_anchor
, &smbios_anchor_len
);
1072 if (smbios_anchor
) {
1073 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-tables",
1074 smbios_tables
, smbios_tables_len
);
1075 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-anchor",
1076 smbios_anchor
, smbios_anchor_len
);
1081 void virt_guest_info_machine_done(Notifier
*notifier
, void *data
)
1083 VirtGuestInfoState
*guest_info_state
= container_of(notifier
,
1084 VirtGuestInfoState
, machine_done
);
1085 virt_acpi_setup(&guest_info_state
->info
);
1086 virt_build_smbios(&guest_info_state
->info
);
1089 static void machvirt_init(MachineState
*machine
)
1091 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1092 qemu_irq pic
[NUM_IRQS
];
1093 MemoryRegion
*sysmem
= get_system_memory();
1094 MemoryRegion
*secure_sysmem
= NULL
;
1095 int gic_version
= vms
->gic_version
;
1096 int n
, virt_max_cpus
;
1097 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1098 const char *cpu_model
= machine
->cpu_model
;
1100 VirtGuestInfoState
*guest_info_state
= g_malloc0(sizeof *guest_info_state
);
1101 VirtGuestInfo
*guest_info
= &guest_info_state
->info
;
1103 bool firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1106 cpu_model
= "cortex-a15";
1109 /* We can probe only here because during property set
1110 * KVM is not available yet
1113 gic_version
= kvm_arm_vgic_probe();
1115 error_report("Unable to determine GIC version supported by host");
1116 error_printf("KVM acceleration is probably not supported\n");
1121 /* Separate the actual CPU model name from any appended features */
1122 cpustr
= g_strsplit(cpu_model
, ",", 2);
1124 vbi
= find_machine_info(cpustr
[0]);
1127 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
1131 /* If we have an EL3 boot ROM then the assumption is that it will
1132 * implement PSCI itself, so disable QEMU's internal implementation
1133 * so it doesn't get in the way. Instead of starting secondary
1134 * CPUs in PSCI powerdown state we will start them all running and
1135 * let the boot ROM sort them out.
1136 * The usual case is that we do use QEMU's PSCI implementation.
1138 vbi
->using_psci
= !(vms
->secure
&& firmware_loaded
);
1140 /* The maximum number of CPUs depends on the GIC version, or on how
1141 * many redistributors we can fit into the memory map.
1143 if (gic_version
== 3) {
1144 virt_max_cpus
= vbi
->memmap
[VIRT_GIC_REDIST
].size
/ 0x20000;
1146 virt_max_cpus
= GIC_NCPU
;
1149 if (max_cpus
> virt_max_cpus
) {
1150 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1151 "supported by machine 'mach-virt' (%d)",
1152 max_cpus
, virt_max_cpus
);
1156 vbi
->smp_cpus
= smp_cpus
;
1158 if (machine
->ram_size
> vbi
->memmap
[VIRT_MEM
].size
) {
1159 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB
);
1164 if (kvm_enabled()) {
1165 error_report("mach-virt: KVM does not support Security extensions");
1169 /* The Secure view of the world is the same as the NonSecure,
1170 * but with a few extra devices. Create it as a container region
1171 * containing the system memory at low priority; any secure-only
1172 * devices go in at higher priority and take precedence.
1174 secure_sysmem
= g_new(MemoryRegion
, 1);
1175 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1177 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1182 for (n
= 0; n
< smp_cpus
; n
++) {
1183 ObjectClass
*oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
1184 CPUClass
*cc
= CPU_CLASS(oc
);
1187 char *cpuopts
= g_strdup(cpustr
[1]);
1190 error_report("Unable to find CPU definition");
1193 cpuobj
= object_new(object_class_get_name(oc
));
1195 /* Handle any CPU options specified by the user */
1196 cc
->parse_features(CPU(cpuobj
), cpuopts
, &err
);
1199 error_report_err(err
);
1204 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1207 if (vbi
->using_psci
) {
1208 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_HVC
,
1209 "psci-conduit", NULL
);
1211 /* Secondary CPUs start in PSCI powered-down state */
1213 object_property_set_bool(cpuobj
, true,
1214 "start-powered-off", NULL
);
1218 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1219 object_property_set_int(cpuobj
, vbi
->memmap
[VIRT_CPUPERIPHS
].base
,
1220 "reset-cbar", &error_abort
);
1223 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1226 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1227 "secure-memory", &error_abort
);
1230 object_property_set_bool(cpuobj
, true, "realized", NULL
);
1233 fdt_add_timer_nodes(vbi
, gic_version
);
1234 fdt_add_cpu_nodes(vbi
);
1235 fdt_add_psci_node(vbi
);
1237 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1239 memory_region_add_subregion(sysmem
, vbi
->memmap
[VIRT_MEM
].base
, ram
);
1241 create_flash(vbi
, sysmem
, secure_sysmem
? secure_sysmem
: sysmem
);
1243 create_gic(vbi
, pic
, gic_version
, vms
->secure
);
1245 create_uart(vbi
, pic
, VIRT_UART
, sysmem
);
1248 create_secure_ram(vbi
, secure_sysmem
);
1249 create_uart(vbi
, pic
, VIRT_SECURE_UART
, secure_sysmem
);
1252 create_rtc(vbi
, pic
);
1254 create_pcie(vbi
, pic
, vms
->highmem
);
1256 create_gpio(vbi
, pic
);
1258 /* Create mmio transports, so the user can create virtio backends
1259 * (which will be automatically plugged in to the transports). If
1260 * no backend is created the transport will just sit harmlessly idle.
1262 create_virtio_devices(vbi
, pic
);
1264 create_fw_cfg(vbi
, &address_space_memory
);
1265 rom_set_fw(fw_cfg_find());
1267 guest_info
->smp_cpus
= smp_cpus
;
1268 guest_info
->fw_cfg
= fw_cfg_find();
1269 guest_info
->memmap
= vbi
->memmap
;
1270 guest_info
->irqmap
= vbi
->irqmap
;
1271 guest_info
->use_highmem
= vms
->highmem
;
1272 guest_info
->gic_version
= gic_version
;
1273 guest_info_state
->machine_done
.notify
= virt_guest_info_machine_done
;
1274 qemu_add_machine_init_done_notifier(&guest_info_state
->machine_done
);
1276 vbi
->bootinfo
.ram_size
= machine
->ram_size
;
1277 vbi
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1278 vbi
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1279 vbi
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1280 vbi
->bootinfo
.nb_cpus
= smp_cpus
;
1281 vbi
->bootinfo
.board_id
= -1;
1282 vbi
->bootinfo
.loader_start
= vbi
->memmap
[VIRT_MEM
].base
;
1283 vbi
->bootinfo
.get_dtb
= machvirt_dtb
;
1284 vbi
->bootinfo
.firmware_loaded
= firmware_loaded
;
1285 arm_load_kernel(ARM_CPU(first_cpu
), &vbi
->bootinfo
);
1288 * arm_load_kernel machine init done notifier registration must
1289 * happen before the platform_bus_create call. In this latter,
1290 * another notifier is registered which adds platform bus nodes.
1291 * Notifiers are executed in registration reverse order.
1293 create_platform_bus(vbi
, pic
);
1296 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1298 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1303 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1305 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1307 vms
->secure
= value
;
1310 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1312 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1314 return vms
->highmem
;
1317 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1319 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1321 vms
->highmem
= value
;
1324 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1326 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1327 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1329 return g_strdup(val
);
1332 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1334 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1336 if (!strcmp(value
, "3")) {
1337 vms
->gic_version
= 3;
1338 } else if (!strcmp(value
, "2")) {
1339 vms
->gic_version
= 2;
1340 } else if (!strcmp(value
, "host")) {
1341 vms
->gic_version
= 0; /* Will probe later */
1343 error_setg(errp
, "Invalid gic-version value");
1344 error_append_hint(errp
, "Valid values are 3, 2, host.\n");
1348 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1352 static const TypeInfo virt_machine_info
= {
1353 .name
= TYPE_VIRT_MACHINE
,
1354 .parent
= TYPE_MACHINE
,
1356 .instance_size
= sizeof(VirtMachineState
),
1357 .class_size
= sizeof(VirtMachineClass
),
1358 .class_init
= virt_machine_class_init
,
1361 static void virt_instance_init(Object
*obj
)
1363 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1365 /* EL3 is disabled by default on virt: this makes us consistent
1366 * between KVM and TCG for this board, and it also allows us to
1367 * boot UEFI blobs which assume no TrustZone support.
1369 vms
->secure
= false;
1370 object_property_add_bool(obj
, "secure", virt_get_secure
,
1371 virt_set_secure
, NULL
);
1372 object_property_set_description(obj
, "secure",
1373 "Set on/off to enable/disable the ARM "
1374 "Security Extensions (TrustZone)",
1377 /* High memory is enabled by default */
1378 vms
->highmem
= true;
1379 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1380 virt_set_highmem
, NULL
);
1381 object_property_set_description(obj
, "highmem",
1382 "Set on/off to enable/disable using "
1383 "physical address space above 32 bits",
1385 /* Default GIC type is v2 */
1386 vms
->gic_version
= 2;
1387 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1388 virt_set_gic_version
, NULL
);
1389 object_property_set_description(obj
, "gic-version",
1391 "Valid values are 2, 3 and host", NULL
);
1394 static void virt_class_init(ObjectClass
*oc
, void *data
)
1396 MachineClass
*mc
= MACHINE_CLASS(oc
);
1398 mc
->desc
= "QEMU 2.6 ARM Virtual Machine";
1400 mc
->init
= machvirt_init
;
1401 /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1402 * it later in machvirt_init, where we have more information about the
1403 * configuration of the particular instance.
1405 mc
->max_cpus
= MAX_CPUMASK_BITS
;
1406 mc
->has_dynamic_sysbus
= true;
1407 mc
->block_default_type
= IF_VIRTIO
;
1409 mc
->pci_allow_0_address
= true;
1412 static const TypeInfo machvirt_info
= {
1413 .name
= MACHINE_TYPE_NAME("virt-2.6"),
1414 .parent
= TYPE_VIRT_MACHINE
,
1415 .instance_init
= virt_instance_init
,
1416 .class_init
= virt_class_init
,
1419 static void machvirt_machine_init(void)
1421 type_register_static(&virt_machine_info
);
1422 type_register_static(&machvirt_info
);
1425 machine_init(machvirt_machine_init
);