2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/runstate.h"
48 #include "sysemu/tpm.h"
49 #include "sysemu/tcg.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "sysemu/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/intc/arm_gicv3_its_common.h"
69 #include "hw/firmware/smbios.h"
70 #include "qapi/visitor.h"
71 #include "qapi/qapi-visit-common.h"
72 #include "standard-headers/linux/input.h"
73 #include "hw/arm/smmuv3.h"
74 #include "hw/acpi/acpi.h"
75 #include "target/arm/internals.h"
76 #include "hw/mem/pc-dimm.h"
77 #include "hw/mem/nvdimm.h"
78 #include "hw/acpi/generic_event_device.h"
79 #include "hw/virtio/virtio-md-pci.h"
80 #include "hw/virtio/virtio-iommu.h"
81 #include "hw/char/pl011.h"
82 #include "qemu/guest-random.h"
84 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
85 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
88 MachineClass *mc = MACHINE_CLASS(oc); \
89 virt_machine_##major##_##minor##_options(mc); \
90 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
95 static const TypeInfo machvirt_##major##_##minor##_info = { \
96 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
97 .parent = TYPE_VIRT_MACHINE, \
98 .class_init = virt_##major##_##minor##_class_init, \
100 static void machvirt_machine_##major##_##minor##_init(void) \
102 type_register_static(&machvirt_##major##_##minor##_info); \
104 type_init(machvirt_machine_##major##_##minor##_init);
106 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
107 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
108 #define DEFINE_VIRT_MACHINE(major, minor) \
109 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
112 /* Number of external interrupt lines to configure the GIC with */
115 #define PLATFORM_BUS_NUM_IRQS 64
117 /* Legacy RAM limit in GB (< version 4.0) */
118 #define LEGACY_RAMLIMIT_GB 255
119 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
121 /* Addresses and sizes of our components.
122 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
123 * 128MB..256MB is used for miscellaneous device I/O.
124 * 256MB..1GB is reserved for possible future PCI support (ie where the
125 * PCI memory window will go if we add a PCI host controller).
126 * 1GB and up is RAM (which may happily spill over into the
127 * high memory region beyond 4GB).
128 * This represents a compromise between how much RAM can be given to
129 * a 32 bit VM and leaving space for expansion and in particular for PCI.
130 * Note that devices should generally be placed at multiples of 0x10000,
131 * to accommodate guests using 64K pages.
133 static const MemMapEntry base_memmap
[] = {
134 /* Space up to 0x8000000 is reserved for a boot ROM */
135 [VIRT_FLASH
] = { 0, 0x08000000 },
136 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
137 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
138 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
139 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
140 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
141 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
142 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
143 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
144 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
145 /* This redistributor space allows up to 2*64kB*123 CPUs */
146 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
147 [VIRT_UART
] = { 0x09000000, 0x00001000 },
148 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
149 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
150 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
151 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
152 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
153 [VIRT_PCDIMM_ACPI
] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN
},
154 [VIRT_ACPI_GED
] = { 0x09080000, ACPI_GED_EVT_SEL_LEN
},
155 [VIRT_NVDIMM_ACPI
] = { 0x09090000, NVDIMM_ACPI_IO_LEN
},
156 [VIRT_PVTIME
] = { 0x090a0000, 0x00010000 },
157 [VIRT_SECURE_GPIO
] = { 0x090b0000, 0x00001000 },
158 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
159 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
160 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
161 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
162 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
163 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
164 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
165 /* Actual RAM size depends on initial RAM and device memory settings */
166 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
170 * Highmem IO Regions: This memory map is floating, located after the RAM.
171 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
172 * top of the RAM, so that its base get the same alignment as the size,
173 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
174 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
175 * Note the extended_memmap is sized so that it eventually also includes the
176 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
177 * index of base_memmap).
179 * The memory map for these Highmem IO Regions can be in legacy or compact
180 * layout, depending on 'compact-highmem' property. With legacy layout, the
181 * PA space for one specific region is always reserved, even if the region
182 * has been disabled or doesn't fit into the PA space. However, the PA space
183 * for the region won't be reserved in these circumstances with compact layout.
185 static MemMapEntry extended_memmap
[] = {
186 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
187 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
188 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
189 /* Second PCIe window */
190 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
193 static const int a15irqmap
[] = {
196 [VIRT_PCIE
] = 3, /* ... to 6 */
198 [VIRT_SECURE_UART
] = 8,
200 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
201 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
202 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
203 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
206 static const char *valid_cpus
[] = {
208 ARM_CPU_TYPE_NAME("cortex-a7"),
209 ARM_CPU_TYPE_NAME("cortex-a15"),
210 ARM_CPU_TYPE_NAME("cortex-a35"),
211 ARM_CPU_TYPE_NAME("cortex-a55"),
212 ARM_CPU_TYPE_NAME("cortex-a72"),
213 ARM_CPU_TYPE_NAME("cortex-a76"),
214 ARM_CPU_TYPE_NAME("cortex-a710"),
215 ARM_CPU_TYPE_NAME("a64fx"),
216 ARM_CPU_TYPE_NAME("neoverse-n1"),
217 ARM_CPU_TYPE_NAME("neoverse-v1"),
218 ARM_CPU_TYPE_NAME("neoverse-n2"),
220 ARM_CPU_TYPE_NAME("cortex-a53"),
221 ARM_CPU_TYPE_NAME("cortex-a57"),
222 ARM_CPU_TYPE_NAME("host"),
223 ARM_CPU_TYPE_NAME("max"),
226 static bool cpu_type_valid(const char *cpu
)
230 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
231 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
238 static void create_randomness(MachineState
*ms
, const char *node
)
245 if (qemu_guest_getrandom(&seed
, sizeof(seed
), NULL
)) {
248 qemu_fdt_setprop_u64(ms
->fdt
, node
, "kaslr-seed", seed
.kaslr
);
249 qemu_fdt_setprop(ms
->fdt
, node
, "rng-seed", seed
.rng
, sizeof(seed
.rng
));
252 static void create_fdt(VirtMachineState
*vms
)
254 MachineState
*ms
= MACHINE(vms
);
255 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
256 void *fdt
= create_device_tree(&vms
->fdt_size
);
259 error_report("create_device_tree() failed");
266 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
267 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
268 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
269 qemu_fdt_setprop_string(fdt
, "/", "model", "linux,dummy-virt");
271 /* /chosen must exist for load_dtb to fill in necessary properties later */
272 qemu_fdt_add_subnode(fdt
, "/chosen");
273 if (vms
->dtb_randomness
) {
274 create_randomness(ms
, "/chosen");
278 qemu_fdt_add_subnode(fdt
, "/secure-chosen");
279 if (vms
->dtb_randomness
) {
280 create_randomness(ms
, "/secure-chosen");
284 /* Clock node, for the benefit of the UART. The kernel device tree
285 * binding documentation claims the PL011 node clock properties are
286 * optional but in practice if you omit them the kernel refuses to
287 * probe for the device.
289 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
290 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
291 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
292 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
293 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
294 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
296 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
298 if (nb_numa_nodes
> 0 && ms
->numa_state
->have_numa_distance
) {
299 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
300 uint32_t *matrix
= g_malloc0(size
);
303 for (i
= 0; i
< nb_numa_nodes
; i
++) {
304 for (j
= 0; j
< nb_numa_nodes
; j
++) {
305 idx
= (i
* nb_numa_nodes
+ j
) * 3;
306 matrix
[idx
+ 0] = cpu_to_be32(i
);
307 matrix
[idx
+ 1] = cpu_to_be32(j
);
309 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
313 qemu_fdt_add_subnode(fdt
, "/distance-map");
314 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
315 "numa-distance-map-v1");
316 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
322 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
324 /* On real hardware these interrupts are level-triggered.
325 * On KVM they were edge-triggered before host kernel version 4.4,
326 * and level-triggered afterwards.
327 * On emulated QEMU they are level-triggered.
329 * Getting the DTB info about them wrong is awkward for some
331 * pre-4.8 ignore the DT and leave the interrupt configured
332 * with whatever the GIC reset value (or the bootloader) left it at
333 * 4.8 before rc6 honour the incorrect data by programming it back
334 * into the GIC, causing problems
335 * 4.8rc6 and later ignore the DT and always write "level triggered"
338 * For backwards-compatibility, virt-2.8 and earlier will continue
339 * to say these are edge-triggered, but later machines will report
340 * the correct information.
343 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
344 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
345 MachineState
*ms
= MACHINE(vms
);
347 if (vmc
->claim_edge_triggered_timers
) {
348 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
351 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
352 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
353 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
354 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
357 qemu_fdt_add_subnode(ms
->fdt
, "/timer");
359 armcpu
= ARM_CPU(qemu_get_cpu(0));
360 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
361 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
362 qemu_fdt_setprop(ms
->fdt
, "/timer", "compatible",
363 compat
, sizeof(compat
));
365 qemu_fdt_setprop_string(ms
->fdt
, "/timer", "compatible",
368 qemu_fdt_setprop(ms
->fdt
, "/timer", "always-on", NULL
, 0);
369 qemu_fdt_setprop_cells(ms
->fdt
, "/timer", "interrupts",
370 GIC_FDT_IRQ_TYPE_PPI
,
371 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ
), irqflags
,
372 GIC_FDT_IRQ_TYPE_PPI
,
373 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ
), irqflags
,
374 GIC_FDT_IRQ_TYPE_PPI
,
375 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ
), irqflags
,
376 GIC_FDT_IRQ_TYPE_PPI
,
377 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ
), irqflags
);
380 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
384 const MachineState
*ms
= MACHINE(vms
);
385 const VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
386 int smp_cpus
= ms
->smp
.cpus
;
389 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
390 * On ARM v8 64-bit systems value should be set to 2,
391 * that corresponds to the MPIDR_EL1 register size.
392 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
393 * in the system, #address-cells can be set to 1, since
394 * MPIDR_EL1[63:32] bits are not used for CPUs
397 * Here we actually don't know whether our system is 32- or 64-bit one.
398 * The simplest way to go is to examine affinity IDs of all our CPUs. If
399 * at least one of them has Aff3 populated, we set #address-cells to 2.
401 for (cpu
= 0; cpu
< smp_cpus
; cpu
++) {
402 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
404 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
410 qemu_fdt_add_subnode(ms
->fdt
, "/cpus");
411 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#address-cells", addr_cells
);
412 qemu_fdt_setprop_cell(ms
->fdt
, "/cpus", "#size-cells", 0x0);
414 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
415 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
416 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
417 CPUState
*cs
= CPU(armcpu
);
419 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
420 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "cpu");
421 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
422 armcpu
->dtb_compatible
);
424 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
&& smp_cpus
> 1) {
425 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
426 "enable-method", "psci");
429 if (addr_cells
== 2) {
430 qemu_fdt_setprop_u64(ms
->fdt
, nodename
, "reg",
431 armcpu
->mp_affinity
);
433 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "reg",
434 armcpu
->mp_affinity
);
437 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
438 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "numa-node-id",
439 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
442 if (!vmc
->no_cpu_topology
) {
443 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle",
444 qemu_fdt_alloc_phandle(ms
->fdt
));
450 if (!vmc
->no_cpu_topology
) {
452 * Add vCPU topology description through fdt node cpu-map.
454 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
455 * In a SMP system, the hierarchy of CPUs can be defined through
456 * four entities that are used to describe the layout of CPUs in
457 * the system: socket/cluster/core/thread.
459 * A socket node represents the boundary of system physical package
460 * and its child nodes must be one or more cluster nodes. A system
461 * can contain several layers of clustering within a single physical
462 * package and cluster nodes can be contained in parent cluster nodes.
464 * Note: currently we only support one layer of clustering within
465 * each physical package.
467 qemu_fdt_add_subnode(ms
->fdt
, "/cpus/cpu-map");
469 for (cpu
= smp_cpus
- 1; cpu
>= 0; cpu
--) {
470 char *cpu_path
= g_strdup_printf("/cpus/cpu@%d", cpu
);
473 if (ms
->smp
.threads
> 1) {
474 map_path
= g_strdup_printf(
475 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
476 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
),
477 (cpu
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
,
478 (cpu
/ ms
->smp
.threads
) % ms
->smp
.cores
,
479 cpu
% ms
->smp
.threads
);
481 map_path
= g_strdup_printf(
482 "/cpus/cpu-map/socket%d/cluster%d/core%d",
483 cpu
/ (ms
->smp
.clusters
* ms
->smp
.cores
),
484 (cpu
/ ms
->smp
.cores
) % ms
->smp
.clusters
,
485 cpu
% ms
->smp
.cores
);
487 qemu_fdt_add_path(ms
->fdt
, map_path
);
488 qemu_fdt_setprop_phandle(ms
->fdt
, map_path
, "cpu", cpu_path
);
496 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
499 MachineState
*ms
= MACHINE(vms
);
501 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
502 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
503 vms
->memmap
[VIRT_GIC_ITS
].base
);
504 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
505 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
507 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
508 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#msi-cells", 1);
509 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
510 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
511 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
512 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
516 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
518 MachineState
*ms
= MACHINE(vms
);
521 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
522 vms
->memmap
[VIRT_GIC_V2M
].base
);
523 vms
->msi_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
524 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
525 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
526 "arm,gic-v2m-frame");
527 qemu_fdt_setprop(ms
->fdt
, nodename
, "msi-controller", NULL
, 0);
528 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
529 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
530 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
531 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
535 static void fdt_add_gic_node(VirtMachineState
*vms
)
537 MachineState
*ms
= MACHINE(vms
);
540 vms
->gic_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
541 qemu_fdt_setprop_cell(ms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
543 nodename
= g_strdup_printf("/intc@%" PRIx64
,
544 vms
->memmap
[VIRT_GIC_DIST
].base
);
545 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
546 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 3);
547 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
548 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 0x2);
549 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 0x2);
550 qemu_fdt_setprop(ms
->fdt
, nodename
, "ranges", NULL
, 0);
551 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
552 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
554 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
557 qemu_fdt_setprop_cell(ms
->fdt
, nodename
,
558 "#redistributor-regions", nb_redist_regions
);
560 if (nb_redist_regions
== 1) {
561 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
562 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
563 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
564 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
565 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
567 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
568 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
569 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
570 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
571 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
572 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
573 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
577 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
578 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
579 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
582 /* 'cortex-a15-gic' means 'GIC v2' */
583 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible",
584 "arm,cortex-a15-gic");
586 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
587 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
588 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
589 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
590 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
592 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
593 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
594 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
595 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
596 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
597 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
598 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
599 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
600 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
601 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
602 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
603 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
607 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
611 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
613 ARMCPU
*armcpu
= ARM_CPU(first_cpu
);
614 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
615 MachineState
*ms
= MACHINE(vms
);
617 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
618 assert(!object_property_get_bool(OBJECT(armcpu
), "pmu", NULL
));
622 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
623 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
624 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
625 (1 << MACHINE(vms
)->smp
.cpus
) - 1);
628 qemu_fdt_add_subnode(ms
->fdt
, "/pmu");
629 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
630 const char compat
[] = "arm,armv8-pmuv3";
631 qemu_fdt_setprop(ms
->fdt
, "/pmu", "compatible",
632 compat
, sizeof(compat
));
633 qemu_fdt_setprop_cells(ms
->fdt
, "/pmu", "interrupts",
634 GIC_FDT_IRQ_TYPE_PPI
,
635 INTID_TO_PPI(VIRTUAL_PMU_IRQ
), irqflags
);
639 static inline DeviceState
*create_acpi_ged(VirtMachineState
*vms
)
642 MachineState
*ms
= MACHINE(vms
);
643 int irq
= vms
->irqmap
[VIRT_ACPI_GED
];
644 uint32_t event
= ACPI_GED_PWR_DOWN_EVT
;
647 event
|= ACPI_GED_MEM_HOTPLUG_EVT
;
650 if (ms
->nvdimms_state
->is_enabled
) {
651 event
|= ACPI_GED_NVDIMM_HOTPLUG_EVT
;
654 dev
= qdev_new(TYPE_ACPI_GED
);
655 qdev_prop_set_uint32(dev
, "ged-event", event
);
656 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
658 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_ACPI_GED
].base
);
659 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, vms
->memmap
[VIRT_PCDIMM_ACPI
].base
);
660 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(vms
->gic
, irq
));
665 static void create_its(VirtMachineState
*vms
)
667 const char *itsclass
= its_class_name();
670 if (!strcmp(itsclass
, "arm-gicv3-its")) {
677 /* Do nothing if not supported */
681 dev
= qdev_new(itsclass
);
683 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(vms
->gic
),
685 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
686 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
688 fdt_add_its_gic_node(vms
);
689 vms
->msi_controller
= VIRT_MSI_CTRL_ITS
;
692 static void create_v2m(VirtMachineState
*vms
)
695 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
698 dev
= qdev_new("arm-gicv2m");
699 qdev_prop_set_uint32(dev
, "base-spi", irq
);
700 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
701 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
702 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
704 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
705 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
706 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
709 fdt_add_v2m_gic_node(vms
);
710 vms
->msi_controller
= VIRT_MSI_CTRL_GICV2M
;
713 static void create_gic(VirtMachineState
*vms
, MemoryRegion
*mem
)
715 MachineState
*ms
= MACHINE(vms
);
716 /* We create a standalone GIC */
717 SysBusDevice
*gicbusdev
;
720 unsigned int smp_cpus
= ms
->smp
.cpus
;
721 uint32_t nb_redist_regions
= 0;
724 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
725 gictype
= gic_class_name();
727 gictype
= gicv3_class_name();
730 switch (vms
->gic_version
) {
731 case VIRT_GIC_VERSION_2
:
734 case VIRT_GIC_VERSION_3
:
737 case VIRT_GIC_VERSION_4
:
741 g_assert_not_reached();
743 vms
->gic
= qdev_new(gictype
);
744 qdev_prop_set_uint32(vms
->gic
, "revision", revision
);
745 qdev_prop_set_uint32(vms
->gic
, "num-cpu", smp_cpus
);
746 /* Note that the num-irq property counts both internal and external
747 * interrupts; there are always 32 of the former (mandated by GIC spec).
749 qdev_prop_set_uint32(vms
->gic
, "num-irq", NUM_IRQS
+ 32);
750 if (!kvm_irqchip_in_kernel()) {
751 qdev_prop_set_bit(vms
->gic
, "has-security-extensions", vms
->secure
);
754 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
755 uint32_t redist0_capacity
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
756 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
758 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
760 qdev_prop_set_uint32(vms
->gic
, "len-redist-region-count",
762 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[0]", redist0_count
);
764 if (!kvm_irqchip_in_kernel()) {
766 object_property_set_link(OBJECT(vms
->gic
), "sysmem",
767 OBJECT(mem
), &error_fatal
);
768 qdev_prop_set_bit(vms
->gic
, "has-lpi", true);
772 if (nb_redist_regions
== 2) {
773 uint32_t redist1_capacity
=
774 virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
776 qdev_prop_set_uint32(vms
->gic
, "redist-region-count[1]",
777 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
780 if (!kvm_irqchip_in_kernel()) {
781 qdev_prop_set_bit(vms
->gic
, "has-virtualization-extensions",
785 gicbusdev
= SYS_BUS_DEVICE(vms
->gic
);
786 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
787 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
788 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
789 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
790 if (nb_redist_regions
== 2) {
791 sysbus_mmio_map(gicbusdev
, 2,
792 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
795 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
797 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
798 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
802 /* Wire the outputs from each CPU's generic timer and the GICv3
803 * maintenance interrupt signal to the appropriate GIC PPI inputs,
804 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
806 for (i
= 0; i
< smp_cpus
; i
++) {
807 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
808 int intidbase
= NUM_IRQS
+ i
* GIC_INTERNAL
;
809 /* Mapping from the output timer irq lines from the CPU to the
810 * GIC PPI inputs we use for the virt board.
812 const int timer_irq
[] = {
813 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
814 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
815 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
816 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
819 for (unsigned irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
820 qdev_connect_gpio_out(cpudev
, irq
,
821 qdev_get_gpio_in(vms
->gic
,
822 intidbase
+ timer_irq
[irq
]));
825 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
) {
826 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
827 intidbase
+ ARCH_GIC_MAINT_IRQ
);
828 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
830 } else if (vms
->virt
) {
831 qemu_irq irq
= qdev_get_gpio_in(vms
->gic
,
832 intidbase
+ ARCH_GIC_MAINT_IRQ
);
833 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
836 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
837 qdev_get_gpio_in(vms
->gic
, intidbase
840 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
841 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
842 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
843 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
844 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
845 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
846 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
849 fdt_add_gic_node(vms
);
851 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& vms
->its
) {
853 } else if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
858 static void create_uart(const VirtMachineState
*vms
, int uart
,
859 MemoryRegion
*mem
, Chardev
*chr
)
862 hwaddr base
= vms
->memmap
[uart
].base
;
863 hwaddr size
= vms
->memmap
[uart
].size
;
864 int irq
= vms
->irqmap
[uart
];
865 const char compat
[] = "arm,pl011\0arm,primecell";
866 const char clocknames
[] = "uartclk\0apb_pclk";
867 DeviceState
*dev
= qdev_new(TYPE_PL011
);
868 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
869 MachineState
*ms
= MACHINE(vms
);
871 qdev_prop_set_chr(dev
, "chardev", chr
);
872 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
873 memory_region_add_subregion(mem
, base
,
874 sysbus_mmio_get_region(s
, 0));
875 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
877 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
878 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
879 /* Note that we can't use setprop_string because of the embedded NUL */
880 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible",
881 compat
, sizeof(compat
));
882 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
884 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
885 GIC_FDT_IRQ_TYPE_SPI
, irq
,
886 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
887 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "clocks",
888 vms
->clock_phandle
, vms
->clock_phandle
);
889 qemu_fdt_setprop(ms
->fdt
, nodename
, "clock-names",
890 clocknames
, sizeof(clocknames
));
892 if (uart
== VIRT_UART
) {
893 qemu_fdt_setprop_string(ms
->fdt
, "/chosen", "stdout-path", nodename
);
895 /* Mark as not usable by the normal world */
896 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
897 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
899 qemu_fdt_setprop_string(ms
->fdt
, "/secure-chosen", "stdout-path",
906 static void create_rtc(const VirtMachineState
*vms
)
909 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
910 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
911 int irq
= vms
->irqmap
[VIRT_RTC
];
912 const char compat
[] = "arm,pl031\0arm,primecell";
913 MachineState
*ms
= MACHINE(vms
);
915 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(vms
->gic
, irq
));
917 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
918 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
919 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
920 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
922 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
923 GIC_FDT_IRQ_TYPE_SPI
, irq
,
924 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
925 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
926 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
930 static DeviceState
*gpio_key_dev
;
931 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
933 VirtMachineState
*s
= container_of(n
, VirtMachineState
, powerdown_notifier
);
936 acpi_send_event(s
->acpi_dev
, ACPI_POWER_DOWN_STATUS
);
938 /* use gpio Pin 3 for power button event */
939 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
943 static void create_gpio_keys(char *fdt
, DeviceState
*pl061_dev
,
946 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
947 qdev_get_gpio_in(pl061_dev
, 3));
949 qemu_fdt_add_subnode(fdt
, "/gpio-keys");
950 qemu_fdt_setprop_string(fdt
, "/gpio-keys", "compatible", "gpio-keys");
952 qemu_fdt_add_subnode(fdt
, "/gpio-keys/poweroff");
953 qemu_fdt_setprop_string(fdt
, "/gpio-keys/poweroff",
954 "label", "GPIO Key Poweroff");
955 qemu_fdt_setprop_cell(fdt
, "/gpio-keys/poweroff", "linux,code",
957 qemu_fdt_setprop_cells(fdt
, "/gpio-keys/poweroff",
958 "gpios", phandle
, 3, 0);
961 #define SECURE_GPIO_POWEROFF 0
962 #define SECURE_GPIO_RESET 1
964 static void create_secure_gpio_pwr(char *fdt
, DeviceState
*pl061_dev
,
967 DeviceState
*gpio_pwr_dev
;
970 gpio_pwr_dev
= sysbus_create_simple("gpio-pwr", -1, NULL
);
972 /* connect secure pl061 to gpio-pwr */
973 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_RESET
,
974 qdev_get_gpio_in_named(gpio_pwr_dev
, "reset", 0));
975 qdev_connect_gpio_out(pl061_dev
, SECURE_GPIO_POWEROFF
,
976 qdev_get_gpio_in_named(gpio_pwr_dev
, "shutdown", 0));
978 qemu_fdt_add_subnode(fdt
, "/gpio-poweroff");
979 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "compatible",
981 qemu_fdt_setprop_cells(fdt
, "/gpio-poweroff",
982 "gpios", phandle
, SECURE_GPIO_POWEROFF
, 0);
983 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "status", "disabled");
984 qemu_fdt_setprop_string(fdt
, "/gpio-poweroff", "secure-status",
987 qemu_fdt_add_subnode(fdt
, "/gpio-restart");
988 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "compatible",
990 qemu_fdt_setprop_cells(fdt
, "/gpio-restart",
991 "gpios", phandle
, SECURE_GPIO_RESET
, 0);
992 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "status", "disabled");
993 qemu_fdt_setprop_string(fdt
, "/gpio-restart", "secure-status",
997 static void create_gpio_devices(const VirtMachineState
*vms
, int gpio
,
1001 DeviceState
*pl061_dev
;
1002 hwaddr base
= vms
->memmap
[gpio
].base
;
1003 hwaddr size
= vms
->memmap
[gpio
].size
;
1004 int irq
= vms
->irqmap
[gpio
];
1005 const char compat
[] = "arm,pl061\0arm,primecell";
1007 MachineState
*ms
= MACHINE(vms
);
1009 pl061_dev
= qdev_new("pl061");
1010 /* Pull lines down to 0 if not driven by the PL061 */
1011 qdev_prop_set_uint32(pl061_dev
, "pullups", 0);
1012 qdev_prop_set_uint32(pl061_dev
, "pulldowns", 0xff);
1013 s
= SYS_BUS_DEVICE(pl061_dev
);
1014 sysbus_realize_and_unref(s
, &error_fatal
);
1015 memory_region_add_subregion(mem
, base
, sysbus_mmio_get_region(s
, 0));
1016 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(vms
->gic
, irq
));
1018 uint32_t phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1019 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
1020 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1021 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1023 qemu_fdt_setprop(ms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
1024 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#gpio-cells", 2);
1025 qemu_fdt_setprop(ms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
1026 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1027 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1028 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
1029 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
1030 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "clock-names", "apb_pclk");
1031 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "phandle", phandle
);
1033 if (gpio
!= VIRT_GPIO
) {
1034 /* Mark as not usable by the normal world */
1035 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1036 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1040 /* Child gpio devices */
1041 if (gpio
== VIRT_GPIO
) {
1042 create_gpio_keys(ms
->fdt
, pl061_dev
, phandle
);
1044 create_secure_gpio_pwr(ms
->fdt
, pl061_dev
, phandle
);
1048 static void create_virtio_devices(const VirtMachineState
*vms
)
1051 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
1052 MachineState
*ms
= MACHINE(vms
);
1054 /* We create the transports in forwards order. Since qbus_realize()
1055 * prepends (not appends) new child buses, the incrementing loop below will
1056 * create a list of virtio-mmio buses with decreasing base addresses.
1058 * When a -device option is processed from the command line,
1059 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1060 * order. The upshot is that -device options in increasing command line
1061 * order are mapped to virtio-mmio buses with decreasing base addresses.
1063 * When this code was originally written, that arrangement ensured that the
1064 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1065 * the first -device on the command line. (The end-to-end order is a
1066 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1067 * guest kernel's name-to-address assignment strategy.)
1069 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1070 * the message, if not necessarily the code, of commit 70161ff336.
1071 * Therefore the loop now establishes the inverse of the original intent.
1073 * Unfortunately, we can't counteract the kernel change by reversing the
1074 * loop; it would break existing command lines.
1076 * In any case, the kernel makes no guarantee about the stability of
1077 * enumeration order of virtio devices (as demonstrated by it changing
1078 * between kernel versions). For reliable and stable identification
1079 * of disks users must use UUIDs or similar mechanisms.
1081 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
1082 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1083 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1085 sysbus_create_simple("virtio-mmio", base
,
1086 qdev_get_gpio_in(vms
->gic
, irq
));
1089 /* We add dtb nodes in reverse order so that they appear in the finished
1090 * device tree lowest address first.
1092 * Note that this mapping is independent of the loop above. The previous
1093 * loop influences virtio device to virtio transport assignment, whereas
1094 * this loop controls how virtio transports are laid out in the dtb.
1096 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
1098 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
1099 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
1101 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
1102 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1103 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1104 "compatible", "virtio,mmio");
1105 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1107 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupts",
1108 GIC_FDT_IRQ_TYPE_SPI
, irq
,
1109 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1110 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1115 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1117 static PFlashCFI01
*virt_flash_create1(VirtMachineState
*vms
,
1119 const char *alias_prop_name
)
1122 * Create a single flash device. We use the same parameters as
1123 * the flash devices on the Versatile Express board.
1125 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
1127 qdev_prop_set_uint64(dev
, "sector-length", VIRT_FLASH_SECTOR_SIZE
);
1128 qdev_prop_set_uint8(dev
, "width", 4);
1129 qdev_prop_set_uint8(dev
, "device-width", 2);
1130 qdev_prop_set_bit(dev
, "big-endian", false);
1131 qdev_prop_set_uint16(dev
, "id0", 0x89);
1132 qdev_prop_set_uint16(dev
, "id1", 0x18);
1133 qdev_prop_set_uint16(dev
, "id2", 0x00);
1134 qdev_prop_set_uint16(dev
, "id3", 0x00);
1135 qdev_prop_set_string(dev
, "name", name
);
1136 object_property_add_child(OBJECT(vms
), name
, OBJECT(dev
));
1137 object_property_add_alias(OBJECT(vms
), alias_prop_name
,
1138 OBJECT(dev
), "drive");
1139 return PFLASH_CFI01(dev
);
1142 static void virt_flash_create(VirtMachineState
*vms
)
1144 vms
->flash
[0] = virt_flash_create1(vms
, "virt.flash0", "pflash0");
1145 vms
->flash
[1] = virt_flash_create1(vms
, "virt.flash1", "pflash1");
1148 static void virt_flash_map1(PFlashCFI01
*flash
,
1149 hwaddr base
, hwaddr size
,
1150 MemoryRegion
*sysmem
)
1152 DeviceState
*dev
= DEVICE(flash
);
1154 assert(QEMU_IS_ALIGNED(size
, VIRT_FLASH_SECTOR_SIZE
));
1155 assert(size
/ VIRT_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
1156 qdev_prop_set_uint32(dev
, "num-blocks", size
/ VIRT_FLASH_SECTOR_SIZE
);
1157 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1159 memory_region_add_subregion(sysmem
, base
,
1160 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
1164 static void virt_flash_map(VirtMachineState
*vms
,
1165 MemoryRegion
*sysmem
,
1166 MemoryRegion
*secure_sysmem
)
1169 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1170 * sysmem is the system memory space. secure_sysmem is the secure view
1171 * of the system, and the first flash device should be made visible only
1172 * there. The second flash device is visible to both secure and nonsecure.
1173 * If sysmem == secure_sysmem this means there is no separate Secure
1174 * address space and both flash devices are generally visible.
1176 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1177 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1179 virt_flash_map1(vms
->flash
[0], flashbase
, flashsize
,
1181 virt_flash_map1(vms
->flash
[1], flashbase
+ flashsize
, flashsize
,
1185 static void virt_flash_fdt(VirtMachineState
*vms
,
1186 MemoryRegion
*sysmem
,
1187 MemoryRegion
*secure_sysmem
)
1189 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
1190 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
1191 MachineState
*ms
= MACHINE(vms
);
1194 if (sysmem
== secure_sysmem
) {
1195 /* Report both flash devices as a single node in the DT */
1196 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
1197 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1198 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1199 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1200 2, flashbase
, 2, flashsize
,
1201 2, flashbase
+ flashsize
, 2, flashsize
);
1202 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1206 * Report the devices as separate nodes so we can mark one as
1207 * only visible to the secure world.
1209 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
1210 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1211 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1212 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1213 2, flashbase
, 2, flashsize
);
1214 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1215 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1216 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1219 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
+ flashsize
);
1220 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1221 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "compatible", "cfi-flash");
1222 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1223 2, flashbase
+ flashsize
, 2, flashsize
);
1224 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "bank-width", 4);
1229 static bool virt_firmware_init(VirtMachineState
*vms
,
1230 MemoryRegion
*sysmem
,
1231 MemoryRegion
*secure_sysmem
)
1234 const char *bios_name
;
1235 BlockBackend
*pflash_blk0
;
1237 /* Map legacy -drive if=pflash to machine properties */
1238 for (i
= 0; i
< ARRAY_SIZE(vms
->flash
); i
++) {
1239 pflash_cfi01_legacy_drive(vms
->flash
[i
],
1240 drive_get(IF_PFLASH
, 0, i
));
1243 virt_flash_map(vms
, sysmem
, secure_sysmem
);
1245 pflash_blk0
= pflash_cfi01_get_blk(vms
->flash
[0]);
1247 bios_name
= MACHINE(vms
)->firmware
;
1254 error_report("The contents of the first flash device may be "
1255 "specified with -bios or with -drive if=pflash... "
1256 "but you cannot use both options at once");
1260 /* Fall back to -bios */
1262 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1264 error_report("Could not find ROM image '%s'", bios_name
);
1267 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(vms
->flash
[0]), 0);
1268 image_size
= load_image_mr(fname
, mr
);
1270 if (image_size
< 0) {
1271 error_report("Could not load ROM image '%s'", bios_name
);
1276 return pflash_blk0
|| bios_name
;
1279 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
1281 MachineState
*ms
= MACHINE(vms
);
1282 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
1283 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
1287 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
1288 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)ms
->smp
.cpus
);
1290 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
1291 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1292 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1293 "compatible", "qemu,fw-cfg-mmio");
1294 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1296 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1301 static void create_pcie_irq_map(const MachineState
*ms
,
1302 uint32_t gic_phandle
,
1303 int first_irq
, const char *nodename
)
1306 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1307 uint32_t *irq_map
= full_irq_map
;
1309 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1310 for (pin
= 0; pin
< 4; pin
++) {
1311 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1312 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1313 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1317 devfn
<< 8, 0, 0, /* devfn */
1318 pin
+ 1, /* PCI pin */
1319 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1321 /* Convert map to big endian */
1322 for (i
= 0; i
< 10; i
++) {
1323 irq_map
[i
] = cpu_to_be32(map
[i
]);
1329 qemu_fdt_setprop(ms
->fdt
, nodename
, "interrupt-map",
1330 full_irq_map
, sizeof(full_irq_map
));
1332 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "interrupt-map-mask",
1333 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1338 static void create_smmu(const VirtMachineState
*vms
,
1342 const char compat
[] = "arm,smmu-v3";
1343 int irq
= vms
->irqmap
[VIRT_SMMU
];
1345 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1346 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1347 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1349 MachineState
*ms
= MACHINE(vms
);
1351 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1355 dev
= qdev_new(TYPE_ARM_SMMUV3
);
1357 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
1359 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1360 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1361 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1362 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1363 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1366 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1367 qemu_fdt_add_subnode(ms
->fdt
, node
);
1368 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1369 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg", 2, base
, 2, size
);
1371 qemu_fdt_setprop_cells(ms
->fdt
, node
, "interrupts",
1372 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1373 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1374 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1375 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1377 qemu_fdt_setprop(ms
->fdt
, node
, "interrupt-names", irq_names
,
1380 qemu_fdt_setprop(ms
->fdt
, node
, "dma-coherent", NULL
, 0);
1382 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1384 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1388 static void create_virtio_iommu_dt_bindings(VirtMachineState
*vms
)
1390 const char compat
[] = "virtio,pci-iommu\0pci1af4,1057";
1391 uint16_t bdf
= vms
->virtio_iommu_bdf
;
1392 MachineState
*ms
= MACHINE(vms
);
1395 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1397 node
= g_strdup_printf("%s/virtio_iommu@%x,%x", vms
->pciehb_nodename
,
1398 PCI_SLOT(bdf
), PCI_FUNC(bdf
));
1399 qemu_fdt_add_subnode(ms
->fdt
, node
);
1400 qemu_fdt_setprop(ms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1401 qemu_fdt_setprop_sized_cells(ms
->fdt
, node
, "reg",
1402 1, bdf
<< 8, 1, 0, 1, 0,
1405 qemu_fdt_setprop_cell(ms
->fdt
, node
, "#iommu-cells", 1);
1406 qemu_fdt_setprop_cell(ms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1409 qemu_fdt_setprop_cells(ms
->fdt
, vms
->pciehb_nodename
, "iommu-map",
1410 0x0, vms
->iommu_phandle
, 0x0, bdf
,
1411 bdf
+ 1, vms
->iommu_phandle
, bdf
+ 1, 0xffff - bdf
);
1414 static void create_pcie(VirtMachineState
*vms
)
1416 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1417 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1418 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1419 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1420 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1421 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1422 hwaddr base_ecam
, size_ecam
;
1423 hwaddr base
= base_mmio
;
1425 int irq
= vms
->irqmap
[VIRT_PCIE
];
1426 MemoryRegion
*mmio_alias
;
1427 MemoryRegion
*mmio_reg
;
1428 MemoryRegion
*ecam_alias
;
1429 MemoryRegion
*ecam_reg
;
1434 MachineState
*ms
= MACHINE(vms
);
1435 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
1437 dev
= qdev_new(TYPE_GPEX_HOST
);
1438 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1440 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1441 base_ecam
= vms
->memmap
[ecam_id
].base
;
1442 size_ecam
= vms
->memmap
[ecam_id
].size
;
1443 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1444 /* Map only the first size_ecam bytes of ECAM space */
1445 ecam_alias
= g_new0(MemoryRegion
, 1);
1446 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1447 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1448 ecam_reg
, 0, size_ecam
);
1449 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1451 /* Map the MMIO window into system address space so as to expose
1452 * the section of PCI MMIO space which starts at the same base address
1453 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1456 mmio_alias
= g_new0(MemoryRegion
, 1);
1457 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1458 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1459 mmio_reg
, base_mmio
, size_mmio
);
1460 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1462 if (vms
->highmem_mmio
) {
1463 /* Map high MMIO space */
1464 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1466 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1467 mmio_reg
, base_mmio_high
, size_mmio_high
);
1468 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1472 /* Map IO port space */
1473 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1475 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1476 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
1477 qdev_get_gpio_in(vms
->gic
, irq
+ i
));
1478 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1481 pci
= PCI_HOST_BRIDGE(dev
);
1482 pci
->bypass_iommu
= vms
->default_bus_bypass_iommu
;
1483 vms
->bus
= pci
->bus
;
1485 for (i
= 0; i
< nb_nics
; i
++) {
1486 pci_nic_init_nofail(&nd_table
[i
], pci
->bus
, mc
->default_nic
, NULL
);
1490 nodename
= vms
->pciehb_nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1491 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1492 qemu_fdt_setprop_string(ms
->fdt
, nodename
,
1493 "compatible", "pci-host-ecam-generic");
1494 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "pci");
1495 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#address-cells", 3);
1496 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#size-cells", 2);
1497 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "linux,pci-domain", 0);
1498 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "bus-range", 0,
1500 qemu_fdt_setprop(ms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1502 if (vms
->msi_phandle
) {
1503 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "msi-map",
1504 0, vms
->msi_phandle
, 0, 0x10000);
1507 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg",
1508 2, base_ecam
, 2, size_ecam
);
1510 if (vms
->highmem_mmio
) {
1511 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1512 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1513 2, base_pio
, 2, size_pio
,
1514 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1515 2, base_mmio
, 2, size_mmio
,
1516 1, FDT_PCI_RANGE_MMIO_64BIT
,
1518 2, base_mmio_high
, 2, size_mmio_high
);
1520 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "ranges",
1521 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1522 2, base_pio
, 2, size_pio
,
1523 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1524 2, base_mmio
, 2, size_mmio
);
1527 qemu_fdt_setprop_cell(ms
->fdt
, nodename
, "#interrupt-cells", 1);
1528 create_pcie_irq_map(ms
, vms
->gic_phandle
, irq
, nodename
);
1531 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(ms
->fdt
);
1533 switch (vms
->iommu
) {
1534 case VIRT_IOMMU_SMMUV3
:
1535 create_smmu(vms
, vms
->bus
);
1536 qemu_fdt_setprop_cells(ms
->fdt
, nodename
, "iommu-map",
1537 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1540 g_assert_not_reached();
1545 static void create_platform_bus(VirtMachineState
*vms
)
1550 MemoryRegion
*sysmem
= get_system_memory();
1552 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1553 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1554 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1555 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1556 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1557 vms
->platform_bus_dev
= dev
;
1559 s
= SYS_BUS_DEVICE(dev
);
1560 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1561 int irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1562 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(vms
->gic
, irq
));
1565 memory_region_add_subregion(sysmem
,
1566 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1567 sysbus_mmio_get_region(s
, 0));
1570 static void create_tag_ram(MemoryRegion
*tag_sysmem
,
1571 hwaddr base
, hwaddr size
,
1574 MemoryRegion
*tagram
= g_new(MemoryRegion
, 1);
1576 memory_region_init_ram(tagram
, NULL
, name
, size
/ 32, &error_fatal
);
1577 memory_region_add_subregion(tag_sysmem
, base
/ 32, tagram
);
1580 static void create_secure_ram(VirtMachineState
*vms
,
1581 MemoryRegion
*secure_sysmem
,
1582 MemoryRegion
*secure_tag_sysmem
)
1584 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1586 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1587 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1588 MachineState
*ms
= MACHINE(vms
);
1590 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1592 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1594 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1595 qemu_fdt_add_subnode(ms
->fdt
, nodename
);
1596 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "device_type", "memory");
1597 qemu_fdt_setprop_sized_cells(ms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1598 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "status", "disabled");
1599 qemu_fdt_setprop_string(ms
->fdt
, nodename
, "secure-status", "okay");
1601 if (secure_tag_sysmem
) {
1602 create_tag_ram(secure_tag_sysmem
, base
, size
, "mach-virt.secure-tag");
1608 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1610 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1612 MachineState
*ms
= MACHINE(board
);
1615 *fdt_size
= board
->fdt_size
;
1619 static void virt_build_smbios(VirtMachineState
*vms
)
1621 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1622 MachineState
*ms
= MACHINE(vms
);
1623 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1624 uint8_t *smbios_tables
, *smbios_anchor
;
1625 size_t smbios_tables_len
, smbios_anchor_len
;
1626 struct smbios_phys_mem_area mem_array
;
1627 const char *product
= "QEMU Virtual Machine";
1629 if (kvm_enabled()) {
1630 product
= "KVM Virtual Machine";
1633 smbios_set_defaults("QEMU", product
,
1634 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1635 true, SMBIOS_ENTRY_POINT_TYPE_64
);
1637 /* build the array of physical mem area from base_memmap */
1638 mem_array
.address
= vms
->memmap
[VIRT_MEM
].base
;
1639 mem_array
.length
= ms
->ram_size
;
1641 smbios_get_tables(ms
, &mem_array
, 1,
1642 &smbios_tables
, &smbios_tables_len
,
1643 &smbios_anchor
, &smbios_anchor_len
,
1646 if (smbios_anchor
) {
1647 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1648 smbios_tables
, smbios_tables_len
);
1649 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1650 smbios_anchor
, smbios_anchor_len
);
1655 void virt_machine_done(Notifier
*notifier
, void *data
)
1657 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1659 MachineState
*ms
= MACHINE(vms
);
1660 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1661 struct arm_boot_info
*info
= &vms
->bootinfo
;
1662 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1665 * If the user provided a dtb, we assume the dynamic sysbus nodes
1666 * already are integrated there. This corresponds to a use case where
1667 * the dynamic sysbus nodes are complex and their generation is not yet
1668 * supported. In that case the user can take charge of the guest dt
1669 * while qemu takes charge of the qom stuff.
1671 if (info
->dtb_filename
== NULL
) {
1672 platform_bus_add_all_fdt_nodes(ms
->fdt
, "/intc",
1673 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1674 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1675 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1677 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
, ms
) < 0) {
1681 fw_cfg_add_extra_pci_roots(vms
->bus
, vms
->fw_cfg
);
1683 virt_acpi_setup(vms
);
1684 virt_build_smbios(vms
);
1687 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1689 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1690 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1692 if (!vmc
->disallow_affinity_adjustment
) {
1693 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1694 * GIC's target-list limitations. 32-bit KVM hosts currently
1695 * always create clusters of 4 CPUs, but that is expected to
1696 * change when they gain support for gicv3. When KVM is enabled
1697 * it will override the changes we make here, therefore our
1698 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1699 * and to improve SGI efficiency.
1701 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
1702 clustersz
= GIC_TARGETLIST_BITS
;
1704 clustersz
= GICV3_TARGETLIST_BITS
;
1707 return arm_cpu_mp_affinity(idx
, clustersz
);
1710 static inline bool *virt_get_high_memmap_enabled(VirtMachineState
*vms
,
1713 bool *enabled_array
[] = {
1714 &vms
->highmem_redists
,
1719 assert(ARRAY_SIZE(extended_memmap
) - VIRT_LOWMEMMAP_LAST
==
1720 ARRAY_SIZE(enabled_array
));
1721 assert(index
- VIRT_LOWMEMMAP_LAST
< ARRAY_SIZE(enabled_array
));
1723 return enabled_array
[index
- VIRT_LOWMEMMAP_LAST
];
1726 static void virt_set_high_memmap(VirtMachineState
*vms
,
1727 hwaddr base
, int pa_bits
)
1729 hwaddr region_base
, region_size
;
1730 bool *region_enabled
, fits
;
1733 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1734 region_enabled
= virt_get_high_memmap_enabled(vms
, i
);
1735 region_base
= ROUND_UP(base
, extended_memmap
[i
].size
);
1736 region_size
= extended_memmap
[i
].size
;
1738 vms
->memmap
[i
].base
= region_base
;
1739 vms
->memmap
[i
].size
= region_size
;
1742 * Check each device to see if it fits in the PA space,
1743 * moving highest_gpa as we go. For compatibility, move
1744 * highest_gpa for disabled fitting devices as well, if
1745 * the compact layout has been disabled.
1747 * For each device that doesn't fit, disable it.
1749 fits
= (region_base
+ region_size
) <= BIT_ULL(pa_bits
);
1750 *region_enabled
&= fits
;
1751 if (vms
->highmem_compact
&& !*region_enabled
) {
1755 base
= region_base
+ region_size
;
1757 vms
->highest_gpa
= base
- 1;
1762 static void virt_set_memmap(VirtMachineState
*vms
, int pa_bits
)
1764 MachineState
*ms
= MACHINE(vms
);
1765 hwaddr base
, device_memory_base
, device_memory_size
, memtop
;
1768 vms
->memmap
= extended_memmap
;
1770 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1771 vms
->memmap
[i
] = base_memmap
[i
];
1774 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1775 error_report("unsupported number of memory slots: %"PRIu64
,
1781 * !highmem is exactly the same as limiting the PA space to 32bit,
1782 * irrespective of the underlying capabilities of the HW.
1784 if (!vms
->highmem
) {
1789 * We compute the base of the high IO region depending on the
1790 * amount of initial and device memory. The device memory start/size
1791 * is aligned on 1GiB. We never put the high IO region below 256GiB
1792 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1793 * The device region size assumes 1GiB page max alignment per slot.
1795 device_memory_base
=
1796 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1797 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1799 /* Base address of the high IO region */
1800 memtop
= base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1801 if (memtop
> BIT_ULL(pa_bits
)) {
1802 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
1803 pa_bits
, memtop
- BIT_ULL(pa_bits
));
1806 if (base
< device_memory_base
) {
1807 error_report("maxmem/slots too huge");
1810 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1811 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1814 /* We know for sure that at least the memory fits in the PA space */
1815 vms
->highest_gpa
= memtop
- 1;
1817 virt_set_high_memmap(vms
, base
, pa_bits
);
1819 if (device_memory_size
> 0) {
1820 machine_memory_devices_init(ms
, device_memory_base
, device_memory_size
);
1824 static VirtGICType
finalize_gic_version_do(const char *accel_name
,
1825 VirtGICType gic_version
,
1827 unsigned int max_cpus
)
1829 /* Convert host/max/nosel to GIC version number */
1830 switch (gic_version
) {
1831 case VIRT_GIC_VERSION_HOST
:
1832 if (!kvm_enabled()) {
1833 error_report("gic-version=host requires KVM");
1837 /* For KVM, gic-version=host means gic-version=max */
1838 return finalize_gic_version_do(accel_name
, VIRT_GIC_VERSION_MAX
,
1839 gics_supported
, max_cpus
);
1840 case VIRT_GIC_VERSION_MAX
:
1841 if (gics_supported
& VIRT_GIC_VERSION_4_MASK
) {
1842 gic_version
= VIRT_GIC_VERSION_4
;
1843 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1844 gic_version
= VIRT_GIC_VERSION_3
;
1846 gic_version
= VIRT_GIC_VERSION_2
;
1849 case VIRT_GIC_VERSION_NOSEL
:
1850 if ((gics_supported
& VIRT_GIC_VERSION_2_MASK
) &&
1851 max_cpus
<= GIC_NCPU
) {
1852 gic_version
= VIRT_GIC_VERSION_2
;
1853 } else if (gics_supported
& VIRT_GIC_VERSION_3_MASK
) {
1855 * in case the host does not support v2 emulation or
1856 * the end-user requested more than 8 VCPUs we now default
1857 * to v3. In any case defaulting to v2 would be broken.
1859 gic_version
= VIRT_GIC_VERSION_3
;
1860 } else if (max_cpus
> GIC_NCPU
) {
1861 error_report("%s only supports GICv2 emulation but more than 8 "
1862 "vcpus are requested", accel_name
);
1866 case VIRT_GIC_VERSION_2
:
1867 case VIRT_GIC_VERSION_3
:
1868 case VIRT_GIC_VERSION_4
:
1872 /* Check chosen version is effectively supported */
1873 switch (gic_version
) {
1874 case VIRT_GIC_VERSION_2
:
1875 if (!(gics_supported
& VIRT_GIC_VERSION_2_MASK
)) {
1876 error_report("%s does not support GICv2 emulation", accel_name
);
1880 case VIRT_GIC_VERSION_3
:
1881 if (!(gics_supported
& VIRT_GIC_VERSION_3_MASK
)) {
1882 error_report("%s does not support GICv3 emulation", accel_name
);
1886 case VIRT_GIC_VERSION_4
:
1887 if (!(gics_supported
& VIRT_GIC_VERSION_4_MASK
)) {
1888 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1894 error_report("logic error in finalize_gic_version");
1903 * finalize_gic_version - Determines the final gic_version
1904 * according to the gic-version property
1906 * Default GIC type is v2
1908 static void finalize_gic_version(VirtMachineState
*vms
)
1910 const char *accel_name
= current_accel_name();
1911 unsigned int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1912 int gics_supported
= 0;
1914 /* Determine which GIC versions the current environment supports */
1915 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1916 int probe_bitmap
= kvm_arm_vgic_probe();
1918 if (!probe_bitmap
) {
1919 error_report("Unable to determine GIC version supported by host");
1923 if (probe_bitmap
& KVM_ARM_VGIC_V2
) {
1924 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1926 if (probe_bitmap
& KVM_ARM_VGIC_V3
) {
1927 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1929 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
1930 /* KVM w/o kernel irqchip can only deal with GICv2 */
1931 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1932 accel_name
= "KVM with kernel-irqchip=off";
1933 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
1934 gics_supported
|= VIRT_GIC_VERSION_2_MASK
;
1935 if (module_object_class_by_name("arm-gicv3")) {
1936 gics_supported
|= VIRT_GIC_VERSION_3_MASK
;
1938 /* GICv4 only makes sense if CPU has EL2 */
1939 gics_supported
|= VIRT_GIC_VERSION_4_MASK
;
1943 error_report("Unsupported accelerator, can not determine GIC support");
1948 * Then convert helpers like host/max to concrete GIC versions and ensure
1949 * the desired version is supported
1951 vms
->gic_version
= finalize_gic_version_do(accel_name
, vms
->gic_version
,
1952 gics_supported
, max_cpus
);
1956 * virt_cpu_post_init() must be called after the CPUs have
1957 * been realized and the GIC has been created.
1959 static void virt_cpu_post_init(VirtMachineState
*vms
, MemoryRegion
*sysmem
)
1961 int max_cpus
= MACHINE(vms
)->smp
.max_cpus
;
1962 bool aarch64
, pmu
, steal_time
;
1965 aarch64
= object_property_get_bool(OBJECT(first_cpu
), "aarch64", NULL
);
1966 pmu
= object_property_get_bool(OBJECT(first_cpu
), "pmu", NULL
);
1967 steal_time
= object_property_get_bool(OBJECT(first_cpu
),
1968 "kvm-steal-time", NULL
);
1970 if (kvm_enabled()) {
1971 hwaddr pvtime_reg_base
= vms
->memmap
[VIRT_PVTIME
].base
;
1972 hwaddr pvtime_reg_size
= vms
->memmap
[VIRT_PVTIME
].size
;
1975 MemoryRegion
*pvtime
= g_new(MemoryRegion
, 1);
1976 hwaddr pvtime_size
= max_cpus
* PVTIME_SIZE_PER_CPU
;
1978 /* The memory region size must be a multiple of host page size. */
1979 pvtime_size
= REAL_HOST_PAGE_ALIGN(pvtime_size
);
1981 if (pvtime_size
> pvtime_reg_size
) {
1982 error_report("pvtime requires a %" HWADDR_PRId
1983 " byte memory region for %d CPUs,"
1984 " but only %" HWADDR_PRId
" has been reserved",
1985 pvtime_size
, max_cpus
, pvtime_reg_size
);
1989 memory_region_init_ram(pvtime
, NULL
, "pvtime", pvtime_size
, NULL
);
1990 memory_region_add_subregion(sysmem
, pvtime_reg_base
, pvtime
);
1995 assert(arm_feature(&ARM_CPU(cpu
)->env
, ARM_FEATURE_PMU
));
1996 if (kvm_irqchip_in_kernel()) {
1997 kvm_arm_pmu_set_irq(cpu
, VIRTUAL_PMU_IRQ
);
1999 kvm_arm_pmu_init(cpu
);
2002 kvm_arm_pvtime_init(cpu
, pvtime_reg_base
+
2003 cpu
->cpu_index
* PVTIME_SIZE_PER_CPU
);
2007 if (aarch64
&& vms
->highmem
) {
2008 int requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2009 int pamax
= arm_pamax(ARM_CPU(first_cpu
));
2011 if (pamax
< requested_pa_size
) {
2012 error_report("VCPU supports less PA bits (%d) than "
2013 "requested by the memory map (%d)",
2014 pamax
, requested_pa_size
);
2021 static void machvirt_init(MachineState
*machine
)
2023 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
2024 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
2025 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2026 const CPUArchIdList
*possible_cpus
;
2027 MemoryRegion
*sysmem
= get_system_memory();
2028 MemoryRegion
*secure_sysmem
= NULL
;
2029 MemoryRegion
*tag_sysmem
= NULL
;
2030 MemoryRegion
*secure_tag_sysmem
= NULL
;
2031 int n
, virt_max_cpus
;
2032 bool firmware_loaded
;
2033 bool aarch64
= true;
2034 bool has_ged
= !vmc
->no_ged
;
2035 unsigned int smp_cpus
= machine
->smp
.cpus
;
2036 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2038 if (!cpu_type_valid(machine
->cpu_type
)) {
2039 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
2043 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2046 * In accelerated mode, the memory map is computed earlier in kvm_type()
2047 * to create a VM with the right number of IPA bits.
2055 * Instantiate a temporary CPU object to find out about what
2056 * we are about to deal with. Once this is done, get rid of
2059 cpuobj
= object_new(possible_cpus
->cpus
[0].type
);
2060 armcpu
= ARM_CPU(cpuobj
);
2062 pa_bits
= arm_pamax(armcpu
);
2064 object_unref(cpuobj
);
2066 virt_set_memmap(vms
, pa_bits
);
2069 /* We can probe only here because during property set
2070 * KVM is not available yet
2072 finalize_gic_version(vms
);
2076 * The Secure view of the world is the same as the NonSecure,
2077 * but with a few extra devices. Create it as a container region
2078 * containing the system memory at low priority; any secure-only
2079 * devices go in at higher priority and take precedence.
2081 secure_sysmem
= g_new(MemoryRegion
, 1);
2082 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
2084 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
2087 firmware_loaded
= virt_firmware_init(vms
, sysmem
,
2088 secure_sysmem
?: sysmem
);
2090 /* If we have an EL3 boot ROM then the assumption is that it will
2091 * implement PSCI itself, so disable QEMU's internal implementation
2092 * so it doesn't get in the way. Instead of starting secondary
2093 * CPUs in PSCI powerdown state we will start them all running and
2094 * let the boot ROM sort them out.
2095 * The usual case is that we do use QEMU's PSCI implementation;
2096 * if the guest has EL2 then we will use SMC as the conduit,
2097 * and otherwise we will use HVC (for backwards compatibility and
2098 * because if we're using KVM then we must use HVC).
2100 if (vms
->secure
&& firmware_loaded
) {
2101 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
2102 } else if (vms
->virt
) {
2103 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
2105 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
2109 * The maximum number of CPUs depends on the GIC version, or on how
2110 * many redistributors we can fit into the memory map (which in turn
2111 * depends on whether this is a GICv3 or v4).
2113 if (vms
->gic_version
== VIRT_GIC_VERSION_2
) {
2114 virt_max_cpus
= GIC_NCPU
;
2116 virt_max_cpus
= virt_redist_capacity(vms
, VIRT_GIC_REDIST
);
2117 if (vms
->highmem_redists
) {
2118 virt_max_cpus
+= virt_redist_capacity(vms
, VIRT_HIGH_GIC_REDIST2
);
2122 if (max_cpus
> virt_max_cpus
) {
2123 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2124 "supported by machine 'mach-virt' (%d)",
2125 max_cpus
, virt_max_cpus
);
2126 if (vms
->gic_version
!= VIRT_GIC_VERSION_2
&& !vms
->highmem_redists
) {
2127 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2133 if (vms
->secure
&& (kvm_enabled() || hvf_enabled())) {
2134 error_report("mach-virt: %s does not support providing "
2135 "Security extensions (TrustZone) to the guest CPU",
2136 current_accel_name());
2140 if (vms
->virt
&& (kvm_enabled() || hvf_enabled())) {
2141 error_report("mach-virt: %s does not support providing "
2142 "Virtualization extensions to the guest CPU",
2143 current_accel_name());
2147 if (vms
->mte
&& (kvm_enabled() || hvf_enabled())) {
2148 error_report("mach-virt: %s does not support providing "
2149 "MTE to the guest CPU",
2150 current_accel_name());
2156 assert(possible_cpus
->len
== max_cpus
);
2157 for (n
= 0; n
< possible_cpus
->len
; n
++) {
2161 if (n
>= smp_cpus
) {
2165 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
2166 object_property_set_int(cpuobj
, "mp-affinity",
2167 possible_cpus
->cpus
[n
].arch_id
, NULL
);
2172 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
2175 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
2178 object_property_set_bool(cpuobj
, "has_el3", false, NULL
);
2181 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2")) {
2182 object_property_set_bool(cpuobj
, "has_el2", false, NULL
);
2185 if (vmc
->kvm_no_adjvtime
&&
2186 object_property_find(cpuobj
, "kvm-no-adjvtime")) {
2187 object_property_set_bool(cpuobj
, "kvm-no-adjvtime", true, NULL
);
2190 if (vmc
->no_kvm_steal_time
&&
2191 object_property_find(cpuobj
, "kvm-steal-time")) {
2192 object_property_set_bool(cpuobj
, "kvm-steal-time", false, NULL
);
2195 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu")) {
2196 object_property_set_bool(cpuobj
, "pmu", false, NULL
);
2199 if (vmc
->no_tcg_lpa2
&& object_property_find(cpuobj
, "lpa2")) {
2200 object_property_set_bool(cpuobj
, "lpa2", false, NULL
);
2203 if (object_property_find(cpuobj
, "reset-cbar")) {
2204 object_property_set_int(cpuobj
, "reset-cbar",
2205 vms
->memmap
[VIRT_CPUPERIPHS
].base
,
2209 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
2212 object_property_set_link(cpuobj
, "secure-memory",
2213 OBJECT(secure_sysmem
), &error_abort
);
2217 /* Create the memory region only once, but link to all cpus. */
2220 * The property exists only if MemTag is supported.
2221 * If it is, we must allocate the ram to back that up.
2223 if (!object_property_find(cpuobj
, "tag-memory")) {
2224 error_report("MTE requested, but not supported "
2225 "by the guest CPU");
2229 tag_sysmem
= g_new(MemoryRegion
, 1);
2230 memory_region_init(tag_sysmem
, OBJECT(machine
),
2231 "tag-memory", UINT64_MAX
/ 32);
2234 secure_tag_sysmem
= g_new(MemoryRegion
, 1);
2235 memory_region_init(secure_tag_sysmem
, OBJECT(machine
),
2236 "secure-tag-memory", UINT64_MAX
/ 32);
2238 /* As with ram, secure-tag takes precedence over tag. */
2239 memory_region_add_subregion_overlap(secure_tag_sysmem
, 0,
2244 object_property_set_link(cpuobj
, "tag-memory", OBJECT(tag_sysmem
),
2247 object_property_set_link(cpuobj
, "secure-tag-memory",
2248 OBJECT(secure_tag_sysmem
),
2253 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
2254 object_unref(cpuobj
);
2256 fdt_add_timer_nodes(vms
);
2257 fdt_add_cpu_nodes(vms
);
2259 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2262 virt_flash_fdt(vms
, sysmem
, secure_sysmem
?: sysmem
);
2264 create_gic(vms
, sysmem
);
2266 virt_cpu_post_init(vms
, sysmem
);
2268 fdt_add_pmu_nodes(vms
);
2270 create_uart(vms
, VIRT_UART
, sysmem
, serial_hd(0));
2273 create_secure_ram(vms
, secure_sysmem
, secure_tag_sysmem
);
2274 create_uart(vms
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
2278 create_tag_ram(tag_sysmem
, vms
->memmap
[VIRT_MEM
].base
,
2279 machine
->ram_size
, "mach-virt.tag");
2282 vms
->highmem_ecam
&= (!firmware_loaded
|| aarch64
);
2288 if (has_ged
&& aarch64
&& firmware_loaded
&& virt_is_acpi_enabled(vms
)) {
2289 vms
->acpi_dev
= create_acpi_ged(vms
);
2291 create_gpio_devices(vms
, VIRT_GPIO
, sysmem
);
2294 if (vms
->secure
&& !vmc
->no_secure_gpio
) {
2295 create_gpio_devices(vms
, VIRT_SECURE_GPIO
, secure_sysmem
);
2298 /* connect powerdown request */
2299 vms
->powerdown_notifier
.notify
= virt_powerdown_req
;
2300 qemu_register_powerdown_notifier(&vms
->powerdown_notifier
);
2302 /* Create mmio transports, so the user can create virtio backends
2303 * (which will be automatically plugged in to the transports). If
2304 * no backend is created the transport will just sit harmlessly idle.
2306 create_virtio_devices(vms
);
2308 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
2309 rom_set_fw(vms
->fw_cfg
);
2311 create_platform_bus(vms
);
2313 if (machine
->nvdimms_state
->is_enabled
) {
2314 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio
= {
2315 .space_id
= AML_AS_SYSTEM_MEMORY
,
2316 .address
= vms
->memmap
[VIRT_NVDIMM_ACPI
].base
,
2317 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
2320 nvdimm_init_acpi_state(machine
->nvdimms_state
, sysmem
,
2321 arm_virt_nvdimm_acpi_dsmio
,
2322 vms
->fw_cfg
, OBJECT(vms
));
2325 vms
->bootinfo
.ram_size
= machine
->ram_size
;
2326 vms
->bootinfo
.board_id
= -1;
2327 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
2328 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
2329 vms
->bootinfo
.skip_dtb_autoload
= true;
2330 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
2331 vms
->bootinfo
.psci_conduit
= vms
->psci_conduit
;
2332 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &vms
->bootinfo
);
2334 vms
->machine_done
.notify
= virt_machine_done
;
2335 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
2338 static bool virt_get_secure(Object
*obj
, Error
**errp
)
2340 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2345 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
2347 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2349 vms
->secure
= value
;
2352 static bool virt_get_virt(Object
*obj
, Error
**errp
)
2354 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2359 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
2361 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2366 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
2368 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2370 return vms
->highmem
;
2373 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
2375 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2377 vms
->highmem
= value
;
2380 static bool virt_get_compact_highmem(Object
*obj
, Error
**errp
)
2382 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2384 return vms
->highmem_compact
;
2387 static void virt_set_compact_highmem(Object
*obj
, bool value
, Error
**errp
)
2389 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2391 vms
->highmem_compact
= value
;
2394 static bool virt_get_highmem_redists(Object
*obj
, Error
**errp
)
2396 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2398 return vms
->highmem_redists
;
2401 static void virt_set_highmem_redists(Object
*obj
, bool value
, Error
**errp
)
2403 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2405 vms
->highmem_redists
= value
;
2408 static bool virt_get_highmem_ecam(Object
*obj
, Error
**errp
)
2410 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2412 return vms
->highmem_ecam
;
2415 static void virt_set_highmem_ecam(Object
*obj
, bool value
, Error
**errp
)
2417 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2419 vms
->highmem_ecam
= value
;
2422 static bool virt_get_highmem_mmio(Object
*obj
, Error
**errp
)
2424 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2426 return vms
->highmem_mmio
;
2429 static void virt_set_highmem_mmio(Object
*obj
, bool value
, Error
**errp
)
2431 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2433 vms
->highmem_mmio
= value
;
2437 static bool virt_get_its(Object
*obj
, Error
**errp
)
2439 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2444 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
2446 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2451 static bool virt_get_dtb_randomness(Object
*obj
, Error
**errp
)
2453 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2455 return vms
->dtb_randomness
;
2458 static void virt_set_dtb_randomness(Object
*obj
, bool value
, Error
**errp
)
2460 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2462 vms
->dtb_randomness
= value
;
2465 static char *virt_get_oem_id(Object
*obj
, Error
**errp
)
2467 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2469 return g_strdup(vms
->oem_id
);
2472 static void virt_set_oem_id(Object
*obj
, const char *value
, Error
**errp
)
2474 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2475 size_t len
= strlen(value
);
2479 "User specified oem-id value is bigger than 6 bytes in size");
2483 strncpy(vms
->oem_id
, value
, 6);
2486 static char *virt_get_oem_table_id(Object
*obj
, Error
**errp
)
2488 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2490 return g_strdup(vms
->oem_table_id
);
2493 static void virt_set_oem_table_id(Object
*obj
, const char *value
,
2496 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2497 size_t len
= strlen(value
);
2501 "User specified oem-table-id value is bigger than 8 bytes in size");
2504 strncpy(vms
->oem_table_id
, value
, 8);
2508 bool virt_is_acpi_enabled(VirtMachineState
*vms
)
2510 if (vms
->acpi
== ON_OFF_AUTO_OFF
) {
2516 static void virt_get_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2517 void *opaque
, Error
**errp
)
2519 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2520 OnOffAuto acpi
= vms
->acpi
;
2522 visit_type_OnOffAuto(v
, name
, &acpi
, errp
);
2525 static void virt_set_acpi(Object
*obj
, Visitor
*v
, const char *name
,
2526 void *opaque
, Error
**errp
)
2528 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2530 visit_type_OnOffAuto(v
, name
, &vms
->acpi
, errp
);
2533 static bool virt_get_ras(Object
*obj
, Error
**errp
)
2535 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2540 static void virt_set_ras(Object
*obj
, bool value
, Error
**errp
)
2542 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2547 static bool virt_get_mte(Object
*obj
, Error
**errp
)
2549 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2554 static void virt_set_mte(Object
*obj
, bool value
, Error
**errp
)
2556 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2561 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
2563 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2566 switch (vms
->gic_version
) {
2567 case VIRT_GIC_VERSION_4
:
2570 case VIRT_GIC_VERSION_3
:
2577 return g_strdup(val
);
2580 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
2582 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2584 if (!strcmp(value
, "4")) {
2585 vms
->gic_version
= VIRT_GIC_VERSION_4
;
2586 } else if (!strcmp(value
, "3")) {
2587 vms
->gic_version
= VIRT_GIC_VERSION_3
;
2588 } else if (!strcmp(value
, "2")) {
2589 vms
->gic_version
= VIRT_GIC_VERSION_2
;
2590 } else if (!strcmp(value
, "host")) {
2591 vms
->gic_version
= VIRT_GIC_VERSION_HOST
; /* Will probe later */
2592 } else if (!strcmp(value
, "max")) {
2593 vms
->gic_version
= VIRT_GIC_VERSION_MAX
; /* Will probe later */
2595 error_setg(errp
, "Invalid gic-version value");
2596 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
2600 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
2602 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2604 switch (vms
->iommu
) {
2605 case VIRT_IOMMU_NONE
:
2606 return g_strdup("none");
2607 case VIRT_IOMMU_SMMUV3
:
2608 return g_strdup("smmuv3");
2610 g_assert_not_reached();
2614 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
2616 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2618 if (!strcmp(value
, "smmuv3")) {
2619 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
2620 } else if (!strcmp(value
, "none")) {
2621 vms
->iommu
= VIRT_IOMMU_NONE
;
2623 error_setg(errp
, "Invalid iommu value");
2624 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
2628 static bool virt_get_default_bus_bypass_iommu(Object
*obj
, Error
**errp
)
2630 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2632 return vms
->default_bus_bypass_iommu
;
2635 static void virt_set_default_bus_bypass_iommu(Object
*obj
, bool value
,
2638 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
2640 vms
->default_bus_bypass_iommu
= value
;
2643 static CpuInstanceProperties
2644 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2646 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2647 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2649 assert(cpu_index
< possible_cpus
->len
);
2650 return possible_cpus
->cpus
[cpu_index
].props
;
2653 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2655 int64_t socket_id
= ms
->possible_cpus
->cpus
[idx
].props
.socket_id
;
2657 return socket_id
% ms
->numa_state
->num_nodes
;
2660 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
2663 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2664 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2665 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2667 if (ms
->possible_cpus
) {
2668 assert(ms
->possible_cpus
->len
== max_cpus
);
2669 return ms
->possible_cpus
;
2672 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2673 sizeof(CPUArchId
) * max_cpus
);
2674 ms
->possible_cpus
->len
= max_cpus
;
2675 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
2676 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
2677 ms
->possible_cpus
->cpus
[n
].arch_id
=
2678 virt_cpu_mp_affinity(vms
, n
);
2680 assert(!mc
->smp_props
.dies_supported
);
2681 ms
->possible_cpus
->cpus
[n
].props
.has_socket_id
= true;
2682 ms
->possible_cpus
->cpus
[n
].props
.socket_id
=
2683 n
/ (ms
->smp
.clusters
* ms
->smp
.cores
* ms
->smp
.threads
);
2684 ms
->possible_cpus
->cpus
[n
].props
.has_cluster_id
= true;
2685 ms
->possible_cpus
->cpus
[n
].props
.cluster_id
=
2686 (n
/ (ms
->smp
.cores
* ms
->smp
.threads
)) % ms
->smp
.clusters
;
2687 ms
->possible_cpus
->cpus
[n
].props
.has_core_id
= true;
2688 ms
->possible_cpus
->cpus
[n
].props
.core_id
=
2689 (n
/ ms
->smp
.threads
) % ms
->smp
.cores
;
2690 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
2691 ms
->possible_cpus
->cpus
[n
].props
.thread_id
=
2692 n
% ms
->smp
.threads
;
2694 return ms
->possible_cpus
;
2697 static void virt_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2700 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2701 const MachineState
*ms
= MACHINE(hotplug_dev
);
2702 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2704 if (!vms
->acpi_dev
) {
2706 "memory hotplug is not enabled: missing acpi-ged device");
2711 error_setg(errp
, "memory hotplug is not enabled: MTE is enabled");
2715 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2716 error_setg(errp
, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2720 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
), NULL
, errp
);
2723 static void virt_memory_plug(HotplugHandler
*hotplug_dev
,
2724 DeviceState
*dev
, Error
**errp
)
2726 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2727 MachineState
*ms
= MACHINE(hotplug_dev
);
2728 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2730 pc_dimm_plug(PC_DIMM(dev
), MACHINE(vms
));
2733 nvdimm_plug(ms
->nvdimms_state
);
2736 hotplug_handler_plug(HOTPLUG_HANDLER(vms
->acpi_dev
),
2740 static void virt_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2741 DeviceState
*dev
, Error
**errp
)
2743 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2745 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2746 virt_memory_pre_plug(hotplug_dev
, dev
, errp
);
2747 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2748 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2749 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2750 hwaddr db_start
= 0, db_end
= 0;
2751 char *resv_prop_str
;
2753 if (vms
->iommu
!= VIRT_IOMMU_NONE
) {
2754 error_setg(errp
, "virt machine does not support multiple IOMMUs");
2758 switch (vms
->msi_controller
) {
2759 case VIRT_MSI_CTRL_NONE
:
2761 case VIRT_MSI_CTRL_ITS
:
2762 /* GITS_TRANSLATER page */
2763 db_start
= base_memmap
[VIRT_GIC_ITS
].base
+ 0x10000;
2764 db_end
= base_memmap
[VIRT_GIC_ITS
].base
+
2765 base_memmap
[VIRT_GIC_ITS
].size
- 1;
2767 case VIRT_MSI_CTRL_GICV2M
:
2768 /* MSI_SETSPI_NS page */
2769 db_start
= base_memmap
[VIRT_GIC_V2M
].base
;
2770 db_end
= db_start
+ base_memmap
[VIRT_GIC_V2M
].size
- 1;
2773 resv_prop_str
= g_strdup_printf("0x%"PRIx64
":0x%"PRIx64
":%u",
2775 VIRTIO_IOMMU_RESV_MEM_T_MSI
);
2777 object_property_set_uint(OBJECT(dev
), "len-reserved-regions", 1, errp
);
2778 object_property_set_str(OBJECT(dev
), "reserved-regions[0]",
2779 resv_prop_str
, errp
);
2780 g_free(resv_prop_str
);
2784 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2785 DeviceState
*dev
, Error
**errp
)
2787 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2789 if (vms
->platform_bus_dev
) {
2790 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
2792 if (device_is_dynamic_sysbus(mc
, dev
)) {
2793 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
2794 SYS_BUS_DEVICE(dev
));
2798 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2799 virt_memory_plug(hotplug_dev
, dev
, errp
);
2800 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2801 virtio_md_pci_plug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2804 if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2805 PCIDevice
*pdev
= PCI_DEVICE(dev
);
2807 vms
->iommu
= VIRT_IOMMU_VIRTIO
;
2808 vms
->virtio_iommu_bdf
= pci_get_bdf(pdev
);
2809 create_virtio_iommu_dt_bindings(vms
);
2813 static void virt_dimm_unplug_request(HotplugHandler
*hotplug_dev
,
2814 DeviceState
*dev
, Error
**errp
)
2816 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2818 if (!vms
->acpi_dev
) {
2820 "memory hotplug is not enabled: missing acpi-ged device");
2824 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2825 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
2829 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
,
2833 static void virt_dimm_unplug(HotplugHandler
*hotplug_dev
,
2834 DeviceState
*dev
, Error
**errp
)
2836 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
2837 Error
*local_err
= NULL
;
2839 hotplug_handler_unplug(HOTPLUG_HANDLER(vms
->acpi_dev
), dev
, &local_err
);
2844 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(vms
));
2845 qdev_unrealize(dev
);
2848 error_propagate(errp
, local_err
);
2851 static void virt_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2852 DeviceState
*dev
, Error
**errp
)
2854 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2855 virt_dimm_unplug_request(hotplug_dev
, dev
, errp
);
2856 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2857 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
),
2860 error_setg(errp
, "device unplug request for unsupported device"
2861 " type: %s", object_get_typename(OBJECT(dev
)));
2865 static void virt_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2866 DeviceState
*dev
, Error
**errp
)
2868 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2869 virt_dimm_unplug(hotplug_dev
, dev
, errp
);
2870 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
)) {
2871 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev
), MACHINE(hotplug_dev
), errp
);
2873 error_setg(errp
, "virt: device unplug for unsupported device"
2874 " type: %s", object_get_typename(OBJECT(dev
)));
2878 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
2881 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2883 if (device_is_dynamic_sysbus(mc
, dev
) ||
2884 object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2885 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_MD_PCI
) ||
2886 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_IOMMU_PCI
)) {
2887 return HOTPLUG_HANDLER(machine
);
2893 * for arm64 kvm_type [7-0] encodes the requested number of bits
2894 * in the IPA address space
2896 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
2898 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
2899 int max_vm_pa_size
, requested_pa_size
;
2902 max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
, &fixed_ipa
);
2904 /* we freeze the memory map to compute the highest gpa */
2905 virt_set_memmap(vms
, max_vm_pa_size
);
2907 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
2910 * KVM requires the IPA size to be at least 32 bits.
2912 if (requested_pa_size
< 32) {
2913 requested_pa_size
= 32;
2916 if (requested_pa_size
> max_vm_pa_size
) {
2917 error_report("-m and ,maxmem option values "
2918 "require an IPA range (%d bits) larger than "
2919 "the one supported by the host (%d bits)",
2920 requested_pa_size
, max_vm_pa_size
);
2924 * We return the requested PA log size, unless KVM only supports
2925 * the implicit legacy 40b IPA setting, in which case the kvm_type
2928 return fixed_ipa
? 0 : requested_pa_size
;
2931 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
2933 MachineClass
*mc
= MACHINE_CLASS(oc
);
2934 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2936 mc
->init
= machvirt_init
;
2937 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2938 * The value may be reduced later when we have more information about the
2939 * configuration of the particular instance.
2942 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
2943 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
2944 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
2945 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
2947 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_TPM_TIS_SYSBUS
);
2949 mc
->block_default_type
= IF_VIRTIO
;
2951 mc
->pci_allow_0_address
= true;
2952 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2953 mc
->minimum_page_bits
= 12;
2954 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
2955 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
2957 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
2959 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("max");
2961 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
2962 mc
->kvm_type
= virt_kvm_type
;
2963 assert(!mc
->get_hotplug_handler
);
2964 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
2965 hc
->pre_plug
= virt_machine_device_pre_plug_cb
;
2966 hc
->plug
= virt_machine_device_plug_cb
;
2967 hc
->unplug_request
= virt_machine_device_unplug_request_cb
;
2968 hc
->unplug
= virt_machine_device_unplug_cb
;
2969 mc
->nvdimm_supported
= true;
2970 mc
->smp_props
.clusters_supported
= true;
2971 mc
->auto_enable_numa_with_memhp
= true;
2972 mc
->auto_enable_numa_with_memdev
= true;
2973 /* platform instead of architectural choice */
2974 mc
->cpu_cluster_has_numa_boundary
= true;
2975 mc
->default_ram_id
= "mach-virt.ram";
2976 mc
->default_nic
= "virtio-net-pci";
2978 object_class_property_add(oc
, "acpi", "OnOffAuto",
2979 virt_get_acpi
, virt_set_acpi
,
2981 object_class_property_set_description(oc
, "acpi",
2983 object_class_property_add_bool(oc
, "secure", virt_get_secure
,
2985 object_class_property_set_description(oc
, "secure",
2986 "Set on/off to enable/disable the ARM "
2987 "Security Extensions (TrustZone)");
2989 object_class_property_add_bool(oc
, "virtualization", virt_get_virt
,
2991 object_class_property_set_description(oc
, "virtualization",
2992 "Set on/off to enable/disable emulating a "
2993 "guest CPU which implements the ARM "
2994 "Virtualization Extensions");
2996 object_class_property_add_bool(oc
, "highmem", virt_get_highmem
,
2998 object_class_property_set_description(oc
, "highmem",
2999 "Set on/off to enable/disable using "
3000 "physical address space above 32 bits");
3002 object_class_property_add_bool(oc
, "compact-highmem",
3003 virt_get_compact_highmem
,
3004 virt_set_compact_highmem
);
3005 object_class_property_set_description(oc
, "compact-highmem",
3006 "Set on/off to enable/disable compact "
3007 "layout for high memory regions");
3009 object_class_property_add_bool(oc
, "highmem-redists",
3010 virt_get_highmem_redists
,
3011 virt_set_highmem_redists
);
3012 object_class_property_set_description(oc
, "highmem-redists",
3013 "Set on/off to enable/disable high "
3014 "memory region for GICv3 or GICv4 "
3017 object_class_property_add_bool(oc
, "highmem-ecam",
3018 virt_get_highmem_ecam
,
3019 virt_set_highmem_ecam
);
3020 object_class_property_set_description(oc
, "highmem-ecam",
3021 "Set on/off to enable/disable high "
3022 "memory region for PCI ECAM");
3024 object_class_property_add_bool(oc
, "highmem-mmio",
3025 virt_get_highmem_mmio
,
3026 virt_set_highmem_mmio
);
3027 object_class_property_set_description(oc
, "highmem-mmio",
3028 "Set on/off to enable/disable high "
3029 "memory region for PCI MMIO");
3031 object_class_property_add_str(oc
, "gic-version", virt_get_gic_version
,
3032 virt_set_gic_version
);
3033 object_class_property_set_description(oc
, "gic-version",
3035 "Valid values are 2, 3, 4, host and max");
3037 object_class_property_add_str(oc
, "iommu", virt_get_iommu
, virt_set_iommu
);
3038 object_class_property_set_description(oc
, "iommu",
3039 "Set the IOMMU type. "
3040 "Valid values are none and smmuv3");
3042 object_class_property_add_bool(oc
, "default-bus-bypass-iommu",
3043 virt_get_default_bus_bypass_iommu
,
3044 virt_set_default_bus_bypass_iommu
);
3045 object_class_property_set_description(oc
, "default-bus-bypass-iommu",
3046 "Set on/off to enable/disable "
3047 "bypass_iommu for default root bus");
3049 object_class_property_add_bool(oc
, "ras", virt_get_ras
,
3051 object_class_property_set_description(oc
, "ras",
3052 "Set on/off to enable/disable reporting host memory errors "
3053 "to a KVM guest using ACPI and guest external abort exceptions");
3055 object_class_property_add_bool(oc
, "mte", virt_get_mte
, virt_set_mte
);
3056 object_class_property_set_description(oc
, "mte",
3057 "Set on/off to enable/disable emulating a "
3058 "guest CPU which implements the ARM "
3059 "Memory Tagging Extension");
3061 object_class_property_add_bool(oc
, "its", virt_get_its
,
3063 object_class_property_set_description(oc
, "its",
3064 "Set on/off to enable/disable "
3065 "ITS instantiation");
3067 object_class_property_add_bool(oc
, "dtb-randomness",
3068 virt_get_dtb_randomness
,
3069 virt_set_dtb_randomness
);
3070 object_class_property_set_description(oc
, "dtb-randomness",
3071 "Set off to disable passing random or "
3072 "non-deterministic dtb nodes to guest");
3074 object_class_property_add_bool(oc
, "dtb-kaslr-seed",
3075 virt_get_dtb_randomness
,
3076 virt_set_dtb_randomness
);
3077 object_class_property_set_description(oc
, "dtb-kaslr-seed",
3078 "Deprecated synonym of dtb-randomness");
3080 object_class_property_add_str(oc
, "x-oem-id",
3083 object_class_property_set_description(oc
, "x-oem-id",
3084 "Override the default value of field OEMID "
3085 "in ACPI table header."
3086 "The string may be up to 6 bytes in size");
3089 object_class_property_add_str(oc
, "x-oem-table-id",
3090 virt_get_oem_table_id
,
3091 virt_set_oem_table_id
);
3092 object_class_property_set_description(oc
, "x-oem-table-id",
3093 "Override the default value of field OEM Table ID "
3094 "in ACPI table header."
3095 "The string may be up to 8 bytes in size");
3099 static void virt_instance_init(Object
*obj
)
3101 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
3102 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
3104 /* EL3 is disabled by default on virt: this makes us consistent
3105 * between KVM and TCG for this board, and it also allows us to
3106 * boot UEFI blobs which assume no TrustZone support.
3108 vms
->secure
= false;
3110 /* EL2 is also disabled by default, for similar reasons */
3113 /* High memory is enabled by default */
3114 vms
->highmem
= true;
3115 vms
->highmem_compact
= !vmc
->no_highmem_compact
;
3116 vms
->gic_version
= VIRT_GIC_VERSION_NOSEL
;
3118 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
3119 vms
->highmem_mmio
= true;
3120 vms
->highmem_redists
= true;
3125 /* Default allows ITS instantiation */
3128 if (vmc
->no_tcg_its
) {
3129 vms
->tcg_its
= false;
3131 vms
->tcg_its
= true;
3135 /* Default disallows iommu instantiation */
3136 vms
->iommu
= VIRT_IOMMU_NONE
;
3138 /* The default root bus is attached to iommu by default */
3139 vms
->default_bus_bypass_iommu
= false;
3141 /* Default disallows RAS instantiation */
3144 /* MTE is disabled by default. */
3147 /* Supply kaslr-seed and rng-seed by default */
3148 vms
->dtb_randomness
= true;
3150 vms
->irqmap
= a15irqmap
;
3152 virt_flash_create(vms
);
3154 vms
->oem_id
= g_strndup(ACPI_BUILD_APPNAME6
, 6);
3155 vms
->oem_table_id
= g_strndup(ACPI_BUILD_APPNAME8
, 8);
3158 static const TypeInfo virt_machine_info
= {
3159 .name
= TYPE_VIRT_MACHINE
,
3160 .parent
= TYPE_MACHINE
,
3162 .instance_size
= sizeof(VirtMachineState
),
3163 .class_size
= sizeof(VirtMachineClass
),
3164 .class_init
= virt_machine_class_init
,
3165 .instance_init
= virt_instance_init
,
3166 .interfaces
= (InterfaceInfo
[]) {
3167 { TYPE_HOTPLUG_HANDLER
},
3172 static void machvirt_machine_init(void)
3174 type_register_static(&virt_machine_info
);
3176 type_init(machvirt_machine_init
);
3178 static void virt_machine_8_2_options(MachineClass
*mc
)
3181 DEFINE_VIRT_MACHINE_AS_LATEST(8, 2)
3183 static void virt_machine_8_1_options(MachineClass
*mc
)
3185 virt_machine_8_2_options(mc
);
3186 compat_props_add(mc
->compat_props
, hw_compat_8_1
, hw_compat_8_1_len
);
3188 DEFINE_VIRT_MACHINE(8, 1)
3190 static void virt_machine_8_0_options(MachineClass
*mc
)
3192 virt_machine_8_1_options(mc
);
3193 compat_props_add(mc
->compat_props
, hw_compat_8_0
, hw_compat_8_0_len
);
3195 DEFINE_VIRT_MACHINE(8, 0)
3197 static void virt_machine_7_2_options(MachineClass
*mc
)
3199 virt_machine_8_0_options(mc
);
3200 compat_props_add(mc
->compat_props
, hw_compat_7_2
, hw_compat_7_2_len
);
3202 DEFINE_VIRT_MACHINE(7, 2)
3204 static void virt_machine_7_1_options(MachineClass
*mc
)
3206 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3208 virt_machine_7_2_options(mc
);
3209 compat_props_add(mc
->compat_props
, hw_compat_7_1
, hw_compat_7_1_len
);
3210 /* Compact layout for high memory regions was introduced with 7.2 */
3211 vmc
->no_highmem_compact
= true;
3213 DEFINE_VIRT_MACHINE(7, 1)
3215 static void virt_machine_7_0_options(MachineClass
*mc
)
3217 virt_machine_7_1_options(mc
);
3218 compat_props_add(mc
->compat_props
, hw_compat_7_0
, hw_compat_7_0_len
);
3220 DEFINE_VIRT_MACHINE(7, 0)
3222 static void virt_machine_6_2_options(MachineClass
*mc
)
3224 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3226 virt_machine_7_0_options(mc
);
3227 compat_props_add(mc
->compat_props
, hw_compat_6_2
, hw_compat_6_2_len
);
3228 vmc
->no_tcg_lpa2
= true;
3230 DEFINE_VIRT_MACHINE(6, 2)
3232 static void virt_machine_6_1_options(MachineClass
*mc
)
3234 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3236 virt_machine_6_2_options(mc
);
3237 compat_props_add(mc
->compat_props
, hw_compat_6_1
, hw_compat_6_1_len
);
3238 mc
->smp_props
.prefer_sockets
= true;
3239 vmc
->no_cpu_topology
= true;
3241 /* qemu ITS was introduced with 6.2 */
3242 vmc
->no_tcg_its
= true;
3244 DEFINE_VIRT_MACHINE(6, 1)
3246 static void virt_machine_6_0_options(MachineClass
*mc
)
3248 virt_machine_6_1_options(mc
);
3249 compat_props_add(mc
->compat_props
, hw_compat_6_0
, hw_compat_6_0_len
);
3251 DEFINE_VIRT_MACHINE(6, 0)
3253 static void virt_machine_5_2_options(MachineClass
*mc
)
3255 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3257 virt_machine_6_0_options(mc
);
3258 compat_props_add(mc
->compat_props
, hw_compat_5_2
, hw_compat_5_2_len
);
3259 vmc
->no_secure_gpio
= true;
3261 DEFINE_VIRT_MACHINE(5, 2)
3263 static void virt_machine_5_1_options(MachineClass
*mc
)
3265 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3267 virt_machine_5_2_options(mc
);
3268 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
3269 vmc
->no_kvm_steal_time
= true;
3271 DEFINE_VIRT_MACHINE(5, 1)
3273 static void virt_machine_5_0_options(MachineClass
*mc
)
3275 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3277 virt_machine_5_1_options(mc
);
3278 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
3279 mc
->numa_mem_supported
= true;
3280 vmc
->acpi_expose_flash
= true;
3281 mc
->auto_enable_numa_with_memdev
= false;
3283 DEFINE_VIRT_MACHINE(5, 0)
3285 static void virt_machine_4_2_options(MachineClass
*mc
)
3287 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3289 virt_machine_5_0_options(mc
);
3290 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
3291 vmc
->kvm_no_adjvtime
= true;
3293 DEFINE_VIRT_MACHINE(4, 2)
3295 static void virt_machine_4_1_options(MachineClass
*mc
)
3297 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3299 virt_machine_4_2_options(mc
);
3300 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
3302 mc
->auto_enable_numa_with_memhp
= false;
3304 DEFINE_VIRT_MACHINE(4, 1)
3306 static void virt_machine_4_0_options(MachineClass
*mc
)
3308 virt_machine_4_1_options(mc
);
3309 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
3311 DEFINE_VIRT_MACHINE(4, 0)
3313 static void virt_machine_3_1_options(MachineClass
*mc
)
3315 virt_machine_4_0_options(mc
);
3316 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
3318 DEFINE_VIRT_MACHINE(3, 1)
3320 static void virt_machine_3_0_options(MachineClass
*mc
)
3322 virt_machine_3_1_options(mc
);
3323 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
3325 DEFINE_VIRT_MACHINE(3, 0)
3327 static void virt_machine_2_12_options(MachineClass
*mc
)
3329 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3331 virt_machine_3_0_options(mc
);
3332 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
3333 vmc
->no_highmem_ecam
= true;
3336 DEFINE_VIRT_MACHINE(2, 12)
3338 static void virt_machine_2_11_options(MachineClass
*mc
)
3340 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3342 virt_machine_2_12_options(mc
);
3343 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
3344 vmc
->smbios_old_sys_ver
= true;
3346 DEFINE_VIRT_MACHINE(2, 11)
3348 static void virt_machine_2_10_options(MachineClass
*mc
)
3350 virt_machine_2_11_options(mc
);
3351 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
3352 /* before 2.11 we never faulted accesses to bad addresses */
3353 mc
->ignore_memory_transaction_failures
= true;
3355 DEFINE_VIRT_MACHINE(2, 10)
3357 static void virt_machine_2_9_options(MachineClass
*mc
)
3359 virt_machine_2_10_options(mc
);
3360 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
3362 DEFINE_VIRT_MACHINE(2, 9)
3364 static void virt_machine_2_8_options(MachineClass
*mc
)
3366 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3368 virt_machine_2_9_options(mc
);
3369 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
3370 /* For 2.8 and earlier we falsely claimed in the DT that
3371 * our timers were edge-triggered, not level-triggered.
3373 vmc
->claim_edge_triggered_timers
= true;
3375 DEFINE_VIRT_MACHINE(2, 8)
3377 static void virt_machine_2_7_options(MachineClass
*mc
)
3379 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3381 virt_machine_2_8_options(mc
);
3382 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
3383 /* ITS was introduced with 2.8 */
3385 /* Stick with 1K pages for migration compatibility */
3386 mc
->minimum_page_bits
= 0;
3388 DEFINE_VIRT_MACHINE(2, 7)
3390 static void virt_machine_2_6_options(MachineClass
*mc
)
3392 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
3394 virt_machine_2_7_options(mc
);
3395 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
3396 vmc
->disallow_affinity_adjustment
= true;
3397 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3400 DEFINE_VIRT_MACHINE(2, 6)