hw/arm_gic.c

   1 /*
   2  * ARM Generic/Distributed Interrupt Controller
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 /* This file contains implementation code for the RealView EB interrupt
  11    controller, MPCore distributed interrupt controller and ARMv7-M
  12    Nested Vectored Interrupt Controller.  */
  13
  14 #include "sysbus.h"
  15
  16 /* Maximum number of possible interrupts, determined by the GIC architecture */
  17 #define GIC_MAXIRQ 1020
  18 /* First 32 are private to each CPU (SGIs and PPIs). */
  19 #define GIC_INTERNAL 32
  20 /* Maximum number of possible CPU interfaces, determined by GIC architecture */
  21 #ifdef NVIC
  22 #define NCPU 1
  23 #else
  24 #define NCPU 8
  25 #endif
  26
  27 //#define DEBUG_GIC
  28
  29 #ifdef DEBUG_GIC
  30 #define DPRINTF(fmt, ...) \
  31 do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
  32 #else
  33 #define DPRINTF(fmt, ...) do {} while(0)
  34 #endif
  35
  36 #ifdef NVIC
  37 static const uint8_t gic_id[] =
  38 { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
  39 /* The NVIC has 16 internal vectors.  However these are not exposed
  40    through the normal GIC interface.  */
  41 #define GIC_BASE_IRQ    32
  42 #else
  43 static const uint8_t gic_id[] =
  44 { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  45 #define GIC_BASE_IRQ    0
  46 #endif
  47
  48 #define FROM_SYSBUSGIC(type, dev) \
  49     DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev))
  50
  51 typedef struct gic_irq_state
  52 {
  53     /* The enable bits are only banked for per-cpu interrupts.  */
  54     unsigned enabled:NCPU;
  55     unsigned pending:NCPU;
  56     unsigned active:NCPU;
  57     unsigned level:NCPU;
  58     unsigned model:1; /* 0 = N:N, 1 = 1:N */
  59     unsigned trigger:1; /* nonzero = edge triggered.  */
  60 } gic_irq_state;
  61
  62 #define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1)))
  63 #if NCPU > 1
  64 #define NUM_CPU(s) ((s)->num_cpu)
  65 #else
  66 #define NUM_CPU(s) 1
  67 #endif
  68
  69 #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
  70 #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
  71 #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
  72 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
  73 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
  74 #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
  75 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
  76 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
  77 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
  78 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
  79 #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
  80 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
  81 #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
  82 #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
  83 #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
  84 #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
  85 #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
  86 #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
  87 #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ?            \
  88                                     s->priority1[irq][cpu] :            \
  89                                     s->priority2[(irq) - GIC_INTERNAL])
  90 #ifdef NVIC
  91 #define GIC_TARGET(irq) 1
  92 #else
  93 #define GIC_TARGET(irq) s->irq_target[irq]
  94 #endif
  95
  96 typedef struct gic_state
  97 {
  98     SysBusDevice busdev;
  99     qemu_irq parent_irq[NCPU];
 100     int enabled;
 101     int cpu_enabled[NCPU];
 102
 103     gic_irq_state irq_state[GIC_MAXIRQ];
 104 #ifndef NVIC
 105     int irq_target[GIC_MAXIRQ];
 106 #endif
 107     int priority1[GIC_INTERNAL][NCPU];
 108     int priority2[GIC_MAXIRQ - GIC_INTERNAL];
 109     int last_active[GIC_MAXIRQ][NCPU];
 110
 111     int priority_mask[NCPU];
 112     int running_irq[NCPU];
 113     int running_priority[NCPU];
 114     int current_pending[NCPU];
 115
 116 #if NCPU > 1
 117     uint32_t num_cpu;
 118 #endif
 119
 120     MemoryRegion iomem; /* Distributor */
 121 #ifndef NVIC
 122     /* This is just so we can have an opaque pointer which identifies
 123      * both this GIC and which CPU interface we should be accessing.
 124      */
 125     struct gic_state *backref[NCPU];
 126     MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */
 127 #endif
 128     uint32_t num_irq;
 129 } gic_state;
 130
 131 static inline int gic_get_current_cpu(gic_state *s)
 132 {
 133 #if NCPU > 1
 134     if (s->num_cpu > 1) {
 135         return cpu_single_env->cpu_index;
 136     }
 137 #endif
 138     return 0;
 139 }
 140
 141 /* TODO: Many places that call this routine could be optimized.  */
 142 /* Update interrupt status after enabled or pending bits have been changed.  */
 143 static void gic_update(gic_state *s)
 144 {
 145     int best_irq;
 146     int best_prio;
 147     int irq;
 148     int level;
 149     int cpu;
 150     int cm;
 151
 152     for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
 153         cm = 1 << cpu;
 154         s->current_pending[cpu] = 1023;
 155         if (!s->enabled || !s->cpu_enabled[cpu]) {
 156             qemu_irq_lower(s->parent_irq[cpu]);
 157             return;
 158         }
 159         best_prio = 0x100;
 160         best_irq = 1023;
 161         for (irq = 0; irq < s->num_irq; irq++) {
 162             if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) {
 163                 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
 164                     best_prio = GIC_GET_PRIORITY(irq, cpu);
 165                     best_irq = irq;
 166                 }
 167             }
 168         }
 169         level = 0;
 170         if (best_prio <= s->priority_mask[cpu]) {
 171             s->current_pending[cpu] = best_irq;
 172             if (best_prio < s->running_priority[cpu]) {
 173                 DPRINTF("Raised pending IRQ %d\n", best_irq);
 174                 level = 1;
 175             }
 176         }
 177         qemu_set_irq(s->parent_irq[cpu], level);
 178     }
 179 }
 180
 181 static void __attribute__((unused))
 182 gic_set_pending_private(gic_state *s, int cpu, int irq)
 183 {
 184     int cm = 1 << cpu;
 185
 186     if (GIC_TEST_PENDING(irq, cm))
 187         return;
 188
 189     DPRINTF("Set %d pending cpu %d\n", irq, cpu);
 190     GIC_SET_PENDING(irq, cm);
 191     gic_update(s);
 192 }
 193
 194 /* Process a change in an external IRQ input.  */
 195 static void gic_set_irq(void *opaque, int irq, int level)
 196 {
 197     /* Meaning of the 'irq' parameter:
 198      *  [0..N-1] : external interrupts
 199      *  [N..N+31] : PPI (internal) interrupts for CPU 0
 200      *  [N+32..N+63] : PPI (internal interrupts for CPU 1
 201      *  ...
 202      */
 203     gic_state *s = (gic_state *)opaque;
 204     int cm, target;
 205     if (irq < (s->num_irq - GIC_INTERNAL)) {
 206         /* The first external input line is internal interrupt 32.  */
 207         cm = ALL_CPU_MASK;
 208         irq += GIC_INTERNAL;
 209         target = GIC_TARGET(irq);
 210     } else {
 211         int cpu;
 212         irq -= (s->num_irq - GIC_INTERNAL);
 213         cpu = irq / GIC_INTERNAL;
 214         irq %= GIC_INTERNAL;
 215         cm = 1 << cpu;
 216         target = cm;
 217     }
 218
 219     if (level == GIC_TEST_LEVEL(irq, cm)) {
 220         return;
 221     }
 222
 223     if (level) {
 224         GIC_SET_LEVEL(irq, cm);
 225         if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
 226             DPRINTF("Set %d pending mask %x\n", irq, target);
 227             GIC_SET_PENDING(irq, target);
 228         }
 229     } else {
 230         GIC_CLEAR_LEVEL(irq, cm);
 231     }
 232     gic_update(s);
 233 }
 234
 235 static void gic_set_running_irq(gic_state *s, int cpu, int irq)
 236 {
 237     s->running_irq[cpu] = irq;
 238     if (irq == 1023) {
 239         s->running_priority[cpu] = 0x100;
 240     } else {
 241         s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu);
 242     }
 243     gic_update(s);
 244 }
 245
 246 static uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
 247 {
 248     int new_irq;
 249     int cm = 1 << cpu;
 250     new_irq = s->current_pending[cpu];
 251     if (new_irq == 1023
 252             || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) {
 253         DPRINTF("ACK no pending IRQ\n");
 254         return 1023;
 255     }
 256     s->last_active[new_irq][cpu] = s->running_irq[cpu];
 257     /* Clear pending flags for both level and edge triggered interrupts.
 258        Level triggered IRQs will be reasserted once they become inactive.  */
 259     GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm);
 260     gic_set_running_irq(s, cpu, new_irq);
 261     DPRINTF("ACK %d\n", new_irq);
 262     return new_irq;
 263 }
 264
 265 static void gic_complete_irq(gic_state * s, int cpu, int irq)
 266 {
 267     int update = 0;
 268     int cm = 1 << cpu;
 269     DPRINTF("EOI %d\n", irq);
 270     if (irq >= s->num_irq) {
 271         /* This handles two cases:
 272          * 1. If software writes the ID of a spurious interrupt [ie 1023]
 273          * to the GICC_EOIR, the GIC ignores that write.
 274          * 2. If software writes the number of a non-existent interrupt
 275          * this must be a subcase of "value written does not match the last
 276          * valid interrupt value read from the Interrupt Acknowledge
 277          * register" and so this is UNPREDICTABLE. We choose to ignore it.
 278          */
 279         return;
 280     }
 281     if (s->running_irq[cpu] == 1023)
 282         return; /* No active IRQ.  */
 283     /* Mark level triggered interrupts as pending if they are still
 284        raised.  */
 285     if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
 286         && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
 287         DPRINTF("Set %d pending mask %x\n", irq, cm);
 288         GIC_SET_PENDING(irq, cm);
 289         update = 1;
 290     }
 291     if (irq != s->running_irq[cpu]) {
 292         /* Complete an IRQ that is not currently running.  */
 293         int tmp = s->running_irq[cpu];
 294         while (s->last_active[tmp][cpu] != 1023) {
 295             if (s->last_active[tmp][cpu] == irq) {
 296                 s->last_active[tmp][cpu] = s->last_active[irq][cpu];
 297                 break;
 298             }
 299             tmp = s->last_active[tmp][cpu];
 300         }
 301         if (update) {
 302             gic_update(s);
 303         }
 304     } else {
 305         /* Complete the current running IRQ.  */
 306         gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]);
 307     }
 308 }
 309
 310 static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
 311 {
 312     gic_state *s = (gic_state *)opaque;
 313     uint32_t res;
 314     int irq;
 315     int i;
 316     int cpu;
 317     int cm;
 318     int mask;
 319
 320     cpu = gic_get_current_cpu(s);
 321     cm = 1 << cpu;
 322     if (offset < 0x100) {
 323 #ifndef NVIC
 324         if (offset == 0)
 325             return s->enabled;
 326         if (offset == 4)
 327             return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
 328         if (offset < 0x08)
 329             return 0;
 330         if (offset >= 0x80) {
 331             /* Interrupt Security , RAZ/WI */
 332             return 0;
 333         }
 334 #endif
 335         goto bad_reg;
 336     } else if (offset < 0x200) {
 337         /* Interrupt Set/Clear Enable.  */
 338         if (offset < 0x180)
 339             irq = (offset - 0x100) * 8;
 340         else
 341             irq = (offset - 0x180) * 8;
 342         irq += GIC_BASE_IRQ;
 343         if (irq >= s->num_irq)
 344             goto bad_reg;
 345         res = 0;
 346         for (i = 0; i < 8; i++) {
 347             if (GIC_TEST_ENABLED(irq + i, cm)) {
 348                 res |= (1 << i);
 349             }
 350         }
 351     } else if (offset < 0x300) {
 352         /* Interrupt Set/Clear Pending.  */
 353         if (offset < 0x280)
 354             irq = (offset - 0x200) * 8;
 355         else
 356             irq = (offset - 0x280) * 8;
 357         irq += GIC_BASE_IRQ;
 358         if (irq >= s->num_irq)
 359             goto bad_reg;
 360         res = 0;
 361         mask = (irq < GIC_INTERNAL) ?  cm : ALL_CPU_MASK;
 362         for (i = 0; i < 8; i++) {
 363             if (GIC_TEST_PENDING(irq + i, mask)) {
 364                 res |= (1 << i);
 365             }
 366         }
 367     } else if (offset < 0x400) {
 368         /* Interrupt Active.  */
 369         irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
 370         if (irq >= s->num_irq)
 371             goto bad_reg;
 372         res = 0;
 373         mask = (irq < GIC_INTERNAL) ?  cm : ALL_CPU_MASK;
 374         for (i = 0; i < 8; i++) {
 375             if (GIC_TEST_ACTIVE(irq + i, mask)) {
 376                 res |= (1 << i);
 377             }
 378         }
 379     } else if (offset < 0x800) {
 380         /* Interrupt Priority.  */
 381         irq = (offset - 0x400) + GIC_BASE_IRQ;
 382         if (irq >= s->num_irq)
 383             goto bad_reg;
 384         res = GIC_GET_PRIORITY(irq, cpu);
 385 #ifndef NVIC
 386     } else if (offset < 0xc00) {
 387         /* Interrupt CPU Target.  */
 388         irq = (offset - 0x800) + GIC_BASE_IRQ;
 389         if (irq >= s->num_irq)
 390             goto bad_reg;
 391         if (irq >= 29 && irq <= 31) {
 392             res = cm;
 393         } else {
 394             res = GIC_TARGET(irq);
 395         }
 396     } else if (offset < 0xf00) {
 397         /* Interrupt Configuration.  */
 398         irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
 399         if (irq >= s->num_irq)
 400             goto bad_reg;
 401         res = 0;
 402         for (i = 0; i < 4; i++) {
 403             if (GIC_TEST_MODEL(irq + i))
 404                 res |= (1 << (i * 2));
 405             if (GIC_TEST_TRIGGER(irq + i))
 406                 res |= (2 << (i * 2));
 407         }
 408 #endif
 409     } else if (offset < 0xfe0) {
 410         goto bad_reg;
 411     } else /* offset >= 0xfe0 */ {
 412         if (offset & 3) {
 413             res = 0;
 414         } else {
 415             res = gic_id[(offset - 0xfe0) >> 2];
 416         }
 417     }
 418     return res;
 419 bad_reg:
 420     hw_error("gic_dist_readb: Bad offset %x\n", (int)offset);
 421     return 0;
 422 }
 423
 424 static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
 425 {
 426     uint32_t val;
 427     val = gic_dist_readb(opaque, offset);
 428     val |= gic_dist_readb(opaque, offset + 1) << 8;
 429     return val;
 430 }
 431
 432 static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
 433 {
 434     uint32_t val;
 435 #ifdef NVIC
 436     gic_state *s = (gic_state *)opaque;
 437     uint32_t addr;
 438     addr = offset;
 439     if (addr < 0x100 || addr > 0xd00)
 440         return nvic_readl(s, addr);
 441 #endif
 442     val = gic_dist_readw(opaque, offset);
 443     val |= gic_dist_readw(opaque, offset + 2) << 16;
 444     return val;
 445 }
 446
 447 static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
 448                             uint32_t value)
 449 {
 450     gic_state *s = (gic_state *)opaque;
 451     int irq;
 452     int i;
 453     int cpu;
 454
 455     cpu = gic_get_current_cpu(s);
 456     if (offset < 0x100) {
 457 #ifdef NVIC
 458         goto bad_reg;
 459 #else
 460         if (offset == 0) {
 461             s->enabled = (value & 1);
 462             DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
 463         } else if (offset < 4) {
 464             /* ignored.  */
 465         } else if (offset >= 0x80) {
 466             /* Interrupt Security Registers, RAZ/WI */
 467         } else {
 468             goto bad_reg;
 469         }
 470 #endif
 471     } else if (offset < 0x180) {
 472         /* Interrupt Set Enable.  */
 473         irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
 474         if (irq >= s->num_irq)
 475             goto bad_reg;
 476         if (irq < 16)
 477           value = 0xff;
 478         for (i = 0; i < 8; i++) {
 479             if (value & (1 << i)) {
 480                 int mask = (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq);
 481                 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 482
 483                 if (!GIC_TEST_ENABLED(irq + i, cm)) {
 484                     DPRINTF("Enabled IRQ %d\n", irq + i);
 485                 }
 486                 GIC_SET_ENABLED(irq + i, cm);
 487                 /* If a raised level triggered IRQ enabled then mark
 488                    is as pending.  */
 489                 if (GIC_TEST_LEVEL(irq + i, mask)
 490                         && !GIC_TEST_TRIGGER(irq + i)) {
 491                     DPRINTF("Set %d pending mask %x\n", irq + i, mask);
 492                     GIC_SET_PENDING(irq + i, mask);
 493                 }
 494             }
 495         }
 496     } else if (offset < 0x200) {
 497         /* Interrupt Clear Enable.  */
 498         irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
 499         if (irq >= s->num_irq)
 500             goto bad_reg;
 501         if (irq < 16)
 502           value = 0;
 503         for (i = 0; i < 8; i++) {
 504             if (value & (1 << i)) {
 505                 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 506
 507                 if (GIC_TEST_ENABLED(irq + i, cm)) {
 508                     DPRINTF("Disabled IRQ %d\n", irq + i);
 509                 }
 510                 GIC_CLEAR_ENABLED(irq + i, cm);
 511             }
 512         }
 513     } else if (offset < 0x280) {
 514         /* Interrupt Set Pending.  */
 515         irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
 516         if (irq >= s->num_irq)
 517             goto bad_reg;
 518         if (irq < 16)
 519           irq = 0;
 520
 521         for (i = 0; i < 8; i++) {
 522             if (value & (1 << i)) {
 523                 GIC_SET_PENDING(irq + i, GIC_TARGET(irq));
 524             }
 525         }
 526     } else if (offset < 0x300) {
 527         /* Interrupt Clear Pending.  */
 528         irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
 529         if (irq >= s->num_irq)
 530             goto bad_reg;
 531         for (i = 0; i < 8; i++) {
 532             /* ??? This currently clears the pending bit for all CPUs, even
 533                for per-CPU interrupts.  It's unclear whether this is the
 534                corect behavior.  */
 535             if (value & (1 << i)) {
 536                 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
 537             }
 538         }
 539     } else if (offset < 0x400) {
 540         /* Interrupt Active.  */
 541         goto bad_reg;
 542     } else if (offset < 0x800) {
 543         /* Interrupt Priority.  */
 544         irq = (offset - 0x400) + GIC_BASE_IRQ;
 545         if (irq >= s->num_irq)
 546             goto bad_reg;
 547         if (irq < GIC_INTERNAL) {
 548             s->priority1[irq][cpu] = value;
 549         } else {
 550             s->priority2[irq - GIC_INTERNAL] = value;
 551         }
 552 #ifndef NVIC
 553     } else if (offset < 0xc00) {
 554         /* Interrupt CPU Target.  */
 555         irq = (offset - 0x800) + GIC_BASE_IRQ;
 556         if (irq >= s->num_irq)
 557             goto bad_reg;
 558         if (irq < 29)
 559             value = 0;
 560         else if (irq < GIC_INTERNAL)
 561             value = ALL_CPU_MASK;
 562         s->irq_target[irq] = value & ALL_CPU_MASK;
 563     } else if (offset < 0xf00) {
 564         /* Interrupt Configuration.  */
 565         irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
 566         if (irq >= s->num_irq)
 567             goto bad_reg;
 568         if (irq < GIC_INTERNAL)
 569             value |= 0xaa;
 570         for (i = 0; i < 4; i++) {
 571             if (value & (1 << (i * 2))) {
 572                 GIC_SET_MODEL(irq + i);
 573             } else {
 574                 GIC_CLEAR_MODEL(irq + i);
 575             }
 576             if (value & (2 << (i * 2))) {
 577                 GIC_SET_TRIGGER(irq + i);
 578             } else {
 579                 GIC_CLEAR_TRIGGER(irq + i);
 580             }
 581         }
 582 #endif
 583     } else {
 584         /* 0xf00 is only handled for 32-bit writes.  */
 585         goto bad_reg;
 586     }
 587     gic_update(s);
 588     return;
 589 bad_reg:
 590     hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
 591 }
 592
 593 static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
 594                             uint32_t value)
 595 {
 596     gic_dist_writeb(opaque, offset, value & 0xff);
 597     gic_dist_writeb(opaque, offset + 1, value >> 8);
 598 }
 599
 600 static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
 601                             uint32_t value)
 602 {
 603     gic_state *s = (gic_state *)opaque;
 604 #ifdef NVIC
 605     uint32_t addr;
 606     addr = offset;
 607     if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
 608         nvic_writel(s, addr, value);
 609         return;
 610     }
 611 #endif
 612     if (offset == 0xf00) {
 613         int cpu;
 614         int irq;
 615         int mask;
 616
 617         cpu = gic_get_current_cpu(s);
 618         irq = value & 0x3ff;
 619         switch ((value >> 24) & 3) {
 620         case 0:
 621             mask = (value >> 16) & ALL_CPU_MASK;
 622             break;
 623         case 1:
 624             mask = ALL_CPU_MASK ^ (1 << cpu);
 625             break;
 626         case 2:
 627             mask = 1 << cpu;
 628             break;
 629         default:
 630             DPRINTF("Bad Soft Int target filter\n");
 631             mask = ALL_CPU_MASK;
 632             break;
 633         }
 634         GIC_SET_PENDING(irq, mask);
 635         gic_update(s);
 636         return;
 637     }
 638     gic_dist_writew(opaque, offset, value & 0xffff);
 639     gic_dist_writew(opaque, offset + 2, value >> 16);
 640 }
 641
 642 static const MemoryRegionOps gic_dist_ops = {
 643     .old_mmio = {
 644         .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, },
 645         .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, },
 646     },
 647     .endianness = DEVICE_NATIVE_ENDIAN,
 648 };
 649
 650 #ifndef NVIC
 651 static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset)
 652 {
 653     switch (offset) {
 654     case 0x00: /* Control */
 655         return s->cpu_enabled[cpu];
 656     case 0x04: /* Priority mask */
 657         return s->priority_mask[cpu];
 658     case 0x08: /* Binary Point */
 659         /* ??? Not implemented.  */
 660         return 0;
 661     case 0x0c: /* Acknowledge */
 662         return gic_acknowledge_irq(s, cpu);
 663     case 0x14: /* Running Priority */
 664         return s->running_priority[cpu];
 665     case 0x18: /* Highest Pending Interrupt */
 666         return s->current_pending[cpu];
 667     default:
 668         hw_error("gic_cpu_read: Bad offset %x\n", (int)offset);
 669         return 0;
 670     }
 671 }
 672
 673 static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)
 674 {
 675     switch (offset) {
 676     case 0x00: /* Control */
 677         s->cpu_enabled[cpu] = (value & 1);
 678         DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis");
 679         break;
 680     case 0x04: /* Priority mask */
 681         s->priority_mask[cpu] = (value & 0xff);
 682         break;
 683     case 0x08: /* Binary Point */
 684         /* ??? Not implemented.  */
 685         break;
 686     case 0x10: /* End Of Interrupt */
 687         return gic_complete_irq(s, cpu, value & 0x3ff);
 688     default:
 689         hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);
 690         return;
 691     }
 692     gic_update(s);
 693 }
 694
 695 /* Wrappers to read/write the GIC CPU interface for the current CPU */
 696 static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
 697                                  unsigned size)
 698 {
 699     gic_state *s = (gic_state *)opaque;
 700     return gic_cpu_read(s, gic_get_current_cpu(s), addr);
 701 }
 702
 703 static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
 704                               uint64_t value, unsigned size)
 705 {
 706     gic_state *s = (gic_state *)opaque;
 707     gic_cpu_write(s, gic_get_current_cpu(s), addr, value);
 708 }
 709
 710 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
 711  * These just decode the opaque pointer into gic_state* + cpu id.
 712  */
 713 static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
 714                                 unsigned size)
 715 {
 716     gic_state **backref = (gic_state **)opaque;
 717     gic_state *s = *backref;
 718     int id = (backref - s->backref);
 719     return gic_cpu_read(s, id, addr);
 720 }
 721
 722 static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
 723                              uint64_t value, unsigned size)
 724 {
 725     gic_state **backref = (gic_state **)opaque;
 726     gic_state *s = *backref;
 727     int id = (backref - s->backref);
 728     gic_cpu_write(s, id, addr, value);
 729 }
 730
 731 static const MemoryRegionOps gic_thiscpu_ops = {
 732     .read = gic_thiscpu_read,
 733     .write = gic_thiscpu_write,
 734     .endianness = DEVICE_NATIVE_ENDIAN,
 735 };
 736
 737 static const MemoryRegionOps gic_cpu_ops = {
 738     .read = gic_do_cpu_read,
 739     .write = gic_do_cpu_write,
 740     .endianness = DEVICE_NATIVE_ENDIAN,
 741 };
 742 #endif
 743
 744 static void gic_reset(gic_state *s)
 745 {
 746     int i;
 747     memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
 748     for (i = 0 ; i < NUM_CPU(s); i++) {
 749         s->priority_mask[i] = 0xf0;
 750         s->current_pending[i] = 1023;
 751         s->running_irq[i] = 1023;
 752         s->running_priority[i] = 0x100;
 753 #ifdef NVIC
 754         /* The NVIC doesn't have per-cpu interfaces, so enable by default.  */
 755         s->cpu_enabled[i] = 1;
 756 #else
 757         s->cpu_enabled[i] = 0;
 758 #endif
 759     }
 760     for (i = 0; i < 16; i++) {
 761         GIC_SET_ENABLED(i, ALL_CPU_MASK);
 762         GIC_SET_TRIGGER(i);
 763     }
 764 #ifdef NVIC
 765     /* The NVIC is always enabled.  */
 766     s->enabled = 1;
 767 #else
 768     s->enabled = 0;
 769 #endif
 770 }
 771
 772 static void gic_save(QEMUFile *f, void *opaque)
 773 {
 774     gic_state *s = (gic_state *)opaque;
 775     int i;
 776     int j;
 777
 778     qemu_put_be32(f, s->enabled);
 779     for (i = 0; i < NUM_CPU(s); i++) {
 780         qemu_put_be32(f, s->cpu_enabled[i]);
 781         for (j = 0; j < GIC_INTERNAL; j++)
 782             qemu_put_be32(f, s->priority1[j][i]);
 783         for (j = 0; j < s->num_irq; j++)
 784             qemu_put_be32(f, s->last_active[j][i]);
 785         qemu_put_be32(f, s->priority_mask[i]);
 786         qemu_put_be32(f, s->running_irq[i]);
 787         qemu_put_be32(f, s->running_priority[i]);
 788         qemu_put_be32(f, s->current_pending[i]);
 789     }
 790     for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
 791         qemu_put_be32(f, s->priority2[i]);
 792     }
 793     for (i = 0; i < s->num_irq; i++) {
 794 #ifndef NVIC
 795         qemu_put_be32(f, s->irq_target[i]);
 796 #endif
 797         qemu_put_byte(f, s->irq_state[i].enabled);
 798         qemu_put_byte(f, s->irq_state[i].pending);
 799         qemu_put_byte(f, s->irq_state[i].active);
 800         qemu_put_byte(f, s->irq_state[i].level);
 801         qemu_put_byte(f, s->irq_state[i].model);
 802         qemu_put_byte(f, s->irq_state[i].trigger);
 803     }
 804 }
 805
 806 static int gic_load(QEMUFile *f, void *opaque, int version_id)
 807 {
 808     gic_state *s = (gic_state *)opaque;
 809     int i;
 810     int j;
 811
 812     if (version_id != 2)
 813         return -EINVAL;
 814
 815     s->enabled = qemu_get_be32(f);
 816     for (i = 0; i < NUM_CPU(s); i++) {
 817         s->cpu_enabled[i] = qemu_get_be32(f);
 818         for (j = 0; j < GIC_INTERNAL; j++)
 819             s->priority1[j][i] = qemu_get_be32(f);
 820         for (j = 0; j < s->num_irq; j++)
 821             s->last_active[j][i] = qemu_get_be32(f);
 822         s->priority_mask[i] = qemu_get_be32(f);
 823         s->running_irq[i] = qemu_get_be32(f);
 824         s->running_priority[i] = qemu_get_be32(f);
 825         s->current_pending[i] = qemu_get_be32(f);
 826     }
 827     for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
 828         s->priority2[i] = qemu_get_be32(f);
 829     }
 830     for (i = 0; i < s->num_irq; i++) {
 831 #ifndef NVIC
 832         s->irq_target[i] = qemu_get_be32(f);
 833 #endif
 834         s->irq_state[i].enabled = qemu_get_byte(f);
 835         s->irq_state[i].pending = qemu_get_byte(f);
 836         s->irq_state[i].active = qemu_get_byte(f);
 837         s->irq_state[i].level = qemu_get_byte(f);
 838         s->irq_state[i].model = qemu_get_byte(f);
 839         s->irq_state[i].trigger = qemu_get_byte(f);
 840     }
 841
 842     return 0;
 843 }
 844
 845 #if NCPU > 1
 846 static void gic_init(gic_state *s, int num_cpu, int num_irq)
 847 #else
 848 static void gic_init(gic_state *s, int num_irq)
 849 #endif
 850 {
 851     int i;
 852
 853 #if NCPU > 1
 854     s->num_cpu = num_cpu;
 855     if (s->num_cpu > NCPU) {
 856         hw_error("requested %u CPUs exceeds GIC maximum %d\n",
 857                  num_cpu, NCPU);
 858     }
 859 #endif
 860     s->num_irq = num_irq + GIC_BASE_IRQ;
 861     if (s->num_irq > GIC_MAXIRQ) {
 862         hw_error("requested %u interrupt lines exceeds GIC maximum %d\n",
 863                  num_irq, GIC_MAXIRQ);
 864     }
 865     /* ITLinesNumber is represented as (N / 32) - 1 (see
 866      * gic_dist_readb) so this is an implementation imposed
 867      * restriction, not an architectural one:
 868      */
 869     if (s->num_irq < 32 || (s->num_irq % 32)) {
 870         hw_error("%d interrupt lines unsupported: not divisible by 32\n",
 871                  num_irq);
 872     }
 873
 874     i = s->num_irq - GIC_INTERNAL;
 875 #ifndef NVIC
 876     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
 877      * GPIO array layout is thus:
 878      *  [0..N-1] SPIs
 879      *  [N..N+31] PPIs for CPU 0
 880      *  [N+32..N+63] PPIs for CPU 1
 881      *   ...
 882      */
 883     i += (GIC_INTERNAL * num_cpu);
 884 #endif
 885     qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i);
 886     for (i = 0; i < NUM_CPU(s); i++) {
 887         sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
 888     }
 889     memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
 890 #ifndef NVIC
 891     /* Memory regions for the CPU interfaces (NVIC doesn't have these):
 892      * a region for "CPU interface for this core", then a region for
 893      * "CPU interface for core 0", "for core 1", ...
 894      * NB that the memory region size of 0x100 applies for the 11MPCore
 895      * and also cores following the GIC v1 spec (ie A9).
 896      * GIC v2 defines a larger memory region (0x1000) so this will need
 897      * to be extended when we implement A15.
 898      */
 899     memory_region_init_io(&s->cpuiomem[0], &gic_thiscpu_ops, s,
 900                           "gic_cpu", 0x100);
 901     for (i = 0; i < NUM_CPU(s); i++) {
 902         s->backref[i] = s;
 903         memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i],
 904                               "gic_cpu", 0x100);
 905     }
 906 #endif
 907
 908     gic_reset(s);
 909     register_savevm(NULL, "arm_gic", -1, 2, gic_save, gic_load, s);
 910 }
 911
 912 #ifndef LEGACY_INCLUDED_GIC
 913
 914 static int arm_gic_init(SysBusDevice *dev)
 915 {
 916     /* Device instance init function for the GIC sysbus device */
 917     int i;
 918     gic_state *s = FROM_SYSBUS(gic_state, dev);
 919     gic_init(s, s->num_cpu, s->num_irq);
 920     /* Distributor */
 921     sysbus_init_mmio(dev, &s->iomem);
 922     /* cpu interfaces (one for "current cpu" plus one per cpu) */
 923     for (i = 0; i <= NUM_CPU(s); i++) {
 924         sysbus_init_mmio(dev, &s->cpuiomem[i]);
 925     }
 926     return 0;
 927 }
 928
 929 static Property arm_gic_properties[] = {
 930     DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1),
 931     DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32),
 932     DEFINE_PROP_END_OF_LIST(),
 933 };
 934
 935 static void arm_gic_class_init(ObjectClass *klass, void *data)
 936 {
 937     DeviceClass *dc = DEVICE_CLASS(klass);
 938     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 939     sbc->init = arm_gic_init;
 940     dc->props = arm_gic_properties;
 941     dc->no_user = 1;
 942 }
 943
 944 static TypeInfo arm_gic_info = {
 945     .name = "arm_gic",
 946     .parent = TYPE_SYS_BUS_DEVICE,
 947     .instance_size = sizeof(gic_state),
 948     .class_init = arm_gic_class_init,
 949 };
 950
 951 static void arm_gic_register_types(void)
 952 {
 953     type_register_static(&arm_gic_info);
 954 }
 955
 956 type_init(arm_gic_register_types)
 957
 958 #endif