hw/arm_gic.c

   1 /*
   2  * ARM Generic/Distributed Interrupt Controller
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 /* This file contains implementation code for the RealView EB interrupt
  11    controller, MPCore distributed interrupt controller and ARMv7-M
  12    Nested Vectored Interrupt Controller.  */
  13
  14 //#define DEBUG_GIC
  15
  16 #ifdef DEBUG_GIC
  17 #define DPRINTF(fmt, ...) \
  18 do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
  19 #else
  20 #define DPRINTF(fmt, ...) do {} while(0)
  21 #endif
  22
  23 #ifdef NVIC
  24 static const uint8_t gic_id[] =
  25 { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
  26 /* The NVIC has 16 internal vectors.  However these are not exposed
  27    through the normal GIC interface.  */
  28 #define GIC_BASE_IRQ    32
  29 #else
  30 static const uint8_t gic_id[] =
  31 { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  32 #define GIC_BASE_IRQ    0
  33 #endif
  34
  35 #define FROM_SYSBUSGIC(type, dev) \
  36     DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev))
  37
  38 typedef struct gic_irq_state
  39 {
  40     /* The enable bits are only banked for per-cpu interrupts.  */
  41     unsigned enabled:NCPU;
  42     unsigned pending:NCPU;
  43     unsigned active:NCPU;
  44     unsigned level:NCPU;
  45     unsigned model:1; /* 0 = N:N, 1 = 1:N */
  46     unsigned trigger:1; /* nonzero = edge triggered.  */
  47 } gic_irq_state;
  48
  49 #define ALL_CPU_MASK ((1 << NCPU) - 1)
  50 #if NCPU > 1
  51 #define NUM_CPU(s) ((s)->num_cpu)
  52 #else
  53 #define NUM_CPU(s) 1
  54 #endif
  55
  56 #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
  57 #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
  58 #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
  59 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
  60 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
  61 #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
  62 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
  63 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
  64 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
  65 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
  66 #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
  67 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
  68 #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
  69 #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
  70 #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
  71 #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
  72 #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
  73 #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
  74 #define GIC_GET_PRIORITY(irq, cpu) \
  75   (((irq) < 32) ? s->priority1[irq][cpu] : s->priority2[(irq) - 32])
  76 #ifdef NVIC
  77 #define GIC_TARGET(irq) 1
  78 #else
  79 #define GIC_TARGET(irq) s->irq_target[irq]
  80 #endif
  81
  82 typedef struct gic_state
  83 {
  84     SysBusDevice busdev;
  85     qemu_irq parent_irq[NCPU];
  86     int enabled;
  87     int cpu_enabled[NCPU];
  88
  89     gic_irq_state irq_state[GIC_NIRQ];
  90 #ifndef NVIC
  91     int irq_target[GIC_NIRQ];
  92 #endif
  93     int priority1[32][NCPU];
  94     int priority2[GIC_NIRQ - 32];
  95     int last_active[GIC_NIRQ][NCPU];
  96
  97     int priority_mask[NCPU];
  98     int running_irq[NCPU];
  99     int running_priority[NCPU];
 100     int current_pending[NCPU];
 101
 102 #if NCPU > 1
 103     int num_cpu;
 104 #endif
 105
 106     MemoryRegion iomem; /* Distributor */
 107 #ifndef NVIC
 108     /* This is just so we can have an opaque pointer which identifies
 109      * both this GIC and which CPU interface we should be accessing.
 110      */
 111     struct gic_state *backref[NCPU];
 112     MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */
 113 #endif
 114 } gic_state;
 115
 116 /* TODO: Many places that call this routine could be optimized.  */
 117 /* Update interrupt status after enabled or pending bits have been changed.  */
 118 static void gic_update(gic_state *s)
 119 {
 120     int best_irq;
 121     int best_prio;
 122     int irq;
 123     int level;
 124     int cpu;
 125     int cm;
 126
 127     for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
 128         cm = 1 << cpu;
 129         s->current_pending[cpu] = 1023;
 130         if (!s->enabled || !s->cpu_enabled[cpu]) {
 131             qemu_irq_lower(s->parent_irq[cpu]);
 132             return;
 133         }
 134         best_prio = 0x100;
 135         best_irq = 1023;
 136         for (irq = 0; irq < GIC_NIRQ; irq++) {
 137             if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) {
 138                 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
 139                     best_prio = GIC_GET_PRIORITY(irq, cpu);
 140                     best_irq = irq;
 141                 }
 142             }
 143         }
 144         level = 0;
 145         if (best_prio <= s->priority_mask[cpu]) {
 146             s->current_pending[cpu] = best_irq;
 147             if (best_prio < s->running_priority[cpu]) {
 148                 DPRINTF("Raised pending IRQ %d\n", best_irq);
 149                 level = 1;
 150             }
 151         }
 152         qemu_set_irq(s->parent_irq[cpu], level);
 153     }
 154 }
 155
 156 static void __attribute__((unused))
 157 gic_set_pending_private(gic_state *s, int cpu, int irq)
 158 {
 159     int cm = 1 << cpu;
 160
 161     if (GIC_TEST_PENDING(irq, cm))
 162         return;
 163
 164     DPRINTF("Set %d pending cpu %d\n", irq, cpu);
 165     GIC_SET_PENDING(irq, cm);
 166     gic_update(s);
 167 }
 168
 169 /* Process a change in an external IRQ input.  */
 170 static void gic_set_irq(void *opaque, int irq, int level)
 171 {
 172     gic_state *s = (gic_state *)opaque;
 173     /* The first external input line is internal interrupt 32.  */
 174     irq += 32;
 175     if (level == GIC_TEST_LEVEL(irq, ALL_CPU_MASK))
 176         return;
 177
 178     if (level) {
 179         GIC_SET_LEVEL(irq, ALL_CPU_MASK);
 180         if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, ALL_CPU_MASK)) {
 181             DPRINTF("Set %d pending mask %x\n", irq, GIC_TARGET(irq));
 182             GIC_SET_PENDING(irq, GIC_TARGET(irq));
 183         }
 184     } else {
 185         GIC_CLEAR_LEVEL(irq, ALL_CPU_MASK);
 186     }
 187     gic_update(s);
 188 }
 189
 190 static void gic_set_running_irq(gic_state *s, int cpu, int irq)
 191 {
 192     s->running_irq[cpu] = irq;
 193     if (irq == 1023) {
 194         s->running_priority[cpu] = 0x100;
 195     } else {
 196         s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu);
 197     }
 198     gic_update(s);
 199 }
 200
 201 static uint32_t gic_acknowledge_irq(gic_state *s, int cpu)
 202 {
 203     int new_irq;
 204     int cm = 1 << cpu;
 205     new_irq = s->current_pending[cpu];
 206     if (new_irq == 1023
 207             || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) {
 208         DPRINTF("ACK no pending IRQ\n");
 209         return 1023;
 210     }
 211     s->last_active[new_irq][cpu] = s->running_irq[cpu];
 212     /* Clear pending flags for both level and edge triggered interrupts.
 213        Level triggered IRQs will be reasserted once they become inactive.  */
 214     GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm);
 215     gic_set_running_irq(s, cpu, new_irq);
 216     DPRINTF("ACK %d\n", new_irq);
 217     return new_irq;
 218 }
 219
 220 static void gic_complete_irq(gic_state * s, int cpu, int irq)
 221 {
 222     int update = 0;
 223     int cm = 1 << cpu;
 224     DPRINTF("EOI %d\n", irq);
 225     if (irq >= GIC_NIRQ) {
 226         /* This handles two cases:
 227          * 1. If software writes the ID of a spurious interrupt [ie 1023]
 228          * to the GICC_EOIR, the GIC ignores that write.
 229          * 2. If software writes the number of a non-existent interrupt
 230          * this must be a subcase of "value written does not match the last
 231          * valid interrupt value read from the Interrupt Acknowledge
 232          * register" and so this is UNPREDICTABLE. We choose to ignore it.
 233          */
 234         return;
 235     }
 236     if (s->running_irq[cpu] == 1023)
 237         return; /* No active IRQ.  */
 238     /* Mark level triggered interrupts as pending if they are still
 239        raised.  */
 240     if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
 241         && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
 242         DPRINTF("Set %d pending mask %x\n", irq, cm);
 243         GIC_SET_PENDING(irq, cm);
 244         update = 1;
 245     }
 246     if (irq != s->running_irq[cpu]) {
 247         /* Complete an IRQ that is not currently running.  */
 248         int tmp = s->running_irq[cpu];
 249         while (s->last_active[tmp][cpu] != 1023) {
 250             if (s->last_active[tmp][cpu] == irq) {
 251                 s->last_active[tmp][cpu] = s->last_active[irq][cpu];
 252                 break;
 253             }
 254             tmp = s->last_active[tmp][cpu];
 255         }
 256         if (update) {
 257             gic_update(s);
 258         }
 259     } else {
 260         /* Complete the current running IRQ.  */
 261         gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]);
 262     }
 263 }
 264
 265 static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
 266 {
 267     gic_state *s = (gic_state *)opaque;
 268     uint32_t res;
 269     int irq;
 270     int i;
 271     int cpu;
 272     int cm;
 273     int mask;
 274
 275     cpu = gic_get_current_cpu();
 276     cm = 1 << cpu;
 277     if (offset < 0x100) {
 278 #ifndef NVIC
 279         if (offset == 0)
 280             return s->enabled;
 281         if (offset == 4)
 282             return ((GIC_NIRQ / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
 283         if (offset < 0x08)
 284             return 0;
 285         if (offset >= 0x80) {
 286             /* Interrupt Security , RAZ/WI */
 287             return 0;
 288         }
 289 #endif
 290         goto bad_reg;
 291     } else if (offset < 0x200) {
 292         /* Interrupt Set/Clear Enable.  */
 293         if (offset < 0x180)
 294             irq = (offset - 0x100) * 8;
 295         else
 296             irq = (offset - 0x180) * 8;
 297         irq += GIC_BASE_IRQ;
 298         if (irq >= GIC_NIRQ)
 299             goto bad_reg;
 300         res = 0;
 301         for (i = 0; i < 8; i++) {
 302             if (GIC_TEST_ENABLED(irq + i, cm)) {
 303                 res |= (1 << i);
 304             }
 305         }
 306     } else if (offset < 0x300) {
 307         /* Interrupt Set/Clear Pending.  */
 308         if (offset < 0x280)
 309             irq = (offset - 0x200) * 8;
 310         else
 311             irq = (offset - 0x280) * 8;
 312         irq += GIC_BASE_IRQ;
 313         if (irq >= GIC_NIRQ)
 314             goto bad_reg;
 315         res = 0;
 316         mask = (irq < 32) ?  cm : ALL_CPU_MASK;
 317         for (i = 0; i < 8; i++) {
 318             if (GIC_TEST_PENDING(irq + i, mask)) {
 319                 res |= (1 << i);
 320             }
 321         }
 322     } else if (offset < 0x400) {
 323         /* Interrupt Active.  */
 324         irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
 325         if (irq >= GIC_NIRQ)
 326             goto bad_reg;
 327         res = 0;
 328         mask = (irq < 32) ?  cm : ALL_CPU_MASK;
 329         for (i = 0; i < 8; i++) {
 330             if (GIC_TEST_ACTIVE(irq + i, mask)) {
 331                 res |= (1 << i);
 332             }
 333         }
 334     } else if (offset < 0x800) {
 335         /* Interrupt Priority.  */
 336         irq = (offset - 0x400) + GIC_BASE_IRQ;
 337         if (irq >= GIC_NIRQ)
 338             goto bad_reg;
 339         res = GIC_GET_PRIORITY(irq, cpu);
 340 #ifndef NVIC
 341     } else if (offset < 0xc00) {
 342         /* Interrupt CPU Target.  */
 343         irq = (offset - 0x800) + GIC_BASE_IRQ;
 344         if (irq >= GIC_NIRQ)
 345             goto bad_reg;
 346         if (irq >= 29 && irq <= 31) {
 347             res = cm;
 348         } else {
 349             res = GIC_TARGET(irq);
 350         }
 351     } else if (offset < 0xf00) {
 352         /* Interrupt Configuration.  */
 353         irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
 354         if (irq >= GIC_NIRQ)
 355             goto bad_reg;
 356         res = 0;
 357         for (i = 0; i < 4; i++) {
 358             if (GIC_TEST_MODEL(irq + i))
 359                 res |= (1 << (i * 2));
 360             if (GIC_TEST_TRIGGER(irq + i))
 361                 res |= (2 << (i * 2));
 362         }
 363 #endif
 364     } else if (offset < 0xfe0) {
 365         goto bad_reg;
 366     } else /* offset >= 0xfe0 */ {
 367         if (offset & 3) {
 368             res = 0;
 369         } else {
 370             res = gic_id[(offset - 0xfe0) >> 2];
 371         }
 372     }
 373     return res;
 374 bad_reg:
 375     hw_error("gic_dist_readb: Bad offset %x\n", (int)offset);
 376     return 0;
 377 }
 378
 379 static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
 380 {
 381     uint32_t val;
 382     val = gic_dist_readb(opaque, offset);
 383     val |= gic_dist_readb(opaque, offset + 1) << 8;
 384     return val;
 385 }
 386
 387 static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
 388 {
 389     uint32_t val;
 390 #ifdef NVIC
 391     gic_state *s = (gic_state *)opaque;
 392     uint32_t addr;
 393     addr = offset;
 394     if (addr < 0x100 || addr > 0xd00)
 395         return nvic_readl(s, addr);
 396 #endif
 397     val = gic_dist_readw(opaque, offset);
 398     val |= gic_dist_readw(opaque, offset + 2) << 16;
 399     return val;
 400 }
 401
 402 static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
 403                             uint32_t value)
 404 {
 405     gic_state *s = (gic_state *)opaque;
 406     int irq;
 407     int i;
 408     int cpu;
 409
 410     cpu = gic_get_current_cpu();
 411     if (offset < 0x100) {
 412 #ifdef NVIC
 413         goto bad_reg;
 414 #else
 415         if (offset == 0) {
 416             s->enabled = (value & 1);
 417             DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
 418         } else if (offset < 4) {
 419             /* ignored.  */
 420         } else if (offset >= 0x80) {
 421             /* Interrupt Security Registers, RAZ/WI */
 422         } else {
 423             goto bad_reg;
 424         }
 425 #endif
 426     } else if (offset < 0x180) {
 427         /* Interrupt Set Enable.  */
 428         irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
 429         if (irq >= GIC_NIRQ)
 430             goto bad_reg;
 431         if (irq < 16)
 432           value = 0xff;
 433         for (i = 0; i < 8; i++) {
 434             if (value & (1 << i)) {
 435                 int mask = (irq < 32) ? (1 << cpu) : GIC_TARGET(irq);
 436                 int cm = (irq < 32) ? (1 << cpu) : ALL_CPU_MASK;
 437
 438                 if (!GIC_TEST_ENABLED(irq + i, cm)) {
 439                     DPRINTF("Enabled IRQ %d\n", irq + i);
 440                 }
 441                 GIC_SET_ENABLED(irq + i, cm);
 442                 /* If a raised level triggered IRQ enabled then mark
 443                    is as pending.  */
 444                 if (GIC_TEST_LEVEL(irq + i, mask)
 445                         && !GIC_TEST_TRIGGER(irq + i)) {
 446                     DPRINTF("Set %d pending mask %x\n", irq + i, mask);
 447                     GIC_SET_PENDING(irq + i, mask);
 448                 }
 449             }
 450         }
 451     } else if (offset < 0x200) {
 452         /* Interrupt Clear Enable.  */
 453         irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
 454         if (irq >= GIC_NIRQ)
 455             goto bad_reg;
 456         if (irq < 16)
 457           value = 0;
 458         for (i = 0; i < 8; i++) {
 459             if (value & (1 << i)) {
 460                 int cm = (irq < 32) ? (1 << cpu) : ALL_CPU_MASK;
 461
 462                 if (GIC_TEST_ENABLED(irq + i, cm)) {
 463                     DPRINTF("Disabled IRQ %d\n", irq + i);
 464                 }
 465                 GIC_CLEAR_ENABLED(irq + i, cm);
 466             }
 467         }
 468     } else if (offset < 0x280) {
 469         /* Interrupt Set Pending.  */
 470         irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
 471         if (irq >= GIC_NIRQ)
 472             goto bad_reg;
 473         if (irq < 16)
 474           irq = 0;
 475
 476         for (i = 0; i < 8; i++) {
 477             if (value & (1 << i)) {
 478                 GIC_SET_PENDING(irq + i, GIC_TARGET(irq));
 479             }
 480         }
 481     } else if (offset < 0x300) {
 482         /* Interrupt Clear Pending.  */
 483         irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
 484         if (irq >= GIC_NIRQ)
 485             goto bad_reg;
 486         for (i = 0; i < 8; i++) {
 487             /* ??? This currently clears the pending bit for all CPUs, even
 488                for per-CPU interrupts.  It's unclear whether this is the
 489                corect behavior.  */
 490             if (value & (1 << i)) {
 491                 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
 492             }
 493         }
 494     } else if (offset < 0x400) {
 495         /* Interrupt Active.  */
 496         goto bad_reg;
 497     } else if (offset < 0x800) {
 498         /* Interrupt Priority.  */
 499         irq = (offset - 0x400) + GIC_BASE_IRQ;
 500         if (irq >= GIC_NIRQ)
 501             goto bad_reg;
 502         if (irq < 32) {
 503             s->priority1[irq][cpu] = value;
 504         } else {
 505             s->priority2[irq - 32] = value;
 506         }
 507 #ifndef NVIC
 508     } else if (offset < 0xc00) {
 509         /* Interrupt CPU Target.  */
 510         irq = (offset - 0x800) + GIC_BASE_IRQ;
 511         if (irq >= GIC_NIRQ)
 512             goto bad_reg;
 513         if (irq < 29)
 514             value = 0;
 515         else if (irq < 32)
 516             value = ALL_CPU_MASK;
 517         s->irq_target[irq] = value & ALL_CPU_MASK;
 518     } else if (offset < 0xf00) {
 519         /* Interrupt Configuration.  */
 520         irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
 521         if (irq >= GIC_NIRQ)
 522             goto bad_reg;
 523         if (irq < 32)
 524             value |= 0xaa;
 525         for (i = 0; i < 4; i++) {
 526             if (value & (1 << (i * 2))) {
 527                 GIC_SET_MODEL(irq + i);
 528             } else {
 529                 GIC_CLEAR_MODEL(irq + i);
 530             }
 531             if (value & (2 << (i * 2))) {
 532                 GIC_SET_TRIGGER(irq + i);
 533             } else {
 534                 GIC_CLEAR_TRIGGER(irq + i);
 535             }
 536         }
 537 #endif
 538     } else {
 539         /* 0xf00 is only handled for 32-bit writes.  */
 540         goto bad_reg;
 541     }
 542     gic_update(s);
 543     return;
 544 bad_reg:
 545     hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
 546 }
 547
 548 static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
 549                             uint32_t value)
 550 {
 551     gic_dist_writeb(opaque, offset, value & 0xff);
 552     gic_dist_writeb(opaque, offset + 1, value >> 8);
 553 }
 554
 555 static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
 556                             uint32_t value)
 557 {
 558     gic_state *s = (gic_state *)opaque;
 559 #ifdef NVIC
 560     uint32_t addr;
 561     addr = offset;
 562     if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
 563         nvic_writel(s, addr, value);
 564         return;
 565     }
 566 #endif
 567     if (offset == 0xf00) {
 568         int cpu;
 569         int irq;
 570         int mask;
 571
 572         cpu = gic_get_current_cpu();
 573         irq = value & 0x3ff;
 574         switch ((value >> 24) & 3) {
 575         case 0:
 576             mask = (value >> 16) & ALL_CPU_MASK;
 577             break;
 578         case 1:
 579             mask = ALL_CPU_MASK ^ (1 << cpu);
 580             break;
 581         case 2:
 582             mask = 1 << cpu;
 583             break;
 584         default:
 585             DPRINTF("Bad Soft Int target filter\n");
 586             mask = ALL_CPU_MASK;
 587             break;
 588         }
 589         GIC_SET_PENDING(irq, mask);
 590         gic_update(s);
 591         return;
 592     }
 593     gic_dist_writew(opaque, offset, value & 0xffff);
 594     gic_dist_writew(opaque, offset + 2, value >> 16);
 595 }
 596
 597 static const MemoryRegionOps gic_dist_ops = {
 598     .old_mmio = {
 599         .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, },
 600         .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, },
 601     },
 602     .endianness = DEVICE_NATIVE_ENDIAN,
 603 };
 604
 605 #ifndef NVIC
 606 static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset)
 607 {
 608     switch (offset) {
 609     case 0x00: /* Control */
 610         return s->cpu_enabled[cpu];
 611     case 0x04: /* Priority mask */
 612         return s->priority_mask[cpu];
 613     case 0x08: /* Binary Point */
 614         /* ??? Not implemented.  */
 615         return 0;
 616     case 0x0c: /* Acknowledge */
 617         return gic_acknowledge_irq(s, cpu);
 618     case 0x14: /* Running Priority */
 619         return s->running_priority[cpu];
 620     case 0x18: /* Highest Pending Interrupt */
 621         return s->current_pending[cpu];
 622     default:
 623         hw_error("gic_cpu_read: Bad offset %x\n", (int)offset);
 624         return 0;
 625     }
 626 }
 627
 628 static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value)
 629 {
 630     switch (offset) {
 631     case 0x00: /* Control */
 632         s->cpu_enabled[cpu] = (value & 1);
 633         DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis");
 634         break;
 635     case 0x04: /* Priority mask */
 636         s->priority_mask[cpu] = (value & 0xff);
 637         break;
 638     case 0x08: /* Binary Point */
 639         /* ??? Not implemented.  */
 640         break;
 641     case 0x10: /* End Of Interrupt */
 642         return gic_complete_irq(s, cpu, value & 0x3ff);
 643     default:
 644         hw_error("gic_cpu_write: Bad offset %x\n", (int)offset);
 645         return;
 646     }
 647     gic_update(s);
 648 }
 649
 650 /* Wrappers to read/write the GIC CPU interface for the current CPU */
 651 static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
 652                                  unsigned size)
 653 {
 654     gic_state *s = (gic_state *)opaque;
 655     return gic_cpu_read(s, gic_get_current_cpu(), addr & 0xff);
 656 }
 657
 658 static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
 659                               uint64_t value, unsigned size)
 660 {
 661     gic_state *s = (gic_state *)opaque;
 662     gic_cpu_write(s, gic_get_current_cpu(), addr & 0xff, value);
 663 }
 664
 665 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
 666  * These just decode the opaque pointer into gic_state* + cpu id.
 667  */
 668 static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
 669                                 unsigned size)
 670 {
 671     gic_state **backref = (gic_state **)opaque;
 672     gic_state *s = *backref;
 673     int id = (backref - s->backref);
 674     return gic_cpu_read(s, id, addr & 0xff);
 675 }
 676
 677 static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
 678                              uint64_t value, unsigned size)
 679 {
 680     gic_state **backref = (gic_state **)opaque;
 681     gic_state *s = *backref;
 682     int id = (backref - s->backref);
 683     gic_cpu_write(s, id, addr & 0xff, value);
 684 }
 685
 686 static const MemoryRegionOps gic_thiscpu_ops = {
 687     .read = gic_thiscpu_read,
 688     .write = gic_thiscpu_write,
 689     .endianness = DEVICE_NATIVE_ENDIAN,
 690 };
 691
 692 static const MemoryRegionOps gic_cpu_ops = {
 693     .read = gic_do_cpu_read,
 694     .write = gic_do_cpu_write,
 695     .endianness = DEVICE_NATIVE_ENDIAN,
 696 };
 697 #endif
 698
 699 static void gic_reset(gic_state *s)
 700 {
 701     int i;
 702     memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
 703     for (i = 0 ; i < NUM_CPU(s); i++) {
 704         s->priority_mask[i] = 0xf0;
 705         s->current_pending[i] = 1023;
 706         s->running_irq[i] = 1023;
 707         s->running_priority[i] = 0x100;
 708 #ifdef NVIC
 709         /* The NVIC doesn't have per-cpu interfaces, so enable by default.  */
 710         s->cpu_enabled[i] = 1;
 711 #else
 712         s->cpu_enabled[i] = 0;
 713 #endif
 714     }
 715     for (i = 0; i < 16; i++) {
 716         GIC_SET_ENABLED(i, ALL_CPU_MASK);
 717         GIC_SET_TRIGGER(i);
 718     }
 719 #ifdef NVIC
 720     /* The NVIC is always enabled.  */
 721     s->enabled = 1;
 722 #else
 723     s->enabled = 0;
 724 #endif
 725 }
 726
 727 static void gic_save(QEMUFile *f, void *opaque)
 728 {
 729     gic_state *s = (gic_state *)opaque;
 730     int i;
 731     int j;
 732
 733     qemu_put_be32(f, s->enabled);
 734     for (i = 0; i < NUM_CPU(s); i++) {
 735         qemu_put_be32(f, s->cpu_enabled[i]);
 736         for (j = 0; j < 32; j++)
 737             qemu_put_be32(f, s->priority1[j][i]);
 738         for (j = 0; j < GIC_NIRQ; j++)
 739             qemu_put_be32(f, s->last_active[j][i]);
 740         qemu_put_be32(f, s->priority_mask[i]);
 741         qemu_put_be32(f, s->running_irq[i]);
 742         qemu_put_be32(f, s->running_priority[i]);
 743         qemu_put_be32(f, s->current_pending[i]);
 744     }
 745     for (i = 0; i < GIC_NIRQ - 32; i++) {
 746         qemu_put_be32(f, s->priority2[i]);
 747     }
 748     for (i = 0; i < GIC_NIRQ; i++) {
 749 #ifndef NVIC
 750         qemu_put_be32(f, s->irq_target[i]);
 751 #endif
 752         qemu_put_byte(f, s->irq_state[i].enabled);
 753         qemu_put_byte(f, s->irq_state[i].pending);
 754         qemu_put_byte(f, s->irq_state[i].active);
 755         qemu_put_byte(f, s->irq_state[i].level);
 756         qemu_put_byte(f, s->irq_state[i].model);
 757         qemu_put_byte(f, s->irq_state[i].trigger);
 758     }
 759 }
 760
 761 static int gic_load(QEMUFile *f, void *opaque, int version_id)
 762 {
 763     gic_state *s = (gic_state *)opaque;
 764     int i;
 765     int j;
 766
 767     if (version_id != 2)
 768         return -EINVAL;
 769
 770     s->enabled = qemu_get_be32(f);
 771     for (i = 0; i < NUM_CPU(s); i++) {
 772         s->cpu_enabled[i] = qemu_get_be32(f);
 773         for (j = 0; j < 32; j++)
 774             s->priority1[j][i] = qemu_get_be32(f);
 775         for (j = 0; j < GIC_NIRQ; j++)
 776             s->last_active[j][i] = qemu_get_be32(f);
 777         s->priority_mask[i] = qemu_get_be32(f);
 778         s->running_irq[i] = qemu_get_be32(f);
 779         s->running_priority[i] = qemu_get_be32(f);
 780         s->current_pending[i] = qemu_get_be32(f);
 781     }
 782     for (i = 0; i < GIC_NIRQ - 32; i++) {
 783         s->priority2[i] = qemu_get_be32(f);
 784     }
 785     for (i = 0; i < GIC_NIRQ; i++) {
 786 #ifndef NVIC
 787         s->irq_target[i] = qemu_get_be32(f);
 788 #endif
 789         s->irq_state[i].enabled = qemu_get_byte(f);
 790         s->irq_state[i].pending = qemu_get_byte(f);
 791         s->irq_state[i].active = qemu_get_byte(f);
 792         s->irq_state[i].level = qemu_get_byte(f);
 793         s->irq_state[i].model = qemu_get_byte(f);
 794         s->irq_state[i].trigger = qemu_get_byte(f);
 795     }
 796
 797     return 0;
 798 }
 799
 800 #if NCPU > 1
 801 static void gic_init(gic_state *s, int num_cpu)
 802 #else
 803 static void gic_init(gic_state *s)
 804 #endif
 805 {
 806     int i;
 807
 808 #if NCPU > 1
 809     s->num_cpu = num_cpu;
 810 #endif
 811     qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, GIC_NIRQ - 32);
 812     for (i = 0; i < NUM_CPU(s); i++) {
 813         sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
 814     }
 815     memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000);
 816 #ifndef NVIC
 817     /* Memory regions for the CPU interfaces (NVIC doesn't have these):
 818      * a region for "CPU interface for this core", then a region for
 819      * "CPU interface for core 0", "for core 1", ...
 820      * NB that the memory region size of 0x100 applies for the 11MPCore
 821      * and also cores following the GIC v1 spec (ie A9).
 822      * GIC v2 defines a larger memory region (0x1000) so this will need
 823      * to be extended when we implement A15.
 824      */
 825     memory_region_init_io(&s->cpuiomem[0], &gic_thiscpu_ops, s,
 826                           "gic_cpu", 0x100);
 827     for (i = 0; i < NUM_CPU(s); i++) {
 828         s->backref[i] = s;
 829         memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i],
 830                               "gic_cpu", 0x100);
 831     }
 832 #endif
 833
 834     gic_reset(s);
 835     register_savevm(NULL, "arm_gic", -1, 2, gic_save, gic_load, s);
 836 }