hw/arm_sysctl.c

   1 /*
   2  * Status and system control registers for ARM RealView/Versatile boards.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw/hw.h"
  11 #include "qemu/timer.h"
  12 #include "qemu/bitops.h"
  13 #include "hw/sysbus.h"
  14 #include "hw/primecell.h"
  15 #include "sysemu/sysemu.h"
  16
  17 #define LOCK_VALUE 0xa05f
  18
  19 typedef struct {
  20     SysBusDevice busdev;
  21     MemoryRegion iomem;
  22     qemu_irq pl110_mux_ctrl;
  23
  24     uint32_t sys_id;
  25     uint32_t leds;
  26     uint16_t lockval;
  27     uint32_t cfgdata1;
  28     uint32_t cfgdata2;
  29     uint32_t flags;
  30     uint32_t nvflags;
  31     uint32_t resetlevel;
  32     uint32_t proc_id;
  33     uint32_t sys_mci;
  34     uint32_t sys_cfgdata;
  35     uint32_t sys_cfgctrl;
  36     uint32_t sys_cfgstat;
  37     uint32_t sys_clcd;
  38     uint32_t db_num_vsensors;
  39     uint32_t *db_voltage;
  40 } arm_sysctl_state;
  41
  42 static const VMStateDescription vmstate_arm_sysctl = {
  43     .name = "realview_sysctl",
  44     .version_id = 3,
  45     .minimum_version_id = 1,
  46     .fields = (VMStateField[]) {
  47         VMSTATE_UINT32(leds, arm_sysctl_state),
  48         VMSTATE_UINT16(lockval, arm_sysctl_state),
  49         VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
  50         VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
  51         VMSTATE_UINT32(flags, arm_sysctl_state),
  52         VMSTATE_UINT32(nvflags, arm_sysctl_state),
  53         VMSTATE_UINT32(resetlevel, arm_sysctl_state),
  54         VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
  55         VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
  56         VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
  57         VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
  58         VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
  59         VMSTATE_END_OF_LIST()
  60     }
  61 };
  62
  63 /* The PB926 actually uses a different format for
  64  * its SYS_ID register. Fortunately the bits which are
  65  * board type on later boards are distinct.
  66  */
  67 #define BOARD_ID_PB926 0x100
  68 #define BOARD_ID_EB 0x140
  69 #define BOARD_ID_PBA8 0x178
  70 #define BOARD_ID_PBX 0x182
  71 #define BOARD_ID_VEXPRESS 0x190
  72
  73 static int board_id(arm_sysctl_state *s)
  74 {
  75     /* Extract the board ID field from the SYS_ID register value */
  76     return (s->sys_id >> 16) & 0xfff;
  77 }
  78
  79 static void arm_sysctl_reset(DeviceState *d)
  80 {
  81     arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
  82
  83     s->leds = 0;
  84     s->lockval = 0;
  85     s->cfgdata1 = 0;
  86     s->cfgdata2 = 0;
  87     s->flags = 0;
  88     s->resetlevel = 0;
  89     if (board_id(s) == BOARD_ID_VEXPRESS) {
  90         /* On VExpress this register will RAZ/WI */
  91         s->sys_clcd = 0;
  92     } else {
  93         /* All others: CLCDID 0x1f, indicating VGA */
  94         s->sys_clcd = 0x1f00;
  95     }
  96 }
  97
  98 static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
  99                                 unsigned size)
 100 {
 101     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 102
 103     switch (offset) {
 104     case 0x00: /* ID */
 105         return s->sys_id;
 106     case 0x04: /* SW */
 107         /* General purpose hardware switches.
 108            We don't have a useful way of exposing these to the user.  */
 109         return 0;
 110     case 0x08: /* LED */
 111         return s->leds;
 112     case 0x20: /* LOCK */
 113         return s->lockval;
 114     case 0x0c: /* OSC0 */
 115     case 0x10: /* OSC1 */
 116     case 0x14: /* OSC2 */
 117     case 0x18: /* OSC3 */
 118     case 0x1c: /* OSC4 */
 119     case 0x24: /* 100HZ */
 120         /* ??? Implement these.  */
 121         return 0;
 122     case 0x28: /* CFGDATA1 */
 123         return s->cfgdata1;
 124     case 0x2c: /* CFGDATA2 */
 125         return s->cfgdata2;
 126     case 0x30: /* FLAGS */
 127         return s->flags;
 128     case 0x38: /* NVFLAGS */
 129         return s->nvflags;
 130     case 0x40: /* RESETCTL */
 131         if (board_id(s) == BOARD_ID_VEXPRESS) {
 132             /* reserved: RAZ/WI */
 133             return 0;
 134         }
 135         return s->resetlevel;
 136     case 0x44: /* PCICTL */
 137         return 1;
 138     case 0x48: /* MCI */
 139         return s->sys_mci;
 140     case 0x4c: /* FLASH */
 141         return 0;
 142     case 0x50: /* CLCD */
 143         return s->sys_clcd;
 144     case 0x54: /* CLCDSER */
 145         return 0;
 146     case 0x58: /* BOOTCS */
 147         return 0;
 148     case 0x5c: /* 24MHz */
 149         return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
 150     case 0x60: /* MISC */
 151         return 0;
 152     case 0x84: /* PROCID0 */
 153         return s->proc_id;
 154     case 0x88: /* PROCID1 */
 155         return 0xff000000;
 156     case 0x64: /* DMAPSR0 */
 157     case 0x68: /* DMAPSR1 */
 158     case 0x6c: /* DMAPSR2 */
 159     case 0x70: /* IOSEL */
 160     case 0x74: /* PLDCTL */
 161     case 0x80: /* BUSID */
 162     case 0x8c: /* OSCRESET0 */
 163     case 0x90: /* OSCRESET1 */
 164     case 0x94: /* OSCRESET2 */
 165     case 0x98: /* OSCRESET3 */
 166     case 0x9c: /* OSCRESET4 */
 167     case 0xc0: /* SYS_TEST_OSC0 */
 168     case 0xc4: /* SYS_TEST_OSC1 */
 169     case 0xc8: /* SYS_TEST_OSC2 */
 170     case 0xcc: /* SYS_TEST_OSC3 */
 171     case 0xd0: /* SYS_TEST_OSC4 */
 172         return 0;
 173     case 0xa0: /* SYS_CFGDATA */
 174         if (board_id(s) != BOARD_ID_VEXPRESS) {
 175             goto bad_reg;
 176         }
 177         return s->sys_cfgdata;
 178     case 0xa4: /* SYS_CFGCTRL */
 179         if (board_id(s) != BOARD_ID_VEXPRESS) {
 180             goto bad_reg;
 181         }
 182         return s->sys_cfgctrl;
 183     case 0xa8: /* SYS_CFGSTAT */
 184         if (board_id(s) != BOARD_ID_VEXPRESS) {
 185             goto bad_reg;
 186         }
 187         return s->sys_cfgstat;
 188     default:
 189     bad_reg:
 190         qemu_log_mask(LOG_GUEST_ERROR,
 191                       "arm_sysctl_read: Bad register offset 0x%x\n",
 192                       (int)offset);
 193         return 0;
 194     }
 195 }
 196
 197 /* SYS_CFGCTRL functions */
 198 #define SYS_CFG_OSC 1
 199 #define SYS_CFG_VOLT 2
 200 #define SYS_CFG_AMP 3
 201 #define SYS_CFG_TEMP 4
 202 #define SYS_CFG_RESET 5
 203 #define SYS_CFG_SCC 6
 204 #define SYS_CFG_MUXFPGA 7
 205 #define SYS_CFG_SHUTDOWN 8
 206 #define SYS_CFG_REBOOT 9
 207 #define SYS_CFG_DVIMODE 11
 208 #define SYS_CFG_POWER 12
 209 #define SYS_CFG_ENERGY 13
 210
 211 /* SYS_CFGCTRL site field values */
 212 #define SYS_CFG_SITE_MB 0
 213 #define SYS_CFG_SITE_DB1 1
 214 #define SYS_CFG_SITE_DB2 2
 215
 216 /**
 217  * vexpress_cfgctrl_read:
 218  * @s: arm_sysctl_state pointer
 219  * @dcc, @function, @site, @position, @device: split out values from
 220  * SYS_CFGCTRL register
 221  * @val: pointer to where to put the read data on success
 222  *
 223  * Handle a VExpress SYS_CFGCTRL register read. On success, return true and
 224  * write the read value to *val. On failure, return false (and val may
 225  * or may not be written to).
 226  */
 227 static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc,
 228                                   unsigned int function, unsigned int site,
 229                                   unsigned int position, unsigned int device,
 230                                   uint32_t *val)
 231 {
 232     /* We don't support anything other than DCC 0, board stack position 0
 233      * or sites other than motherboard/daughterboard:
 234      */
 235     if (dcc != 0 || position != 0 ||
 236         (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
 237         goto cfgctrl_unimp;
 238     }
 239
 240     switch (function) {
 241     case SYS_CFG_VOLT:
 242         if (site == SYS_CFG_SITE_DB1 && device < s->db_num_vsensors) {
 243             *val = s->db_voltage[device];
 244             return true;
 245         }
 246         if (site == SYS_CFG_SITE_MB && device == 0) {
 247             /* There is only one motherboard voltage sensor:
 248              * VIO : 3.3V : bus voltage between mother and daughterboard
 249              */
 250             *val = 3300000;
 251             return true;
 252         }
 253         break;
 254     default:
 255         break;
 256     }
 257
 258 cfgctrl_unimp:
 259     qemu_log_mask(LOG_UNIMP,
 260                   "arm_sysctl: Unimplemented SYS_CFGCTRL read of function "
 261                   "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
 262                   function, dcc, site, position, device);
 263     return false;
 264 }
 265
 266 /**
 267  * vexpress_cfgctrl_write:
 268  * @s: arm_sysctl_state pointer
 269  * @dcc, @function, @site, @position, @device: split out values from
 270  * SYS_CFGCTRL register
 271  * @val: data to write
 272  *
 273  * Handle a VExpress SYS_CFGCTRL register write. On success, return true.
 274  * On failure, return false.
 275  */
 276 static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc,
 277                                    unsigned int function, unsigned int site,
 278                                    unsigned int position, unsigned int device,
 279                                    uint32_t val)
 280 {
 281     /* We don't support anything other than DCC 0, board stack position 0
 282      * or sites other than motherboard/daughterboard:
 283      */
 284     if (dcc != 0 || position != 0 ||
 285         (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
 286         goto cfgctrl_unimp;
 287     }
 288
 289     switch (function) {
 290     case SYS_CFG_MUXFPGA:
 291         if (site == SYS_CFG_SITE_MB && device == 0) {
 292             /* Select whether video output comes from motherboard
 293              * or daughterboard: log and ignore as QEMU doesn't
 294              * support this.
 295              */
 296             qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output "
 297                           "not supported, ignoring\n");
 298             return true;
 299         }
 300         break;
 301     case SYS_CFG_SHUTDOWN:
 302         if (site == SYS_CFG_SITE_MB && device == 0) {
 303             qemu_system_shutdown_request();
 304             return true;
 305         }
 306         break;
 307     case SYS_CFG_REBOOT:
 308         if (site == SYS_CFG_SITE_MB && device == 0) {
 309             qemu_system_reset_request();
 310             return true;
 311         }
 312         break;
 313     case SYS_CFG_DVIMODE:
 314         if (site == SYS_CFG_SITE_MB && device == 0) {
 315             /* Selecting DVI mode is meaningless for QEMU: we will
 316              * always display the output correctly according to the
 317              * pixel height/width programmed into the CLCD controller.
 318              */
 319             return true;
 320         }
 321     default:
 322         break;
 323     }
 324
 325 cfgctrl_unimp:
 326     qemu_log_mask(LOG_UNIMP,
 327                   "arm_sysctl: Unimplemented SYS_CFGCTRL write of function "
 328                   "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
 329                   function, dcc, site, position, device);
 330     return false;
 331 }
 332
 333 static void arm_sysctl_write(void *opaque, hwaddr offset,
 334                              uint64_t val, unsigned size)
 335 {
 336     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 337
 338     switch (offset) {
 339     case 0x08: /* LED */
 340         s->leds = val;
 341         break;
 342     case 0x0c: /* OSC0 */
 343     case 0x10: /* OSC1 */
 344     case 0x14: /* OSC2 */
 345     case 0x18: /* OSC3 */
 346     case 0x1c: /* OSC4 */
 347         /* ??? */
 348         break;
 349     case 0x20: /* LOCK */
 350         if (val == LOCK_VALUE)
 351             s->lockval = val;
 352         else
 353             s->lockval = val & 0x7fff;
 354         break;
 355     case 0x28: /* CFGDATA1 */
 356         /* ??? Need to implement this.  */
 357         s->cfgdata1 = val;
 358         break;
 359     case 0x2c: /* CFGDATA2 */
 360         /* ??? Need to implement this.  */
 361         s->cfgdata2 = val;
 362         break;
 363     case 0x30: /* FLAGSSET */
 364         s->flags |= val;
 365         break;
 366     case 0x34: /* FLAGSCLR */
 367         s->flags &= ~val;
 368         break;
 369     case 0x38: /* NVFLAGSSET */
 370         s->nvflags |= val;
 371         break;
 372     case 0x3c: /* NVFLAGSCLR */
 373         s->nvflags &= ~val;
 374         break;
 375     case 0x40: /* RESETCTL */
 376         switch (board_id(s)) {
 377         case BOARD_ID_PB926:
 378             if (s->lockval == LOCK_VALUE) {
 379                 s->resetlevel = val;
 380                 if (val & 0x100) {
 381                     qemu_system_reset_request();
 382                 }
 383             }
 384             break;
 385         case BOARD_ID_PBX:
 386         case BOARD_ID_PBA8:
 387             if (s->lockval == LOCK_VALUE) {
 388                 s->resetlevel = val;
 389                 if (val & 0x04) {
 390                     qemu_system_reset_request();
 391                 }
 392             }
 393             break;
 394         case BOARD_ID_VEXPRESS:
 395         case BOARD_ID_EB:
 396         default:
 397             /* reserved: RAZ/WI */
 398             break;
 399         }
 400         break;
 401     case 0x44: /* PCICTL */
 402         /* nothing to do.  */
 403         break;
 404     case 0x4c: /* FLASH */
 405         break;
 406     case 0x50: /* CLCD */
 407         switch (board_id(s)) {
 408         case BOARD_ID_PB926:
 409             /* On 926 bits 13:8 are R/O, bits 1:0 control
 410              * the mux that defines how to interpret the PL110
 411              * graphics format, and other bits are r/w but we
 412              * don't implement them to do anything.
 413              */
 414             s->sys_clcd &= 0x3f00;
 415             s->sys_clcd |= val & ~0x3f00;
 416             qemu_set_irq(s->pl110_mux_ctrl, val & 3);
 417             break;
 418         case BOARD_ID_EB:
 419             /* The EB is the same except that there is no mux since
 420              * the EB has a PL111.
 421              */
 422             s->sys_clcd &= 0x3f00;
 423             s->sys_clcd |= val & ~0x3f00;
 424             break;
 425         case BOARD_ID_PBA8:
 426         case BOARD_ID_PBX:
 427             /* On PBA8 and PBX bit 7 is r/w and all other bits
 428              * are either r/o or RAZ/WI.
 429              */
 430             s->sys_clcd &= (1 << 7);
 431             s->sys_clcd |= val & ~(1 << 7);
 432             break;
 433         case BOARD_ID_VEXPRESS:
 434         default:
 435             /* On VExpress this register is unimplemented and will RAZ/WI */
 436             break;
 437         }
 438         break;
 439     case 0x54: /* CLCDSER */
 440     case 0x64: /* DMAPSR0 */
 441     case 0x68: /* DMAPSR1 */
 442     case 0x6c: /* DMAPSR2 */
 443     case 0x70: /* IOSEL */
 444     case 0x74: /* PLDCTL */
 445     case 0x80: /* BUSID */
 446     case 0x84: /* PROCID0 */
 447     case 0x88: /* PROCID1 */
 448     case 0x8c: /* OSCRESET0 */
 449     case 0x90: /* OSCRESET1 */
 450     case 0x94: /* OSCRESET2 */
 451     case 0x98: /* OSCRESET3 */
 452     case 0x9c: /* OSCRESET4 */
 453         break;
 454     case 0xa0: /* SYS_CFGDATA */
 455         if (board_id(s) != BOARD_ID_VEXPRESS) {
 456             goto bad_reg;
 457         }
 458         s->sys_cfgdata = val;
 459         return;
 460     case 0xa4: /* SYS_CFGCTRL */
 461         if (board_id(s) != BOARD_ID_VEXPRESS) {
 462             goto bad_reg;
 463         }
 464         /* Undefined bits [19:18] are RAZ/WI, and writing to
 465          * the start bit just triggers the action; it always reads
 466          * as zero.
 467          */
 468         s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31));
 469         if (val & (1 << 31)) {
 470             /* Start bit set -- actually do something */
 471             unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4);
 472             unsigned int function = extract32(s->sys_cfgctrl, 20, 6);
 473             unsigned int site = extract32(s->sys_cfgctrl, 16, 2);
 474             unsigned int position = extract32(s->sys_cfgctrl, 12, 4);
 475             unsigned int device = extract32(s->sys_cfgctrl, 0, 12);
 476             s->sys_cfgstat = 1;            /* complete */
 477             if (s->sys_cfgctrl & (1 << 30)) {
 478                 if (!vexpress_cfgctrl_write(s, dcc, function, site, position,
 479                                             device, s->sys_cfgdata)) {
 480                     s->sys_cfgstat |= 2;        /* error */
 481                 }
 482             } else {
 483                 uint32_t val;
 484                 if (!vexpress_cfgctrl_read(s, dcc, function, site, position,
 485                                            device, &val)) {
 486                     s->sys_cfgstat |= 2;        /* error */
 487                 } else {
 488                     s->sys_cfgdata = val;
 489                 }
 490             }
 491         }
 492         s->sys_cfgctrl &= ~(1 << 31);
 493         return;
 494     case 0xa8: /* SYS_CFGSTAT */
 495         if (board_id(s) != BOARD_ID_VEXPRESS) {
 496             goto bad_reg;
 497         }
 498         s->sys_cfgstat = val & 3;
 499         return;
 500     default:
 501     bad_reg:
 502         qemu_log_mask(LOG_GUEST_ERROR,
 503                       "arm_sysctl_write: Bad register offset 0x%x\n",
 504                       (int)offset);
 505         return;
 506     }
 507 }
 508
 509 static const MemoryRegionOps arm_sysctl_ops = {
 510     .read = arm_sysctl_read,
 511     .write = arm_sysctl_write,
 512     .endianness = DEVICE_NATIVE_ENDIAN,
 513 };
 514
 515 static void arm_sysctl_gpio_set(void *opaque, int line, int level)
 516 {
 517     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 518     switch (line) {
 519     case ARM_SYSCTL_GPIO_MMC_WPROT:
 520     {
 521         /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
 522          * for all later boards it is bit 1.
 523          */
 524         int bit = 2;
 525         if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
 526             bit = 4;
 527         }
 528         s->sys_mci &= ~bit;
 529         if (level) {
 530             s->sys_mci |= bit;
 531         }
 532         break;
 533     }
 534     case ARM_SYSCTL_GPIO_MMC_CARDIN:
 535         s->sys_mci &= ~1;
 536         if (level) {
 537             s->sys_mci |= 1;
 538         }
 539         break;
 540     }
 541 }
 542
 543 static void arm_sysctl_init(Object *obj)
 544 {
 545     DeviceState *dev = DEVICE(obj);
 546     SysBusDevice *sd = SYS_BUS_DEVICE(obj);
 547     arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sd);
 548
 549     memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
 550     sysbus_init_mmio(sd, &s->iomem);
 551     qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2);
 552     qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1);
 553 }
 554
 555 static void arm_sysctl_finalize(Object *obj)
 556 {
 557     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 558     arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
 559     g_free(s->db_voltage);
 560 }
 561
 562 static Property arm_sysctl_properties[] = {
 563     DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
 564     DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
 565     /* Daughterboard power supply voltages (as reported via SYS_CFG) */
 566     DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors,
 567                       db_voltage, qdev_prop_uint32, uint32_t),
 568     DEFINE_PROP_END_OF_LIST(),
 569 };
 570
 571 static void arm_sysctl_class_init(ObjectClass *klass, void *data)
 572 {
 573     DeviceClass *dc = DEVICE_CLASS(klass);
 574
 575     dc->reset = arm_sysctl_reset;
 576     dc->vmsd = &vmstate_arm_sysctl;
 577     dc->props = arm_sysctl_properties;
 578 }
 579
 580 static const TypeInfo arm_sysctl_info = {
 581     .name          = "realview_sysctl",
 582     .parent        = TYPE_SYS_BUS_DEVICE,
 583     .instance_size = sizeof(arm_sysctl_state),
 584     .instance_init = arm_sysctl_init,
 585     .instance_finalize = arm_sysctl_finalize,
 586     .class_init    = arm_sysctl_class_init,
 587 };
 588
 589 static void arm_sysctl_register_types(void)
 590 {
 591     type_register_static(&arm_sysctl_info);
 592 }
 593
 594 type_init(arm_sysctl_register_types)