hw/audio/cs4231.c

   1 /*
   2  * QEMU Crystal CS4231 audio chip emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "trace.h"
  27
  28 /*
  29  * In addition to Crystal CS4231 there is a DMA controller on Sparc.
  30  */
  31 #define CS_SIZE 0x40
  32 #define CS_REGS 16
  33 #define CS_DREGS 32
  34 #define CS_MAXDREG (CS_DREGS - 1)
  35
  36 #define TYPE_CS4231 "SUNW,CS4231"
  37 #define CS4231(obj) \
  38     OBJECT_CHECK(CSState, (obj), TYPE_CS4231)
  39
  40 typedef struct CSState {
  41     SysBusDevice parent_obj;
  42
  43     MemoryRegion iomem;
  44     qemu_irq irq;
  45     uint32_t regs[CS_REGS];
  46     uint8_t dregs[CS_DREGS];
  47 } CSState;
  48
  49 #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
  50 #define CS_VER 0xa0
  51 #define CS_CDC_VER 0x8a
  52
  53 static void cs_reset(DeviceState *d)
  54 {
  55     CSState *s = CS4231(d);
  56
  57     memset(s->regs, 0, CS_REGS * 4);
  58     memset(s->dregs, 0, CS_DREGS);
  59     s->dregs[12] = CS_CDC_VER;
  60     s->dregs[25] = CS_VER;
  61 }
  62
  63 static uint64_t cs_mem_read(void *opaque, hwaddr addr,
  64                             unsigned size)
  65 {
  66     CSState *s = opaque;
  67     uint32_t saddr, ret;
  68
  69     saddr = addr >> 2;
  70     switch (saddr) {
  71     case 1:
  72         switch (CS_RAP(s)) {
  73         case 3: // Write only
  74             ret = 0;
  75             break;
  76         default:
  77             ret = s->dregs[CS_RAP(s)];
  78             break;
  79         }
  80         trace_cs4231_mem_readl_dreg(CS_RAP(s), ret);
  81         break;
  82     default:
  83         ret = s->regs[saddr];
  84         trace_cs4231_mem_readl_reg(saddr, ret);
  85         break;
  86     }
  87     return ret;
  88 }
  89
  90 static void cs_mem_write(void *opaque, hwaddr addr,
  91                          uint64_t val, unsigned size)
  92 {
  93     CSState *s = opaque;
  94     uint32_t saddr;
  95
  96     saddr = addr >> 2;
  97     trace_cs4231_mem_writel_reg(saddr, s->regs[saddr], val);
  98     switch (saddr) {
  99     case 1:
 100         trace_cs4231_mem_writel_dreg(CS_RAP(s), s->dregs[CS_RAP(s)], val);
 101         switch(CS_RAP(s)) {
 102         case 11:
 103         case 25: // Read only
 104             break;
 105         case 12:
 106             val &= 0x40;
 107             val |= CS_CDC_VER; // Codec version
 108             s->dregs[CS_RAP(s)] = val;
 109             break;
 110         default:
 111             s->dregs[CS_RAP(s)] = val;
 112             break;
 113         }
 114         break;
 115     case 2: // Read only
 116         break;
 117     case 4:
 118         if (val & 1) {
 119             cs_reset(DEVICE(s));
 120         }
 121         val &= 0x7f;
 122         s->regs[saddr] = val;
 123         break;
 124     default:
 125         s->regs[saddr] = val;
 126         break;
 127     }
 128 }
 129
 130 static const MemoryRegionOps cs_mem_ops = {
 131     .read = cs_mem_read,
 132     .write = cs_mem_write,
 133     .endianness = DEVICE_NATIVE_ENDIAN,
 134 };
 135
 136 static const VMStateDescription vmstate_cs4231 = {
 137     .name ="cs4231",
 138     .version_id = 1,
 139     .minimum_version_id = 1,
 140     .minimum_version_id_old = 1,
 141     .fields      = (VMStateField []) {
 142         VMSTATE_UINT32_ARRAY(regs, CSState, CS_REGS),
 143         VMSTATE_UINT8_ARRAY(dregs, CSState, CS_DREGS),
 144         VMSTATE_END_OF_LIST()
 145     }
 146 };
 147
 148 static int cs4231_init1(SysBusDevice *dev)
 149 {
 150     CSState *s = CS4231(dev);
 151
 152     memory_region_init_io(&s->iomem, OBJECT(s), &cs_mem_ops, s, "cs4321",
 153                           CS_SIZE);
 154     sysbus_init_mmio(dev, &s->iomem);
 155     sysbus_init_irq(dev, &s->irq);
 156
 157     return 0;
 158 }
 159
 160 static Property cs4231_properties[] = {
 161     {.name = NULL},
 162 };
 163
 164 static void cs4231_class_init(ObjectClass *klass, void *data)
 165 {
 166     DeviceClass *dc = DEVICE_CLASS(klass);
 167     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 168
 169     k->init = cs4231_init1;
 170     dc->reset = cs_reset;
 171     dc->vmsd = &vmstate_cs4231;
 172     dc->props = cs4231_properties;
 173 }
 174
 175 static const TypeInfo cs4231_info = {
 176     .name          = TYPE_CS4231,
 177     .parent        = TYPE_SYS_BUS_DEVICE,
 178     .instance_size = sizeof(CSState),
 179     .class_init    = cs4231_class_init,
 180 };
 181
 182 static void cs4231_register_types(void)
 183 {
 184     type_register_static(&cs4231_info);
 185 }
 186
 187 type_init(cs4231_register_types)