hw/block/m25p80.c

   1 /*
   2  * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
   3  * set. Known devices table current as of Jun/2012 and taken from linux.
   4  * See drivers/mtd/devices/m25p80.c.
   5  *
   6  * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
   7  * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
   8  * Copyright (C) 2012 PetaLogix
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 or
  13  * (at your option) a later version of the License.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #include "hw/hw.h"
  25 #include "sysemu/blockdev.h"
  26 #include "hw/ssi.h"
  27
  28 #ifndef M25P80_ERR_DEBUG
  29 #define M25P80_ERR_DEBUG 0
  30 #endif
  31
  32 #define DB_PRINT_L(level, ...) do { \
  33     if (M25P80_ERR_DEBUG > (level)) { \
  34         fprintf(stderr,  ": %s: ", __func__); \
  35         fprintf(stderr, ## __VA_ARGS__); \
  36     } \
  37 } while (0);
  38
  39 /* Fields for FlashPartInfo->flags */
  40
  41 /* erase capabilities */
  42 #define ER_4K 1
  43 #define ER_32K 2
  44 /* set to allow the page program command to write 0s back to 1. Useful for
  45  * modelling EEPROM with SPI flash command set
  46  */
  47 #define WR_1 0x100
  48
  49 typedef struct FlashPartInfo {
  50     const char *part_name;
  51     /* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */
  52     uint32_t jedec;
  53     /* extended jedec code */
  54     uint16_t ext_jedec;
  55     /* there is confusion between manufacturers as to what a sector is. In this
  56      * device model, a "sector" is the size that is erased by the ERASE_SECTOR
  57      * command (opcode 0xd8).
  58      */
  59     uint32_t sector_size;
  60     uint32_t n_sectors;
  61     uint32_t page_size;
  62     uint8_t flags;
  63 } FlashPartInfo;
  64
  65 /* adapted from linux */
  66
  67 #define INFO(_part_name, _jedec, _ext_jedec, _sector_size, _n_sectors, _flags)\
  68     .part_name = (_part_name),\
  69     .jedec = (_jedec),\
  70     .ext_jedec = (_ext_jedec),\
  71     .sector_size = (_sector_size),\
  72     .n_sectors = (_n_sectors),\
  73     .page_size = 256,\
  74     .flags = (_flags),\
  75
  76 #define JEDEC_NUMONYX 0x20
  77 #define JEDEC_WINBOND 0xEF
  78 #define JEDEC_SPANSION 0x01
  79
  80 static const FlashPartInfo known_devices[] = {
  81     /* Atmel -- some are (confusingly) marketed as "DataFlash" */
  82     { INFO("at25fs010",   0x1f6601,      0,  32 << 10,   4, ER_4K) },
  83     { INFO("at25fs040",   0x1f6604,      0,  64 << 10,   8, ER_4K) },
  84
  85     { INFO("at25df041a",  0x1f4401,      0,  64 << 10,   8, ER_4K) },
  86     { INFO("at25df321a",  0x1f4701,      0,  64 << 10,  64, ER_4K) },
  87     { INFO("at25df641",   0x1f4800,      0,  64 << 10, 128, ER_4K) },
  88
  89     { INFO("at26f004",    0x1f0400,      0,  64 << 10,   8, ER_4K) },
  90     { INFO("at26df081a",  0x1f4501,      0,  64 << 10,  16, ER_4K) },
  91     { INFO("at26df161a",  0x1f4601,      0,  64 << 10,  32, ER_4K) },
  92     { INFO("at26df321",   0x1f4700,      0,  64 << 10,  64, ER_4K) },
  93
  94     { INFO("at45db081d",  0x1f2500,      0,  64 << 10,  16, ER_4K) },
  95
  96     /* EON -- en25xxx */
  97     { INFO("en25f32",     0x1c3116,      0,  64 << 10,  64, ER_4K) },
  98     { INFO("en25p32",     0x1c2016,      0,  64 << 10,  64, 0) },
  99     { INFO("en25q32b",    0x1c3016,      0,  64 << 10,  64, 0) },
 100     { INFO("en25p64",     0x1c2017,      0,  64 << 10, 128, 0) },
 101     { INFO("en25q64",     0x1c3017,      0,  64 << 10, 128, ER_4K) },
 102
 103     /* GigaDevice */
 104     { INFO("gd25q32",     0xc84016,      0,  64 << 10,  64, ER_4K) },
 105     { INFO("gd25q64",     0xc84017,      0,  64 << 10, 128, ER_4K) },
 106
 107     /* Intel/Numonyx -- xxxs33b */
 108     { INFO("160s33b",     0x898911,      0,  64 << 10,  32, 0) },
 109     { INFO("320s33b",     0x898912,      0,  64 << 10,  64, 0) },
 110     { INFO("640s33b",     0x898913,      0,  64 << 10, 128, 0) },
 111     { INFO("n25q064",     0x20ba17,      0,  64 << 10, 128, 0) },
 112
 113     /* Macronix */
 114     { INFO("mx25l2005a",  0xc22012,      0,  64 << 10,   4, ER_4K) },
 115     { INFO("mx25l4005a",  0xc22013,      0,  64 << 10,   8, ER_4K) },
 116     { INFO("mx25l8005",   0xc22014,      0,  64 << 10,  16, 0) },
 117     { INFO("mx25l1606e",  0xc22015,      0,  64 << 10,  32, ER_4K) },
 118     { INFO("mx25l3205d",  0xc22016,      0,  64 << 10,  64, 0) },
 119     { INFO("mx25l6405d",  0xc22017,      0,  64 << 10, 128, 0) },
 120     { INFO("mx25l12805d", 0xc22018,      0,  64 << 10, 256, 0) },
 121     { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
 122     { INFO("mx25l25635e", 0xc22019,      0,  64 << 10, 512, 0) },
 123     { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
 124
 125     /* Micron */
 126     { INFO("n25q128a11",  0x20bb18,      0,  64 << 10, 256, 0) },
 127     { INFO("n25q128a13",  0x20ba18,      0,  64 << 10, 256, 0) },
 128     { INFO("n25q256a",    0x20ba19,      0,  64 << 10, 512, ER_4K) },
 129
 130     /* Spansion -- single (large) sector size only, at least
 131      * for the chips listed here (without boot sectors).
 132      */
 133     { INFO("s25sl032p",   0x010215, 0x4d00,  64 << 10,  64, ER_4K) },
 134     { INFO("s25sl064p",   0x010216, 0x4d00,  64 << 10, 128, ER_4K) },
 135     { INFO("s25fl256s0",  0x010219, 0x4d00, 256 << 10, 128, 0) },
 136     { INFO("s25fl256s1",  0x010219, 0x4d01,  64 << 10, 512, 0) },
 137     { INFO("s25fl512s",   0x010220, 0x4d00, 256 << 10, 256, 0) },
 138     { INFO("s70fl01gs",   0x010221, 0x4d00, 256 << 10, 256, 0) },
 139     { INFO("s25sl12800",  0x012018, 0x0300, 256 << 10,  64, 0) },
 140     { INFO("s25sl12801",  0x012018, 0x0301,  64 << 10, 256, 0) },
 141     { INFO("s25fl129p0",  0x012018, 0x4d00, 256 << 10,  64, 0) },
 142     { INFO("s25fl129p1",  0x012018, 0x4d01,  64 << 10, 256, 0) },
 143     { INFO("s25sl004a",   0x010212,      0,  64 << 10,   8, 0) },
 144     { INFO("s25sl008a",   0x010213,      0,  64 << 10,  16, 0) },
 145     { INFO("s25sl016a",   0x010214,      0,  64 << 10,  32, 0) },
 146     { INFO("s25sl032a",   0x010215,      0,  64 << 10,  64, 0) },
 147     { INFO("s25sl064a",   0x010216,      0,  64 << 10, 128, 0) },
 148     { INFO("s25fl016k",   0xef4015,      0,  64 << 10,  32, ER_4K | ER_32K) },
 149     { INFO("s25fl064k",   0xef4017,      0,  64 << 10, 128, ER_4K | ER_32K) },
 150
 151     /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
 152     { INFO("sst25vf040b", 0xbf258d,      0,  64 << 10,   8, ER_4K) },
 153     { INFO("sst25vf080b", 0xbf258e,      0,  64 << 10,  16, ER_4K) },
 154     { INFO("sst25vf016b", 0xbf2541,      0,  64 << 10,  32, ER_4K) },
 155     { INFO("sst25vf032b", 0xbf254a,      0,  64 << 10,  64, ER_4K) },
 156     { INFO("sst25wf512",  0xbf2501,      0,  64 << 10,   1, ER_4K) },
 157     { INFO("sst25wf010",  0xbf2502,      0,  64 << 10,   2, ER_4K) },
 158     { INFO("sst25wf020",  0xbf2503,      0,  64 << 10,   4, ER_4K) },
 159     { INFO("sst25wf040",  0xbf2504,      0,  64 << 10,   8, ER_4K) },
 160
 161     /* ST Microelectronics -- newer production may have feature updates */
 162     { INFO("m25p05",      0x202010,      0,  32 << 10,   2, 0) },
 163     { INFO("m25p10",      0x202011,      0,  32 << 10,   4, 0) },
 164     { INFO("m25p20",      0x202012,      0,  64 << 10,   4, 0) },
 165     { INFO("m25p40",      0x202013,      0,  64 << 10,   8, 0) },
 166     { INFO("m25p80",      0x202014,      0,  64 << 10,  16, 0) },
 167     { INFO("m25p16",      0x202015,      0,  64 << 10,  32, 0) },
 168     { INFO("m25p32",      0x202016,      0,  64 << 10,  64, 0) },
 169     { INFO("m25p64",      0x202017,      0,  64 << 10, 128, 0) },
 170     { INFO("m25p128",     0x202018,      0, 256 << 10,  64, 0) },
 171     { INFO("n25q032",     0x20ba16,      0,  64 << 10,  64, 0) },
 172
 173     { INFO("m45pe10",     0x204011,      0,  64 << 10,   2, 0) },
 174     { INFO("m45pe80",     0x204014,      0,  64 << 10,  16, 0) },
 175     { INFO("m45pe16",     0x204015,      0,  64 << 10,  32, 0) },
 176
 177     { INFO("m25pe20",     0x208012,      0,  64 << 10,   4, 0) },
 178     { INFO("m25pe80",     0x208014,      0,  64 << 10,  16, 0) },
 179     { INFO("m25pe16",     0x208015,      0,  64 << 10,  32, ER_4K) },
 180
 181     { INFO("m25px32",     0x207116,      0,  64 << 10,  64, ER_4K) },
 182     { INFO("m25px32-s0",  0x207316,      0,  64 << 10,  64, ER_4K) },
 183     { INFO("m25px32-s1",  0x206316,      0,  64 << 10,  64, ER_4K) },
 184     { INFO("m25px64",     0x207117,      0,  64 << 10, 128, 0) },
 185
 186     /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
 187     { INFO("w25x10",      0xef3011,      0,  64 << 10,   2, ER_4K) },
 188     { INFO("w25x20",      0xef3012,      0,  64 << 10,   4, ER_4K) },
 189     { INFO("w25x40",      0xef3013,      0,  64 << 10,   8, ER_4K) },
 190     { INFO("w25x80",      0xef3014,      0,  64 << 10,  16, ER_4K) },
 191     { INFO("w25x16",      0xef3015,      0,  64 << 10,  32, ER_4K) },
 192     { INFO("w25x32",      0xef3016,      0,  64 << 10,  64, ER_4K) },
 193     { INFO("w25q32",      0xef4016,      0,  64 << 10,  64, ER_4K) },
 194     { INFO("w25q32dw",    0xef6016,      0,  64 << 10,  64, ER_4K) },
 195     { INFO("w25x64",      0xef3017,      0,  64 << 10, 128, ER_4K) },
 196     { INFO("w25q64",      0xef4017,      0,  64 << 10, 128, ER_4K) },
 197     { INFO("w25q80",      0xef5014,      0,  64 << 10,  16, ER_4K) },
 198     { INFO("w25q80bl",    0xef4014,      0,  64 << 10,  16, ER_4K) },
 199     { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K) },
 200
 201     /* Numonyx -- n25q128 */
 202     { INFO("n25q128",      0x20ba18,      0,  64 << 10, 256, 0) },
 203 };
 204
 205 typedef enum {
 206     NOP = 0,
 207     WRSR = 0x1,
 208     WRDI = 0x4,
 209     RDSR = 0x5,
 210     WREN = 0x6,
 211     JEDEC_READ = 0x9f,
 212     BULK_ERASE = 0xc7,
 213
 214     READ = 0x3,
 215     FAST_READ = 0xb,
 216     DOR = 0x3b,
 217     QOR = 0x6b,
 218     DIOR = 0xbb,
 219     QIOR = 0xeb,
 220
 221     PP = 0x2,
 222     DPP = 0xa2,
 223     QPP = 0x32,
 224
 225     ERASE_4K = 0x20,
 226     ERASE_32K = 0x52,
 227     ERASE_SECTOR = 0xd8,
 228 } FlashCMD;
 229
 230 typedef enum {
 231     STATE_IDLE,
 232     STATE_PAGE_PROGRAM,
 233     STATE_READ,
 234     STATE_COLLECTING_DATA,
 235     STATE_READING_DATA,
 236 } CMDState;
 237
 238 typedef struct Flash {
 239     SSISlave ssidev;
 240     uint32_t r;
 241
 242     BlockDriverState *bdrv;
 243
 244     uint8_t *storage;
 245     uint32_t size;
 246     int page_size;
 247
 248     uint8_t state;
 249     uint8_t data[16];
 250     uint32_t len;
 251     uint32_t pos;
 252     uint8_t needed_bytes;
 253     uint8_t cmd_in_progress;
 254     uint64_t cur_addr;
 255     bool write_enable;
 256
 257     int64_t dirty_page;
 258
 259     const FlashPartInfo *pi;
 260
 261 } Flash;
 262
 263 typedef struct M25P80Class {
 264     SSISlaveClass parent_class;
 265     FlashPartInfo *pi;
 266 } M25P80Class;
 267
 268 #define TYPE_M25P80 "m25p80-generic"
 269 #define M25P80(obj) \
 270      OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
 271 #define M25P80_CLASS(klass) \
 272      OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
 273 #define M25P80_GET_CLASS(obj) \
 274      OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
 275
 276 static void bdrv_sync_complete(void *opaque, int ret)
 277 {
 278     /* do nothing. Masters do not directly interact with the backing store,
 279      * only the working copy so no mutexing required.
 280      */
 281 }
 282
 283 static void flash_sync_page(Flash *s, int page)
 284 {
 285     if (s->bdrv) {
 286         int bdrv_sector, nb_sectors;
 287         QEMUIOVector iov;
 288
 289         bdrv_sector = (page * s->pi->page_size) / BDRV_SECTOR_SIZE;
 290         nb_sectors = DIV_ROUND_UP(s->pi->page_size, BDRV_SECTOR_SIZE);
 291         qemu_iovec_init(&iov, 1);
 292         qemu_iovec_add(&iov, s->storage + bdrv_sector * BDRV_SECTOR_SIZE,
 293                                                 nb_sectors * BDRV_SECTOR_SIZE);
 294         bdrv_aio_writev(s->bdrv, bdrv_sector, &iov, nb_sectors,
 295                                                 bdrv_sync_complete, NULL);
 296     }
 297 }
 298
 299 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
 300 {
 301     int64_t start, end, nb_sectors;
 302     QEMUIOVector iov;
 303
 304     if (!s->bdrv) {
 305         return;
 306     }
 307
 308     assert(!(len % BDRV_SECTOR_SIZE));
 309     start = off / BDRV_SECTOR_SIZE;
 310     end = (off + len) / BDRV_SECTOR_SIZE;
 311     nb_sectors = end - start;
 312     qemu_iovec_init(&iov, 1);
 313     qemu_iovec_add(&iov, s->storage + (start * BDRV_SECTOR_SIZE),
 314                                         nb_sectors * BDRV_SECTOR_SIZE);
 315     bdrv_aio_writev(s->bdrv, start, &iov, nb_sectors, bdrv_sync_complete, NULL);
 316 }
 317
 318 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
 319 {
 320     uint32_t len;
 321     uint8_t capa_to_assert = 0;
 322
 323     switch (cmd) {
 324     case ERASE_4K:
 325         len = 4 << 10;
 326         capa_to_assert = ER_4K;
 327         break;
 328     case ERASE_32K:
 329         len = 32 << 10;
 330         capa_to_assert = ER_32K;
 331         break;
 332     case ERASE_SECTOR:
 333         len = s->pi->sector_size;
 334         break;
 335     case BULK_ERASE:
 336         len = s->size;
 337         break;
 338     default:
 339         abort();
 340     }
 341
 342     DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
 343     if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
 344         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
 345                       " device\n", len);
 346     }
 347
 348     if (!s->write_enable) {
 349         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
 350         return;
 351     }
 352     memset(s->storage + offset, 0xff, len);
 353     flash_sync_area(s, offset, len);
 354 }
 355
 356 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
 357 {
 358     if (s->dirty_page >= 0 && s->dirty_page != newpage) {
 359         flash_sync_page(s, s->dirty_page);
 360         s->dirty_page = newpage;
 361     }
 362 }
 363
 364 static inline
 365 void flash_write8(Flash *s, uint64_t addr, uint8_t data)
 366 {
 367     int64_t page = addr / s->pi->page_size;
 368     uint8_t prev = s->storage[s->cur_addr];
 369
 370     if (!s->write_enable) {
 371         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
 372     }
 373
 374     if ((prev ^ data) & data) {
 375         DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 "  %" PRIx8
 376                    " -> %" PRIx8 "\n", addr, prev, data);
 377     }
 378
 379     if (s->pi->flags & WR_1) {
 380         s->storage[s->cur_addr] = data;
 381     } else {
 382         s->storage[s->cur_addr] &= data;
 383     }
 384
 385     flash_sync_dirty(s, page);
 386     s->dirty_page = page;
 387 }
 388
 389 static void complete_collecting_data(Flash *s)
 390 {
 391     s->cur_addr = s->data[0] << 16;
 392     s->cur_addr |= s->data[1] << 8;
 393     s->cur_addr |= s->data[2];
 394
 395     s->state = STATE_IDLE;
 396
 397     switch (s->cmd_in_progress) {
 398     case DPP:
 399     case QPP:
 400     case PP:
 401         s->state = STATE_PAGE_PROGRAM;
 402         break;
 403     case READ:
 404     case FAST_READ:
 405     case DOR:
 406     case QOR:
 407     case DIOR:
 408     case QIOR:
 409         s->state = STATE_READ;
 410         break;
 411     case ERASE_4K:
 412     case ERASE_32K:
 413     case ERASE_SECTOR:
 414         flash_erase(s, s->cur_addr, s->cmd_in_progress);
 415         break;
 416     case WRSR:
 417         if (s->write_enable) {
 418             s->write_enable = false;
 419         }
 420         break;
 421     default:
 422         break;
 423     }
 424 }
 425
 426 static void decode_new_cmd(Flash *s, uint32_t value)
 427 {
 428     s->cmd_in_progress = value;
 429     DB_PRINT_L(0, "decoded new command:%x\n", value);
 430
 431     switch (value) {
 432
 433     case ERASE_4K:
 434     case ERASE_32K:
 435     case ERASE_SECTOR:
 436     case READ:
 437     case DPP:
 438     case QPP:
 439     case PP:
 440         s->needed_bytes = 3;
 441         s->pos = 0;
 442         s->len = 0;
 443         s->state = STATE_COLLECTING_DATA;
 444         break;
 445
 446     case FAST_READ:
 447     case DOR:
 448     case QOR:
 449         s->needed_bytes = 4;
 450         s->pos = 0;
 451         s->len = 0;
 452         s->state = STATE_COLLECTING_DATA;
 453         break;
 454
 455     case DIOR:
 456         switch ((s->pi->jedec >> 16) & 0xFF) {
 457         case JEDEC_WINBOND:
 458         case JEDEC_SPANSION:
 459             s->needed_bytes = 4;
 460             break;
 461         case JEDEC_NUMONYX:
 462         default:
 463             s->needed_bytes = 5;
 464         }
 465         s->pos = 0;
 466         s->len = 0;
 467         s->state = STATE_COLLECTING_DATA;
 468         break;
 469
 470     case QIOR:
 471         switch ((s->pi->jedec >> 16) & 0xFF) {
 472         case JEDEC_WINBOND:
 473         case JEDEC_SPANSION:
 474             s->needed_bytes = 6;
 475             break;
 476         case JEDEC_NUMONYX:
 477         default:
 478             s->needed_bytes = 8;
 479         }
 480         s->pos = 0;
 481         s->len = 0;
 482         s->state = STATE_COLLECTING_DATA;
 483         break;
 484
 485     case WRSR:
 486         if (s->write_enable) {
 487             s->needed_bytes = 1;
 488             s->pos = 0;
 489             s->len = 0;
 490             s->state = STATE_COLLECTING_DATA;
 491         }
 492         break;
 493
 494     case WRDI:
 495         s->write_enable = false;
 496         break;
 497     case WREN:
 498         s->write_enable = true;
 499         break;
 500
 501     case RDSR:
 502         s->data[0] = (!!s->write_enable) << 1;
 503         s->pos = 0;
 504         s->len = 1;
 505         s->state = STATE_READING_DATA;
 506         break;
 507
 508     case JEDEC_READ:
 509         DB_PRINT_L(0, "populated jedec code\n");
 510         s->data[0] = (s->pi->jedec >> 16) & 0xff;
 511         s->data[1] = (s->pi->jedec >> 8) & 0xff;
 512         s->data[2] = s->pi->jedec & 0xff;
 513         if (s->pi->ext_jedec) {
 514             s->data[3] = (s->pi->ext_jedec >> 8) & 0xff;
 515             s->data[4] = s->pi->ext_jedec & 0xff;
 516             s->len = 5;
 517         } else {
 518             s->len = 3;
 519         }
 520         s->pos = 0;
 521         s->state = STATE_READING_DATA;
 522         break;
 523
 524     case BULK_ERASE:
 525         if (s->write_enable) {
 526             DB_PRINT_L(0, "chip erase\n");
 527             flash_erase(s, 0, BULK_ERASE);
 528         } else {
 529             qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
 530                           "protect!\n");
 531         }
 532         break;
 533     case NOP:
 534         break;
 535     default:
 536         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
 537         break;
 538     }
 539 }
 540
 541 static int m25p80_cs(SSISlave *ss, bool select)
 542 {
 543     Flash *s = FROM_SSI_SLAVE(Flash, ss);
 544
 545     if (select) {
 546         s->len = 0;
 547         s->pos = 0;
 548         s->state = STATE_IDLE;
 549         flash_sync_dirty(s, -1);
 550     }
 551
 552     DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
 553
 554     return 0;
 555 }
 556
 557 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
 558 {
 559     Flash *s = FROM_SSI_SLAVE(Flash, ss);
 560     uint32_t r = 0;
 561
 562     switch (s->state) {
 563
 564     case STATE_PAGE_PROGRAM:
 565         DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n",
 566                    s->cur_addr, (uint8_t)tx);
 567         flash_write8(s, s->cur_addr, (uint8_t)tx);
 568         s->cur_addr++;
 569         break;
 570
 571     case STATE_READ:
 572         r = s->storage[s->cur_addr];
 573         DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr,
 574                    (uint8_t)r);
 575         s->cur_addr = (s->cur_addr + 1) % s->size;
 576         break;
 577
 578     case STATE_COLLECTING_DATA:
 579         s->data[s->len] = (uint8_t)tx;
 580         s->len++;
 581
 582         if (s->len == s->needed_bytes) {
 583             complete_collecting_data(s);
 584         }
 585         break;
 586
 587     case STATE_READING_DATA:
 588         r = s->data[s->pos];
 589         s->pos++;
 590         if (s->pos == s->len) {
 591             s->pos = 0;
 592             s->state = STATE_IDLE;
 593         }
 594         break;
 595
 596     default:
 597     case STATE_IDLE:
 598         decode_new_cmd(s, (uint8_t)tx);
 599         break;
 600     }
 601
 602     return r;
 603 }
 604
 605 static int m25p80_init(SSISlave *ss)
 606 {
 607     DriveInfo *dinfo;
 608     Flash *s = FROM_SSI_SLAVE(Flash, ss);
 609     M25P80Class *mc = M25P80_GET_CLASS(s);
 610
 611     s->pi = mc->pi;
 612
 613     s->size = s->pi->sector_size * s->pi->n_sectors;
 614     s->dirty_page = -1;
 615     s->storage = qemu_blockalign(s->bdrv, s->size);
 616
 617     dinfo = drive_get_next(IF_MTD);
 618
 619     if (dinfo && dinfo->bdrv) {
 620         DB_PRINT_L(0, "Binding to IF_MTD drive\n");
 621         s->bdrv = dinfo->bdrv;
 622         /* FIXME: Move to late init */
 623         if (bdrv_read(s->bdrv, 0, s->storage, DIV_ROUND_UP(s->size,
 624                                                     BDRV_SECTOR_SIZE))) {
 625             fprintf(stderr, "Failed to initialize SPI flash!\n");
 626             return 1;
 627         }
 628     } else {
 629         DB_PRINT_L(0, "No BDRV - binding to RAM\n");
 630         memset(s->storage, 0xFF, s->size);
 631     }
 632
 633     return 0;
 634 }
 635
 636 static void m25p80_pre_save(void *opaque)
 637 {
 638     flash_sync_dirty((Flash *)opaque, -1);
 639 }
 640
 641 static const VMStateDescription vmstate_m25p80 = {
 642     .name = "xilinx_spi",
 643     .version_id = 1,
 644     .minimum_version_id = 1,
 645     .minimum_version_id_old = 1,
 646     .pre_save = m25p80_pre_save,
 647     .fields = (VMStateField[]) {
 648         VMSTATE_UINT8(state, Flash),
 649         VMSTATE_UINT8_ARRAY(data, Flash, 16),
 650         VMSTATE_UINT32(len, Flash),
 651         VMSTATE_UINT32(pos, Flash),
 652         VMSTATE_UINT8(needed_bytes, Flash),
 653         VMSTATE_UINT8(cmd_in_progress, Flash),
 654         VMSTATE_UINT64(cur_addr, Flash),
 655         VMSTATE_BOOL(write_enable, Flash),
 656         VMSTATE_END_OF_LIST()
 657     }
 658 };
 659
 660 static void m25p80_class_init(ObjectClass *klass, void *data)
 661 {
 662     DeviceClass *dc = DEVICE_CLASS(klass);
 663     SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
 664     M25P80Class *mc = M25P80_CLASS(klass);
 665
 666     k->init = m25p80_init;
 667     k->transfer = m25p80_transfer8;
 668     k->set_cs = m25p80_cs;
 669     k->cs_polarity = SSI_CS_LOW;
 670     dc->vmsd = &vmstate_m25p80;
 671     mc->pi = data;
 672 }
 673
 674 static const TypeInfo m25p80_info = {
 675     .name           = TYPE_M25P80,
 676     .parent         = TYPE_SSI_SLAVE,
 677     .instance_size  = sizeof(Flash),
 678     .class_size     = sizeof(M25P80Class),
 679     .abstract       = true,
 680 };
 681
 682 static void m25p80_register_types(void)
 683 {
 684     int i;
 685
 686     type_register_static(&m25p80_info);
 687     for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
 688         TypeInfo ti = {
 689             .name       = known_devices[i].part_name,
 690             .parent     = TYPE_M25P80,
 691             .class_init = m25p80_class_init,
 692             .class_data = (void *)&known_devices[i],
 693         };
 694         type_register(&ti);
 695     }
 696 }
 697
 698 type_init(m25p80_register_types)