hw/char/cadence_uart.c

   1 /*
   2  * Device model for Cadence UART
   3  *
   4  * Copyright (c) 2010 Xilinx Inc.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
   6  * Copyright (c) 2012 PetaLogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *            M.Habib
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "hw/sysbus.h"
  20 #include "sysemu/char.h"
  21 #include "qemu/timer.h"
  22
  23 #ifdef CADENCE_UART_ERR_DEBUG
  24 #define DB_PRINT(...) do { \
  25     fprintf(stderr,  ": %s: ", __func__); \
  26     fprintf(stderr, ## __VA_ARGS__); \
  27     } while (0);
  28 #else
  29     #define DB_PRINT(...)
  30 #endif
  31
  32 #define UART_SR_INTR_RTRIG     0x00000001
  33 #define UART_SR_INTR_REMPTY    0x00000002
  34 #define UART_SR_INTR_RFUL      0x00000004
  35 #define UART_SR_INTR_TEMPTY    0x00000008
  36 #define UART_SR_INTR_TFUL      0x00000010
  37 /* bits fields in CSR that correlate to CISR. If any of these bits are set in
  38  * SR, then the same bit in CISR is set high too */
  39 #define UART_SR_TO_CISR_MASK   0x0000001F
  40
  41 #define UART_INTR_ROVR         0x00000020
  42 #define UART_INTR_FRAME        0x00000040
  43 #define UART_INTR_PARE         0x00000080
  44 #define UART_INTR_TIMEOUT      0x00000100
  45 #define UART_INTR_DMSI         0x00000200
  46
  47 #define UART_SR_RACTIVE    0x00000400
  48 #define UART_SR_TACTIVE    0x00000800
  49 #define UART_SR_FDELT      0x00001000
  50
  51 #define UART_CR_RXRST       0x00000001
  52 #define UART_CR_TXRST       0x00000002
  53 #define UART_CR_RX_EN       0x00000004
  54 #define UART_CR_RX_DIS      0x00000008
  55 #define UART_CR_TX_EN       0x00000010
  56 #define UART_CR_TX_DIS      0x00000020
  57 #define UART_CR_RST_TO      0x00000040
  58 #define UART_CR_STARTBRK    0x00000080
  59 #define UART_CR_STOPBRK     0x00000100
  60
  61 #define UART_MR_CLKS            0x00000001
  62 #define UART_MR_CHRL            0x00000006
  63 #define UART_MR_CHRL_SH         1
  64 #define UART_MR_PAR             0x00000038
  65 #define UART_MR_PAR_SH          3
  66 #define UART_MR_NBSTOP          0x000000C0
  67 #define UART_MR_NBSTOP_SH       6
  68 #define UART_MR_CHMODE          0x00000300
  69 #define UART_MR_CHMODE_SH       8
  70 #define UART_MR_UCLKEN          0x00000400
  71 #define UART_MR_IRMODE          0x00000800
  72
  73 #define UART_DATA_BITS_6       (0x3 << UART_MR_CHRL_SH)
  74 #define UART_DATA_BITS_7       (0x2 << UART_MR_CHRL_SH)
  75 #define UART_PARITY_ODD        (0x1 << UART_MR_PAR_SH)
  76 #define UART_PARITY_EVEN       (0x0 << UART_MR_PAR_SH)
  77 #define UART_STOP_BITS_1       (0x3 << UART_MR_NBSTOP_SH)
  78 #define UART_STOP_BITS_2       (0x2 << UART_MR_NBSTOP_SH)
  79 #define NORMAL_MODE            (0x0 << UART_MR_CHMODE_SH)
  80 #define ECHO_MODE              (0x1 << UART_MR_CHMODE_SH)
  81 #define LOCAL_LOOPBACK         (0x2 << UART_MR_CHMODE_SH)
  82 #define REMOTE_LOOPBACK        (0x3 << UART_MR_CHMODE_SH)
  83
  84 #define RX_FIFO_SIZE           16
  85 #define TX_FIFO_SIZE           16
  86 #define UART_INPUT_CLK         50000000
  87
  88 #define R_CR       (0x00/4)
  89 #define R_MR       (0x04/4)
  90 #define R_IER      (0x08/4)
  91 #define R_IDR      (0x0C/4)
  92 #define R_IMR      (0x10/4)
  93 #define R_CISR     (0x14/4)
  94 #define R_BRGR     (0x18/4)
  95 #define R_RTOR     (0x1C/4)
  96 #define R_RTRIG    (0x20/4)
  97 #define R_MCR      (0x24/4)
  98 #define R_MSR      (0x28/4)
  99 #define R_SR       (0x2C/4)
 100 #define R_TX_RX    (0x30/4)
 101 #define R_BDIV     (0x34/4)
 102 #define R_FDEL     (0x38/4)
 103 #define R_PMIN     (0x3C/4)
 104 #define R_PWID     (0x40/4)
 105 #define R_TTRIG    (0x44/4)
 106
 107 #define R_MAX (R_TTRIG + 1)
 108
 109 #define TYPE_CADENCE_UART "cadence_uart"
 110 #define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART)
 111
 112 typedef struct {
 113     SysBusDevice parent_obj;
 114
 115     MemoryRegion iomem;
 116     uint32_t r[R_MAX];
 117     uint8_t r_fifo[RX_FIFO_SIZE];
 118     uint32_t rx_wpos;
 119     uint32_t rx_count;
 120     uint64_t char_tx_time;
 121     CharDriverState *chr;
 122     qemu_irq irq;
 123     struct QEMUTimer *fifo_trigger_handle;
 124     struct QEMUTimer *tx_time_handle;
 125 } UartState;
 126
 127 static void uart_update_status(UartState *s)
 128 {
 129     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
 130     qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
 131 }
 132
 133 static void fifo_trigger_update(void *opaque)
 134 {
 135     UartState *s = (UartState *)opaque;
 136
 137     s->r[R_CISR] |= UART_INTR_TIMEOUT;
 138
 139     uart_update_status(s);
 140 }
 141
 142 static void uart_tx_redo(UartState *s)
 143 {
 144     uint64_t new_tx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 145
 146     timer_mod(s->tx_time_handle, new_tx_time + s->char_tx_time);
 147
 148     s->r[R_SR] |= UART_SR_INTR_TEMPTY;
 149
 150     uart_update_status(s);
 151 }
 152
 153 static void uart_tx_write(void *opaque)
 154 {
 155     UartState *s = (UartState *)opaque;
 156
 157     uart_tx_redo(s);
 158 }
 159
 160 static void uart_rx_reset(UartState *s)
 161 {
 162     s->rx_wpos = 0;
 163     s->rx_count = 0;
 164     if (s->chr) {
 165         qemu_chr_accept_input(s->chr);
 166     }
 167
 168     s->r[R_SR] |= UART_SR_INTR_REMPTY;
 169     s->r[R_SR] &= ~UART_SR_INTR_RFUL;
 170 }
 171
 172 static void uart_tx_reset(UartState *s)
 173 {
 174     s->r[R_SR] |= UART_SR_INTR_TEMPTY;
 175     s->r[R_SR] &= ~UART_SR_INTR_TFUL;
 176 }
 177
 178 static void uart_send_breaks(UartState *s)
 179 {
 180     int break_enabled = 1;
 181
 182     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 183                                &break_enabled);
 184 }
 185
 186 static void uart_parameters_setup(UartState *s)
 187 {
 188     QEMUSerialSetParams ssp;
 189     unsigned int baud_rate, packet_size;
 190
 191     baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
 192             UART_INPUT_CLK / 8 : UART_INPUT_CLK;
 193
 194     ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
 195     packet_size = 1;
 196
 197     switch (s->r[R_MR] & UART_MR_PAR) {
 198     case UART_PARITY_EVEN:
 199         ssp.parity = 'E';
 200         packet_size++;
 201         break;
 202     case UART_PARITY_ODD:
 203         ssp.parity = 'O';
 204         packet_size++;
 205         break;
 206     default:
 207         ssp.parity = 'N';
 208         break;
 209     }
 210
 211     switch (s->r[R_MR] & UART_MR_CHRL) {
 212     case UART_DATA_BITS_6:
 213         ssp.data_bits = 6;
 214         break;
 215     case UART_DATA_BITS_7:
 216         ssp.data_bits = 7;
 217         break;
 218     default:
 219         ssp.data_bits = 8;
 220         break;
 221     }
 222
 223     switch (s->r[R_MR] & UART_MR_NBSTOP) {
 224     case UART_STOP_BITS_1:
 225         ssp.stop_bits = 1;
 226         break;
 227     default:
 228         ssp.stop_bits = 2;
 229         break;
 230     }
 231
 232     packet_size += ssp.data_bits + ssp.stop_bits;
 233     s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size;
 234     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 235 }
 236
 237 static int uart_can_receive(void *opaque)
 238 {
 239     UartState *s = (UartState *)opaque;
 240
 241     return RX_FIFO_SIZE - s->rx_count;
 242 }
 243
 244 static void uart_ctrl_update(UartState *s)
 245 {
 246     if (s->r[R_CR] & UART_CR_TXRST) {
 247         uart_tx_reset(s);
 248     }
 249
 250     if (s->r[R_CR] & UART_CR_RXRST) {
 251         uart_rx_reset(s);
 252     }
 253
 254     s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
 255
 256     if ((s->r[R_CR] & UART_CR_TX_EN) && !(s->r[R_CR] & UART_CR_TX_DIS)) {
 257             uart_tx_redo(s);
 258     }
 259
 260     if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
 261         uart_send_breaks(s);
 262     }
 263 }
 264
 265 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
 266 {
 267     UartState *s = (UartState *)opaque;
 268     uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 269     int i;
 270
 271     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 272         return;
 273     }
 274
 275     s->r[R_SR] &= ~UART_SR_INTR_REMPTY;
 276
 277     if (s->rx_count == RX_FIFO_SIZE) {
 278         s->r[R_CISR] |= UART_INTR_ROVR;
 279     } else {
 280         for (i = 0; i < size; i++) {
 281             s->r_fifo[s->rx_wpos] = buf[i];
 282             s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
 283             s->rx_count++;
 284
 285             if (s->rx_count == RX_FIFO_SIZE) {
 286                 s->r[R_SR] |= UART_SR_INTR_RFUL;
 287                 break;
 288             }
 289
 290             if (s->rx_count >= s->r[R_RTRIG]) {
 291                 s->r[R_SR] |= UART_SR_INTR_RTRIG;
 292             }
 293         }
 294         timer_mod(s->fifo_trigger_handle, new_rx_time +
 295                                                 (s->char_tx_time * 4));
 296     }
 297     uart_update_status(s);
 298 }
 299
 300 static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size)
 301 {
 302     if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
 303         return;
 304     }
 305
 306     qemu_chr_fe_write_all(s->chr, buf, size);
 307 }
 308
 309 static void uart_receive(void *opaque, const uint8_t *buf, int size)
 310 {
 311     UartState *s = (UartState *)opaque;
 312     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 313
 314     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
 315         uart_write_rx_fifo(opaque, buf, size);
 316     }
 317     if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
 318         uart_write_tx_fifo(s, buf, size);
 319     }
 320 }
 321
 322 static void uart_event(void *opaque, int event)
 323 {
 324     UartState *s = (UartState *)opaque;
 325     uint8_t buf = '\0';
 326
 327     if (event == CHR_EVENT_BREAK) {
 328         uart_write_rx_fifo(opaque, &buf, 1);
 329     }
 330
 331     uart_update_status(s);
 332 }
 333
 334 static void uart_read_rx_fifo(UartState *s, uint32_t *c)
 335 {
 336     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 337         return;
 338     }
 339
 340     s->r[R_SR] &= ~UART_SR_INTR_RFUL;
 341
 342     if (s->rx_count) {
 343         uint32_t rx_rpos =
 344                 (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
 345         *c = s->r_fifo[rx_rpos];
 346         s->rx_count--;
 347
 348         if (!s->rx_count) {
 349             s->r[R_SR] |= UART_SR_INTR_REMPTY;
 350         }
 351         qemu_chr_accept_input(s->chr);
 352     } else {
 353         *c = 0;
 354         s->r[R_SR] |= UART_SR_INTR_REMPTY;
 355     }
 356
 357     if (s->rx_count < s->r[R_RTRIG]) {
 358         s->r[R_SR] &= ~UART_SR_INTR_RTRIG;
 359     }
 360     uart_update_status(s);
 361 }
 362
 363 static void uart_write(void *opaque, hwaddr offset,
 364                           uint64_t value, unsigned size)
 365 {
 366     UartState *s = (UartState *)opaque;
 367
 368     DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
 369     offset >>= 2;
 370     switch (offset) {
 371     case R_IER: /* ier (wts imr) */
 372         s->r[R_IMR] |= value;
 373         break;
 374     case R_IDR: /* idr (wtc imr) */
 375         s->r[R_IMR] &= ~value;
 376         break;
 377     case R_IMR: /* imr (read only) */
 378         break;
 379     case R_CISR: /* cisr (wtc) */
 380         s->r[R_CISR] &= ~value;
 381         break;
 382     case R_TX_RX: /* UARTDR */
 383         switch (s->r[R_MR] & UART_MR_CHMODE) {
 384         case NORMAL_MODE:
 385             uart_write_tx_fifo(s, (uint8_t *) &value, 1);
 386             break;
 387         case LOCAL_LOOPBACK:
 388             uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
 389             break;
 390         }
 391         break;
 392     default:
 393         s->r[offset] = value;
 394     }
 395
 396     switch (offset) {
 397     case R_CR:
 398         uart_ctrl_update(s);
 399         break;
 400     case R_MR:
 401         uart_parameters_setup(s);
 402         break;
 403     }
 404 }
 405
 406 static uint64_t uart_read(void *opaque, hwaddr offset,
 407         unsigned size)
 408 {
 409     UartState *s = (UartState *)opaque;
 410     uint32_t c = 0;
 411
 412     offset >>= 2;
 413     if (offset >= R_MAX) {
 414         c = 0;
 415     } else if (offset == R_TX_RX) {
 416         uart_read_rx_fifo(s, &c);
 417     } else {
 418        c = s->r[offset];
 419     }
 420
 421     DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
 422     return c;
 423 }
 424
 425 static const MemoryRegionOps uart_ops = {
 426     .read = uart_read,
 427     .write = uart_write,
 428     .endianness = DEVICE_NATIVE_ENDIAN,
 429 };
 430
 431 static void cadence_uart_reset(UartState *s)
 432 {
 433     s->r[R_CR] = 0x00000128;
 434     s->r[R_IMR] = 0;
 435     s->r[R_CISR] = 0;
 436     s->r[R_RTRIG] = 0x00000020;
 437     s->r[R_BRGR] = 0x0000000F;
 438     s->r[R_TTRIG] = 0x00000020;
 439
 440     uart_rx_reset(s);
 441     uart_tx_reset(s);
 442
 443     s->rx_count = 0;
 444     s->rx_wpos = 0;
 445 }
 446
 447 static int cadence_uart_init(SysBusDevice *dev)
 448 {
 449     UartState *s = CADENCE_UART(dev);
 450
 451     memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s, "uart", 0x1000);
 452     sysbus_init_mmio(dev, &s->iomem);
 453     sysbus_init_irq(dev, &s->irq);
 454
 455     s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 456             (QEMUTimerCB *)fifo_trigger_update, s);
 457
 458     s->tx_time_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 459             (QEMUTimerCB *)uart_tx_write, s);
 460
 461     s->char_tx_time = (get_ticks_per_sec() / 9600) * 10;
 462
 463     s->chr = qemu_char_get_next_serial();
 464
 465     cadence_uart_reset(s);
 466
 467     if (s->chr) {
 468         qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
 469                               uart_event, s);
 470     }
 471
 472     return 0;
 473 }
 474
 475 static int cadence_uart_post_load(void *opaque, int version_id)
 476 {
 477     UartState *s = opaque;
 478
 479     uart_parameters_setup(s);
 480     uart_update_status(s);
 481     return 0;
 482 }
 483
 484 static const VMStateDescription vmstate_cadence_uart = {
 485     .name = "cadence_uart",
 486     .version_id = 1,
 487     .minimum_version_id = 1,
 488     .minimum_version_id_old = 1,
 489     .post_load = cadence_uart_post_load,
 490     .fields = (VMStateField[]) {
 491         VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
 492         VMSTATE_UINT8_ARRAY(r_fifo, UartState, RX_FIFO_SIZE),
 493         VMSTATE_UINT32(rx_count, UartState),
 494         VMSTATE_UINT32(rx_wpos, UartState),
 495         VMSTATE_TIMER(fifo_trigger_handle, UartState),
 496         VMSTATE_TIMER(tx_time_handle, UartState),
 497         VMSTATE_END_OF_LIST()
 498     }
 499 };
 500
 501 static void cadence_uart_class_init(ObjectClass *klass, void *data)
 502 {
 503     DeviceClass *dc = DEVICE_CLASS(klass);
 504     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 505
 506     sdc->init = cadence_uart_init;
 507     dc->vmsd = &vmstate_cadence_uart;
 508 }
 509
 510 static const TypeInfo cadence_uart_info = {
 511     .name          = TYPE_CADENCE_UART,
 512     .parent        = TYPE_SYS_BUS_DEVICE,
 513     .instance_size = sizeof(UartState),
 514     .class_init    = cadence_uart_class_init,
 515 };
 516
 517 static void cadence_uart_register_types(void)
 518 {
 519     type_register_static(&cadence_uart_info);
 520 }
 521
 522 type_init(cadence_uart_register_types)