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Fix pc migration from qemu <= 1.5
[qemu.git] / hw / char / exynos4210_uart.c
1 /*
2 * Exynos4210 UART Emulation
3 *
4 * Copyright (C) 2011 Samsung Electronics Co Ltd.
5 * Maksim Kozlov, <m.kozlov@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 *
20 */
21
22 #include "hw/sysbus.h"
23 #include "sysemu/sysemu.h"
24 #include "sysemu/char.h"
25
26 #include "hw/arm/exynos4210.h"
27
28 #undef DEBUG_UART
29 #undef DEBUG_UART_EXTEND
30 #undef DEBUG_IRQ
31 #undef DEBUG_Rx_DATA
32 #undef DEBUG_Tx_DATA
33
34 #define DEBUG_UART 0
35 #define DEBUG_UART_EXTEND 0
36 #define DEBUG_IRQ 0
37 #define DEBUG_Rx_DATA 0
38 #define DEBUG_Tx_DATA 0
39
40 #if DEBUG_UART
41 #define PRINT_DEBUG(fmt, args...) \
42 do { \
43 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
44 } while (0)
45
46 #if DEBUG_UART_EXTEND
47 #define PRINT_DEBUG_EXTEND(fmt, args...) \
48 do { \
49 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
50 } while (0)
51 #else
52 #define PRINT_DEBUG_EXTEND(fmt, args...) \
53 do {} while (0)
54 #endif /* EXTEND */
55
56 #else
57 #define PRINT_DEBUG(fmt, args...) \
58 do {} while (0)
59 #define PRINT_DEBUG_EXTEND(fmt, args...) \
60 do {} while (0)
61 #endif
62
63 #define PRINT_ERROR(fmt, args...) \
64 do { \
65 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
66 } while (0)
67
68 /*
69 * Offsets for UART registers relative to SFR base address
70 * for UARTn
71 *
72 */
73 #define ULCON 0x0000 /* Line Control */
74 #define UCON 0x0004 /* Control */
75 #define UFCON 0x0008 /* FIFO Control */
76 #define UMCON 0x000C /* Modem Control */
77 #define UTRSTAT 0x0010 /* Tx/Rx Status */
78 #define UERSTAT 0x0014 /* UART Error Status */
79 #define UFSTAT 0x0018 /* FIFO Status */
80 #define UMSTAT 0x001C /* Modem Status */
81 #define UTXH 0x0020 /* Transmit Buffer */
82 #define URXH 0x0024 /* Receive Buffer */
83 #define UBRDIV 0x0028 /* Baud Rate Divisor */
84 #define UFRACVAL 0x002C /* Divisor Fractional Value */
85 #define UINTP 0x0030 /* Interrupt Pending */
86 #define UINTSP 0x0034 /* Interrupt Source Pending */
87 #define UINTM 0x0038 /* Interrupt Mask */
88
89 /*
90 * for indexing register in the uint32_t array
91 *
92 * 'reg' - register offset (see offsets definitions above)
93 *
94 */
95 #define I_(reg) (reg / sizeof(uint32_t))
96
97 typedef struct Exynos4210UartReg {
98 const char *name; /* the only reason is the debug output */
99 hwaddr offset;
100 uint32_t reset_value;
101 } Exynos4210UartReg;
102
103 static Exynos4210UartReg exynos4210_uart_regs[] = {
104 {"ULCON", ULCON, 0x00000000},
105 {"UCON", UCON, 0x00003000},
106 {"UFCON", UFCON, 0x00000000},
107 {"UMCON", UMCON, 0x00000000},
108 {"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */
109 {"UERSTAT", UERSTAT, 0x00000000}, /* RO */
110 {"UFSTAT", UFSTAT, 0x00000000}, /* RO */
111 {"UMSTAT", UMSTAT, 0x00000000}, /* RO */
112 {"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/
113 {"URXH", URXH, 0x00000000}, /* RO */
114 {"UBRDIV", UBRDIV, 0x00000000},
115 {"UFRACVAL", UFRACVAL, 0x00000000},
116 {"UINTP", UINTP, 0x00000000},
117 {"UINTSP", UINTSP, 0x00000000},
118 {"UINTM", UINTM, 0x00000000},
119 };
120
121 #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C
122
123 /* UART FIFO Control */
124 #define UFCON_FIFO_ENABLE 0x1
125 #define UFCON_Rx_FIFO_RESET 0x2
126 #define UFCON_Tx_FIFO_RESET 0x4
127 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8
128 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
129 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4
130 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
131
132 /* Uart FIFO Status */
133 #define UFSTAT_Rx_FIFO_COUNT 0xff
134 #define UFSTAT_Rx_FIFO_FULL 0x100
135 #define UFSTAT_Rx_FIFO_ERROR 0x200
136 #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16
137 #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
138 #define UFSTAT_Tx_FIFO_FULL_SHIFT 24
139 #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
140
141 /* UART Interrupt Source Pending */
142 #define UINTSP_RXD 0x1 /* Receive interrupt */
143 #define UINTSP_ERROR 0x2 /* Error interrupt */
144 #define UINTSP_TXD 0x4 /* Transmit interrupt */
145 #define UINTSP_MODEM 0x8 /* Modem interrupt */
146
147 /* UART Line Control */
148 #define ULCON_IR_MODE_SHIFT 6
149 #define ULCON_PARITY_SHIFT 3
150 #define ULCON_STOP_BIT_SHIFT 1
151
152 /* UART Tx/Rx Status */
153 #define UTRSTAT_TRANSMITTER_EMPTY 0x4
154 #define UTRSTAT_Tx_BUFFER_EMPTY 0x2
155 #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1
156
157 /* UART Error Status */
158 #define UERSTAT_OVERRUN 0x1
159 #define UERSTAT_PARITY 0x2
160 #define UERSTAT_FRAME 0x4
161 #define UERSTAT_BREAK 0x8
162
163 typedef struct {
164 uint8_t *data;
165 uint32_t sp, rp; /* store and retrieve pointers */
166 uint32_t size;
167 } Exynos4210UartFIFO;
168
169 #define TYPE_EXYNOS4210_UART "exynos4210.uart"
170 #define EXYNOS4210_UART(obj) \
171 OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART)
172
173 typedef struct Exynos4210UartState {
174 SysBusDevice parent_obj;
175
176 MemoryRegion iomem;
177
178 uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
179 Exynos4210UartFIFO rx;
180 Exynos4210UartFIFO tx;
181
182 CharDriverState *chr;
183 qemu_irq irq;
184
185 uint32_t channel;
186
187 } Exynos4210UartState;
188
189
190 #if DEBUG_UART
191 /* Used only for debugging inside PRINT_DEBUG_... macros */
192 static const char *exynos4210_uart_regname(hwaddr offset)
193 {
194
195 int regs_number = sizeof(exynos4210_uart_regs) / sizeof(Exynos4210UartReg);
196 int i;
197
198 for (i = 0; i < regs_number; i++) {
199 if (offset == exynos4210_uart_regs[i].offset) {
200 return exynos4210_uart_regs[i].name;
201 }
202 }
203
204 return NULL;
205 }
206 #endif
207
208
209 static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch)
210 {
211 q->data[q->sp] = ch;
212 q->sp = (q->sp + 1) % q->size;
213 }
214
215 static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
216 {
217 uint8_t ret = q->data[q->rp];
218 q->rp = (q->rp + 1) % q->size;
219 return ret;
220 }
221
222 static int fifo_elements_number(Exynos4210UartFIFO *q)
223 {
224 if (q->sp < q->rp) {
225 return q->size - q->rp + q->sp;
226 }
227
228 return q->sp - q->rp;
229 }
230
231 static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
232 {
233 return q->size - fifo_elements_number(q);
234 }
235
236 static void fifo_reset(Exynos4210UartFIFO *q)
237 {
238 if (q->data != NULL) {
239 g_free(q->data);
240 q->data = NULL;
241 }
242
243 q->data = (uint8_t *)g_malloc0(q->size);
244
245 q->sp = 0;
246 q->rp = 0;
247 }
248
249 static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
250 {
251 uint32_t level = 0;
252 uint32_t reg;
253
254 reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >>
255 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;
256
257 switch (s->channel) {
258 case 0:
259 level = reg * 32;
260 break;
261 case 1:
262 case 4:
263 level = reg * 8;
264 break;
265 case 2:
266 case 3:
267 level = reg * 2;
268 break;
269 default:
270 level = 0;
271 PRINT_ERROR("Wrong UART channel number: %d\n", s->channel);
272 }
273
274 return level;
275 }
276
277 static void exynos4210_uart_update_irq(Exynos4210UartState *s)
278 {
279 /*
280 * The Tx interrupt is always requested if the number of data in the
281 * transmit FIFO is smaller than the trigger level.
282 */
283 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
284
285 uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >>
286 UFSTAT_Tx_FIFO_COUNT_SHIFT;
287
288 if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
289 s->reg[I_(UINTSP)] |= UINTSP_TXD;
290 }
291 }
292
293 s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)];
294
295 if (s->reg[I_(UINTP)]) {
296 qemu_irq_raise(s->irq);
297
298 #if DEBUG_IRQ
299 fprintf(stderr, "UART%d: IRQ has been raised: %08x\n",
300 s->channel, s->reg[I_(UINTP)]);
301 #endif
302
303 } else {
304 qemu_irq_lower(s->irq);
305 }
306 }
307
308 static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
309 {
310 int speed, parity, data_bits, stop_bits, frame_size;
311 QEMUSerialSetParams ssp;
312 uint64_t uclk_rate;
313
314 if (s->reg[I_(UBRDIV)] == 0) {
315 return;
316 }
317
318 frame_size = 1; /* start bit */
319 if (s->reg[I_(ULCON)] & 0x20) {
320 frame_size++; /* parity bit */
321 if (s->reg[I_(ULCON)] & 0x28) {
322 parity = 'E';
323 } else {
324 parity = 'O';
325 }
326 } else {
327 parity = 'N';
328 }
329
330 if (s->reg[I_(ULCON)] & 0x4) {
331 stop_bits = 2;
332 } else {
333 stop_bits = 1;
334 }
335
336 data_bits = (s->reg[I_(ULCON)] & 0x3) + 5;
337
338 frame_size += data_bits + stop_bits;
339
340 uclk_rate = 24000000;
341
342 speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) +
343 (s->reg[I_(UFRACVAL)] & 0x7) + 16);
344
345 ssp.speed = speed;
346 ssp.parity = parity;
347 ssp.data_bits = data_bits;
348 ssp.stop_bits = stop_bits;
349
350 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
351
352 PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",
353 s->channel, speed, parity, data_bits, stop_bits);
354 }
355
356 static void exynos4210_uart_write(void *opaque, hwaddr offset,
357 uint64_t val, unsigned size)
358 {
359 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
360 uint8_t ch;
361
362 PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel,
363 offset, exynos4210_uart_regname(offset), (long long unsigned int)val);
364
365 switch (offset) {
366 case ULCON:
367 case UBRDIV:
368 case UFRACVAL:
369 s->reg[I_(offset)] = val;
370 exynos4210_uart_update_parameters(s);
371 break;
372 case UFCON:
373 s->reg[I_(UFCON)] = val;
374 if (val & UFCON_Rx_FIFO_RESET) {
375 fifo_reset(&s->rx);
376 s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET;
377 PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel);
378 }
379 if (val & UFCON_Tx_FIFO_RESET) {
380 fifo_reset(&s->tx);
381 s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET;
382 PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel);
383 }
384 break;
385
386 case UTXH:
387 if (s->chr) {
388 s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
389 UTRSTAT_Tx_BUFFER_EMPTY);
390 ch = (uint8_t)val;
391 qemu_chr_fe_write(s->chr, &ch, 1);
392 #if DEBUG_Tx_DATA
393 fprintf(stderr, "%c", ch);
394 #endif
395 s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY |
396 UTRSTAT_Tx_BUFFER_EMPTY;
397 s->reg[I_(UINTSP)] |= UINTSP_TXD;
398 exynos4210_uart_update_irq(s);
399 }
400 break;
401
402 case UINTP:
403 s->reg[I_(UINTP)] &= ~val;
404 s->reg[I_(UINTSP)] &= ~val;
405 PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n",
406 s->channel, offset, s->reg[I_(UINTP)]);
407 exynos4210_uart_update_irq(s);
408 break;
409 case UTRSTAT:
410 case UERSTAT:
411 case UFSTAT:
412 case UMSTAT:
413 case URXH:
414 PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n",
415 s->channel, exynos4210_uart_regname(offset), offset);
416 break;
417 case UINTSP:
418 s->reg[I_(UINTSP)] &= ~val;
419 break;
420 case UINTM:
421 s->reg[I_(UINTM)] = val;
422 exynos4210_uart_update_irq(s);
423 break;
424 case UCON:
425 case UMCON:
426 default:
427 s->reg[I_(offset)] = val;
428 break;
429 }
430 }
431 static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
432 unsigned size)
433 {
434 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
435 uint32_t res;
436
437 switch (offset) {
438 case UERSTAT: /* Read Only */
439 res = s->reg[I_(UERSTAT)];
440 s->reg[I_(UERSTAT)] = 0;
441 return res;
442 case UFSTAT: /* Read Only */
443 s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff;
444 if (fifo_empty_elements_number(&s->rx) == 0) {
445 s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL;
446 s->reg[I_(UFSTAT)] &= ~0xff;
447 }
448 return s->reg[I_(UFSTAT)];
449 case URXH:
450 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
451 if (fifo_elements_number(&s->rx)) {
452 res = fifo_retrieve(&s->rx);
453 #if DEBUG_Rx_DATA
454 fprintf(stderr, "%c", res);
455 #endif
456 if (!fifo_elements_number(&s->rx)) {
457 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
458 } else {
459 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
460 }
461 } else {
462 s->reg[I_(UINTSP)] |= UINTSP_ERROR;
463 exynos4210_uart_update_irq(s);
464 res = 0;
465 }
466 } else {
467 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
468 res = s->reg[I_(URXH)];
469 }
470 return res;
471 case UTXH:
472 PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n",
473 s->channel, exynos4210_uart_regname(offset), offset);
474 break;
475 default:
476 return s->reg[I_(offset)];
477 }
478
479 return 0;
480 }
481
482 static const MemoryRegionOps exynos4210_uart_ops = {
483 .read = exynos4210_uart_read,
484 .write = exynos4210_uart_write,
485 .endianness = DEVICE_NATIVE_ENDIAN,
486 .valid = {
487 .max_access_size = 4,
488 .unaligned = false
489 },
490 };
491
492 static int exynos4210_uart_can_receive(void *opaque)
493 {
494 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
495
496 return fifo_empty_elements_number(&s->rx);
497 }
498
499
500 static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
501 {
502 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
503 int i;
504
505 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
506 if (fifo_empty_elements_number(&s->rx) < size) {
507 for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) {
508 fifo_store(&s->rx, buf[i]);
509 }
510 s->reg[I_(UINTSP)] |= UINTSP_ERROR;
511 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
512 } else {
513 for (i = 0; i < size; i++) {
514 fifo_store(&s->rx, buf[i]);
515 }
516 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
517 }
518 /* XXX: Around here we maybe should check Rx trigger level */
519 s->reg[I_(UINTSP)] |= UINTSP_RXD;
520 } else {
521 s->reg[I_(URXH)] = buf[0];
522 s->reg[I_(UINTSP)] |= UINTSP_RXD;
523 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
524 }
525
526 exynos4210_uart_update_irq(s);
527 }
528
529
530 static void exynos4210_uart_event(void *opaque, int event)
531 {
532 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
533
534 if (event == CHR_EVENT_BREAK) {
535 /* When the RxDn is held in logic 0, then a null byte is pushed into the
536 * fifo */
537 fifo_store(&s->rx, '\0');
538 s->reg[I_(UERSTAT)] |= UERSTAT_BREAK;
539 exynos4210_uart_update_irq(s);
540 }
541 }
542
543
544 static void exynos4210_uart_reset(DeviceState *dev)
545 {
546 Exynos4210UartState *s = EXYNOS4210_UART(dev);
547 int regs_number = sizeof(exynos4210_uart_regs)/sizeof(Exynos4210UartReg);
548 int i;
549
550 for (i = 0; i < regs_number; i++) {
551 s->reg[I_(exynos4210_uart_regs[i].offset)] =
552 exynos4210_uart_regs[i].reset_value;
553 }
554
555 fifo_reset(&s->rx);
556 fifo_reset(&s->tx);
557
558 PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size);
559 }
560
561 static const VMStateDescription vmstate_exynos4210_uart_fifo = {
562 .name = "exynos4210.uart.fifo",
563 .version_id = 1,
564 .minimum_version_id = 1,
565 .minimum_version_id_old = 1,
566 .fields = (VMStateField[]) {
567 VMSTATE_UINT32(sp, Exynos4210UartFIFO),
568 VMSTATE_UINT32(rp, Exynos4210UartFIFO),
569 VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, 0, size),
570 VMSTATE_END_OF_LIST()
571 }
572 };
573
574 static const VMStateDescription vmstate_exynos4210_uart = {
575 .name = "exynos4210.uart",
576 .version_id = 1,
577 .minimum_version_id = 1,
578 .minimum_version_id_old = 1,
579 .fields = (VMStateField[]) {
580 VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
581 vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
582 VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,
583 EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
584 VMSTATE_END_OF_LIST()
585 }
586 };
587
588 DeviceState *exynos4210_uart_create(hwaddr addr,
589 int fifo_size,
590 int channel,
591 CharDriverState *chr,
592 qemu_irq irq)
593 {
594 DeviceState *dev;
595 SysBusDevice *bus;
596
597 const char chr_name[] = "serial";
598 char label[ARRAY_SIZE(chr_name) + 1];
599
600 dev = qdev_create(NULL, TYPE_EXYNOS4210_UART);
601
602 if (!chr) {
603 if (channel >= MAX_SERIAL_PORTS) {
604 hw_error("Only %d serial ports are supported by QEMU.\n",
605 MAX_SERIAL_PORTS);
606 }
607 chr = serial_hds[channel];
608 if (!chr) {
609 snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel);
610 chr = qemu_chr_new(label, "null", NULL);
611 if (!(chr)) {
612 hw_error("Can't assign serial port to UART%d.\n", channel);
613 }
614 }
615 }
616
617 qdev_prop_set_chr(dev, "chardev", chr);
618 qdev_prop_set_uint32(dev, "channel", channel);
619 qdev_prop_set_uint32(dev, "rx-size", fifo_size);
620 qdev_prop_set_uint32(dev, "tx-size", fifo_size);
621
622 bus = SYS_BUS_DEVICE(dev);
623 qdev_init_nofail(dev);
624 if (addr != (hwaddr)-1) {
625 sysbus_mmio_map(bus, 0, addr);
626 }
627 sysbus_connect_irq(bus, 0, irq);
628
629 return dev;
630 }
631
632 static int exynos4210_uart_init(SysBusDevice *dev)
633 {
634 Exynos4210UartState *s = EXYNOS4210_UART(dev);
635
636 /* memory mapping */
637 memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_uart_ops, s,
638 "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);
639 sysbus_init_mmio(dev, &s->iomem);
640
641 sysbus_init_irq(dev, &s->irq);
642
643 qemu_chr_add_handlers(s->chr, exynos4210_uart_can_receive,
644 exynos4210_uart_receive, exynos4210_uart_event, s);
645
646 return 0;
647 }
648
649 static Property exynos4210_uart_properties[] = {
650 DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr),
651 DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0),
652 DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16),
653 DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16),
654 DEFINE_PROP_END_OF_LIST(),
655 };
656
657 static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
658 {
659 DeviceClass *dc = DEVICE_CLASS(klass);
660 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
661
662 k->init = exynos4210_uart_init;
663 dc->reset = exynos4210_uart_reset;
664 dc->props = exynos4210_uart_properties;
665 dc->vmsd = &vmstate_exynos4210_uart;
666 }
667
668 static const TypeInfo exynos4210_uart_info = {
669 .name = TYPE_EXYNOS4210_UART,
670 .parent = TYPE_SYS_BUS_DEVICE,
671 .instance_size = sizeof(Exynos4210UartState),
672 .class_init = exynos4210_uart_class_init,
673 };
674
675 static void exynos4210_uart_register(void)
676 {
677 type_register_static(&exynos4210_uart_info);
678 }
679
680 type_init(exynos4210_uart_register)
Qemu copy for testing