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cirrus_vga: Add a VGACommonState local var to cirrus_vga_ioport_{read, write}
[qemu.git] / hw / cirrus_vga.c
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #include "kvm.h"
35
36 /*
37 * TODO:
38 * - destination write mask support not complete (bits 5..7)
39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
43 //#define DEBUG_CIRRUS
44 //#define DEBUG_BITBLT
45
46 /***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
52 // ID
53 #define CIRRUS_ID_CLGD5422 (0x23<<2)
54 #define CIRRUS_ID_CLGD5426 (0x24<<2)
55 #define CIRRUS_ID_CLGD5424 (0x25<<2)
56 #define CIRRUS_ID_CLGD5428 (0x26<<2)
57 #define CIRRUS_ID_CLGD5430 (0x28<<2)
58 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
59 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
60 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
61
62 // sequencer 0x07
63 #define CIRRUS_SR7_BPP_VGA 0x00
64 #define CIRRUS_SR7_BPP_SVGA 0x01
65 #define CIRRUS_SR7_BPP_MASK 0x0e
66 #define CIRRUS_SR7_BPP_8 0x00
67 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
68 #define CIRRUS_SR7_BPP_24 0x04
69 #define CIRRUS_SR7_BPP_16 0x06
70 #define CIRRUS_SR7_BPP_32 0x08
71 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
72
73 // sequencer 0x0f
74 #define CIRRUS_MEMSIZE_512k 0x08
75 #define CIRRUS_MEMSIZE_1M 0x10
76 #define CIRRUS_MEMSIZE_2M 0x18
77 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
78
79 // sequencer 0x12
80 #define CIRRUS_CURSOR_SHOW 0x01
81 #define CIRRUS_CURSOR_HIDDENPEL 0x02
82 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
83
84 // sequencer 0x17
85 #define CIRRUS_BUSTYPE_VLBFAST 0x10
86 #define CIRRUS_BUSTYPE_PCI 0x20
87 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
88 #define CIRRUS_BUSTYPE_ISA 0x38
89 #define CIRRUS_MMIO_ENABLE 0x04
90 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
91 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
92
93 // control 0x0b
94 #define CIRRUS_BANKING_DUAL 0x01
95 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
96
97 // control 0x30
98 #define CIRRUS_BLTMODE_BACKWARDS 0x01
99 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
100 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
101 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
102 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
103 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
104 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
105 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
106 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
107 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
108 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
109
110 // control 0x31
111 #define CIRRUS_BLT_BUSY 0x01
112 #define CIRRUS_BLT_START 0x02
113 #define CIRRUS_BLT_RESET 0x04
114 #define CIRRUS_BLT_FIFOUSED 0x10
115 #define CIRRUS_BLT_AUTOSTART 0x80
116
117 // control 0x32
118 #define CIRRUS_ROP_0 0x00
119 #define CIRRUS_ROP_SRC_AND_DST 0x05
120 #define CIRRUS_ROP_NOP 0x06
121 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
122 #define CIRRUS_ROP_NOTDST 0x0b
123 #define CIRRUS_ROP_SRC 0x0d
124 #define CIRRUS_ROP_1 0x0e
125 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
126 #define CIRRUS_ROP_SRC_XOR_DST 0x59
127 #define CIRRUS_ROP_SRC_OR_DST 0x6d
128 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
129 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
130 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
131 #define CIRRUS_ROP_NOTSRC 0xd0
132 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
133 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
134
135 #define CIRRUS_ROP_NOP_INDEX 2
136 #define CIRRUS_ROP_SRC_INDEX 5
137
138 // control 0x33
139 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
140 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
141 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
142
143 // memory-mapped IO
144 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
145 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
146 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
147 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
148 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
149 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
150 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
151 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
152 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
153 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
154 #define CIRRUS_MMIO_BLTROP 0x1a // byte
155 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
156 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
157 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
158 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
159 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
160 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
161 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
162 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
166 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
167 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
168 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
169 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
170 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
171 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
172 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
173
174 // PCI 0x04: command(word), 0x06(word): status
175 #define PCI_COMMAND_IOACCESS 0x0001
176 #define PCI_COMMAND_MEMACCESS 0x0002
177 #define PCI_COMMAND_BUSMASTER 0x0004
178 #define PCI_COMMAND_SPECIALCYCLE 0x0008
179 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
180 #define PCI_COMMAND_PALETTESNOOPING 0x0020
181 #define PCI_COMMAND_PARITYDETECTION 0x0040
182 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
183 #define PCI_COMMAND_SERR 0x0100
184 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
185 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
186 #define PCI_CLASS_BASE_DISPLAY 0x03
187 // PCI 0x08, 0x00ff0000
188 #define PCI_CLASS_SUB_VGA 0x00
189 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
190 // 0x10-0x3f (headertype 00h)
191 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
192 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
193 #define PCI_MAP_MEM 0x0
194 #define PCI_MAP_IO 0x1
195 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
196 #define PCI_MAP_IO_ADDR_MASK (~0x3)
197 #define PCI_MAP_MEMFLAGS_32BIT 0x0
198 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
199 #define PCI_MAP_MEMFLAGS_64BIT 0x4
200 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
201 // PCI 0x28: cardbus CIS pointer
202 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
203 // PCI 0x30: expansion ROM base address
204 #define PCI_ROMBIOS_ENABLED 0x1
205 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
206 // PCI 0x38: reserved
207 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
208
209 #define CIRRUS_PNPMMIO_SIZE 0x1000
210
211
212 /* I/O and memory hook */
213 #define CIRRUS_HOOK_NOT_HANDLED 0
214 #define CIRRUS_HOOK_HANDLED 1
215
216 #define ABS(a) ((signed)(a) > 0 ? a : -a)
217
218 #define BLTUNSAFE(s) \
219 ( \
220 ( /* check dst is within bounds */ \
221 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
222 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
223 (s)->vga.vram_size \
224 ) || \
225 ( /* check src is within bounds */ \
226 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
227 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
228 (s)->vga.vram_size \
229 ) \
230 )
231
232 struct CirrusVGAState;
233 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
234 uint8_t * dst, const uint8_t * src,
235 int dstpitch, int srcpitch,
236 int bltwidth, int bltheight);
237 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
238 uint8_t *dst, int dst_pitch, int width, int height);
239
240 typedef struct CirrusVGAState {
241 VGACommonState vga;
242
243 int cirrus_linear_io_addr;
244 int cirrus_linear_bitblt_io_addr;
245 int cirrus_mmio_io_addr;
246 uint32_t cirrus_addr_mask;
247 uint32_t linear_mmio_mask;
248 uint8_t cirrus_shadow_gr0;
249 uint8_t cirrus_shadow_gr1;
250 uint8_t cirrus_hidden_dac_lockindex;
251 uint8_t cirrus_hidden_dac_data;
252 uint32_t cirrus_bank_base[2];
253 uint32_t cirrus_bank_limit[2];
254 uint8_t cirrus_hidden_palette[48];
255 uint32_t hw_cursor_x;
256 uint32_t hw_cursor_y;
257 int cirrus_blt_pixelwidth;
258 int cirrus_blt_width;
259 int cirrus_blt_height;
260 int cirrus_blt_dstpitch;
261 int cirrus_blt_srcpitch;
262 uint32_t cirrus_blt_fgcol;
263 uint32_t cirrus_blt_bgcol;
264 uint32_t cirrus_blt_dstaddr;
265 uint32_t cirrus_blt_srcaddr;
266 uint8_t cirrus_blt_mode;
267 uint8_t cirrus_blt_modeext;
268 cirrus_bitblt_rop_t cirrus_rop;
269 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
270 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
271 uint8_t *cirrus_srcptr;
272 uint8_t *cirrus_srcptr_end;
273 uint32_t cirrus_srccounter;
274 /* hwcursor display state */
275 int last_hw_cursor_size;
276 int last_hw_cursor_x;
277 int last_hw_cursor_y;
278 int last_hw_cursor_y_start;
279 int last_hw_cursor_y_end;
280 int real_vram_size; /* XXX: suppress that */
281 int device_id;
282 int bustype;
283 } CirrusVGAState;
284
285 typedef struct PCICirrusVGAState {
286 PCIDevice dev;
287 CirrusVGAState cirrus_vga;
288 } PCICirrusVGAState;
289
290 static uint8_t rop_to_index[256];
291
292 /***************************************
293 *
294 * prototypes.
295 *
296 ***************************************/
297
298
299 static void cirrus_bitblt_reset(CirrusVGAState *s);
300 static void cirrus_update_memory_access(CirrusVGAState *s);
301
302 /***************************************
303 *
304 * raster operations
305 *
306 ***************************************/
307
308 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
309 uint8_t *dst,const uint8_t *src,
310 int dstpitch,int srcpitch,
311 int bltwidth,int bltheight)
312 {
313 }
314
315 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
316 uint8_t *dst,
317 int dstpitch, int bltwidth,int bltheight)
318 {
319 }
320
321 #define ROP_NAME 0
322 #define ROP_OP(d, s) d = 0
323 #include "cirrus_vga_rop.h"
324
325 #define ROP_NAME src_and_dst
326 #define ROP_OP(d, s) d = (s) & (d)
327 #include "cirrus_vga_rop.h"
328
329 #define ROP_NAME src_and_notdst
330 #define ROP_OP(d, s) d = (s) & (~(d))
331 #include "cirrus_vga_rop.h"
332
333 #define ROP_NAME notdst
334 #define ROP_OP(d, s) d = ~(d)
335 #include "cirrus_vga_rop.h"
336
337 #define ROP_NAME src
338 #define ROP_OP(d, s) d = s
339 #include "cirrus_vga_rop.h"
340
341 #define ROP_NAME 1
342 #define ROP_OP(d, s) d = ~0
343 #include "cirrus_vga_rop.h"
344
345 #define ROP_NAME notsrc_and_dst
346 #define ROP_OP(d, s) d = (~(s)) & (d)
347 #include "cirrus_vga_rop.h"
348
349 #define ROP_NAME src_xor_dst
350 #define ROP_OP(d, s) d = (s) ^ (d)
351 #include "cirrus_vga_rop.h"
352
353 #define ROP_NAME src_or_dst
354 #define ROP_OP(d, s) d = (s) | (d)
355 #include "cirrus_vga_rop.h"
356
357 #define ROP_NAME notsrc_or_notdst
358 #define ROP_OP(d, s) d = (~(s)) | (~(d))
359 #include "cirrus_vga_rop.h"
360
361 #define ROP_NAME src_notxor_dst
362 #define ROP_OP(d, s) d = ~((s) ^ (d))
363 #include "cirrus_vga_rop.h"
364
365 #define ROP_NAME src_or_notdst
366 #define ROP_OP(d, s) d = (s) | (~(d))
367 #include "cirrus_vga_rop.h"
368
369 #define ROP_NAME notsrc
370 #define ROP_OP(d, s) d = (~(s))
371 #include "cirrus_vga_rop.h"
372
373 #define ROP_NAME notsrc_or_dst
374 #define ROP_OP(d, s) d = (~(s)) | (d)
375 #include "cirrus_vga_rop.h"
376
377 #define ROP_NAME notsrc_and_notdst
378 #define ROP_OP(d, s) d = (~(s)) & (~(d))
379 #include "cirrus_vga_rop.h"
380
381 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
382 cirrus_bitblt_rop_fwd_0,
383 cirrus_bitblt_rop_fwd_src_and_dst,
384 cirrus_bitblt_rop_nop,
385 cirrus_bitblt_rop_fwd_src_and_notdst,
386 cirrus_bitblt_rop_fwd_notdst,
387 cirrus_bitblt_rop_fwd_src,
388 cirrus_bitblt_rop_fwd_1,
389 cirrus_bitblt_rop_fwd_notsrc_and_dst,
390 cirrus_bitblt_rop_fwd_src_xor_dst,
391 cirrus_bitblt_rop_fwd_src_or_dst,
392 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
393 cirrus_bitblt_rop_fwd_src_notxor_dst,
394 cirrus_bitblt_rop_fwd_src_or_notdst,
395 cirrus_bitblt_rop_fwd_notsrc,
396 cirrus_bitblt_rop_fwd_notsrc_or_dst,
397 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
398 };
399
400 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
401 cirrus_bitblt_rop_bkwd_0,
402 cirrus_bitblt_rop_bkwd_src_and_dst,
403 cirrus_bitblt_rop_nop,
404 cirrus_bitblt_rop_bkwd_src_and_notdst,
405 cirrus_bitblt_rop_bkwd_notdst,
406 cirrus_bitblt_rop_bkwd_src,
407 cirrus_bitblt_rop_bkwd_1,
408 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
409 cirrus_bitblt_rop_bkwd_src_xor_dst,
410 cirrus_bitblt_rop_bkwd_src_or_dst,
411 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
412 cirrus_bitblt_rop_bkwd_src_notxor_dst,
413 cirrus_bitblt_rop_bkwd_src_or_notdst,
414 cirrus_bitblt_rop_bkwd_notsrc,
415 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
416 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
417 };
418
419 #define TRANSP_ROP(name) {\
420 name ## _8,\
421 name ## _16,\
422 }
423 #define TRANSP_NOP(func) {\
424 func,\
425 func,\
426 }
427
428 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
429 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
430 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
431 TRANSP_NOP(cirrus_bitblt_rop_nop),
432 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
433 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
434 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
435 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
436 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
437 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
445 };
446
447 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
448 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
449 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
450 TRANSP_NOP(cirrus_bitblt_rop_nop),
451 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
452 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
453 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
454 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
455 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
456 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
464 };
465
466 #define ROP2(name) {\
467 name ## _8,\
468 name ## _16,\
469 name ## _24,\
470 name ## _32,\
471 }
472
473 #define ROP_NOP2(func) {\
474 func,\
475 func,\
476 func,\
477 func,\
478 }
479
480 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
481 ROP2(cirrus_patternfill_0),
482 ROP2(cirrus_patternfill_src_and_dst),
483 ROP_NOP2(cirrus_bitblt_rop_nop),
484 ROP2(cirrus_patternfill_src_and_notdst),
485 ROP2(cirrus_patternfill_notdst),
486 ROP2(cirrus_patternfill_src),
487 ROP2(cirrus_patternfill_1),
488 ROP2(cirrus_patternfill_notsrc_and_dst),
489 ROP2(cirrus_patternfill_src_xor_dst),
490 ROP2(cirrus_patternfill_src_or_dst),
491 ROP2(cirrus_patternfill_notsrc_or_notdst),
492 ROP2(cirrus_patternfill_src_notxor_dst),
493 ROP2(cirrus_patternfill_src_or_notdst),
494 ROP2(cirrus_patternfill_notsrc),
495 ROP2(cirrus_patternfill_notsrc_or_dst),
496 ROP2(cirrus_patternfill_notsrc_and_notdst),
497 };
498
499 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
500 ROP2(cirrus_colorexpand_transp_0),
501 ROP2(cirrus_colorexpand_transp_src_and_dst),
502 ROP_NOP2(cirrus_bitblt_rop_nop),
503 ROP2(cirrus_colorexpand_transp_src_and_notdst),
504 ROP2(cirrus_colorexpand_transp_notdst),
505 ROP2(cirrus_colorexpand_transp_src),
506 ROP2(cirrus_colorexpand_transp_1),
507 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
508 ROP2(cirrus_colorexpand_transp_src_xor_dst),
509 ROP2(cirrus_colorexpand_transp_src_or_dst),
510 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
511 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
512 ROP2(cirrus_colorexpand_transp_src_or_notdst),
513 ROP2(cirrus_colorexpand_transp_notsrc),
514 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
515 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
516 };
517
518 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
519 ROP2(cirrus_colorexpand_0),
520 ROP2(cirrus_colorexpand_src_and_dst),
521 ROP_NOP2(cirrus_bitblt_rop_nop),
522 ROP2(cirrus_colorexpand_src_and_notdst),
523 ROP2(cirrus_colorexpand_notdst),
524 ROP2(cirrus_colorexpand_src),
525 ROP2(cirrus_colorexpand_1),
526 ROP2(cirrus_colorexpand_notsrc_and_dst),
527 ROP2(cirrus_colorexpand_src_xor_dst),
528 ROP2(cirrus_colorexpand_src_or_dst),
529 ROP2(cirrus_colorexpand_notsrc_or_notdst),
530 ROP2(cirrus_colorexpand_src_notxor_dst),
531 ROP2(cirrus_colorexpand_src_or_notdst),
532 ROP2(cirrus_colorexpand_notsrc),
533 ROP2(cirrus_colorexpand_notsrc_or_dst),
534 ROP2(cirrus_colorexpand_notsrc_and_notdst),
535 };
536
537 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
538 ROP2(cirrus_colorexpand_pattern_transp_0),
539 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
540 ROP_NOP2(cirrus_bitblt_rop_nop),
541 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
542 ROP2(cirrus_colorexpand_pattern_transp_notdst),
543 ROP2(cirrus_colorexpand_pattern_transp_src),
544 ROP2(cirrus_colorexpand_pattern_transp_1),
545 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
546 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
547 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
548 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
549 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
550 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
551 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
552 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
553 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
554 };
555
556 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
557 ROP2(cirrus_colorexpand_pattern_0),
558 ROP2(cirrus_colorexpand_pattern_src_and_dst),
559 ROP_NOP2(cirrus_bitblt_rop_nop),
560 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
561 ROP2(cirrus_colorexpand_pattern_notdst),
562 ROP2(cirrus_colorexpand_pattern_src),
563 ROP2(cirrus_colorexpand_pattern_1),
564 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
565 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
566 ROP2(cirrus_colorexpand_pattern_src_or_dst),
567 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
568 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
569 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
570 ROP2(cirrus_colorexpand_pattern_notsrc),
571 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
572 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
573 };
574
575 static const cirrus_fill_t cirrus_fill[16][4] = {
576 ROP2(cirrus_fill_0),
577 ROP2(cirrus_fill_src_and_dst),
578 ROP_NOP2(cirrus_bitblt_fill_nop),
579 ROP2(cirrus_fill_src_and_notdst),
580 ROP2(cirrus_fill_notdst),
581 ROP2(cirrus_fill_src),
582 ROP2(cirrus_fill_1),
583 ROP2(cirrus_fill_notsrc_and_dst),
584 ROP2(cirrus_fill_src_xor_dst),
585 ROP2(cirrus_fill_src_or_dst),
586 ROP2(cirrus_fill_notsrc_or_notdst),
587 ROP2(cirrus_fill_src_notxor_dst),
588 ROP2(cirrus_fill_src_or_notdst),
589 ROP2(cirrus_fill_notsrc),
590 ROP2(cirrus_fill_notsrc_or_dst),
591 ROP2(cirrus_fill_notsrc_and_notdst),
592 };
593
594 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
595 {
596 unsigned int color;
597 switch (s->cirrus_blt_pixelwidth) {
598 case 1:
599 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
600 break;
601 case 2:
602 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
603 s->cirrus_blt_fgcol = le16_to_cpu(color);
604 break;
605 case 3:
606 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
607 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
608 break;
609 default:
610 case 4:
611 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
612 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
613 s->cirrus_blt_fgcol = le32_to_cpu(color);
614 break;
615 }
616 }
617
618 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
619 {
620 unsigned int color;
621 switch (s->cirrus_blt_pixelwidth) {
622 case 1:
623 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
624 break;
625 case 2:
626 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
627 s->cirrus_blt_bgcol = le16_to_cpu(color);
628 break;
629 case 3:
630 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
631 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
632 break;
633 default:
634 case 4:
635 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
636 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
637 s->cirrus_blt_bgcol = le32_to_cpu(color);
638 break;
639 }
640 }
641
642 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
643 int off_pitch, int bytesperline,
644 int lines)
645 {
646 int y;
647 int off_cur;
648 int off_cur_end;
649
650 for (y = 0; y < lines; y++) {
651 off_cur = off_begin;
652 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
653 off_cur &= TARGET_PAGE_MASK;
654 while (off_cur < off_cur_end) {
655 cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur);
656 off_cur += TARGET_PAGE_SIZE;
657 }
658 off_begin += off_pitch;
659 }
660 }
661
662 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
663 const uint8_t * src)
664 {
665 uint8_t *dst;
666
667 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
668
669 if (BLTUNSAFE(s))
670 return 0;
671
672 (*s->cirrus_rop) (s, dst, src,
673 s->cirrus_blt_dstpitch, 0,
674 s->cirrus_blt_width, s->cirrus_blt_height);
675 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
676 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
677 s->cirrus_blt_height);
678 return 1;
679 }
680
681 /* fill */
682
683 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
684 {
685 cirrus_fill_t rop_func;
686
687 if (BLTUNSAFE(s))
688 return 0;
689 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
690 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
691 s->cirrus_blt_dstpitch,
692 s->cirrus_blt_width, s->cirrus_blt_height);
693 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
694 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
695 s->cirrus_blt_height);
696 cirrus_bitblt_reset(s);
697 return 1;
698 }
699
700 /***************************************
701 *
702 * bitblt (video-to-video)
703 *
704 ***************************************/
705
706 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
707 {
708 return cirrus_bitblt_common_patterncopy(s,
709 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
710 s->cirrus_addr_mask));
711 }
712
713 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
714 {
715 int sx, sy;
716 int dx, dy;
717 int width, height;
718 int depth;
719 int notify = 0;
720
721 depth = s->vga.get_bpp(&s->vga) / 8;
722 s->vga.get_resolution(&s->vga, &width, &height);
723
724 /* extra x, y */
725 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
726 sy = (src / ABS(s->cirrus_blt_srcpitch));
727 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
728 dy = (dst / ABS(s->cirrus_blt_dstpitch));
729
730 /* normalize width */
731 w /= depth;
732
733 /* if we're doing a backward copy, we have to adjust
734 our x/y to be the upper left corner (instead of the lower
735 right corner) */
736 if (s->cirrus_blt_dstpitch < 0) {
737 sx -= (s->cirrus_blt_width / depth) - 1;
738 dx -= (s->cirrus_blt_width / depth) - 1;
739 sy -= s->cirrus_blt_height - 1;
740 dy -= s->cirrus_blt_height - 1;
741 }
742
743 /* are we in the visible portion of memory? */
744 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
745 (sx + w) <= width && (sy + h) <= height &&
746 (dx + w) <= width && (dy + h) <= height) {
747 notify = 1;
748 }
749
750 /* make to sure only copy if it's a plain copy ROP */
751 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
752 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
753 notify = 0;
754
755 /* we have to flush all pending changes so that the copy
756 is generated at the appropriate moment in time */
757 if (notify)
758 vga_hw_update();
759
760 (*s->cirrus_rop) (s, s->vga.vram_ptr +
761 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
762 s->vga.vram_ptr +
763 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
764 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
765 s->cirrus_blt_width, s->cirrus_blt_height);
766
767 if (notify)
768 qemu_console_copy(s->vga.ds,
769 sx, sy, dx, dy,
770 s->cirrus_blt_width / depth,
771 s->cirrus_blt_height);
772
773 /* we don't have to notify the display that this portion has
774 changed since qemu_console_copy implies this */
775
776 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
777 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
778 s->cirrus_blt_height);
779 }
780
781 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
782 {
783 if (BLTUNSAFE(s))
784 return 0;
785
786 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
787 s->cirrus_blt_srcaddr - s->vga.start_addr,
788 s->cirrus_blt_width, s->cirrus_blt_height);
789
790 return 1;
791 }
792
793 /***************************************
794 *
795 * bitblt (cpu-to-video)
796 *
797 ***************************************/
798
799 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
800 {
801 int copy_count;
802 uint8_t *end_ptr;
803
804 if (s->cirrus_srccounter > 0) {
805 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
806 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
807 the_end:
808 s->cirrus_srccounter = 0;
809 cirrus_bitblt_reset(s);
810 } else {
811 /* at least one scan line */
812 do {
813 (*s->cirrus_rop)(s, s->vga.vram_ptr +
814 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
815 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
816 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
817 s->cirrus_blt_width, 1);
818 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
819 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
820 if (s->cirrus_srccounter <= 0)
821 goto the_end;
822 /* more bytes than needed can be transfered because of
823 word alignment, so we keep them for the next line */
824 /* XXX: keep alignment to speed up transfer */
825 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
826 copy_count = s->cirrus_srcptr_end - end_ptr;
827 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
828 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
829 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
830 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
831 }
832 }
833 }
834
835 /***************************************
836 *
837 * bitblt wrapper
838 *
839 ***************************************/
840
841 static void cirrus_bitblt_reset(CirrusVGAState * s)
842 {
843 int need_update;
844
845 s->vga.gr[0x31] &=
846 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
847 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
848 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
849 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
850 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
851 s->cirrus_srccounter = 0;
852 if (!need_update)
853 return;
854 cirrus_update_memory_access(s);
855 }
856
857 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
858 {
859 int w;
860
861 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
862 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
863 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
864
865 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
866 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
867 s->cirrus_blt_srcpitch = 8;
868 } else {
869 /* XXX: check for 24 bpp */
870 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
871 }
872 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
873 } else {
874 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
875 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
876 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
877 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
878 else
879 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
880 } else {
881 /* always align input size to 32 bits */
882 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
883 }
884 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
885 }
886 s->cirrus_srcptr = s->cirrus_bltbuf;
887 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
888 cirrus_update_memory_access(s);
889 return 1;
890 }
891
892 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
893 {
894 /* XXX */
895 #ifdef DEBUG_BITBLT
896 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
897 #endif
898 return 0;
899 }
900
901 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
902 {
903 int ret;
904
905 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
906 ret = cirrus_bitblt_videotovideo_patterncopy(s);
907 } else {
908 ret = cirrus_bitblt_videotovideo_copy(s);
909 }
910 if (ret)
911 cirrus_bitblt_reset(s);
912 return ret;
913 }
914
915 static void cirrus_bitblt_start(CirrusVGAState * s)
916 {
917 uint8_t blt_rop;
918
919 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
920
921 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
922 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
923 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
924 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
925 s->cirrus_blt_dstaddr =
926 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
927 s->cirrus_blt_srcaddr =
928 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
929 s->cirrus_blt_mode = s->vga.gr[0x30];
930 s->cirrus_blt_modeext = s->vga.gr[0x33];
931 blt_rop = s->vga.gr[0x32];
932
933 #ifdef DEBUG_BITBLT
934 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
935 blt_rop,
936 s->cirrus_blt_mode,
937 s->cirrus_blt_modeext,
938 s->cirrus_blt_width,
939 s->cirrus_blt_height,
940 s->cirrus_blt_dstpitch,
941 s->cirrus_blt_srcpitch,
942 s->cirrus_blt_dstaddr,
943 s->cirrus_blt_srcaddr,
944 s->vga.gr[0x2f]);
945 #endif
946
947 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
948 case CIRRUS_BLTMODE_PIXELWIDTH8:
949 s->cirrus_blt_pixelwidth = 1;
950 break;
951 case CIRRUS_BLTMODE_PIXELWIDTH16:
952 s->cirrus_blt_pixelwidth = 2;
953 break;
954 case CIRRUS_BLTMODE_PIXELWIDTH24:
955 s->cirrus_blt_pixelwidth = 3;
956 break;
957 case CIRRUS_BLTMODE_PIXELWIDTH32:
958 s->cirrus_blt_pixelwidth = 4;
959 break;
960 default:
961 #ifdef DEBUG_BITBLT
962 printf("cirrus: bitblt - pixel width is unknown\n");
963 #endif
964 goto bitblt_ignore;
965 }
966 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
967
968 if ((s->
969 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
970 CIRRUS_BLTMODE_MEMSYSDEST))
971 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
972 #ifdef DEBUG_BITBLT
973 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
974 #endif
975 goto bitblt_ignore;
976 }
977
978 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
979 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
980 CIRRUS_BLTMODE_TRANSPARENTCOMP |
981 CIRRUS_BLTMODE_PATTERNCOPY |
982 CIRRUS_BLTMODE_COLOREXPAND)) ==
983 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
984 cirrus_bitblt_fgcol(s);
985 cirrus_bitblt_solidfill(s, blt_rop);
986 } else {
987 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
988 CIRRUS_BLTMODE_PATTERNCOPY)) ==
989 CIRRUS_BLTMODE_COLOREXPAND) {
990
991 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
992 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
993 cirrus_bitblt_bgcol(s);
994 else
995 cirrus_bitblt_fgcol(s);
996 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
997 } else {
998 cirrus_bitblt_fgcol(s);
999 cirrus_bitblt_bgcol(s);
1000 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1001 }
1002 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1003 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1004 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1005 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1006 cirrus_bitblt_bgcol(s);
1007 else
1008 cirrus_bitblt_fgcol(s);
1009 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1010 } else {
1011 cirrus_bitblt_fgcol(s);
1012 cirrus_bitblt_bgcol(s);
1013 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1014 }
1015 } else {
1016 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1017 }
1018 } else {
1019 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1020 if (s->cirrus_blt_pixelwidth > 2) {
1021 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1022 goto bitblt_ignore;
1023 }
1024 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1025 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1026 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1027 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1028 } else {
1029 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1030 }
1031 } else {
1032 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1033 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1034 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1035 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1036 } else {
1037 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1038 }
1039 }
1040 }
1041 // setup bitblt engine.
1042 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1043 if (!cirrus_bitblt_cputovideo(s))
1044 goto bitblt_ignore;
1045 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1046 if (!cirrus_bitblt_videotocpu(s))
1047 goto bitblt_ignore;
1048 } else {
1049 if (!cirrus_bitblt_videotovideo(s))
1050 goto bitblt_ignore;
1051 }
1052 }
1053 return;
1054 bitblt_ignore:;
1055 cirrus_bitblt_reset(s);
1056 }
1057
1058 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1059 {
1060 unsigned old_value;
1061
1062 old_value = s->vga.gr[0x31];
1063 s->vga.gr[0x31] = reg_value;
1064
1065 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1066 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1067 cirrus_bitblt_reset(s);
1068 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1069 ((reg_value & CIRRUS_BLT_START) != 0)) {
1070 cirrus_bitblt_start(s);
1071 }
1072 }
1073
1074
1075 /***************************************
1076 *
1077 * basic parameters
1078 *
1079 ***************************************/
1080
1081 static void cirrus_get_offsets(VGACommonState *s1,
1082 uint32_t *pline_offset,
1083 uint32_t *pstart_addr,
1084 uint32_t *pline_compare)
1085 {
1086 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1087 uint32_t start_addr, line_offset, line_compare;
1088
1089 line_offset = s->vga.cr[0x13]
1090 | ((s->vga.cr[0x1b] & 0x10) << 4);
1091 line_offset <<= 3;
1092 *pline_offset = line_offset;
1093
1094 start_addr = (s->vga.cr[0x0c] << 8)
1095 | s->vga.cr[0x0d]
1096 | ((s->vga.cr[0x1b] & 0x01) << 16)
1097 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1098 | ((s->vga.cr[0x1d] & 0x80) << 12);
1099 *pstart_addr = start_addr;
1100
1101 line_compare = s->vga.cr[0x18] |
1102 ((s->vga.cr[0x07] & 0x10) << 4) |
1103 ((s->vga.cr[0x09] & 0x40) << 3);
1104 *pline_compare = line_compare;
1105 }
1106
1107 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1108 {
1109 uint32_t ret = 16;
1110
1111 switch (s->cirrus_hidden_dac_data & 0xf) {
1112 case 0:
1113 ret = 15;
1114 break; /* Sierra HiColor */
1115 case 1:
1116 ret = 16;
1117 break; /* XGA HiColor */
1118 default:
1119 #ifdef DEBUG_CIRRUS
1120 printf("cirrus: invalid DAC value %x in 16bpp\n",
1121 (s->cirrus_hidden_dac_data & 0xf));
1122 #endif
1123 ret = 15; /* XXX */
1124 break;
1125 }
1126 return ret;
1127 }
1128
1129 static int cirrus_get_bpp(VGACommonState *s1)
1130 {
1131 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1132 uint32_t ret = 8;
1133
1134 if ((s->vga.sr[0x07] & 0x01) != 0) {
1135 /* Cirrus SVGA */
1136 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1137 case CIRRUS_SR7_BPP_8:
1138 ret = 8;
1139 break;
1140 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1141 ret = cirrus_get_bpp16_depth(s);
1142 break;
1143 case CIRRUS_SR7_BPP_24:
1144 ret = 24;
1145 break;
1146 case CIRRUS_SR7_BPP_16:
1147 ret = cirrus_get_bpp16_depth(s);
1148 break;
1149 case CIRRUS_SR7_BPP_32:
1150 ret = 32;
1151 break;
1152 default:
1153 #ifdef DEBUG_CIRRUS
1154 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1155 #endif
1156 ret = 8;
1157 break;
1158 }
1159 } else {
1160 /* VGA */
1161 ret = 0;
1162 }
1163
1164 return ret;
1165 }
1166
1167 static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1168 {
1169 int width, height;
1170
1171 width = (s->cr[0x01] + 1) * 8;
1172 height = s->cr[0x12] |
1173 ((s->cr[0x07] & 0x02) << 7) |
1174 ((s->cr[0x07] & 0x40) << 3);
1175 height = (height + 1);
1176 /* interlace support */
1177 if (s->cr[0x1a] & 0x01)
1178 height = height * 2;
1179 *pwidth = width;
1180 *pheight = height;
1181 }
1182
1183 /***************************************
1184 *
1185 * bank memory
1186 *
1187 ***************************************/
1188
1189 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1190 {
1191 unsigned offset;
1192 unsigned limit;
1193
1194 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1195 offset = s->vga.gr[0x09 + bank_index];
1196 else /* single bank */
1197 offset = s->vga.gr[0x09];
1198
1199 if ((s->vga.gr[0x0b] & 0x20) != 0)
1200 offset <<= 14;
1201 else
1202 offset <<= 12;
1203
1204 if (s->real_vram_size <= offset)
1205 limit = 0;
1206 else
1207 limit = s->real_vram_size - offset;
1208
1209 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1210 if (limit > 0x8000) {
1211 offset += 0x8000;
1212 limit -= 0x8000;
1213 } else {
1214 limit = 0;
1215 }
1216 }
1217
1218 if (limit > 0) {
1219 /* Thinking about changing bank base? First, drop the dirty bitmap information
1220 * on the current location, otherwise we lose this pointer forever */
1221 if (s->vga.lfb_vram_mapped) {
1222 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1223 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1224 }
1225 s->cirrus_bank_base[bank_index] = offset;
1226 s->cirrus_bank_limit[bank_index] = limit;
1227 } else {
1228 s->cirrus_bank_base[bank_index] = 0;
1229 s->cirrus_bank_limit[bank_index] = 0;
1230 }
1231 }
1232
1233 /***************************************
1234 *
1235 * I/O access between 0x3c4-0x3c5
1236 *
1237 ***************************************/
1238
1239 static int
1240 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1241 {
1242 switch (reg_index) {
1243 case 0x00: // Standard VGA
1244 case 0x01: // Standard VGA
1245 case 0x02: // Standard VGA
1246 case 0x03: // Standard VGA
1247 case 0x04: // Standard VGA
1248 return CIRRUS_HOOK_NOT_HANDLED;
1249 case 0x06: // Unlock Cirrus extensions
1250 *reg_value = s->vga.sr[reg_index];
1251 break;
1252 case 0x10:
1253 case 0x30:
1254 case 0x50:
1255 case 0x70: // Graphics Cursor X
1256 case 0x90:
1257 case 0xb0:
1258 case 0xd0:
1259 case 0xf0: // Graphics Cursor X
1260 *reg_value = s->vga.sr[0x10];
1261 break;
1262 case 0x11:
1263 case 0x31:
1264 case 0x51:
1265 case 0x71: // Graphics Cursor Y
1266 case 0x91:
1267 case 0xb1:
1268 case 0xd1:
1269 case 0xf1: // Graphics Cursor Y
1270 *reg_value = s->vga.sr[0x11];
1271 break;
1272 case 0x05: // ???
1273 case 0x07: // Extended Sequencer Mode
1274 case 0x08: // EEPROM Control
1275 case 0x09: // Scratch Register 0
1276 case 0x0a: // Scratch Register 1
1277 case 0x0b: // VCLK 0
1278 case 0x0c: // VCLK 1
1279 case 0x0d: // VCLK 2
1280 case 0x0e: // VCLK 3
1281 case 0x0f: // DRAM Control
1282 case 0x12: // Graphics Cursor Attribute
1283 case 0x13: // Graphics Cursor Pattern Address
1284 case 0x14: // Scratch Register 2
1285 case 0x15: // Scratch Register 3
1286 case 0x16: // Performance Tuning Register
1287 case 0x17: // Configuration Readback and Extended Control
1288 case 0x18: // Signature Generator Control
1289 case 0x19: // Signal Generator Result
1290 case 0x1a: // Signal Generator Result
1291 case 0x1b: // VCLK 0 Denominator & Post
1292 case 0x1c: // VCLK 1 Denominator & Post
1293 case 0x1d: // VCLK 2 Denominator & Post
1294 case 0x1e: // VCLK 3 Denominator & Post
1295 case 0x1f: // BIOS Write Enable and MCLK select
1296 #ifdef DEBUG_CIRRUS
1297 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1298 #endif
1299 *reg_value = s->vga.sr[reg_index];
1300 break;
1301 default:
1302 #ifdef DEBUG_CIRRUS
1303 printf("cirrus: inport sr_index %02x\n", reg_index);
1304 #endif
1305 *reg_value = 0xff;
1306 break;
1307 }
1308
1309 return CIRRUS_HOOK_HANDLED;
1310 }
1311
1312 static int
1313 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1314 {
1315 switch (reg_index) {
1316 case 0x00: // Standard VGA
1317 case 0x01: // Standard VGA
1318 case 0x02: // Standard VGA
1319 case 0x03: // Standard VGA
1320 case 0x04: // Standard VGA
1321 return CIRRUS_HOOK_NOT_HANDLED;
1322 case 0x06: // Unlock Cirrus extensions
1323 reg_value &= 0x17;
1324 if (reg_value == 0x12) {
1325 s->vga.sr[reg_index] = 0x12;
1326 } else {
1327 s->vga.sr[reg_index] = 0x0f;
1328 }
1329 break;
1330 case 0x10:
1331 case 0x30:
1332 case 0x50:
1333 case 0x70: // Graphics Cursor X
1334 case 0x90:
1335 case 0xb0:
1336 case 0xd0:
1337 case 0xf0: // Graphics Cursor X
1338 s->vga.sr[0x10] = reg_value;
1339 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1340 break;
1341 case 0x11:
1342 case 0x31:
1343 case 0x51:
1344 case 0x71: // Graphics Cursor Y
1345 case 0x91:
1346 case 0xb1:
1347 case 0xd1:
1348 case 0xf1: // Graphics Cursor Y
1349 s->vga.sr[0x11] = reg_value;
1350 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1351 break;
1352 case 0x07: // Extended Sequencer Mode
1353 cirrus_update_memory_access(s);
1354 case 0x08: // EEPROM Control
1355 case 0x09: // Scratch Register 0
1356 case 0x0a: // Scratch Register 1
1357 case 0x0b: // VCLK 0
1358 case 0x0c: // VCLK 1
1359 case 0x0d: // VCLK 2
1360 case 0x0e: // VCLK 3
1361 case 0x0f: // DRAM Control
1362 case 0x12: // Graphics Cursor Attribute
1363 case 0x13: // Graphics Cursor Pattern Address
1364 case 0x14: // Scratch Register 2
1365 case 0x15: // Scratch Register 3
1366 case 0x16: // Performance Tuning Register
1367 case 0x18: // Signature Generator Control
1368 case 0x19: // Signature Generator Result
1369 case 0x1a: // Signature Generator Result
1370 case 0x1b: // VCLK 0 Denominator & Post
1371 case 0x1c: // VCLK 1 Denominator & Post
1372 case 0x1d: // VCLK 2 Denominator & Post
1373 case 0x1e: // VCLK 3 Denominator & Post
1374 case 0x1f: // BIOS Write Enable and MCLK select
1375 s->vga.sr[reg_index] = reg_value;
1376 #ifdef DEBUG_CIRRUS
1377 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1378 reg_index, reg_value);
1379 #endif
1380 break;
1381 case 0x17: // Configuration Readback and Extended Control
1382 s->vga.sr[reg_index] = (s->vga.sr[reg_index] & 0x38) | (reg_value & 0xc7);
1383 cirrus_update_memory_access(s);
1384 break;
1385 default:
1386 #ifdef DEBUG_CIRRUS
1387 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1388 reg_value);
1389 #endif
1390 break;
1391 }
1392
1393 return CIRRUS_HOOK_HANDLED;
1394 }
1395
1396 /***************************************
1397 *
1398 * I/O access at 0x3c6
1399 *
1400 ***************************************/
1401
1402 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1403 {
1404 *reg_value = 0xff;
1405 if (++s->cirrus_hidden_dac_lockindex == 5) {
1406 *reg_value = s->cirrus_hidden_dac_data;
1407 s->cirrus_hidden_dac_lockindex = 0;
1408 }
1409 }
1410
1411 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1412 {
1413 if (s->cirrus_hidden_dac_lockindex == 4) {
1414 s->cirrus_hidden_dac_data = reg_value;
1415 #if defined(DEBUG_CIRRUS)
1416 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1417 #endif
1418 }
1419 s->cirrus_hidden_dac_lockindex = 0;
1420 }
1421
1422 /***************************************
1423 *
1424 * I/O access at 0x3c9
1425 *
1426 ***************************************/
1427
1428 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1429 {
1430 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1431 return CIRRUS_HOOK_NOT_HANDLED;
1432 *reg_value =
1433 s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1434 s->vga.dac_sub_index];
1435 if (++s->vga.dac_sub_index == 3) {
1436 s->vga.dac_sub_index = 0;
1437 s->vga.dac_read_index++;
1438 }
1439 return CIRRUS_HOOK_HANDLED;
1440 }
1441
1442 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1443 {
1444 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1445 return CIRRUS_HOOK_NOT_HANDLED;
1446 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1447 if (++s->vga.dac_sub_index == 3) {
1448 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1449 s->vga.dac_cache, 3);
1450 /* XXX update cursor */
1451 s->vga.dac_sub_index = 0;
1452 s->vga.dac_write_index++;
1453 }
1454 return CIRRUS_HOOK_HANDLED;
1455 }
1456
1457 /***************************************
1458 *
1459 * I/O access between 0x3ce-0x3cf
1460 *
1461 ***************************************/
1462
1463 static int
1464 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1465 {
1466 switch (reg_index) {
1467 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1468 *reg_value = s->cirrus_shadow_gr0;
1469 return CIRRUS_HOOK_HANDLED;
1470 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1471 *reg_value = s->cirrus_shadow_gr1;
1472 return CIRRUS_HOOK_HANDLED;
1473 case 0x02: // Standard VGA
1474 case 0x03: // Standard VGA
1475 case 0x04: // Standard VGA
1476 case 0x06: // Standard VGA
1477 case 0x07: // Standard VGA
1478 case 0x08: // Standard VGA
1479 return CIRRUS_HOOK_NOT_HANDLED;
1480 case 0x05: // Standard VGA, Cirrus extended mode
1481 default:
1482 break;
1483 }
1484
1485 if (reg_index < 0x3a) {
1486 *reg_value = s->vga.gr[reg_index];
1487 } else {
1488 #ifdef DEBUG_CIRRUS
1489 printf("cirrus: inport gr_index %02x\n", reg_index);
1490 #endif
1491 *reg_value = 0xff;
1492 }
1493
1494 return CIRRUS_HOOK_HANDLED;
1495 }
1496
1497 static int
1498 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1499 {
1500 #if defined(DEBUG_BITBLT) && 0
1501 printf("gr%02x: %02x\n", reg_index, reg_value);
1502 #endif
1503 switch (reg_index) {
1504 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1505 s->cirrus_shadow_gr0 = reg_value;
1506 return CIRRUS_HOOK_NOT_HANDLED;
1507 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1508 s->cirrus_shadow_gr1 = reg_value;
1509 return CIRRUS_HOOK_NOT_HANDLED;
1510 case 0x02: // Standard VGA
1511 case 0x03: // Standard VGA
1512 case 0x04: // Standard VGA
1513 case 0x06: // Standard VGA
1514 case 0x07: // Standard VGA
1515 case 0x08: // Standard VGA
1516 return CIRRUS_HOOK_NOT_HANDLED;
1517 case 0x05: // Standard VGA, Cirrus extended mode
1518 s->vga.gr[reg_index] = reg_value & 0x7f;
1519 cirrus_update_memory_access(s);
1520 break;
1521 case 0x09: // bank offset #0
1522 case 0x0A: // bank offset #1
1523 s->vga.gr[reg_index] = reg_value;
1524 cirrus_update_bank_ptr(s, 0);
1525 cirrus_update_bank_ptr(s, 1);
1526 cirrus_update_memory_access(s);
1527 break;
1528 case 0x0B:
1529 s->vga.gr[reg_index] = reg_value;
1530 cirrus_update_bank_ptr(s, 0);
1531 cirrus_update_bank_ptr(s, 1);
1532 cirrus_update_memory_access(s);
1533 break;
1534 case 0x10: // BGCOLOR 0x0000ff00
1535 case 0x11: // FGCOLOR 0x0000ff00
1536 case 0x12: // BGCOLOR 0x00ff0000
1537 case 0x13: // FGCOLOR 0x00ff0000
1538 case 0x14: // BGCOLOR 0xff000000
1539 case 0x15: // FGCOLOR 0xff000000
1540 case 0x20: // BLT WIDTH 0x0000ff
1541 case 0x22: // BLT HEIGHT 0x0000ff
1542 case 0x24: // BLT DEST PITCH 0x0000ff
1543 case 0x26: // BLT SRC PITCH 0x0000ff
1544 case 0x28: // BLT DEST ADDR 0x0000ff
1545 case 0x29: // BLT DEST ADDR 0x00ff00
1546 case 0x2c: // BLT SRC ADDR 0x0000ff
1547 case 0x2d: // BLT SRC ADDR 0x00ff00
1548 case 0x2f: // BLT WRITEMASK
1549 case 0x30: // BLT MODE
1550 case 0x32: // RASTER OP
1551 case 0x33: // BLT MODEEXT
1552 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1553 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1554 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1555 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1556 s->vga.gr[reg_index] = reg_value;
1557 break;
1558 case 0x21: // BLT WIDTH 0x001f00
1559 case 0x23: // BLT HEIGHT 0x001f00
1560 case 0x25: // BLT DEST PITCH 0x001f00
1561 case 0x27: // BLT SRC PITCH 0x001f00
1562 s->vga.gr[reg_index] = reg_value & 0x1f;
1563 break;
1564 case 0x2a: // BLT DEST ADDR 0x3f0000
1565 s->vga.gr[reg_index] = reg_value & 0x3f;
1566 /* if auto start mode, starts bit blt now */
1567 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1568 cirrus_bitblt_start(s);
1569 }
1570 break;
1571 case 0x2e: // BLT SRC ADDR 0x3f0000
1572 s->vga.gr[reg_index] = reg_value & 0x3f;
1573 break;
1574 case 0x31: // BLT STATUS/START
1575 cirrus_write_bitblt(s, reg_value);
1576 break;
1577 default:
1578 #ifdef DEBUG_CIRRUS
1579 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1580 reg_value);
1581 #endif
1582 break;
1583 }
1584
1585 return CIRRUS_HOOK_HANDLED;
1586 }
1587
1588 /***************************************
1589 *
1590 * I/O access between 0x3d4-0x3d5
1591 *
1592 ***************************************/
1593
1594 static int
1595 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1596 {
1597 switch (reg_index) {
1598 case 0x00: // Standard VGA
1599 case 0x01: // Standard VGA
1600 case 0x02: // Standard VGA
1601 case 0x03: // Standard VGA
1602 case 0x04: // Standard VGA
1603 case 0x05: // Standard VGA
1604 case 0x06: // Standard VGA
1605 case 0x07: // Standard VGA
1606 case 0x08: // Standard VGA
1607 case 0x09: // Standard VGA
1608 case 0x0a: // Standard VGA
1609 case 0x0b: // Standard VGA
1610 case 0x0c: // Standard VGA
1611 case 0x0d: // Standard VGA
1612 case 0x0e: // Standard VGA
1613 case 0x0f: // Standard VGA
1614 case 0x10: // Standard VGA
1615 case 0x11: // Standard VGA
1616 case 0x12: // Standard VGA
1617 case 0x13: // Standard VGA
1618 case 0x14: // Standard VGA
1619 case 0x15: // Standard VGA
1620 case 0x16: // Standard VGA
1621 case 0x17: // Standard VGA
1622 case 0x18: // Standard VGA
1623 return CIRRUS_HOOK_NOT_HANDLED;
1624 case 0x24: // Attribute Controller Toggle Readback (R)
1625 *reg_value = (s->vga.ar_flip_flop << 7);
1626 break;
1627 case 0x19: // Interlace End
1628 case 0x1a: // Miscellaneous Control
1629 case 0x1b: // Extended Display Control
1630 case 0x1c: // Sync Adjust and Genlock
1631 case 0x1d: // Overlay Extended Control
1632 case 0x22: // Graphics Data Latches Readback (R)
1633 case 0x25: // Part Status
1634 case 0x27: // Part ID (R)
1635 *reg_value = s->vga.cr[reg_index];
1636 break;
1637 case 0x26: // Attribute Controller Index Readback (R)
1638 *reg_value = s->vga.ar_index & 0x3f;
1639 break;
1640 default:
1641 #ifdef DEBUG_CIRRUS
1642 printf("cirrus: inport cr_index %02x\n", reg_index);
1643 *reg_value = 0xff;
1644 #endif
1645 break;
1646 }
1647
1648 return CIRRUS_HOOK_HANDLED;
1649 }
1650
1651 static int
1652 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1653 {
1654 switch (reg_index) {
1655 case 0x00: // Standard VGA
1656 case 0x01: // Standard VGA
1657 case 0x02: // Standard VGA
1658 case 0x03: // Standard VGA
1659 case 0x04: // Standard VGA
1660 case 0x05: // Standard VGA
1661 case 0x06: // Standard VGA
1662 case 0x07: // Standard VGA
1663 case 0x08: // Standard VGA
1664 case 0x09: // Standard VGA
1665 case 0x0a: // Standard VGA
1666 case 0x0b: // Standard VGA
1667 case 0x0c: // Standard VGA
1668 case 0x0d: // Standard VGA
1669 case 0x0e: // Standard VGA
1670 case 0x0f: // Standard VGA
1671 case 0x10: // Standard VGA
1672 case 0x11: // Standard VGA
1673 case 0x12: // Standard VGA
1674 case 0x13: // Standard VGA
1675 case 0x14: // Standard VGA
1676 case 0x15: // Standard VGA
1677 case 0x16: // Standard VGA
1678 case 0x17: // Standard VGA
1679 case 0x18: // Standard VGA
1680 return CIRRUS_HOOK_NOT_HANDLED;
1681 case 0x19: // Interlace End
1682 case 0x1a: // Miscellaneous Control
1683 case 0x1b: // Extended Display Control
1684 case 0x1c: // Sync Adjust and Genlock
1685 case 0x1d: // Overlay Extended Control
1686 s->vga.cr[reg_index] = reg_value;
1687 #ifdef DEBUG_CIRRUS
1688 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1689 reg_index, reg_value);
1690 #endif
1691 break;
1692 case 0x22: // Graphics Data Latches Readback (R)
1693 case 0x24: // Attribute Controller Toggle Readback (R)
1694 case 0x26: // Attribute Controller Index Readback (R)
1695 case 0x27: // Part ID (R)
1696 break;
1697 case 0x25: // Part Status
1698 default:
1699 #ifdef DEBUG_CIRRUS
1700 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1701 reg_value);
1702 #endif
1703 break;
1704 }
1705
1706 return CIRRUS_HOOK_HANDLED;
1707 }
1708
1709 /***************************************
1710 *
1711 * memory-mapped I/O (bitblt)
1712 *
1713 ***************************************/
1714
1715 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1716 {
1717 int value = 0xff;
1718
1719 switch (address) {
1720 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1721 cirrus_hook_read_gr(s, 0x00, &value);
1722 break;
1723 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1724 cirrus_hook_read_gr(s, 0x10, &value);
1725 break;
1726 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1727 cirrus_hook_read_gr(s, 0x12, &value);
1728 break;
1729 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1730 cirrus_hook_read_gr(s, 0x14, &value);
1731 break;
1732 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1733 cirrus_hook_read_gr(s, 0x01, &value);
1734 break;
1735 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1736 cirrus_hook_read_gr(s, 0x11, &value);
1737 break;
1738 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1739 cirrus_hook_read_gr(s, 0x13, &value);
1740 break;
1741 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1742 cirrus_hook_read_gr(s, 0x15, &value);
1743 break;
1744 case (CIRRUS_MMIO_BLTWIDTH + 0):
1745 cirrus_hook_read_gr(s, 0x20, &value);
1746 break;
1747 case (CIRRUS_MMIO_BLTWIDTH + 1):
1748 cirrus_hook_read_gr(s, 0x21, &value);
1749 break;
1750 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1751 cirrus_hook_read_gr(s, 0x22, &value);
1752 break;
1753 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1754 cirrus_hook_read_gr(s, 0x23, &value);
1755 break;
1756 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1757 cirrus_hook_read_gr(s, 0x24, &value);
1758 break;
1759 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1760 cirrus_hook_read_gr(s, 0x25, &value);
1761 break;
1762 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1763 cirrus_hook_read_gr(s, 0x26, &value);
1764 break;
1765 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1766 cirrus_hook_read_gr(s, 0x27, &value);
1767 break;
1768 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1769 cirrus_hook_read_gr(s, 0x28, &value);
1770 break;
1771 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1772 cirrus_hook_read_gr(s, 0x29, &value);
1773 break;
1774 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1775 cirrus_hook_read_gr(s, 0x2a, &value);
1776 break;
1777 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1778 cirrus_hook_read_gr(s, 0x2c, &value);
1779 break;
1780 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1781 cirrus_hook_read_gr(s, 0x2d, &value);
1782 break;
1783 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1784 cirrus_hook_read_gr(s, 0x2e, &value);
1785 break;
1786 case CIRRUS_MMIO_BLTWRITEMASK:
1787 cirrus_hook_read_gr(s, 0x2f, &value);
1788 break;
1789 case CIRRUS_MMIO_BLTMODE:
1790 cirrus_hook_read_gr(s, 0x30, &value);
1791 break;
1792 case CIRRUS_MMIO_BLTROP:
1793 cirrus_hook_read_gr(s, 0x32, &value);
1794 break;
1795 case CIRRUS_MMIO_BLTMODEEXT:
1796 cirrus_hook_read_gr(s, 0x33, &value);
1797 break;
1798 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1799 cirrus_hook_read_gr(s, 0x34, &value);
1800 break;
1801 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1802 cirrus_hook_read_gr(s, 0x35, &value);
1803 break;
1804 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1805 cirrus_hook_read_gr(s, 0x38, &value);
1806 break;
1807 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1808 cirrus_hook_read_gr(s, 0x39, &value);
1809 break;
1810 case CIRRUS_MMIO_BLTSTATUS:
1811 cirrus_hook_read_gr(s, 0x31, &value);
1812 break;
1813 default:
1814 #ifdef DEBUG_CIRRUS
1815 printf("cirrus: mmio read - address 0x%04x\n", address);
1816 #endif
1817 break;
1818 }
1819
1820 return (uint8_t) value;
1821 }
1822
1823 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1824 uint8_t value)
1825 {
1826 switch (address) {
1827 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1828 cirrus_hook_write_gr(s, 0x00, value);
1829 break;
1830 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1831 cirrus_hook_write_gr(s, 0x10, value);
1832 break;
1833 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1834 cirrus_hook_write_gr(s, 0x12, value);
1835 break;
1836 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1837 cirrus_hook_write_gr(s, 0x14, value);
1838 break;
1839 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1840 cirrus_hook_write_gr(s, 0x01, value);
1841 break;
1842 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1843 cirrus_hook_write_gr(s, 0x11, value);
1844 break;
1845 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1846 cirrus_hook_write_gr(s, 0x13, value);
1847 break;
1848 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1849 cirrus_hook_write_gr(s, 0x15, value);
1850 break;
1851 case (CIRRUS_MMIO_BLTWIDTH + 0):
1852 cirrus_hook_write_gr(s, 0x20, value);
1853 break;
1854 case (CIRRUS_MMIO_BLTWIDTH + 1):
1855 cirrus_hook_write_gr(s, 0x21, value);
1856 break;
1857 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1858 cirrus_hook_write_gr(s, 0x22, value);
1859 break;
1860 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1861 cirrus_hook_write_gr(s, 0x23, value);
1862 break;
1863 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1864 cirrus_hook_write_gr(s, 0x24, value);
1865 break;
1866 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1867 cirrus_hook_write_gr(s, 0x25, value);
1868 break;
1869 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1870 cirrus_hook_write_gr(s, 0x26, value);
1871 break;
1872 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1873 cirrus_hook_write_gr(s, 0x27, value);
1874 break;
1875 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1876 cirrus_hook_write_gr(s, 0x28, value);
1877 break;
1878 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1879 cirrus_hook_write_gr(s, 0x29, value);
1880 break;
1881 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1882 cirrus_hook_write_gr(s, 0x2a, value);
1883 break;
1884 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1885 /* ignored */
1886 break;
1887 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1888 cirrus_hook_write_gr(s, 0x2c, value);
1889 break;
1890 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1891 cirrus_hook_write_gr(s, 0x2d, value);
1892 break;
1893 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1894 cirrus_hook_write_gr(s, 0x2e, value);
1895 break;
1896 case CIRRUS_MMIO_BLTWRITEMASK:
1897 cirrus_hook_write_gr(s, 0x2f, value);
1898 break;
1899 case CIRRUS_MMIO_BLTMODE:
1900 cirrus_hook_write_gr(s, 0x30, value);
1901 break;
1902 case CIRRUS_MMIO_BLTROP:
1903 cirrus_hook_write_gr(s, 0x32, value);
1904 break;
1905 case CIRRUS_MMIO_BLTMODEEXT:
1906 cirrus_hook_write_gr(s, 0x33, value);
1907 break;
1908 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1909 cirrus_hook_write_gr(s, 0x34, value);
1910 break;
1911 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1912 cirrus_hook_write_gr(s, 0x35, value);
1913 break;
1914 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1915 cirrus_hook_write_gr(s, 0x38, value);
1916 break;
1917 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1918 cirrus_hook_write_gr(s, 0x39, value);
1919 break;
1920 case CIRRUS_MMIO_BLTSTATUS:
1921 cirrus_hook_write_gr(s, 0x31, value);
1922 break;
1923 default:
1924 #ifdef DEBUG_CIRRUS
1925 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1926 address, value);
1927 #endif
1928 break;
1929 }
1930 }
1931
1932 /***************************************
1933 *
1934 * write mode 4/5
1935 *
1936 * assume TARGET_PAGE_SIZE >= 16
1937 *
1938 ***************************************/
1939
1940 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1941 unsigned mode,
1942 unsigned offset,
1943 uint32_t mem_value)
1944 {
1945 int x;
1946 unsigned val = mem_value;
1947 uint8_t *dst;
1948
1949 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1950 for (x = 0; x < 8; x++) {
1951 if (val & 0x80) {
1952 *dst = s->cirrus_shadow_gr1;
1953 } else if (mode == 5) {
1954 *dst = s->cirrus_shadow_gr0;
1955 }
1956 val <<= 1;
1957 dst++;
1958 }
1959 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1960 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
1961 }
1962
1963 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1964 unsigned mode,
1965 unsigned offset,
1966 uint32_t mem_value)
1967 {
1968 int x;
1969 unsigned val = mem_value;
1970 uint8_t *dst;
1971
1972 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1973 for (x = 0; x < 8; x++) {
1974 if (val & 0x80) {
1975 *dst = s->cirrus_shadow_gr1;
1976 *(dst + 1) = s->vga.gr[0x11];
1977 } else if (mode == 5) {
1978 *dst = s->cirrus_shadow_gr0;
1979 *(dst + 1) = s->vga.gr[0x10];
1980 }
1981 val <<= 1;
1982 dst += 2;
1983 }
1984 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1985 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
1986 }
1987
1988 /***************************************
1989 *
1990 * memory access between 0xa0000-0xbffff
1991 *
1992 ***************************************/
1993
1994 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1995 {
1996 CirrusVGAState *s = opaque;
1997 unsigned bank_index;
1998 unsigned bank_offset;
1999 uint32_t val;
2000
2001 if ((s->vga.sr[0x07] & 0x01) == 0) {
2002 return vga_mem_readb(s, addr);
2003 }
2004
2005 addr &= 0x1ffff;
2006
2007 if (addr < 0x10000) {
2008 /* XXX handle bitblt */
2009 /* video memory */
2010 bank_index = addr >> 15;
2011 bank_offset = addr & 0x7fff;
2012 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2013 bank_offset += s->cirrus_bank_base[bank_index];
2014 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2015 bank_offset <<= 4;
2016 } else if (s->vga.gr[0x0B] & 0x02) {
2017 bank_offset <<= 3;
2018 }
2019 bank_offset &= s->cirrus_addr_mask;
2020 val = *(s->vga.vram_ptr + bank_offset);
2021 } else
2022 val = 0xff;
2023 } else if (addr >= 0x18000 && addr < 0x18100) {
2024 /* memory-mapped I/O */
2025 val = 0xff;
2026 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2027 val = cirrus_mmio_blt_read(s, addr & 0xff);
2028 }
2029 } else {
2030 val = 0xff;
2031 #ifdef DEBUG_CIRRUS
2032 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
2033 #endif
2034 }
2035 return val;
2036 }
2037
2038 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2039 {
2040 uint32_t v;
2041 #ifdef TARGET_WORDS_BIGENDIAN
2042 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2043 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2044 #else
2045 v = cirrus_vga_mem_readb(opaque, addr);
2046 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2047 #endif
2048 return v;
2049 }
2050
2051 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2052 {
2053 uint32_t v;
2054 #ifdef TARGET_WORDS_BIGENDIAN
2055 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2056 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2057 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2058 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2059 #else
2060 v = cirrus_vga_mem_readb(opaque, addr);
2061 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2062 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2063 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2064 #endif
2065 return v;
2066 }
2067
2068 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2069 uint32_t mem_value)
2070 {
2071 CirrusVGAState *s = opaque;
2072 unsigned bank_index;
2073 unsigned bank_offset;
2074 unsigned mode;
2075
2076 if ((s->vga.sr[0x07] & 0x01) == 0) {
2077 vga_mem_writeb(s, addr, mem_value);
2078 return;
2079 }
2080
2081 addr &= 0x1ffff;
2082
2083 if (addr < 0x10000) {
2084 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2085 /* bitblt */
2086 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2087 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2088 cirrus_bitblt_cputovideo_next(s);
2089 }
2090 } else {
2091 /* video memory */
2092 bank_index = addr >> 15;
2093 bank_offset = addr & 0x7fff;
2094 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2095 bank_offset += s->cirrus_bank_base[bank_index];
2096 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2097 bank_offset <<= 4;
2098 } else if (s->vga.gr[0x0B] & 0x02) {
2099 bank_offset <<= 3;
2100 }
2101 bank_offset &= s->cirrus_addr_mask;
2102 mode = s->vga.gr[0x05] & 0x7;
2103 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2104 *(s->vga.vram_ptr + bank_offset) = mem_value;
2105 cpu_physical_memory_set_dirty(s->vga.vram_offset +
2106 bank_offset);
2107 } else {
2108 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2109 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2110 bank_offset,
2111 mem_value);
2112 } else {
2113 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2114 bank_offset,
2115 mem_value);
2116 }
2117 }
2118 }
2119 }
2120 } else if (addr >= 0x18000 && addr < 0x18100) {
2121 /* memory-mapped I/O */
2122 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2123 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2124 }
2125 } else {
2126 #ifdef DEBUG_CIRRUS
2127 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2128 mem_value);
2129 #endif
2130 }
2131 }
2132
2133 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2134 {
2135 #ifdef TARGET_WORDS_BIGENDIAN
2136 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2137 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2138 #else
2139 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2140 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2141 #endif
2142 }
2143
2144 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2145 {
2146 #ifdef TARGET_WORDS_BIGENDIAN
2147 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2148 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2149 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2150 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2151 #else
2152 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2153 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2154 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2155 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2156 #endif
2157 }
2158
2159 static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = {
2160 cirrus_vga_mem_readb,
2161 cirrus_vga_mem_readw,
2162 cirrus_vga_mem_readl,
2163 };
2164
2165 static CPUWriteMemoryFunc * const cirrus_vga_mem_write[3] = {
2166 cirrus_vga_mem_writeb,
2167 cirrus_vga_mem_writew,
2168 cirrus_vga_mem_writel,
2169 };
2170
2171 /***************************************
2172 *
2173 * hardware cursor
2174 *
2175 ***************************************/
2176
2177 static inline void invalidate_cursor1(CirrusVGAState *s)
2178 {
2179 if (s->last_hw_cursor_size) {
2180 vga_invalidate_scanlines(&s->vga,
2181 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2182 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2183 }
2184 }
2185
2186 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2187 {
2188 const uint8_t *src;
2189 uint32_t content;
2190 int y, y_min, y_max;
2191
2192 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2193 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2194 src += (s->vga.sr[0x13] & 0x3c) * 256;
2195 y_min = 64;
2196 y_max = -1;
2197 for(y = 0; y < 64; y++) {
2198 content = ((uint32_t *)src)[0] |
2199 ((uint32_t *)src)[1] |
2200 ((uint32_t *)src)[2] |
2201 ((uint32_t *)src)[3];
2202 if (content) {
2203 if (y < y_min)
2204 y_min = y;
2205 if (y > y_max)
2206 y_max = y;
2207 }
2208 src += 16;
2209 }
2210 } else {
2211 src += (s->vga.sr[0x13] & 0x3f) * 256;
2212 y_min = 32;
2213 y_max = -1;
2214 for(y = 0; y < 32; y++) {
2215 content = ((uint32_t *)src)[0] |
2216 ((uint32_t *)(src + 128))[0];
2217 if (content) {
2218 if (y < y_min)
2219 y_min = y;
2220 if (y > y_max)
2221 y_max = y;
2222 }
2223 src += 4;
2224 }
2225 }
2226 if (y_min > y_max) {
2227 s->last_hw_cursor_y_start = 0;
2228 s->last_hw_cursor_y_end = 0;
2229 } else {
2230 s->last_hw_cursor_y_start = y_min;
2231 s->last_hw_cursor_y_end = y_max + 1;
2232 }
2233 }
2234
2235 /* NOTE: we do not currently handle the cursor bitmap change, so we
2236 update the cursor only if it moves. */
2237 static void cirrus_cursor_invalidate(VGACommonState *s1)
2238 {
2239 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2240 int size;
2241
2242 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2243 size = 0;
2244 } else {
2245 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2246 size = 64;
2247 else
2248 size = 32;
2249 }
2250 /* invalidate last cursor and new cursor if any change */
2251 if (s->last_hw_cursor_size != size ||
2252 s->last_hw_cursor_x != s->hw_cursor_x ||
2253 s->last_hw_cursor_y != s->hw_cursor_y) {
2254
2255 invalidate_cursor1(s);
2256
2257 s->last_hw_cursor_size = size;
2258 s->last_hw_cursor_x = s->hw_cursor_x;
2259 s->last_hw_cursor_y = s->hw_cursor_y;
2260 /* compute the real cursor min and max y */
2261 cirrus_cursor_compute_yrange(s);
2262 invalidate_cursor1(s);
2263 }
2264 }
2265
2266 static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
2267 {
2268 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2269 int w, h, bpp, x1, x2, poffset;
2270 unsigned int color0, color1;
2271 const uint8_t *palette, *src;
2272 uint32_t content;
2273
2274 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2275 return;
2276 /* fast test to see if the cursor intersects with the scan line */
2277 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2278 h = 64;
2279 } else {
2280 h = 32;
2281 }
2282 if (scr_y < s->hw_cursor_y ||
2283 scr_y >= (s->hw_cursor_y + h))
2284 return;
2285
2286 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2287 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2288 src += (s->vga.sr[0x13] & 0x3c) * 256;
2289 src += (scr_y - s->hw_cursor_y) * 16;
2290 poffset = 8;
2291 content = ((uint32_t *)src)[0] |
2292 ((uint32_t *)src)[1] |
2293 ((uint32_t *)src)[2] |
2294 ((uint32_t *)src)[3];
2295 } else {
2296 src += (s->vga.sr[0x13] & 0x3f) * 256;
2297 src += (scr_y - s->hw_cursor_y) * 4;
2298 poffset = 128;
2299 content = ((uint32_t *)src)[0] |
2300 ((uint32_t *)(src + 128))[0];
2301 }
2302 /* if nothing to draw, no need to continue */
2303 if (!content)
2304 return;
2305 w = h;
2306
2307 x1 = s->hw_cursor_x;
2308 if (x1 >= s->vga.last_scr_width)
2309 return;
2310 x2 = s->hw_cursor_x + w;
2311 if (x2 > s->vga.last_scr_width)
2312 x2 = s->vga.last_scr_width;
2313 w = x2 - x1;
2314 palette = s->cirrus_hidden_palette;
2315 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2316 c6_to_8(palette[0x0 * 3 + 1]),
2317 c6_to_8(palette[0x0 * 3 + 2]));
2318 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2319 c6_to_8(palette[0xf * 3 + 1]),
2320 c6_to_8(palette[0xf * 3 + 2]));
2321 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
2322 d1 += x1 * bpp;
2323 switch(ds_get_bits_per_pixel(s->vga.ds)) {
2324 default:
2325 break;
2326 case 8:
2327 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2328 break;
2329 case 15:
2330 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2331 break;
2332 case 16:
2333 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2334 break;
2335 case 32:
2336 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2337 break;
2338 }
2339 }
2340
2341 /***************************************
2342 *
2343 * LFB memory access
2344 *
2345 ***************************************/
2346
2347 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2348 {
2349 CirrusVGAState *s = opaque;
2350 uint32_t ret;
2351
2352 addr &= s->cirrus_addr_mask;
2353
2354 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2355 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2356 /* memory-mapped I/O */
2357 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2358 } else if (0) {
2359 /* XXX handle bitblt */
2360 ret = 0xff;
2361 } else {
2362 /* video memory */
2363 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2364 addr <<= 4;
2365 } else if (s->vga.gr[0x0B] & 0x02) {
2366 addr <<= 3;
2367 }
2368 addr &= s->cirrus_addr_mask;
2369 ret = *(s->vga.vram_ptr + addr);
2370 }
2371
2372 return ret;
2373 }
2374
2375 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2376 {
2377 uint32_t v;
2378 #ifdef TARGET_WORDS_BIGENDIAN
2379 v = cirrus_linear_readb(opaque, addr) << 8;
2380 v |= cirrus_linear_readb(opaque, addr + 1);
2381 #else
2382 v = cirrus_linear_readb(opaque, addr);
2383 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2384 #endif
2385 return v;
2386 }
2387
2388 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2389 {
2390 uint32_t v;
2391 #ifdef TARGET_WORDS_BIGENDIAN
2392 v = cirrus_linear_readb(opaque, addr) << 24;
2393 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2394 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2395 v |= cirrus_linear_readb(opaque, addr + 3);
2396 #else
2397 v = cirrus_linear_readb(opaque, addr);
2398 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2399 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2400 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2401 #endif
2402 return v;
2403 }
2404
2405 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2406 uint32_t val)
2407 {
2408 CirrusVGAState *s = opaque;
2409 unsigned mode;
2410
2411 addr &= s->cirrus_addr_mask;
2412
2413 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2414 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2415 /* memory-mapped I/O */
2416 cirrus_mmio_blt_write(s, addr & 0xff, val);
2417 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2418 /* bitblt */
2419 *s->cirrus_srcptr++ = (uint8_t) val;
2420 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2421 cirrus_bitblt_cputovideo_next(s);
2422 }
2423 } else {
2424 /* video memory */
2425 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2426 addr <<= 4;
2427 } else if (s->vga.gr[0x0B] & 0x02) {
2428 addr <<= 3;
2429 }
2430 addr &= s->cirrus_addr_mask;
2431
2432 mode = s->vga.gr[0x05] & 0x7;
2433 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2434 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2435 cpu_physical_memory_set_dirty(s->vga.vram_offset + addr);
2436 } else {
2437 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2438 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2439 } else {
2440 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2441 }
2442 }
2443 }
2444 }
2445
2446 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2447 uint32_t val)
2448 {
2449 #ifdef TARGET_WORDS_BIGENDIAN
2450 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2451 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2452 #else
2453 cirrus_linear_writeb(opaque, addr, val & 0xff);
2454 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2455 #endif
2456 }
2457
2458 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2459 uint32_t val)
2460 {
2461 #ifdef TARGET_WORDS_BIGENDIAN
2462 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2463 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2464 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2465 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2466 #else
2467 cirrus_linear_writeb(opaque, addr, val & 0xff);
2468 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2469 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2470 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2471 #endif
2472 }
2473
2474
2475 static CPUReadMemoryFunc * const cirrus_linear_read[3] = {
2476 cirrus_linear_readb,
2477 cirrus_linear_readw,
2478 cirrus_linear_readl,
2479 };
2480
2481 static CPUWriteMemoryFunc * const cirrus_linear_write[3] = {
2482 cirrus_linear_writeb,
2483 cirrus_linear_writew,
2484 cirrus_linear_writel,
2485 };
2486
2487 /***************************************
2488 *
2489 * system to screen memory access
2490 *
2491 ***************************************/
2492
2493
2494 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2495 {
2496 uint32_t ret;
2497
2498 /* XXX handle bitblt */
2499 ret = 0xff;
2500 return ret;
2501 }
2502
2503 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2504 {
2505 uint32_t v;
2506 #ifdef TARGET_WORDS_BIGENDIAN
2507 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2508 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2509 #else
2510 v = cirrus_linear_bitblt_readb(opaque, addr);
2511 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2512 #endif
2513 return v;
2514 }
2515
2516 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2517 {
2518 uint32_t v;
2519 #ifdef TARGET_WORDS_BIGENDIAN
2520 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2521 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2522 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2523 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2524 #else
2525 v = cirrus_linear_bitblt_readb(opaque, addr);
2526 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2527 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2528 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2529 #endif
2530 return v;
2531 }
2532
2533 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2534 uint32_t val)
2535 {
2536 CirrusVGAState *s = opaque;
2537
2538 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2539 /* bitblt */
2540 *s->cirrus_srcptr++ = (uint8_t) val;
2541 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2542 cirrus_bitblt_cputovideo_next(s);
2543 }
2544 }
2545 }
2546
2547 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2548 uint32_t val)
2549 {
2550 #ifdef TARGET_WORDS_BIGENDIAN
2551 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2552 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2553 #else
2554 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2555 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2556 #endif
2557 }
2558
2559 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2560 uint32_t val)
2561 {
2562 #ifdef TARGET_WORDS_BIGENDIAN
2563 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2564 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2565 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2566 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2567 #else
2568 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2569 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2570 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2571 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2572 #endif
2573 }
2574
2575
2576 static CPUReadMemoryFunc * const cirrus_linear_bitblt_read[3] = {
2577 cirrus_linear_bitblt_readb,
2578 cirrus_linear_bitblt_readw,
2579 cirrus_linear_bitblt_readl,
2580 };
2581
2582 static CPUWriteMemoryFunc * const cirrus_linear_bitblt_write[3] = {
2583 cirrus_linear_bitblt_writeb,
2584 cirrus_linear_bitblt_writew,
2585 cirrus_linear_bitblt_writel,
2586 };
2587
2588 static void map_linear_vram(CirrusVGAState *s)
2589 {
2590 if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
2591 s->vga.map_addr = s->vga.lfb_addr;
2592 s->vga.map_end = s->vga.lfb_end;
2593 cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset);
2594 }
2595
2596 if (!s->vga.map_addr)
2597 return;
2598
2599 s->vga.lfb_vram_mapped = 0;
2600
2601 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2602 && !((s->vga.sr[0x07] & 0x01) == 0)
2603 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2604 && !(s->vga.gr[0x0B] & 0x02)) {
2605
2606 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2607 (s->vga.vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2608 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2609 (s->vga.vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2610
2611 s->vga.lfb_vram_mapped = 1;
2612 }
2613 else {
2614 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2615 s->vga.vga_io_memory);
2616 }
2617
2618 vga_dirty_log_start(&s->vga);
2619 }
2620
2621 static void unmap_linear_vram(CirrusVGAState *s)
2622 {
2623 if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end)
2624 s->vga.map_addr = s->vga.map_end = 0;
2625
2626 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2627 s->vga.vga_io_memory);
2628 }
2629
2630 /* Compute the memory access functions */
2631 static void cirrus_update_memory_access(CirrusVGAState *s)
2632 {
2633 unsigned mode;
2634
2635 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2636 goto generic_io;
2637 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2638 goto generic_io;
2639 } else {
2640 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2641 goto generic_io;
2642 } else if (s->vga.gr[0x0B] & 0x02) {
2643 goto generic_io;
2644 }
2645
2646 mode = s->vga.gr[0x05] & 0x7;
2647 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2648 map_linear_vram(s);
2649 } else {
2650 generic_io:
2651 unmap_linear_vram(s);
2652 }
2653 }
2654 }
2655
2656
2657 /* I/O ports */
2658
2659 static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr)
2660 {
2661 CirrusVGAState *c = opaque;
2662 VGACommonState *s = &c->vga;
2663 int val, index;
2664
2665 if (vga_ioport_invalid(s, addr)) {
2666 val = 0xff;
2667 } else {
2668 switch (addr) {
2669 case 0x3c0:
2670 if (s->ar_flip_flop == 0) {
2671 val = s->ar_index;
2672 } else {
2673 val = 0;
2674 }
2675 break;
2676 case 0x3c1:
2677 index = s->ar_index & 0x1f;
2678 if (index < 21)
2679 val = s->ar[index];
2680 else
2681 val = 0;
2682 break;
2683 case 0x3c2:
2684 val = s->st00;
2685 break;
2686 case 0x3c4:
2687 val = s->sr_index;
2688 break;
2689 case 0x3c5:
2690 if (cirrus_hook_read_sr(c, s->sr_index, &val))
2691 break;
2692 val = s->sr[s->sr_index];
2693 #ifdef DEBUG_VGA_REG
2694 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2695 #endif
2696 break;
2697 case 0x3c6:
2698 cirrus_read_hidden_dac(c, &val);
2699 break;
2700 case 0x3c7:
2701 val = s->dac_state;
2702 break;
2703 case 0x3c8:
2704 val = s->dac_write_index;
2705 c->cirrus_hidden_dac_lockindex = 0;
2706 break;
2707 case 0x3c9:
2708 if (cirrus_hook_read_palette(c, &val))
2709 break;
2710 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2711 if (++s->dac_sub_index == 3) {
2712 s->dac_sub_index = 0;
2713 s->dac_read_index++;
2714 }
2715 break;
2716 case 0x3ca:
2717 val = s->fcr;
2718 break;
2719 case 0x3cc:
2720 val = s->msr;
2721 break;
2722 case 0x3ce:
2723 val = s->gr_index;
2724 break;
2725 case 0x3cf:
2726 if (cirrus_hook_read_gr(c, s->gr_index, &val))
2727 break;
2728 val = s->gr[s->gr_index];
2729 #ifdef DEBUG_VGA_REG
2730 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2731 #endif
2732 break;
2733 case 0x3b4:
2734 case 0x3d4:
2735 val = s->cr_index;
2736 break;
2737 case 0x3b5:
2738 case 0x3d5:
2739 if (cirrus_hook_read_cr(c, s->cr_index, &val))
2740 break;
2741 val = s->cr[s->cr_index];
2742 #ifdef DEBUG_VGA_REG
2743 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2744 #endif
2745 break;
2746 case 0x3ba:
2747 case 0x3da:
2748 /* just toggle to fool polling */
2749 val = s->st01 = s->retrace(s);
2750 s->ar_flip_flop = 0;
2751 break;
2752 default:
2753 val = 0x00;
2754 break;
2755 }
2756 }
2757 #if defined(DEBUG_VGA)
2758 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2759 #endif
2760 return val;
2761 }
2762
2763 static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2764 {
2765 CirrusVGAState *c = opaque;
2766 VGACommonState *s = &c->vga;
2767 int index;
2768
2769 /* check port range access depending on color/monochrome mode */
2770 if (vga_ioport_invalid(s, addr)) {
2771 return;
2772 }
2773 #ifdef DEBUG_VGA
2774 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2775 #endif
2776
2777 switch (addr) {
2778 case 0x3c0:
2779 if (s->ar_flip_flop == 0) {
2780 val &= 0x3f;
2781 s->ar_index = val;
2782 } else {
2783 index = s->ar_index & 0x1f;
2784 switch (index) {
2785 case 0x00 ... 0x0f:
2786 s->ar[index] = val & 0x3f;
2787 break;
2788 case 0x10:
2789 s->ar[index] = val & ~0x10;
2790 break;
2791 case 0x11:
2792 s->ar[index] = val;
2793 break;
2794 case 0x12:
2795 s->ar[index] = val & ~0xc0;
2796 break;
2797 case 0x13:
2798 s->ar[index] = val & ~0xf0;
2799 break;
2800 case 0x14:
2801 s->ar[index] = val & ~0xf0;
2802 break;
2803 default:
2804 break;
2805 }
2806 }
2807 s->ar_flip_flop ^= 1;
2808 break;
2809 case 0x3c2:
2810 s->msr = val & ~0x10;
2811 s->update_retrace_info(s);
2812 break;
2813 case 0x3c4:
2814 s->sr_index = val;
2815 break;
2816 case 0x3c5:
2817 if (cirrus_hook_write_sr(c, s->sr_index, val))
2818 break;
2819 #ifdef DEBUG_VGA_REG
2820 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2821 #endif
2822 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2823 if (s->sr_index == 1) s->update_retrace_info(s);
2824 break;
2825 case 0x3c6:
2826 cirrus_write_hidden_dac(c, val);
2827 break;
2828 case 0x3c7:
2829 s->dac_read_index = val;
2830 s->dac_sub_index = 0;
2831 s->dac_state = 3;
2832 break;
2833 case 0x3c8:
2834 s->dac_write_index = val;
2835 s->dac_sub_index = 0;
2836 s->dac_state = 0;
2837 break;
2838 case 0x3c9:
2839 if (cirrus_hook_write_palette(c, val))
2840 break;
2841 s->dac_cache[s->dac_sub_index] = val;
2842 if (++s->dac_sub_index == 3) {
2843 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2844 s->dac_sub_index = 0;
2845 s->dac_write_index++;
2846 }
2847 break;
2848 case 0x3ce:
2849 s->gr_index = val;
2850 break;
2851 case 0x3cf:
2852 if (cirrus_hook_write_gr(c, s->gr_index, val))
2853 break;
2854 #ifdef DEBUG_VGA_REG
2855 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2856 #endif
2857 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2858 break;
2859 case 0x3b4:
2860 case 0x3d4:
2861 s->cr_index = val;
2862 break;
2863 case 0x3b5:
2864 case 0x3d5:
2865 if (cirrus_hook_write_cr(c, s->cr_index, val))
2866 break;
2867 #ifdef DEBUG_VGA_REG
2868 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2869 #endif
2870 /* handle CR0-7 protection */
2871 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2872 /* can always write bit 4 of CR7 */
2873 if (s->cr_index == 7)
2874 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2875 return;
2876 }
2877 switch (s->cr_index) {
2878 case 0x01: /* horizontal display end */
2879 case 0x07:
2880 case 0x09:
2881 case 0x0c:
2882 case 0x0d:
2883 case 0x12: /* vertical display end */
2884 s->cr[s->cr_index] = val;
2885 break;
2886
2887 default:
2888 s->cr[s->cr_index] = val;
2889 break;
2890 }
2891
2892 switch(s->cr_index) {
2893 case 0x00:
2894 case 0x04:
2895 case 0x05:
2896 case 0x06:
2897 case 0x07:
2898 case 0x11:
2899 case 0x17:
2900 s->update_retrace_info(s);
2901 break;
2902 }
2903 break;
2904 case 0x3ba:
2905 case 0x3da:
2906 s->fcr = val & 0x10;
2907 break;
2908 }
2909 }
2910
2911 /***************************************
2912 *
2913 * memory-mapped I/O access
2914 *
2915 ***************************************/
2916
2917 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2918 {
2919 CirrusVGAState *s = opaque;
2920
2921 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2922
2923 if (addr >= 0x100) {
2924 return cirrus_mmio_blt_read(s, addr - 0x100);
2925 } else {
2926 return cirrus_vga_ioport_read(s, addr + 0x3c0);
2927 }
2928 }
2929
2930 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2931 {
2932 uint32_t v;
2933 #ifdef TARGET_WORDS_BIGENDIAN
2934 v = cirrus_mmio_readb(opaque, addr) << 8;
2935 v |= cirrus_mmio_readb(opaque, addr + 1);
2936 #else
2937 v = cirrus_mmio_readb(opaque, addr);
2938 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2939 #endif
2940 return v;
2941 }
2942
2943 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2944 {
2945 uint32_t v;
2946 #ifdef TARGET_WORDS_BIGENDIAN
2947 v = cirrus_mmio_readb(opaque, addr) << 24;
2948 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2949 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2950 v |= cirrus_mmio_readb(opaque, addr + 3);
2951 #else
2952 v = cirrus_mmio_readb(opaque, addr);
2953 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2954 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2955 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2956 #endif
2957 return v;
2958 }
2959
2960 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2961 uint32_t val)
2962 {
2963 CirrusVGAState *s = opaque;
2964
2965 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2966
2967 if (addr >= 0x100) {
2968 cirrus_mmio_blt_write(s, addr - 0x100, val);
2969 } else {
2970 cirrus_vga_ioport_write(s, addr + 0x3c0, val);
2971 }
2972 }
2973
2974 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
2975 uint32_t val)
2976 {
2977 #ifdef TARGET_WORDS_BIGENDIAN
2978 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2979 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2980 #else
2981 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2982 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2983 #endif
2984 }
2985
2986 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
2987 uint32_t val)
2988 {
2989 #ifdef TARGET_WORDS_BIGENDIAN
2990 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2991 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2992 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2993 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2994 #else
2995 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2996 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2997 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2998 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2999 #endif
3000 }
3001
3002
3003 static CPUReadMemoryFunc * const cirrus_mmio_read[3] = {
3004 cirrus_mmio_readb,
3005 cirrus_mmio_readw,
3006 cirrus_mmio_readl,
3007 };
3008
3009 static CPUWriteMemoryFunc * const cirrus_mmio_write[3] = {
3010 cirrus_mmio_writeb,
3011 cirrus_mmio_writew,
3012 cirrus_mmio_writel,
3013 };
3014
3015 /* load/save state */
3016
3017 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3018 {
3019 CirrusVGAState *s = opaque;
3020
3021 qemu_put_be32s(f, &s->vga.latch);
3022 qemu_put_8s(f, &s->vga.sr_index);
3023 qemu_put_buffer(f, s->vga.sr, 256);
3024 qemu_put_8s(f, &s->vga.gr_index);
3025 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3026 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3027 qemu_put_buffer(f, s->vga.gr + 2, 254);
3028 qemu_put_8s(f, &s->vga.ar_index);
3029 qemu_put_buffer(f, s->vga.ar, 21);
3030 qemu_put_be32(f, s->vga.ar_flip_flop);
3031 qemu_put_8s(f, &s->vga.cr_index);
3032 qemu_put_buffer(f, s->vga.cr, 256);
3033 qemu_put_8s(f, &s->vga.msr);
3034 qemu_put_8s(f, &s->vga.fcr);
3035 qemu_put_8s(f, &s->vga.st00);
3036 qemu_put_8s(f, &s->vga.st01);
3037
3038 qemu_put_8s(f, &s->vga.dac_state);
3039 qemu_put_8s(f, &s->vga.dac_sub_index);
3040 qemu_put_8s(f, &s->vga.dac_read_index);
3041 qemu_put_8s(f, &s->vga.dac_write_index);
3042 qemu_put_buffer(f, s->vga.dac_cache, 3);
3043 qemu_put_buffer(f, s->vga.palette, 768);
3044
3045 qemu_put_be32(f, s->vga.bank_offset);
3046
3047 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3048 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3049
3050 qemu_put_be32s(f, &s->hw_cursor_x);
3051 qemu_put_be32s(f, &s->hw_cursor_y);
3052 /* XXX: we do not save the bitblt state - we assume we do not save
3053 the state when the blitter is active */
3054 }
3055
3056 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3057 {
3058 CirrusVGAState *s = opaque;
3059
3060 if (version_id > 2)
3061 return -EINVAL;
3062
3063 qemu_get_be32s(f, &s->vga.latch);
3064 qemu_get_8s(f, &s->vga.sr_index);
3065 qemu_get_buffer(f, s->vga.sr, 256);
3066 qemu_get_8s(f, &s->vga.gr_index);
3067 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3068 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3069 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3070 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3071 qemu_get_buffer(f, s->vga.gr + 2, 254);
3072 qemu_get_8s(f, &s->vga.ar_index);
3073 qemu_get_buffer(f, s->vga.ar, 21);
3074 s->vga.ar_flip_flop=qemu_get_be32(f);
3075 qemu_get_8s(f, &s->vga.cr_index);
3076 qemu_get_buffer(f, s->vga.cr, 256);
3077 qemu_get_8s(f, &s->vga.msr);
3078 qemu_get_8s(f, &s->vga.fcr);
3079 qemu_get_8s(f, &s->vga.st00);
3080 qemu_get_8s(f, &s->vga.st01);
3081
3082 qemu_get_8s(f, &s->vga.dac_state);
3083 qemu_get_8s(f, &s->vga.dac_sub_index);
3084 qemu_get_8s(f, &s->vga.dac_read_index);
3085 qemu_get_8s(f, &s->vga.dac_write_index);
3086 qemu_get_buffer(f, s->vga.dac_cache, 3);
3087 qemu_get_buffer(f, s->vga.palette, 768);
3088
3089 s->vga.bank_offset = qemu_get_be32(f);
3090
3091 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3092 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3093
3094 qemu_get_be32s(f, &s->hw_cursor_x);
3095 qemu_get_be32s(f, &s->hw_cursor_y);
3096
3097 cirrus_update_memory_access(s);
3098 /* force refresh */
3099 s->vga.graphic_mode = -1;
3100 cirrus_update_bank_ptr(s, 0);
3101 cirrus_update_bank_ptr(s, 1);
3102 return 0;
3103 }
3104
3105 static void pci_cirrus_vga_save(QEMUFile *f, void *opaque)
3106 {
3107 PCICirrusVGAState *s = opaque;
3108
3109 pci_device_save(&s->dev, f);
3110 cirrus_vga_save(f, &s->cirrus_vga);
3111 }
3112
3113 static int pci_cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3114 {
3115 PCICirrusVGAState *s = opaque;
3116 int ret;
3117
3118 if (version_id > 2)
3119 return -EINVAL;
3120
3121 if (version_id >= 2) {
3122 ret = pci_device_load(&s->dev, f);
3123 if (ret < 0)
3124 return ret;
3125 }
3126
3127 return cirrus_vga_load(f, &s->cirrus_vga, version_id);
3128 }
3129
3130 /***************************************
3131 *
3132 * initialize
3133 *
3134 ***************************************/
3135
3136 static void cirrus_reset(void *opaque)
3137 {
3138 CirrusVGAState *s = opaque;
3139
3140 vga_common_reset(&s->vga);
3141 unmap_linear_vram(s);
3142 s->vga.sr[0x06] = 0x0f;
3143 if (s->device_id == CIRRUS_ID_CLGD5446) {
3144 /* 4MB 64 bit memory config, always PCI */
3145 s->vga.sr[0x1F] = 0x2d; // MemClock
3146 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
3147 s->vga.sr[0x0f] = 0x98;
3148 s->vga.sr[0x17] = 0x20;
3149 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3150 } else {
3151 s->vga.sr[0x1F] = 0x22; // MemClock
3152 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
3153 s->vga.sr[0x17] = s->bustype;
3154 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3155 }
3156 s->vga.cr[0x27] = s->device_id;
3157
3158 /* Win2K seems to assume that the pattern buffer is at 0xff
3159 initially ! */
3160 memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
3161
3162 s->cirrus_hidden_dac_lockindex = 5;
3163 s->cirrus_hidden_dac_data = 0;
3164 }
3165
3166 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3167 {
3168 int i;
3169 static int inited;
3170
3171 if (!inited) {
3172 inited = 1;
3173 for(i = 0;i < 256; i++)
3174 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3175 rop_to_index[CIRRUS_ROP_0] = 0;
3176 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3177 rop_to_index[CIRRUS_ROP_NOP] = 2;
3178 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3179 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3180 rop_to_index[CIRRUS_ROP_SRC] = 5;
3181 rop_to_index[CIRRUS_ROP_1] = 6;
3182 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3183 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3184 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3185 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3186 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3187 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3188 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3189 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3190 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3191 s->device_id = device_id;
3192 if (is_pci)
3193 s->bustype = CIRRUS_BUSTYPE_PCI;
3194 else
3195 s->bustype = CIRRUS_BUSTYPE_ISA;
3196 }
3197
3198 register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
3199
3200 register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
3201 register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
3202 register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
3203 register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s);
3204
3205 register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s);
3206
3207 register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s);
3208 register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s);
3209 register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
3210 register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
3211
3212 s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read,
3213 cirrus_vga_mem_write, s);
3214 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3215 s->vga.vga_io_memory);
3216 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3217
3218 /* I/O handler for LFB */
3219 s->cirrus_linear_io_addr =
3220 cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s);
3221
3222 /* I/O handler for LFB */
3223 s->cirrus_linear_bitblt_io_addr =
3224 cpu_register_io_memory(cirrus_linear_bitblt_read,
3225 cirrus_linear_bitblt_write, s);
3226
3227 /* I/O handler for memory-mapped I/O */
3228 s->cirrus_mmio_io_addr =
3229 cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s);
3230
3231 s->real_vram_size =
3232 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3233
3234 /* XXX: s->vga.vram_size must be a power of two */
3235 s->cirrus_addr_mask = s->real_vram_size - 1;
3236 s->linear_mmio_mask = s->real_vram_size - 256;
3237
3238 s->vga.get_bpp = cirrus_get_bpp;
3239 s->vga.get_offsets = cirrus_get_offsets;
3240 s->vga.get_resolution = cirrus_get_resolution;
3241 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
3242 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
3243
3244 qemu_register_reset(cirrus_reset, s);
3245 cirrus_reset(s);
3246 }
3247
3248 /***************************************
3249 *
3250 * ISA bus support
3251 *
3252 ***************************************/
3253
3254 void isa_cirrus_vga_init(void)
3255 {
3256 CirrusVGAState *s;
3257
3258 s = qemu_mallocz(sizeof(CirrusVGAState));
3259
3260 vga_common_init(&s->vga, VGA_RAM_SIZE);
3261 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3262 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3263 s->vga.screen_dump, s->vga.text_update,
3264 &s->vga);
3265 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3266 /* XXX ISA-LFB support */
3267 }
3268
3269 /***************************************
3270 *
3271 * PCI bus support
3272 *
3273 ***************************************/
3274
3275 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3276 uint32_t addr, uint32_t size, int type)
3277 {
3278 CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
3279
3280 /* XXX: add byte swapping apertures */
3281 cpu_register_physical_memory(addr, s->vga.vram_size,
3282 s->cirrus_linear_io_addr);
3283 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3284 s->cirrus_linear_bitblt_io_addr);
3285
3286 s->vga.map_addr = s->vga.map_end = 0;
3287 s->vga.lfb_addr = addr & TARGET_PAGE_MASK;
3288 s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3289 /* account for overflow */
3290 if (s->vga.lfb_end < addr + VGA_RAM_SIZE)
3291 s->vga.lfb_end = addr + VGA_RAM_SIZE;
3292
3293 vga_dirty_log_start(&s->vga);
3294 }
3295
3296 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3297 uint32_t addr, uint32_t size, int type)
3298 {
3299 CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
3300
3301 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3302 s->cirrus_mmio_io_addr);
3303 }
3304
3305 static void pci_cirrus_write_config(PCIDevice *d,
3306 uint32_t address, uint32_t val, int len)
3307 {
3308 PCICirrusVGAState *pvs = DO_UPCAST(PCICirrusVGAState, dev, d);
3309 CirrusVGAState *s = &pvs->cirrus_vga;
3310
3311 pci_default_write_config(d, address, val, len);
3312 if (s->vga.map_addr && d->io_regions[0].addr == -1)
3313 s->vga.map_addr = 0;
3314 cirrus_update_memory_access(s);
3315 }
3316
3317 static int pci_cirrus_vga_initfn(PCIDevice *dev)
3318 {
3319 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
3320 CirrusVGAState *s = &d->cirrus_vga;
3321 uint8_t *pci_conf = d->dev.config;
3322 int device_id = CIRRUS_ID_CLGD5446;
3323
3324 /* setup VGA */
3325 vga_common_init(&s->vga, VGA_RAM_SIZE);
3326 cirrus_init_common(s, device_id, 1);
3327 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3328 s->vga.screen_dump, s->vga.text_update,
3329 &s->vga);
3330
3331 /* setup PCI */
3332 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3333 pci_config_set_device_id(pci_conf, device_id);
3334 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3335 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
3336 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
3337
3338 /* setup memory space */
3339 /* memory #0 LFB */
3340 /* memory #1 memory-mapped I/O */
3341 /* XXX: s->vga.vram_size must be a power of two */
3342 pci_register_bar((PCIDevice *)d, 0, 0x2000000,
3343 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3344 if (device_id == CIRRUS_ID_CLGD5446) {
3345 pci_register_bar((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3346 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3347 }
3348 register_savevm("cirrus_vga", 0, 2, pci_cirrus_vga_save, pci_cirrus_vga_load, d);
3349 /* XXX: ROM BIOS */
3350 return 0;
3351 }
3352
3353 void pci_cirrus_vga_init(PCIBus *bus)
3354 {
3355 pci_create_simple(bus, -1, "Cirrus VGA");
3356 }
3357
3358 static PCIDeviceInfo cirrus_vga_info = {
3359 .qdev.name = "Cirrus VGA",
3360 .qdev.size = sizeof(PCICirrusVGAState),
3361 .init = pci_cirrus_vga_initfn,
3362 .config_write = pci_cirrus_write_config,
3363 };
3364
3365 static void cirrus_vga_register(void)
3366 {
3367 pci_qdev_register(&cirrus_vga_info);
3368 }
3369 device_init(cirrus_vga_register);
Qemu copy for testing