2 * Cortex-A9MPCore internal peripheral emulation.
4 * Copyright (c) 2009 CodeSourcery.
5 * Copyright (c) 2011 Linaro Limited.
6 * Written by Paul Brook, Peter Maydell.
8 * This code is licensed under the GPL.
11 #include "hw/cpu/a9mpcore.h"
13 static void a9mp_priv_set_irq(void *opaque
, int irq
, int level
)
15 A9MPPrivState
*s
= (A9MPPrivState
*)opaque
;
17 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s
->gic
), irq
), level
);
20 static void a9mp_priv_initfn(Object
*obj
)
22 A9MPPrivState
*s
= A9MPCORE_PRIV(obj
);
24 memory_region_init(&s
->container
, obj
, "a9mp-priv-container", 0x2000);
25 sysbus_init_mmio(SYS_BUS_DEVICE(obj
), &s
->container
);
27 object_initialize(&s
->gic
, sizeof(s
->gic
), TYPE_ARM_GIC
);
28 qdev_set_parent_bus(DEVICE(&s
->gic
), sysbus_get_default());
30 object_initialize(&s
->scu
, sizeof(s
->scu
), TYPE_A9_SCU
);
31 qdev_set_parent_bus(DEVICE(&s
->scu
), sysbus_get_default());
33 object_initialize(&s
->mptimer
, sizeof(s
->mptimer
), TYPE_ARM_MPTIMER
);
34 qdev_set_parent_bus(DEVICE(&s
->mptimer
), sysbus_get_default());
36 object_initialize(&s
->wdt
, sizeof(s
->wdt
), TYPE_ARM_MPTIMER
);
37 qdev_set_parent_bus(DEVICE(&s
->wdt
), sysbus_get_default());
40 static void a9mp_priv_realize(DeviceState
*dev
, Error
**errp
)
42 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
43 A9MPPrivState
*s
= A9MPCORE_PRIV(dev
);
44 DeviceState
*gicdev
, *scudev
, *mptimerdev
, *wdtdev
;
45 SysBusDevice
*timerbusdev
, *wdtbusdev
, *gicbusdev
, *scubusdev
;
49 gicdev
= DEVICE(&s
->gic
);
50 qdev_prop_set_uint32(gicdev
, "num-cpu", s
->num_cpu
);
51 qdev_prop_set_uint32(gicdev
, "num-irq", s
->num_irq
);
52 object_property_set_bool(OBJECT(&s
->gic
), true, "realized", &err
);
54 error_propagate(errp
, err
);
57 gicbusdev
= SYS_BUS_DEVICE(&s
->gic
);
59 /* Pass through outbound IRQ lines from the GIC */
60 sysbus_pass_irq(sbd
, gicbusdev
);
62 /* Pass through inbound GPIO lines to the GIC */
63 qdev_init_gpio_in(dev
, a9mp_priv_set_irq
, s
->num_irq
- 32);
65 scudev
= DEVICE(&s
->scu
);
66 qdev_prop_set_uint32(scudev
, "num-cpu", s
->num_cpu
);
67 object_property_set_bool(OBJECT(&s
->scu
), true, "realized", &err
);
69 error_propagate(errp
, err
);
72 scubusdev
= SYS_BUS_DEVICE(&s
->scu
);
74 mptimerdev
= DEVICE(&s
->mptimer
);
75 qdev_prop_set_uint32(mptimerdev
, "num-cpu", s
->num_cpu
);
76 object_property_set_bool(OBJECT(&s
->mptimer
), true, "realized", &err
);
78 error_propagate(errp
, err
);
81 timerbusdev
= SYS_BUS_DEVICE(&s
->mptimer
);
83 wdtdev
= DEVICE(&s
->wdt
);
84 qdev_prop_set_uint32(wdtdev
, "num-cpu", s
->num_cpu
);
85 object_property_set_bool(OBJECT(&s
->wdt
), true, "realized", &err
);
87 error_propagate(errp
, err
);
90 wdtbusdev
= SYS_BUS_DEVICE(&s
->wdt
);
92 /* Memory map (addresses are offsets from PERIPHBASE):
93 * 0x0000-0x00ff -- Snoop Control Unit
94 * 0x0100-0x01ff -- GIC CPU interface
95 * 0x0200-0x02ff -- Global Timer
96 * 0x0300-0x05ff -- nothing
97 * 0x0600-0x06ff -- private timers and watchdogs
98 * 0x0700-0x0fff -- nothing
99 * 0x1000-0x1fff -- GIC Distributor
101 * We should implement the global timer but don't currently do so.
103 memory_region_add_subregion(&s
->container
, 0,
104 sysbus_mmio_get_region(scubusdev
, 0));
105 /* GIC CPU interface */
106 memory_region_add_subregion(&s
->container
, 0x100,
107 sysbus_mmio_get_region(gicbusdev
, 1));
108 /* Note that the A9 exposes only the "timer/watchdog for this core"
109 * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
111 memory_region_add_subregion(&s
->container
, 0x600,
112 sysbus_mmio_get_region(timerbusdev
, 0));
113 memory_region_add_subregion(&s
->container
, 0x620,
114 sysbus_mmio_get_region(wdtbusdev
, 0));
115 memory_region_add_subregion(&s
->container
, 0x1000,
116 sysbus_mmio_get_region(gicbusdev
, 0));
118 /* Wire up the interrupt from each watchdog and timer.
119 * For each core the timer is PPI 29 and the watchdog PPI 30.
121 for (i
= 0; i
< s
->num_cpu
; i
++) {
122 int ppibase
= (s
->num_irq
- 32) + i
* 32;
123 sysbus_connect_irq(timerbusdev
, i
,
124 qdev_get_gpio_in(gicdev
, ppibase
+ 29));
125 sysbus_connect_irq(wdtbusdev
, i
,
126 qdev_get_gpio_in(gicdev
, ppibase
+ 30));
130 static Property a9mp_priv_properties
[] = {
131 DEFINE_PROP_UINT32("num-cpu", A9MPPrivState
, num_cpu
, 1),
132 /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
133 * IRQ lines (with another 32 internal). We default to 64+32, which
134 * is the number provided by the Cortex-A9MP test chip in the
135 * Realview PBX-A9 and Versatile Express A9 development boards.
136 * Other boards may differ and should set this property appropriately.
138 DEFINE_PROP_UINT32("num-irq", A9MPPrivState
, num_irq
, 96),
139 DEFINE_PROP_END_OF_LIST(),
142 static void a9mp_priv_class_init(ObjectClass
*klass
, void *data
)
144 DeviceClass
*dc
= DEVICE_CLASS(klass
);
146 dc
->realize
= a9mp_priv_realize
;
147 dc
->props
= a9mp_priv_properties
;
150 static const TypeInfo a9mp_priv_info
= {
151 .name
= TYPE_A9MPCORE_PRIV
,
152 .parent
= TYPE_SYS_BUS_DEVICE
,
153 .instance_size
= sizeof(A9MPPrivState
),
154 .instance_init
= a9mp_priv_initfn
,
155 .class_init
= a9mp_priv_class_init
,
158 static void a9mp_register_types(void)
160 type_register_static(&a9mp_priv_info
);
163 type_init(a9mp_register_types
)