hw/cris/axis_dev88.c

   1 /*
   2  * QEMU model for the AXIS devboard 88.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "net/net.h"
  27 #include "hw/block/flash.h"
  28 #include "hw/boards.h"
  29 #include "hw/cris/etraxfs.h"
  30 #include "hw/loader.h"
  31 #include "elf.h"
  32 #include "boot.h"
  33 #include "sysemu/blockdev.h"
  34 #include "exec/address-spaces.h"
  35 #include "sysemu/qtest.h"
  36
  37 #define D(x)
  38 #define DNAND(x)
  39
  40 struct nand_state_t
  41 {
  42     DeviceState *nand;
  43     MemoryRegion iomem;
  44     unsigned int rdy:1;
  45     unsigned int ale:1;
  46     unsigned int cle:1;
  47     unsigned int ce:1;
  48 };
  49
  50 static struct nand_state_t nand_state;
  51 static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
  52 {
  53     struct nand_state_t *s = opaque;
  54     uint32_t r;
  55     int rdy;
  56
  57     r = nand_getio(s->nand);
  58     nand_getpins(s->nand, &rdy);
  59     s->rdy = rdy;
  60
  61     DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
  62     return r;
  63 }
  64
  65 static void
  66 nand_write(void *opaque, hwaddr addr, uint64_t value,
  67            unsigned size)
  68 {
  69     struct nand_state_t *s = opaque;
  70     int rdy;
  71
  72     DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
  73     nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
  74     nand_setio(s->nand, value);
  75     nand_getpins(s->nand, &rdy);
  76     s->rdy = rdy;
  77 }
  78
  79 static const MemoryRegionOps nand_ops = {
  80     .read = nand_read,
  81     .write = nand_write,
  82     .endianness = DEVICE_NATIVE_ENDIAN,
  83 };
  84
  85 struct tempsensor_t
  86 {
  87     unsigned int shiftreg;
  88     unsigned int count;
  89     enum {
  90         ST_OUT, ST_IN, ST_Z
  91     } state;
  92
  93     uint16_t regs[3];
  94 };
  95
  96 static void tempsensor_clkedge(struct tempsensor_t *s,
  97                                unsigned int clk, unsigned int data_in)
  98 {
  99     D(printf("%s clk=%d state=%d sr=%x\n", __func__,
 100              clk, s->state, s->shiftreg));
 101     if (s->count == 0) {
 102         s->count = 16;
 103         s->state = ST_OUT;
 104     }
 105     switch (s->state) {
 106         case ST_OUT:
 107             /* Output reg is clocked at negedge.  */
 108             if (!clk) {
 109                 s->count--;
 110                 s->shiftreg <<= 1;
 111                 if (s->count == 0) {
 112                     s->shiftreg = 0;
 113                     s->state = ST_IN;
 114                     s->count = 16;
 115                 }
 116             }
 117             break;
 118         case ST_Z:
 119             if (clk) {
 120                 s->count--;
 121                 if (s->count == 0) {
 122                     s->shiftreg = 0;
 123                     s->state = ST_OUT;
 124                     s->count = 16;
 125                 }
 126             }
 127             break;
 128         case ST_IN:
 129             /* Indata is sampled at posedge.  */
 130             if (clk) {
 131                 s->count--;
 132                 s->shiftreg <<= 1;
 133                 s->shiftreg |= data_in & 1;
 134                 if (s->count == 0) {
 135                     D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
 136                     s->regs[0] = s->shiftreg;
 137                     s->state = ST_OUT;
 138                     s->count = 16;
 139
 140                     if ((s->regs[0] & 0xff) == 0) {
 141                         /* 25 degrees celcius.  */
 142                         s->shiftreg = 0x0b9f;
 143                     } else if ((s->regs[0] & 0xff) == 0xff) {
 144                         /* Sensor ID, 0x8100 LM70.  */
 145                         s->shiftreg = 0x8100;
 146                     } else
 147                         printf("Invalid tempsens state %x\n", s->regs[0]);
 148                 }
 149             }
 150             break;
 151     }
 152 }
 153
 154
 155 #define RW_PA_DOUT    0x00
 156 #define R_PA_DIN      0x01
 157 #define RW_PA_OE      0x02
 158 #define RW_PD_DOUT    0x10
 159 #define R_PD_DIN      0x11
 160 #define RW_PD_OE      0x12
 161
 162 static struct gpio_state_t
 163 {
 164     MemoryRegion iomem;
 165     struct nand_state_t *nand;
 166     struct tempsensor_t tempsensor;
 167     uint32_t regs[0x5c / 4];
 168 } gpio_state;
 169
 170 static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
 171 {
 172     struct gpio_state_t *s = opaque;
 173     uint32_t r = 0;
 174
 175     addr >>= 2;
 176     switch (addr)
 177     {
 178         case R_PA_DIN:
 179             r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
 180
 181             /* Encode pins from the nand.  */
 182             r |= s->nand->rdy << 7;
 183             break;
 184         case R_PD_DIN:
 185             r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
 186
 187             /* Encode temp sensor pins.  */
 188             r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
 189             break;
 190
 191         default:
 192             r = s->regs[addr];
 193             break;
 194     }
 195     return r;
 196     D(printf("%s %x=%x\n", __func__, addr, r));
 197 }
 198
 199 static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
 200                        unsigned size)
 201 {
 202     struct gpio_state_t *s = opaque;
 203     D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
 204
 205     addr >>= 2;
 206     switch (addr)
 207     {
 208         case RW_PA_DOUT:
 209             /* Decode nand pins.  */
 210             s->nand->ale = !!(value & (1 << 6));
 211             s->nand->cle = !!(value & (1 << 5));
 212             s->nand->ce  = !!(value & (1 << 4));
 213
 214             s->regs[addr] = value;
 215             break;
 216
 217         case RW_PD_DOUT:
 218             /* Temp sensor clk.  */
 219             if ((s->regs[addr] ^ value) & 2)
 220                 tempsensor_clkedge(&s->tempsensor, !!(value & 2),
 221                                    !!(value & 16));
 222             s->regs[addr] = value;
 223             break;
 224
 225         default:
 226             s->regs[addr] = value;
 227             break;
 228     }
 229 }
 230
 231 static const MemoryRegionOps gpio_ops = {
 232     .read = gpio_read,
 233     .write = gpio_write,
 234     .endianness = DEVICE_NATIVE_ENDIAN,
 235     .valid = {
 236         .min_access_size = 4,
 237         .max_access_size = 4,
 238     },
 239 };
 240
 241 #define INTMEM_SIZE (128 * 1024)
 242
 243 static struct cris_load_info li;
 244
 245 static
 246 void axisdev88_init(QEMUMachineInitArgs *args)
 247 {
 248     ram_addr_t ram_size = args->ram_size;
 249     const char *cpu_model = args->cpu_model;
 250     const char *kernel_filename = args->kernel_filename;
 251     const char *kernel_cmdline = args->kernel_cmdline;
 252     CRISCPU *cpu;
 253     CPUCRISState *env;
 254     DeviceState *dev;
 255     SysBusDevice *s;
 256     DriveInfo *nand;
 257     qemu_irq irq[30], nmi[2], *cpu_irq;
 258     void *etraxfs_dmac;
 259     struct etraxfs_dma_client *dma_eth;
 260     int i;
 261     MemoryRegion *address_space_mem = get_system_memory();
 262     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
 263     MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
 264
 265     /* init CPUs */
 266     if (cpu_model == NULL) {
 267         cpu_model = "crisv32";
 268     }
 269     cpu = cpu_cris_init(cpu_model);
 270     env = &cpu->env;
 271
 272     /* allocate RAM */
 273     memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size);
 274     vmstate_register_ram_global(phys_ram);
 275     memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
 276
 277     /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
 278        internal memory.  */
 279     memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE);
 280     vmstate_register_ram_global(phys_intmem);
 281     memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
 282
 283       /* Attach a NAND flash to CS1.  */
 284     nand = drive_get(IF_MTD, 0, 0);
 285     nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
 286                                 NAND_MFR_STMICRO, 0x39);
 287     memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
 288                           "nand", 0x05000000);
 289     memory_region_add_subregion(address_space_mem, 0x10000000,
 290                                 &nand_state.iomem);
 291
 292     gpio_state.nand = &nand_state;
 293     memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
 294                           "gpio", 0x5c);
 295     memory_region_add_subregion(address_space_mem, 0x3001a000,
 296                                 &gpio_state.iomem);
 297
 298
 299     cpu_irq = cris_pic_init_cpu(env);
 300     dev = qdev_create(NULL, "etraxfs,pic");
 301     /* FIXME: Is there a proper way to signal vectors to the CPU core?  */
 302     qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
 303     qdev_init_nofail(dev);
 304     s = SYS_BUS_DEVICE(dev);
 305     sysbus_mmio_map(s, 0, 0x3001c000);
 306     sysbus_connect_irq(s, 0, cpu_irq[0]);
 307     sysbus_connect_irq(s, 1, cpu_irq[1]);
 308     for (i = 0; i < 30; i++) {
 309         irq[i] = qdev_get_gpio_in(dev, i);
 310     }
 311     nmi[0] = qdev_get_gpio_in(dev, 30);
 312     nmi[1] = qdev_get_gpio_in(dev, 31);
 313
 314     etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
 315     for (i = 0; i < 10; i++) {
 316         /* On ETRAX, odd numbered channels are inputs.  */
 317         etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
 318     }
 319
 320     /* Add the two ethernet blocks.  */
 321     dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels.  */
 322     etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
 323     if (nb_nics > 1) {
 324         etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
 325     }
 326
 327     /* The DMA Connector block is missing, hardwire things for now.  */
 328     etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
 329     etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
 330     if (nb_nics > 1) {
 331         etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
 332         etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
 333     }
 334
 335     /* 2 timers.  */
 336     sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
 337     sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
 338
 339     for (i = 0; i < 4; i++) {
 340         sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
 341                              irq[0x14 + i]);
 342     }
 343
 344     if (kernel_filename) {
 345         li.image_filename = kernel_filename;
 346         li.cmdline = kernel_cmdline;
 347         cris_load_image(cpu, &li);
 348     } else if (!qtest_enabled()) {
 349         fprintf(stderr, "Kernel image must be specified\n");
 350         exit(1);
 351     }
 352 }
 353
 354 static QEMUMachine axisdev88_machine = {
 355     .name = "axis-dev88",
 356     .desc = "AXIS devboard 88",
 357     .init = axisdev88_init,
 358     .is_default = 1,
 359 };
 360
 361 static void axisdev88_machine_init(void)
 362 {
 363     qemu_register_machine(&axisdev88_machine);
 364 }
 365
 366 machine_init(axisdev88_machine_init);