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4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 //#define DEBUG_CUDA_PACKET
29 /* Bits in B data register: all active low */
30 #define TREQ 0x08 /* Transfer request (input) */
31 #define TACK 0x10 /* Transfer acknowledge (output) */
32 #define TIP 0x20 /* Transfer in progress (output) */
35 #define SR_CTRL 0x1c /* Shift register control bits */
36 #define SR_EXT 0x0c /* Shift on external clock */
37 #define SR_OUT 0x10 /* Shift out if 1 */
39 /* Bits in IFR and IER */
40 #define IER_SET 0x80 /* set bits in IER */
41 #define IER_CLR 0 /* clear bits in IER */
42 #define SR_INT 0x04 /* Shift register full/empty */
43 #define T1_INT 0x40 /* Timer 1 interrupt */
46 #define T1MODE 0xc0 /* Timer 1 mode */
47 #define T1MODE_CONT 0x40 /* continuous interrupts */
49 /* commands (1st byte) */
52 #define ERROR_PACKET 2
53 #define TIMER_PACKET 3
54 #define POWER_PACKET 4
55 #define MACIIC_PACKET 5
59 /* CUDA commands (2nd byte) */
60 #define CUDA_WARM_START 0x0
61 #define CUDA_AUTOPOLL 0x1
62 #define CUDA_GET_6805_ADDR 0x2
63 #define CUDA_GET_TIME 0x3
64 #define CUDA_GET_PRAM 0x7
65 #define CUDA_SET_6805_ADDR 0x8
66 #define CUDA_SET_TIME 0x9
67 #define CUDA_POWERDOWN 0xa
68 #define CUDA_POWERUP_TIME 0xb
69 #define CUDA_SET_PRAM 0xc
70 #define CUDA_MS_RESET 0xd
71 #define CUDA_SEND_DFAC 0xe
72 #define CUDA_BATTERY_SWAP_SENSE 0x10
73 #define CUDA_RESET_SYSTEM 0x11
74 #define CUDA_SET_IPL 0x12
75 #define CUDA_FILE_SERVER_FLAG 0x13
76 #define CUDA_SET_AUTO_RATE 0x14
77 #define CUDA_GET_AUTO_RATE 0x16
78 #define CUDA_SET_DEVICE_LIST 0x19
79 #define CUDA_GET_DEVICE_LIST 0x1a
80 #define CUDA_SET_ONE_SECOND_MODE 0x1b
81 #define CUDA_SET_POWER_MESSAGES 0x21
82 #define CUDA_GET_SET_IIC 0x22
83 #define CUDA_WAKEUP 0x23
84 #define CUDA_TIMER_TICKLE 0x24
85 #define CUDA_COMBINED_FORMAT_IIC 0x25
87 #define CUDA_TIMER_FREQ (4700000 / 6)
88 #define CUDA_ADB_POLL_FREQ 50
90 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
91 #define RTC_OFFSET 2082844800
93 typedef struct CUDATimer
{
95 uint16_t counter_value
; /* counter value at load time */
97 int64_t next_irq_time
;
101 typedef struct CUDAState
{
103 uint8_t b
; /* B-side data */
104 uint8_t a
; /* A-side data */
105 uint8_t dirb
; /* B-side direction (1=output) */
106 uint8_t dira
; /* A-side direction (1=output) */
107 uint8_t sr
; /* Shift register */
108 uint8_t acr
; /* Auxiliary control register */
109 uint8_t pcr
; /* Peripheral control register */
110 uint8_t ifr
; /* Interrupt flag register */
111 uint8_t ier
; /* Interrupt enable register */
112 uint8_t anh
; /* A-side data, no handshake */
116 uint8_t last_b
; /* last value of B register */
117 uint8_t last_acr
; /* last value of B register */
127 uint8_t data_in
[128];
128 uint8_t data_out
[16];
129 QEMUTimer
*adb_poll_timer
;
132 static CUDAState cuda_state
;
135 static void cuda_update(CUDAState
*s
);
136 static void cuda_receive_packet_from_host(CUDAState
*s
,
137 const uint8_t *data
, int len
);
138 static void cuda_timer_update(CUDAState
*s
, CUDATimer
*ti
,
139 int64_t current_time
);
141 static void cuda_update_irq(CUDAState
*s
)
143 if (s
->ifr
& s
->ier
& (SR_INT
| T1_INT
)) {
144 s
->set_irq(s
->irq_opaque
, s
->irq
, 1);
146 s
->set_irq(s
->irq_opaque
, s
->irq
, 0);
150 static unsigned int get_counter(CUDATimer
*s
)
153 unsigned int counter
;
155 d
= muldiv64(qemu_get_clock(vm_clock
) - s
->load_time
,
156 CUDA_TIMER_FREQ
, ticks_per_sec
);
157 if (d
<= s
->counter_value
) {
160 counter
= s
->latch
- 1 - ((d
- s
->counter_value
) % s
->latch
);
165 static void set_counter(CUDAState
*s
, CUDATimer
*ti
, unsigned int val
)
168 printf("cuda: T%d.counter=%d\n",
169 1 + (ti
->timer
== NULL
), val
);
171 ti
->load_time
= qemu_get_clock(vm_clock
);
172 ti
->counter_value
= val
;
173 cuda_timer_update(s
, ti
, ti
->load_time
);
176 static int64_t get_next_irq_time(CUDATimer
*s
, int64_t current_time
)
178 int64_t d
, next_time
, base
;
179 /* current counter value */
180 d
= muldiv64(current_time
- s
->load_time
,
181 CUDA_TIMER_FREQ
, ticks_per_sec
);
182 if (d
< s
->counter_value
) {
183 next_time
= s
->counter_value
+ 1;
186 base
= ((d
- s
->counter_value
+ 1) / s
->latch
);
187 base
= (base
* s
->latch
) + s
->counter_value
;
188 next_time
= base
+ s
->latch
;
192 printf("latch=%d counter=%lld delta_next=%lld\n",
193 s
->latch
, d
, next_time
- d
);
196 next_time
= muldiv64(next_time
, ticks_per_sec
, CUDA_TIMER_FREQ
) +
198 if (next_time
<= current_time
)
199 next_time
= current_time
+ 1;
203 static void cuda_timer_update(CUDAState
*s
, CUDATimer
*ti
,
204 int64_t current_time
)
208 if ((s
->acr
& T1MODE
) != T1MODE_CONT
) {
209 qemu_del_timer(ti
->timer
);
211 ti
->next_irq_time
= get_next_irq_time(ti
, current_time
);
212 qemu_mod_timer(ti
->timer
, ti
->next_irq_time
);
216 static void cuda_timer1(void *opaque
)
218 CUDAState
*s
= opaque
;
219 CUDATimer
*ti
= &s
->timers
[0];
221 cuda_timer_update(s
, ti
, ti
->next_irq_time
);
226 static uint32_t cuda_readb(void *opaque
, target_phys_addr_t addr
)
228 CUDAState
*s
= opaque
;
231 addr
= (addr
>> 9) & 0xf;
246 val
= get_counter(&s
->timers
[0]) & 0xff;
251 val
= get_counter(&s
->timers
[0]) >> 8;
256 val
= s
->timers
[0].latch
& 0xff;
259 val
= (s
->timers
[0].latch
>> 8) & 0xff;
262 val
= get_counter(&s
->timers
[1]) & 0xff;
265 val
= get_counter(&s
->timers
[1]) >> 8;
290 if (addr
!= 13 || val
!= 0)
291 printf("cuda: read: reg=0x%x val=%02x\n", addr
, val
);
296 static void cuda_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
298 CUDAState
*s
= opaque
;
300 addr
= (addr
>> 9) & 0xf;
302 printf("cuda: write: reg=0x%x val=%02x\n", addr
, val
);
320 val
= val
| (get_counter(&s
->timers
[0]) & 0xff00);
321 set_counter(s
, &s
->timers
[0], val
);
324 val
= (val
<< 8) | (get_counter(&s
->timers
[0]) & 0xff);
325 set_counter(s
, &s
->timers
[0], val
);
328 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff00) | val
;
329 cuda_timer_update(s
, &s
->timers
[0], qemu_get_clock(vm_clock
));
332 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff) | (val
<< 8);
333 cuda_timer_update(s
, &s
->timers
[0], qemu_get_clock(vm_clock
));
336 val
= val
| (get_counter(&s
->timers
[1]) & 0xff00);
337 set_counter(s
, &s
->timers
[1], val
);
340 val
= (val
<< 8) | (get_counter(&s
->timers
[1]) & 0xff);
341 set_counter(s
, &s
->timers
[1], val
);
348 cuda_timer_update(s
, &s
->timers
[0], qemu_get_clock(vm_clock
));
363 s
->ier
|= val
& 0x7f;
369 /* XXX: please explain me why the SPEC is not correct ! */
381 /* NOTE: TIP and TREQ are negated */
382 static void cuda_update(CUDAState
*s
)
384 int packet_received
, len
;
388 /* transfer requested from host */
390 if (s
->acr
& SR_OUT
) {
392 if ((s
->b
& (TACK
| TIP
)) != (s
->last_b
& (TACK
| TIP
))) {
393 if (s
->data_out_index
< sizeof(s
->data_out
)) {
395 printf("cuda: send: %02x\n", s
->sr
);
397 s
->data_out
[s
->data_out_index
++] = s
->sr
;
403 if (s
->data_in_index
< s
->data_in_size
) {
405 if ((s
->b
& (TACK
| TIP
)) != (s
->last_b
& (TACK
| TIP
))) {
406 s
->sr
= s
->data_in
[s
->data_in_index
++];
408 printf("cuda: recv: %02x\n", s
->sr
);
410 /* indicate end of transfer */
411 if (s
->data_in_index
>= s
->data_in_size
) {
412 s
->b
= (s
->b
| TREQ
);
420 /* no transfer requested: handle sync case */
421 if ((s
->last_b
& TIP
) && (s
->b
& TACK
) != (s
->last_b
& TACK
)) {
422 /* update TREQ state each time TACK change state */
424 s
->b
= (s
->b
| TREQ
);
426 s
->b
= (s
->b
& ~TREQ
);
430 if (!(s
->last_b
& TIP
)) {
431 /* handle end of host to cuda transfert */
432 packet_received
= (s
->data_out_index
> 0);
433 /* always an IRQ at the end of transfert */
437 /* signal if there is data to read */
438 if (s
->data_in_index
< s
->data_in_size
) {
439 s
->b
= (s
->b
& ~TREQ
);
444 s
->last_acr
= s
->acr
;
447 /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
449 if (packet_received
) {
450 len
= s
->data_out_index
;
451 s
->data_out_index
= 0;
452 cuda_receive_packet_from_host(s
, s
->data_out
, len
);
456 static void cuda_send_packet_to_host(CUDAState
*s
,
457 const uint8_t *data
, int len
)
459 #ifdef DEBUG_CUDA_PACKET
462 printf("cuda_send_packet_to_host:\n");
463 for(i
= 0; i
< len
; i
++)
464 printf(" %02x", data
[i
]);
468 memcpy(s
->data_in
, data
, len
);
469 s
->data_in_size
= len
;
470 s
->data_in_index
= 0;
476 static void cuda_adb_poll(void *opaque
)
478 CUDAState
*s
= opaque
;
479 uint8_t obuf
[ADB_MAX_OUT_LEN
+ 2];
482 olen
= adb_poll(&adb_bus
, obuf
+ 2);
484 obuf
[0] = ADB_PACKET
;
485 obuf
[1] = 0x40; /* polled data */
486 cuda_send_packet_to_host(s
, obuf
, olen
+ 2);
488 qemu_mod_timer(s
->adb_poll_timer
,
489 qemu_get_clock(vm_clock
) +
490 (ticks_per_sec
/ CUDA_ADB_POLL_FREQ
));
493 static void cuda_receive_packet(CUDAState
*s
,
494 const uint8_t *data
, int len
)
501 autopoll
= (data
[1] != 0);
502 if (autopoll
!= s
->autopoll
) {
503 s
->autopoll
= autopoll
;
505 qemu_mod_timer(s
->adb_poll_timer
,
506 qemu_get_clock(vm_clock
) +
507 (ticks_per_sec
/ CUDA_ADB_POLL_FREQ
));
509 qemu_del_timer(s
->adb_poll_timer
);
512 obuf
[0] = CUDA_PACKET
;
514 cuda_send_packet_to_host(s
, obuf
, 2);
518 /* XXX: add time support ? */
519 ti
= time(NULL
) + RTC_OFFSET
;
520 obuf
[0] = CUDA_PACKET
;
527 cuda_send_packet_to_host(s
, obuf
, 7);
529 case CUDA_FILE_SERVER_FLAG
:
530 case CUDA_SET_DEVICE_LIST
:
531 case CUDA_SET_AUTO_RATE
:
532 case CUDA_SET_POWER_MESSAGES
:
533 obuf
[0] = CUDA_PACKET
;
535 cuda_send_packet_to_host(s
, obuf
, 2);
538 obuf
[0] = CUDA_PACKET
;
540 cuda_send_packet_to_host(s
, obuf
, 2);
541 qemu_system_shutdown_request();
548 static void cuda_receive_packet_from_host(CUDAState
*s
,
549 const uint8_t *data
, int len
)
551 #ifdef DEBUG_CUDA_PACKET
554 printf("cuda_receive_packet_from_host:\n");
555 for(i
= 0; i
< len
; i
++)
556 printf(" %02x", data
[i
]);
563 uint8_t obuf
[ADB_MAX_OUT_LEN
+ 2];
565 olen
= adb_request(&adb_bus
, obuf
+ 2, data
+ 1, len
- 1);
567 obuf
[0] = ADB_PACKET
;
571 obuf
[0] = ADB_PACKET
;
575 cuda_send_packet_to_host(s
, obuf
, olen
+ 2);
579 cuda_receive_packet(s
, data
+ 1, len
- 1);
584 static void cuda_writew (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
588 static void cuda_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
592 static uint32_t cuda_readw (void *opaque
, target_phys_addr_t addr
)
597 static uint32_t cuda_readl (void *opaque
, target_phys_addr_t addr
)
602 static CPUWriteMemoryFunc
*cuda_write
[] = {
608 static CPUReadMemoryFunc
*cuda_read
[] = {
614 int cuda_init(SetIRQFunc
*set_irq
, void *irq_opaque
, int irq
)
616 CUDAState
*s
= &cuda_state
;
619 s
->set_irq
= set_irq
;
620 s
->irq_opaque
= irq_opaque
;
623 s
->timers
[0].timer
= qemu_new_timer(vm_clock
, cuda_timer1
, s
);
624 s
->timers
[0].latch
= 0x10000;
625 set_counter(s
, &s
->timers
[0], 0xffff);
626 s
->timers
[1].latch
= 0x10000;
627 // s->ier = T1_INT | SR_INT;
629 set_counter(s
, &s
->timers
[1], 0xffff);
631 s
->adb_poll_timer
= qemu_new_timer(vm_clock
, cuda_adb_poll
, s
);
632 cuda_mem_index
= cpu_register_io_memory(0, cuda_read
, cuda_write
, s
);
633 return cuda_mem_index
;