hw/cuda.c

   1 /*
   2  * QEMU CUDA support
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 //#define DEBUG_CUDA
  27 //#define DEBUG_CUDA_PACKET
  28
  29 /* Bits in B data register: all active low */
  30 #define TREQ            0x08            /* Transfer request (input) */
  31 #define TACK            0x10            /* Transfer acknowledge (output) */
  32 #define TIP             0x20            /* Transfer in progress (output) */
  33
  34 /* Bits in ACR */
  35 #define SR_CTRL         0x1c            /* Shift register control bits */
  36 #define SR_EXT          0x0c            /* Shift on external clock */
  37 #define SR_OUT          0x10            /* Shift out if 1 */
  38
  39 /* Bits in IFR and IER */
  40 #define IER_SET         0x80            /* set bits in IER */
  41 #define IER_CLR         0               /* clear bits in IER */
  42 #define SR_INT          0x04            /* Shift register full/empty */
  43 #define T1_INT          0x40            /* Timer 1 interrupt */
  44
  45 /* Bits in ACR */
  46 #define T1MODE          0xc0            /* Timer 1 mode */
  47 #define T1MODE_CONT     0x40            /*  continuous interrupts */
  48
  49 /* commands (1st byte) */
  50 #define ADB_PACKET      0
  51 #define CUDA_PACKET     1
  52 #define ERROR_PACKET    2
  53 #define TIMER_PACKET    3
  54 #define POWER_PACKET    4
  55 #define MACIIC_PACKET   5
  56 #define PMU_PACKET      6
  57
  58
  59 /* CUDA commands (2nd byte) */
  60 #define CUDA_WARM_START                 0x0
  61 #define CUDA_AUTOPOLL                   0x1
  62 #define CUDA_GET_6805_ADDR              0x2
  63 #define CUDA_GET_TIME                   0x3
  64 #define CUDA_GET_PRAM                   0x7
  65 #define CUDA_SET_6805_ADDR              0x8
  66 #define CUDA_SET_TIME                   0x9
  67 #define CUDA_POWERDOWN                  0xa
  68 #define CUDA_POWERUP_TIME               0xb
  69 #define CUDA_SET_PRAM                   0xc
  70 #define CUDA_MS_RESET                   0xd
  71 #define CUDA_SEND_DFAC                  0xe
  72 #define CUDA_BATTERY_SWAP_SENSE         0x10
  73 #define CUDA_RESET_SYSTEM               0x11
  74 #define CUDA_SET_IPL                    0x12
  75 #define CUDA_FILE_SERVER_FLAG           0x13
  76 #define CUDA_SET_AUTO_RATE              0x14
  77 #define CUDA_GET_AUTO_RATE              0x16
  78 #define CUDA_SET_DEVICE_LIST            0x19
  79 #define CUDA_GET_DEVICE_LIST            0x1a
  80 #define CUDA_SET_ONE_SECOND_MODE        0x1b
  81 #define CUDA_SET_POWER_MESSAGES         0x21
  82 #define CUDA_GET_SET_IIC                0x22
  83 #define CUDA_WAKEUP                     0x23
  84 #define CUDA_TIMER_TICKLE               0x24
  85 #define CUDA_COMBINED_FORMAT_IIC        0x25
  86
  87 #define CUDA_TIMER_FREQ (4700000 / 6)
  88 #define CUDA_ADB_POLL_FREQ 50
  89
  90 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
  91 #define RTC_OFFSET                      2082844800
  92
  93 typedef struct CUDATimer {
  94     unsigned int latch;
  95     uint16_t counter_value; /* counter value at load time */
  96     int64_t load_time;
  97     int64_t next_irq_time;
  98     QEMUTimer *timer;
  99 } CUDATimer;
 100
 101 typedef struct CUDAState {
 102     /* cuda registers */
 103     uint8_t b;      /* B-side data */
 104     uint8_t a;      /* A-side data */
 105     uint8_t dirb;   /* B-side direction (1=output) */
 106     uint8_t dira;   /* A-side direction (1=output) */
 107     uint8_t sr;     /* Shift register */
 108     uint8_t acr;    /* Auxiliary control register */
 109     uint8_t pcr;    /* Peripheral control register */
 110     uint8_t ifr;    /* Interrupt flag register */
 111     uint8_t ier;    /* Interrupt enable register */
 112     uint8_t anh;    /* A-side data, no handshake */
 113
 114     CUDATimer timers[2];
 115
 116     uint8_t last_b; /* last value of B register */
 117     uint8_t last_acr; /* last value of B register */
 118
 119     int data_in_size;
 120     int data_in_index;
 121     int data_out_index;
 122
 123     SetIRQFunc *set_irq;
 124     int irq;
 125     void *irq_opaque;
 126     uint8_t autopoll;
 127     uint8_t data_in[128];
 128     uint8_t data_out[16];
 129     QEMUTimer *adb_poll_timer;
 130 } CUDAState;
 131
 132 static CUDAState cuda_state;
 133 ADBBusState adb_bus;
 134
 135 static void cuda_update(CUDAState *s);
 136 static void cuda_receive_packet_from_host(CUDAState *s,
 137                                           const uint8_t *data, int len);
 138 static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
 139                               int64_t current_time);
 140
 141 static void cuda_update_irq(CUDAState *s)
 142 {
 143     if (s->ifr & s->ier & (SR_INT | T1_INT)) {
 144         s->set_irq(s->irq_opaque, s->irq, 1);
 145     } else {
 146         s->set_irq(s->irq_opaque, s->irq, 0);
 147     }
 148 }
 149
 150 static unsigned int get_counter(CUDATimer *s)
 151 {
 152     int64_t d;
 153     unsigned int counter;
 154
 155     d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
 156                  CUDA_TIMER_FREQ, ticks_per_sec);
 157     if (d <= s->counter_value) {
 158         counter = d;
 159     } else {
 160         counter = s->latch - 1 - ((d - s->counter_value) % s->latch);
 161     }
 162     return counter;
 163 }
 164
 165 static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
 166 {
 167 #ifdef DEBUG_CUDA
 168     printf("cuda: T%d.counter=%d\n",
 169            1 + (ti->timer == NULL), val);
 170 #endif
 171     ti->load_time = qemu_get_clock(vm_clock);
 172     ti->counter_value = val;
 173     cuda_timer_update(s, ti, ti->load_time);
 174 }
 175
 176 static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
 177 {
 178     int64_t d, next_time, base;
 179     /* current counter value */
 180     d = muldiv64(current_time - s->load_time,
 181                  CUDA_TIMER_FREQ, ticks_per_sec);
 182     if (d < s->counter_value) {
 183         next_time = s->counter_value + 1;
 184     } else
 185     {
 186         base = ((d - s->counter_value + 1) / s->latch);
 187         base = (base * s->latch) + s->counter_value;
 188         next_time = base + s->latch;
 189     }
 190 #if 0
 191 #ifdef DEBUG_CUDA
 192     printf("latch=%d counter=%lld delta_next=%lld\n",
 193            s->latch, d, next_time - d);
 194 #endif
 195 #endif
 196     next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
 197         s->load_time;
 198     if (next_time <= current_time)
 199         next_time = current_time + 1;
 200     return next_time;
 201 }
 202
 203 static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
 204                               int64_t current_time)
 205 {
 206     if (!ti->timer)
 207         return;
 208     if ((s->acr & T1MODE) != T1MODE_CONT) {
 209         qemu_del_timer(ti->timer);
 210     } else {
 211         ti->next_irq_time = get_next_irq_time(ti, current_time);
 212         qemu_mod_timer(ti->timer, ti->next_irq_time);
 213     }
 214 }
 215
 216 static void cuda_timer1(void *opaque)
 217 {
 218     CUDAState *s = opaque;
 219     CUDATimer *ti = &s->timers[0];
 220
 221     cuda_timer_update(s, ti, ti->next_irq_time);
 222     s->ifr |= T1_INT;
 223     cuda_update_irq(s);
 224 }
 225
 226 static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
 227 {
 228     CUDAState *s = opaque;
 229     uint32_t val;
 230
 231     addr = (addr >> 9) & 0xf;
 232     switch(addr) {
 233     case 0:
 234         val = s->b;
 235         break;
 236     case 1:
 237         val = s->a;
 238         break;
 239     case 2:
 240         val = s->dirb;
 241         break;
 242     case 3:
 243         val = s->dira;
 244         break;
 245     case 4:
 246         val = get_counter(&s->timers[0]) & 0xff;
 247         s->ifr &= ~T1_INT;
 248         cuda_update_irq(s);
 249         break;
 250     case 5:
 251         val = get_counter(&s->timers[0]) >> 8;
 252         s->ifr &= ~T1_INT;
 253         cuda_update_irq(s);
 254         break;
 255     case 6:
 256         val = s->timers[0].latch & 0xff;
 257         break;
 258     case 7:
 259         val = (s->timers[0].latch >> 8) & 0xff;
 260         break;
 261     case 8:
 262         val = get_counter(&s->timers[1]) & 0xff;
 263         break;
 264     case 9:
 265         val = get_counter(&s->timers[1]) >> 8;
 266         break;
 267     case 10:
 268         val = s->sr;
 269         s->ifr &= ~SR_INT;
 270         cuda_update_irq(s);
 271         break;
 272     case 11:
 273         val = s->acr;
 274         break;
 275     case 12:
 276         val = s->pcr;
 277         break;
 278     case 13:
 279         val = s->ifr;
 280         break;
 281     case 14:
 282         val = s->ier;
 283         break;
 284     default:
 285     case 15:
 286         val = s->anh;
 287         break;
 288     }
 289 #ifdef DEBUG_CUDA
 290     if (addr != 13 || val != 0)
 291         printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
 292 #endif
 293     return val;
 294 }
 295
 296 static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 297 {
 298     CUDAState *s = opaque;
 299
 300     addr = (addr >> 9) & 0xf;
 301 #ifdef DEBUG_CUDA
 302     printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
 303 #endif
 304
 305     switch(addr) {
 306     case 0:
 307         s->b = val;
 308         cuda_update(s);
 309         break;
 310     case 1:
 311         s->a = val;
 312         break;
 313     case 2:
 314         s->dirb = val;
 315         break;
 316     case 3:
 317         s->dira = val;
 318         break;
 319     case 4:
 320         val = val | (get_counter(&s->timers[0]) & 0xff00);
 321         set_counter(s, &s->timers[0], val);
 322         break;
 323     case 5:
 324         val = (val << 8) |  (get_counter(&s->timers[0]) & 0xff);
 325         set_counter(s, &s->timers[0], val);
 326         break;
 327     case 6:
 328         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 329         cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
 330         break;
 331     case 7:
 332         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 333         cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
 334         break;
 335     case 8:
 336         val = val | (get_counter(&s->timers[1]) & 0xff00);
 337         set_counter(s, &s->timers[1], val);
 338         break;
 339     case 9:
 340         val = (val << 8) |  (get_counter(&s->timers[1]) & 0xff);
 341         set_counter(s, &s->timers[1], val);
 342         break;
 343     case 10:
 344         s->sr = val;
 345         break;
 346     case 11:
 347         s->acr = val;
 348         cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
 349         cuda_update(s);
 350         break;
 351     case 12:
 352         s->pcr = val;
 353         break;
 354     case 13:
 355         /* reset bits */
 356         s->ifr &= ~val;
 357         cuda_update_irq(s);
 358         break;
 359     case 14:
 360 #if 0
 361         if (val & IER_SET) {
 362             /* set bits */
 363             s->ier |= val & 0x7f;
 364         } else {
 365             /* reset bits */
 366             s->ier &= ~val;
 367         }
 368 #else
 369         /* XXX: please explain me why the SPEC is not correct ! */
 370         s->ier = val;
 371 #endif
 372         cuda_update_irq(s);
 373         break;
 374     default:
 375     case 15:
 376         s->anh = val;
 377         break;
 378     }
 379 }
 380
 381 /* NOTE: TIP and TREQ are negated */
 382 static void cuda_update(CUDAState *s)
 383 {
 384     int packet_received, len;
 385
 386     packet_received = 0;
 387     if (!(s->b & TIP)) {
 388         /* transfer requested from host */
 389
 390         if (s->acr & SR_OUT) {
 391             /* data output */
 392             if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
 393                 if (s->data_out_index < sizeof(s->data_out)) {
 394 #ifdef DEBUG_CUDA
 395                     printf("cuda: send: %02x\n", s->sr);
 396 #endif
 397                     s->data_out[s->data_out_index++] = s->sr;
 398                     s->ifr |= SR_INT;
 399                     cuda_update_irq(s);
 400                 }
 401             }
 402         } else {
 403             if (s->data_in_index < s->data_in_size) {
 404                 /* data input */
 405                 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
 406                     s->sr = s->data_in[s->data_in_index++];
 407 #ifdef DEBUG_CUDA
 408                     printf("cuda: recv: %02x\n", s->sr);
 409 #endif
 410                     /* indicate end of transfer */
 411                     if (s->data_in_index >= s->data_in_size) {
 412                         s->b = (s->b | TREQ);
 413                     }
 414                     s->ifr |= SR_INT;
 415                     cuda_update_irq(s);
 416                 }
 417             }
 418         }
 419     } else {
 420         /* no transfer requested: handle sync case */
 421         if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
 422             /* update TREQ state each time TACK change state */
 423             if (s->b & TACK)
 424                 s->b = (s->b | TREQ);
 425             else
 426                 s->b = (s->b & ~TREQ);
 427             s->ifr |= SR_INT;
 428             cuda_update_irq(s);
 429         } else {
 430             if (!(s->last_b & TIP)) {
 431                 /* handle end of host to cuda transfert */
 432                 packet_received = (s->data_out_index > 0);
 433                 /* always an IRQ at the end of transfert */
 434                 s->ifr |= SR_INT;
 435                 cuda_update_irq(s);
 436             }
 437             /* signal if there is data to read */
 438             if (s->data_in_index < s->data_in_size) {
 439                 s->b = (s->b & ~TREQ);
 440             }
 441         }
 442     }
 443
 444     s->last_acr = s->acr;
 445     s->last_b = s->b;
 446
 447     /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
 448        recursively */
 449     if (packet_received) {
 450         len = s->data_out_index;
 451         s->data_out_index = 0;
 452         cuda_receive_packet_from_host(s, s->data_out, len);
 453     }
 454 }
 455
 456 static void cuda_send_packet_to_host(CUDAState *s,
 457                                      const uint8_t *data, int len)
 458 {
 459 #ifdef DEBUG_CUDA_PACKET
 460     {
 461         int i;
 462         printf("cuda_send_packet_to_host:\n");
 463         for(i = 0; i < len; i++)
 464             printf(" %02x", data[i]);
 465         printf("\n");
 466     }
 467 #endif
 468     memcpy(s->data_in, data, len);
 469     s->data_in_size = len;
 470     s->data_in_index = 0;
 471     cuda_update(s);
 472     s->ifr |= SR_INT;
 473     cuda_update_irq(s);
 474 }
 475
 476 static void cuda_adb_poll(void *opaque)
 477 {
 478     CUDAState *s = opaque;
 479     uint8_t obuf[ADB_MAX_OUT_LEN + 2];
 480     int olen;
 481
 482     olen = adb_poll(&adb_bus, obuf + 2);
 483     if (olen > 0) {
 484         obuf[0] = ADB_PACKET;
 485         obuf[1] = 0x40; /* polled data */
 486         cuda_send_packet_to_host(s, obuf, olen + 2);
 487     }
 488     qemu_mod_timer(s->adb_poll_timer,
 489                    qemu_get_clock(vm_clock) +
 490                    (ticks_per_sec / CUDA_ADB_POLL_FREQ));
 491 }
 492
 493 static void cuda_receive_packet(CUDAState *s,
 494                                 const uint8_t *data, int len)
 495 {
 496     uint8_t obuf[16];
 497     int ti, autopoll;
 498
 499     switch(data[0]) {
 500     case CUDA_AUTOPOLL:
 501         autopoll = (data[1] != 0);
 502         if (autopoll != s->autopoll) {
 503             s->autopoll = autopoll;
 504             if (autopoll) {
 505                 qemu_mod_timer(s->adb_poll_timer,
 506                                qemu_get_clock(vm_clock) +
 507                                (ticks_per_sec / CUDA_ADB_POLL_FREQ));
 508             } else {
 509                 qemu_del_timer(s->adb_poll_timer);
 510             }
 511         }
 512         obuf[0] = CUDA_PACKET;
 513         obuf[1] = data[1];
 514         cuda_send_packet_to_host(s, obuf, 2);
 515         break;
 516     case CUDA_GET_TIME:
 517     case CUDA_SET_TIME:
 518         /* XXX: add time support ? */
 519         ti = time(NULL) + RTC_OFFSET;
 520         obuf[0] = CUDA_PACKET;
 521         obuf[1] = 0;
 522         obuf[2] = 0;
 523         obuf[3] = ti >> 24;
 524         obuf[4] = ti >> 16;
 525         obuf[5] = ti >> 8;
 526         obuf[6] = ti;
 527         cuda_send_packet_to_host(s, obuf, 7);
 528         break;
 529     case CUDA_FILE_SERVER_FLAG:
 530     case CUDA_SET_DEVICE_LIST:
 531     case CUDA_SET_AUTO_RATE:
 532     case CUDA_SET_POWER_MESSAGES:
 533         obuf[0] = CUDA_PACKET;
 534         obuf[1] = 0;
 535         cuda_send_packet_to_host(s, obuf, 2);
 536         break;
 537     case CUDA_POWERDOWN:
 538         obuf[0] = CUDA_PACKET;
 539         obuf[1] = 0;
 540         cuda_send_packet_to_host(s, obuf, 2);
 541         qemu_system_shutdown_request();
 542         break;
 543     default:
 544         break;
 545     }
 546 }
 547
 548 static void cuda_receive_packet_from_host(CUDAState *s,
 549                                           const uint8_t *data, int len)
 550 {
 551 #ifdef DEBUG_CUDA_PACKET
 552     {
 553         int i;
 554         printf("cuda_receive_packet_from_host:\n");
 555         for(i = 0; i < len; i++)
 556             printf(" %02x", data[i]);
 557         printf("\n");
 558     }
 559 #endif
 560     switch(data[0]) {
 561     case ADB_PACKET:
 562         {
 563             uint8_t obuf[ADB_MAX_OUT_LEN + 2];
 564             int olen;
 565             olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
 566             if (olen > 0) {
 567                 obuf[0] = ADB_PACKET;
 568                 obuf[1] = 0x00;
 569             } else {
 570                 /* error */
 571                 obuf[0] = ADB_PACKET;
 572                 obuf[1] = -olen;
 573                 olen = 0;
 574             }
 575             cuda_send_packet_to_host(s, obuf, olen + 2);
 576         }
 577         break;
 578     case CUDA_PACKET:
 579         cuda_receive_packet(s, data + 1, len - 1);
 580         break;
 581     }
 582 }
 583
 584 static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 585 {
 586 }
 587
 588 static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 589 {
 590 }
 591
 592 static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
 593 {
 594     return 0;
 595 }
 596
 597 static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
 598 {
 599     return 0;
 600 }
 601
 602 static CPUWriteMemoryFunc *cuda_write[] = {
 603     &cuda_writeb,
 604     &cuda_writew,
 605     &cuda_writel,
 606 };
 607
 608 static CPUReadMemoryFunc *cuda_read[] = {
 609     &cuda_readb,
 610     &cuda_readw,
 611     &cuda_readl,
 612 };
 613
 614 int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq)
 615 {
 616     CUDAState *s = &cuda_state;
 617     int cuda_mem_index;
 618
 619     s->set_irq = set_irq;
 620     s->irq_opaque = irq_opaque;
 621     s->irq = irq;
 622
 623     s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
 624     s->timers[0].latch = 0x10000;
 625     set_counter(s, &s->timers[0], 0xffff);
 626     s->timers[1].latch = 0x10000;
 627     //    s->ier = T1_INT | SR_INT;
 628     s->ier = 0;
 629     set_counter(s, &s->timers[1], 0xffff);
 630
 631     s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
 632     cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
 633     return cuda_mem_index;
 634 }