2 * QEMU TCX Frame buffer
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu-common.h"
26 #include "ui/console.h"
27 #include "ui/pixel_ops.h"
28 #include "hw/sysbus.h"
32 #define TCX_DAC_NREGS 16
33 #define TCX_THC_NREGS_8 0x081c
34 #define TCX_THC_NREGS_24 0x1000
35 #define TCX_TEC_NREGS 0x1000
37 typedef struct TCXState
{
41 uint32_t *vram24
, *cplane
;
42 MemoryRegion vram_mem
;
43 MemoryRegion vram_8bit
;
44 MemoryRegion vram_24bit
;
45 MemoryRegion vram_cplane
;
50 ram_addr_t vram24_offset
, cplane_offset
;
52 uint32_t palette
[256];
53 uint8_t r
[256], g
[256], b
[256];
54 uint16_t width
, height
, depth
;
55 uint8_t dac_index
, dac_state
;
58 static void tcx_set_dirty(TCXState
*s
)
60 memory_region_set_dirty(&s
->vram_mem
, 0, MAXX
* MAXY
);
63 static void tcx24_set_dirty(TCXState
*s
)
65 memory_region_set_dirty(&s
->vram_mem
, s
->vram24_offset
, MAXX
* MAXY
* 4);
66 memory_region_set_dirty(&s
->vram_mem
, s
->cplane_offset
, MAXX
* MAXY
* 4);
69 static void update_palette_entries(TCXState
*s
, int start
, int end
)
71 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
74 for (i
= start
; i
< end
; i
++) {
75 switch (surface_bits_per_pixel(surface
)) {
78 s
->palette
[i
] = rgb_to_pixel8(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
81 s
->palette
[i
] = rgb_to_pixel15(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
84 s
->palette
[i
] = rgb_to_pixel16(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
87 if (is_surface_bgr(surface
)) {
88 s
->palette
[i
] = rgb_to_pixel32bgr(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
90 s
->palette
[i
] = rgb_to_pixel32(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
102 static void tcx_draw_line32(TCXState
*s1
, uint8_t *d
,
103 const uint8_t *s
, int width
)
107 uint32_t *p
= (uint32_t *)d
;
109 for(x
= 0; x
< width
; x
++) {
111 *p
++ = s1
->palette
[val
];
115 static void tcx_draw_line16(TCXState
*s1
, uint8_t *d
,
116 const uint8_t *s
, int width
)
120 uint16_t *p
= (uint16_t *)d
;
122 for(x
= 0; x
< width
; x
++) {
124 *p
++ = s1
->palette
[val
];
128 static void tcx_draw_line8(TCXState
*s1
, uint8_t *d
,
129 const uint8_t *s
, int width
)
134 for(x
= 0; x
< width
; x
++) {
136 *d
++ = s1
->palette
[val
];
141 XXX Could be much more optimal:
142 * detect if line/page/whole screen is in 24 bit mode
143 * if destination is also BGR, use memcpy
145 static inline void tcx24_draw_line32(TCXState
*s1
, uint8_t *d
,
146 const uint8_t *s
, int width
,
147 const uint32_t *cplane
,
150 DisplaySurface
*surface
= qemu_console_surface(s1
->con
);
153 uint32_t *p
= (uint32_t *)d
;
156 bgr
= is_surface_bgr(surface
);
157 for(x
= 0; x
< width
; x
++, s
++, s24
++) {
158 if ((be32_to_cpu(*cplane
++) & 0xff000000) == 0x03000000) {
159 // 24-bit direct, BGR order
166 dval
= rgb_to_pixel32bgr(r
, g
, b
);
168 dval
= rgb_to_pixel32(r
, g
, b
);
171 dval
= s1
->palette
[val
];
177 static inline int check_dirty(TCXState
*s
, ram_addr_t page
, ram_addr_t page24
,
182 ret
= memory_region_get_dirty(&s
->vram_mem
, page
, TARGET_PAGE_SIZE
,
184 ret
|= memory_region_get_dirty(&s
->vram_mem
, page24
, TARGET_PAGE_SIZE
* 4,
186 ret
|= memory_region_get_dirty(&s
->vram_mem
, cpage
, TARGET_PAGE_SIZE
* 4,
191 static inline void reset_dirty(TCXState
*ts
, ram_addr_t page_min
,
192 ram_addr_t page_max
, ram_addr_t page24
,
195 memory_region_reset_dirty(&ts
->vram_mem
,
197 (page_max
- page_min
) + TARGET_PAGE_SIZE
,
199 memory_region_reset_dirty(&ts
->vram_mem
,
200 page24
+ page_min
* 4,
201 (page_max
- page_min
) * 4 + TARGET_PAGE_SIZE
,
203 memory_region_reset_dirty(&ts
->vram_mem
,
204 cpage
+ page_min
* 4,
205 (page_max
- page_min
) * 4 + TARGET_PAGE_SIZE
,
209 /* Fixed line length 1024 allows us to do nice tricks not possible on
211 static void tcx_update_display(void *opaque
)
213 TCXState
*ts
= opaque
;
214 DisplaySurface
*surface
= qemu_console_surface(ts
->con
);
215 ram_addr_t page
, page_min
, page_max
;
216 int y
, y_start
, dd
, ds
;
218 void (*f
)(TCXState
*s1
, uint8_t *dst
, const uint8_t *src
, int width
);
220 if (surface_bits_per_pixel(surface
) == 0) {
228 d
= surface_data(surface
);
230 dd
= surface_stride(surface
);
233 switch (surface_bits_per_pixel(surface
)) {
249 for(y
= 0; y
< ts
->height
; y
+= 4, page
+= TARGET_PAGE_SIZE
) {
250 if (memory_region_get_dirty(&ts
->vram_mem
, page
, TARGET_PAGE_SIZE
,
258 f(ts
, d
, s
, ts
->width
);
261 f(ts
, d
, s
, ts
->width
);
264 f(ts
, d
, s
, ts
->width
);
267 f(ts
, d
, s
, ts
->width
);
272 /* flush to display */
273 dpy_gfx_update(ts
->con
, 0, y_start
,
274 ts
->width
, y
- y_start
);
282 /* flush to display */
283 dpy_gfx_update(ts
->con
, 0, y_start
,
284 ts
->width
, y
- y_start
);
286 /* reset modified pages */
287 if (page_max
>= page_min
) {
288 memory_region_reset_dirty(&ts
->vram_mem
,
290 (page_max
- page_min
) + TARGET_PAGE_SIZE
,
295 static void tcx24_update_display(void *opaque
)
297 TCXState
*ts
= opaque
;
298 DisplaySurface
*surface
= qemu_console_surface(ts
->con
);
299 ram_addr_t page
, page_min
, page_max
, cpage
, page24
;
300 int y
, y_start
, dd
, ds
;
302 uint32_t *cptr
, *s24
;
304 if (surface_bits_per_pixel(surface
) != 32) {
309 page24
= ts
->vram24_offset
;
310 cpage
= ts
->cplane_offset
;
314 d
= surface_data(surface
);
318 dd
= surface_stride(surface
);
321 for(y
= 0; y
< ts
->height
; y
+= 4, page
+= TARGET_PAGE_SIZE
,
322 page24
+= TARGET_PAGE_SIZE
, cpage
+= TARGET_PAGE_SIZE
) {
323 if (check_dirty(ts
, page
, page24
, cpage
)) {
330 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
335 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
340 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
345 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
352 /* flush to display */
353 dpy_gfx_update(ts
->con
, 0, y_start
,
354 ts
->width
, y
- y_start
);
364 /* flush to display */
365 dpy_gfx_update(ts
->con
, 0, y_start
,
366 ts
->width
, y
- y_start
);
368 /* reset modified pages */
369 if (page_max
>= page_min
) {
370 reset_dirty(ts
, page_min
, page_max
, page24
, cpage
);
374 static void tcx_invalidate_display(void *opaque
)
376 TCXState
*s
= opaque
;
379 qemu_console_resize(s
->con
, s
->width
, s
->height
);
382 static void tcx24_invalidate_display(void *opaque
)
384 TCXState
*s
= opaque
;
388 qemu_console_resize(s
->con
, s
->width
, s
->height
);
391 static int vmstate_tcx_post_load(void *opaque
, int version_id
)
393 TCXState
*s
= opaque
;
395 update_palette_entries(s
, 0, 256);
396 if (s
->depth
== 24) {
405 static const VMStateDescription vmstate_tcx
= {
408 .minimum_version_id
= 4,
409 .minimum_version_id_old
= 4,
410 .post_load
= vmstate_tcx_post_load
,
411 .fields
= (VMStateField
[]) {
412 VMSTATE_UINT16(height
, TCXState
),
413 VMSTATE_UINT16(width
, TCXState
),
414 VMSTATE_UINT16(depth
, TCXState
),
415 VMSTATE_BUFFER(r
, TCXState
),
416 VMSTATE_BUFFER(g
, TCXState
),
417 VMSTATE_BUFFER(b
, TCXState
),
418 VMSTATE_UINT8(dac_index
, TCXState
),
419 VMSTATE_UINT8(dac_state
, TCXState
),
420 VMSTATE_END_OF_LIST()
424 static void tcx_reset(DeviceState
*d
)
426 TCXState
*s
= container_of(d
, TCXState
, busdev
.qdev
);
428 /* Initialize palette */
429 memset(s
->r
, 0, 256);
430 memset(s
->g
, 0, 256);
431 memset(s
->b
, 0, 256);
432 s
->r
[255] = s
->g
[255] = s
->b
[255] = 255;
433 update_palette_entries(s
, 0, 256);
434 memset(s
->vram
, 0, MAXX
*MAXY
);
435 memory_region_reset_dirty(&s
->vram_mem
, 0, MAXX
* MAXY
* (1 + 4 + 4),
441 static uint64_t tcx_dac_readl(void *opaque
, hwaddr addr
,
447 static void tcx_dac_writel(void *opaque
, hwaddr addr
, uint64_t val
,
450 TCXState
*s
= opaque
;
454 s
->dac_index
= val
>> 24;
458 switch (s
->dac_state
) {
460 s
->r
[s
->dac_index
] = val
>> 24;
461 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
465 s
->g
[s
->dac_index
] = val
>> 24;
466 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
470 s
->b
[s
->dac_index
] = val
>> 24;
471 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
472 s
->dac_index
= (s
->dac_index
+ 1) & 255; // Index autoincrement
483 static const MemoryRegionOps tcx_dac_ops
= {
484 .read
= tcx_dac_readl
,
485 .write
= tcx_dac_writel
,
486 .endianness
= DEVICE_NATIVE_ENDIAN
,
488 .min_access_size
= 4,
489 .max_access_size
= 4,
493 static uint64_t dummy_readl(void *opaque
, hwaddr addr
,
499 static void dummy_writel(void *opaque
, hwaddr addr
,
500 uint64_t val
, unsigned size
)
504 static const MemoryRegionOps dummy_ops
= {
506 .write
= dummy_writel
,
507 .endianness
= DEVICE_NATIVE_ENDIAN
,
509 .min_access_size
= 4,
510 .max_access_size
= 4,
514 static const GraphicHwOps tcx_ops
= {
515 .invalidate
= tcx_invalidate_display
,
516 .gfx_update
= tcx_update_display
,
519 static const GraphicHwOps tcx24_ops
= {
520 .invalidate
= tcx24_invalidate_display
,
521 .gfx_update
= tcx24_update_display
,
524 static int tcx_init1(SysBusDevice
*dev
)
526 TCXState
*s
= FROM_SYSBUS(TCXState
, dev
);
527 ram_addr_t vram_offset
= 0;
531 memory_region_init_ram(&s
->vram_mem
, "tcx.vram",
532 s
->vram_size
* (1 + 4 + 4));
533 vmstate_register_ram_global(&s
->vram_mem
);
534 vram_base
= memory_region_get_ram_ptr(&s
->vram_mem
);
539 memory_region_init_alias(&s
->vram_8bit
, "tcx.vram.8bit",
540 &s
->vram_mem
, vram_offset
, size
);
541 sysbus_init_mmio(dev
, &s
->vram_8bit
);
546 memory_region_init_io(&s
->dac
, &tcx_dac_ops
, s
, "tcx.dac", TCX_DAC_NREGS
);
547 sysbus_init_mmio(dev
, &s
->dac
);
550 memory_region_init_io(&s
->tec
, &dummy_ops
, s
, "tcx.tec", TCX_TEC_NREGS
);
551 sysbus_init_mmio(dev
, &s
->tec
);
552 /* THC: NetBSD writes here even with 8-bit display: dummy */
553 memory_region_init_io(&s
->thc24
, &dummy_ops
, s
, "tcx.thc24",
555 sysbus_init_mmio(dev
, &s
->thc24
);
557 if (s
->depth
== 24) {
559 size
= s
->vram_size
* 4;
560 s
->vram24
= (uint32_t *)vram_base
;
561 s
->vram24_offset
= vram_offset
;
562 memory_region_init_alias(&s
->vram_24bit
, "tcx.vram.24bit",
563 &s
->vram_mem
, vram_offset
, size
);
564 sysbus_init_mmio(dev
, &s
->vram_24bit
);
569 size
= s
->vram_size
* 4;
570 s
->cplane
= (uint32_t *)vram_base
;
571 s
->cplane_offset
= vram_offset
;
572 memory_region_init_alias(&s
->vram_cplane
, "tcx.vram.cplane",
573 &s
->vram_mem
, vram_offset
, size
);
574 sysbus_init_mmio(dev
, &s
->vram_cplane
);
576 s
->con
= graphic_console_init(DEVICE(dev
), &tcx24_ops
, s
);
578 /* THC 8 bit (dummy) */
579 memory_region_init_io(&s
->thc8
, &dummy_ops
, s
, "tcx.thc8",
581 sysbus_init_mmio(dev
, &s
->thc8
);
583 s
->con
= graphic_console_init(DEVICE(dev
), &tcx_ops
, s
);
586 qemu_console_resize(s
->con
, s
->width
, s
->height
);
590 static Property tcx_properties
[] = {
591 DEFINE_PROP_HEX32("vram_size", TCXState
, vram_size
, -1),
592 DEFINE_PROP_UINT16("width", TCXState
, width
, -1),
593 DEFINE_PROP_UINT16("height", TCXState
, height
, -1),
594 DEFINE_PROP_UINT16("depth", TCXState
, depth
, -1),
595 DEFINE_PROP_END_OF_LIST(),
598 static void tcx_class_init(ObjectClass
*klass
, void *data
)
600 DeviceClass
*dc
= DEVICE_CLASS(klass
);
601 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
604 dc
->reset
= tcx_reset
;
605 dc
->vmsd
= &vmstate_tcx
;
606 dc
->props
= tcx_properties
;
609 static const TypeInfo tcx_info
= {
611 .parent
= TYPE_SYS_BUS_DEVICE
,
612 .instance_size
= sizeof(TCXState
),
613 .class_init
= tcx_class_init
,
616 static void tcx_register_types(void)
618 type_register_static(&tcx_info
);
621 type_init(tcx_register_types
)