hw/display/vga-pci.c

   1 /*
   2  * QEMU PCI VGA Emulator.
   3  *
   4  * see docs/specs/standard-vga.txt for virtual hardware specs.
   5  *
   6  * Copyright (c) 2003 Fabrice Bellard
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #include "qemu/osdep.h"
  27 #include "hw/hw.h"
  28 #include "hw/pci/pci.h"
  29 #include "vga_int.h"
  30 #include "ui/pixel_ops.h"
  31 #include "qemu/timer.h"
  32 #include "hw/loader.h"
  33 #include "hw/display/edid.h"
  34
  35 enum vga_pci_flags {
  36     PCI_VGA_FLAG_ENABLE_MMIO = 1,
  37     PCI_VGA_FLAG_ENABLE_QEXT = 2,
  38     PCI_VGA_FLAG_ENABLE_EDID = 3,
  39 };
  40
  41 typedef struct PCIVGAState {
  42     PCIDevice dev;
  43     VGACommonState vga;
  44     uint32_t flags;
  45     qemu_edid_info edid_info;
  46     MemoryRegion mmio;
  47     MemoryRegion mrs[4];
  48     uint8_t edid[256];
  49 } PCIVGAState;
  50
  51 #define TYPE_PCI_VGA "pci-vga"
  52 #define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)
  53
  54 static const VMStateDescription vmstate_vga_pci = {
  55     .name = "vga",
  56     .version_id = 2,
  57     .minimum_version_id = 2,
  58     .fields = (VMStateField[]) {
  59         VMSTATE_PCI_DEVICE(dev, PCIVGAState),
  60         VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
  61         VMSTATE_END_OF_LIST()
  62     }
  63 };
  64
  65 static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
  66                                     unsigned size)
  67 {
  68     VGACommonState *s = ptr;
  69     uint64_t ret = 0;
  70
  71     switch (size) {
  72     case 1:
  73         ret = vga_ioport_read(s, addr + 0x3c0);
  74         break;
  75     case 2:
  76         ret  = vga_ioport_read(s, addr + 0x3c0);
  77         ret |= vga_ioport_read(s, addr + 0x3c1) << 8;
  78         break;
  79     }
  80     return ret;
  81 }
  82
  83 static void pci_vga_ioport_write(void *ptr, hwaddr addr,
  84                                  uint64_t val, unsigned size)
  85 {
  86     VGACommonState *s = ptr;
  87
  88     switch (size) {
  89     case 1:
  90         vga_ioport_write(s, addr + 0x3c0, val);
  91         break;
  92     case 2:
  93         /*
  94          * Update bytes in little endian order.  Allows to update
  95          * indexed registers with a single word write because the
  96          * index byte is updated first.
  97          */
  98         vga_ioport_write(s, addr + 0x3c0, val & 0xff);
  99         vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
 100         break;
 101     }
 102 }
 103
 104 static const MemoryRegionOps pci_vga_ioport_ops = {
 105     .read = pci_vga_ioport_read,
 106     .write = pci_vga_ioport_write,
 107     .valid.min_access_size = 1,
 108     .valid.max_access_size = 4,
 109     .impl.min_access_size = 1,
 110     .impl.max_access_size = 2,
 111     .endianness = DEVICE_LITTLE_ENDIAN,
 112 };
 113
 114 static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
 115                                    unsigned size)
 116 {
 117     VGACommonState *s = ptr;
 118     int index = addr >> 1;
 119
 120     vbe_ioport_write_index(s, 0, index);
 121     return vbe_ioport_read_data(s, 0);
 122 }
 123
 124 static void pci_vga_bochs_write(void *ptr, hwaddr addr,
 125                                 uint64_t val, unsigned size)
 126 {
 127     VGACommonState *s = ptr;
 128     int index = addr >> 1;
 129
 130     vbe_ioport_write_index(s, 0, index);
 131     vbe_ioport_write_data(s, 0, val);
 132 }
 133
 134 static const MemoryRegionOps pci_vga_bochs_ops = {
 135     .read = pci_vga_bochs_read,
 136     .write = pci_vga_bochs_write,
 137     .valid.min_access_size = 1,
 138     .valid.max_access_size = 4,
 139     .impl.min_access_size = 2,
 140     .impl.max_access_size = 2,
 141     .endianness = DEVICE_LITTLE_ENDIAN,
 142 };
 143
 144 static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
 145 {
 146     VGACommonState *s = ptr;
 147
 148     switch (addr) {
 149     case PCI_VGA_QEXT_REG_SIZE:
 150         return PCI_VGA_QEXT_SIZE;
 151     case PCI_VGA_QEXT_REG_BYTEORDER:
 152         return s->big_endian_fb ?
 153             PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
 154     default:
 155         return 0;
 156     }
 157 }
 158
 159 static void pci_vga_qext_write(void *ptr, hwaddr addr,
 160                                uint64_t val, unsigned size)
 161 {
 162     VGACommonState *s = ptr;
 163
 164     switch (addr) {
 165     case PCI_VGA_QEXT_REG_BYTEORDER:
 166         if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
 167             s->big_endian_fb = true;
 168         }
 169         if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
 170             s->big_endian_fb = false;
 171         }
 172         break;
 173     }
 174 }
 175
 176 static bool vga_get_big_endian_fb(Object *obj, Error **errp)
 177 {
 178     PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
 179
 180     return d->vga.big_endian_fb;
 181 }
 182
 183 static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
 184 {
 185     PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
 186
 187     d->vga.big_endian_fb = value;
 188 }
 189
 190 static const MemoryRegionOps pci_vga_qext_ops = {
 191     .read = pci_vga_qext_read,
 192     .write = pci_vga_qext_write,
 193     .valid.min_access_size = 4,
 194     .valid.max_access_size = 4,
 195     .endianness = DEVICE_LITTLE_ENDIAN,
 196 };
 197
 198 void pci_std_vga_mmio_region_init(VGACommonState *s,
 199                                   Object *owner,
 200                                   MemoryRegion *parent,
 201                                   MemoryRegion *subs,
 202                                   bool qext, bool edid)
 203 {
 204     PCIVGAState *d = container_of(s, PCIVGAState, vga);
 205
 206     memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s,
 207                           "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
 208     memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
 209                                 &subs[0]);
 210
 211     memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s,
 212                           "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
 213     memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
 214                                 &subs[1]);
 215
 216     if (qext) {
 217         memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s,
 218                               "qemu extended regs", PCI_VGA_QEXT_SIZE);
 219         memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
 220                                     &subs[2]);
 221     }
 222
 223     if (edid) {
 224         qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info);
 225         qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid));
 226         memory_region_add_subregion(parent, 0, &subs[3]);
 227     }
 228 }
 229
 230 static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
 231 {
 232     PCIVGAState *d = PCI_VGA(dev);
 233     VGACommonState *s = &d->vga;
 234     bool qext = false;
 235     bool edid = false;
 236
 237     /* vga + console init */
 238     vga_common_init(s, OBJECT(dev));
 239     vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
 240              true);
 241
 242     s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
 243
 244     /* XXX: VGA_RAM_SIZE must be a power of two */
 245     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
 246
 247     /* mmio bar for vga register access */
 248     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
 249         memory_region_init(&d->mmio, NULL, "vga.mmio",
 250                            PCI_VGA_MMIO_SIZE);
 251
 252         if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
 253             qext = true;
 254             pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
 255         }
 256         if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
 257             edid = true;
 258         }
 259         pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs,
 260                                      qext, edid);
 261
 262         pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
 263     }
 264
 265     if (!dev->rom_bar) {
 266         /* compatibility with pc-0.13 and older */
 267         vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
 268     }
 269 }
 270
 271 static void pci_std_vga_init(Object *obj)
 272 {
 273     /* Expose framebuffer byteorder via QOM */
 274     object_property_add_bool(obj, "big-endian-framebuffer",
 275                              vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
 276 }
 277
 278 static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
 279 {
 280     PCIVGAState *d = PCI_VGA(dev);
 281     VGACommonState *s = &d->vga;
 282     bool qext = false;
 283     bool edid = false;
 284
 285     /* vga + console init */
 286     vga_common_init(s, OBJECT(dev));
 287     s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
 288
 289     /* mmio bar */
 290     memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio",
 291                        PCI_VGA_MMIO_SIZE);
 292
 293     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
 294         qext = true;
 295         pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
 296     }
 297     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
 298         edid = true;
 299     }
 300     pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid);
 301
 302     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
 303     pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
 304 }
 305
 306 static void pci_secondary_vga_exit(PCIDevice *dev)
 307 {
 308     PCIVGAState *d = PCI_VGA(dev);
 309     VGACommonState *s = &d->vga;
 310
 311     graphic_console_close(s->con);
 312     memory_region_del_subregion(&d->mmio, &d->mrs[0]);
 313     memory_region_del_subregion(&d->mmio, &d->mrs[1]);
 314     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
 315         memory_region_del_subregion(&d->mmio, &d->mrs[2]);
 316     }
 317     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
 318         memory_region_del_subregion(&d->mmio, &d->mrs[3]);
 319     }
 320 }
 321
 322 static void pci_secondary_vga_init(Object *obj)
 323 {
 324     /* Expose framebuffer byteorder via QOM */
 325     object_property_add_bool(obj, "big-endian-framebuffer",
 326                              vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
 327 }
 328
 329 static void pci_secondary_vga_reset(DeviceState *dev)
 330 {
 331     PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
 332     vga_common_reset(&d->vga);
 333 }
 334
 335 static Property vga_pci_properties[] = {
 336     DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
 337     DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
 338     DEFINE_PROP_BIT("qemu-extended-regs",
 339                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
 340     DEFINE_PROP_BIT("edid",
 341                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, false),
 342     DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
 343     DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false),
 344     DEFINE_PROP_END_OF_LIST(),
 345 };
 346
 347 static Property secondary_pci_properties[] = {
 348     DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
 349     DEFINE_PROP_BIT("qemu-extended-regs",
 350                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
 351     DEFINE_PROP_BIT("edid",
 352                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, false),
 353     DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
 354     DEFINE_PROP_END_OF_LIST(),
 355 };
 356
 357 static void vga_pci_class_init(ObjectClass *klass, void *data)
 358 {
 359     DeviceClass *dc = DEVICE_CLASS(klass);
 360     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 361
 362     k->vendor_id = PCI_VENDOR_ID_QEMU;
 363     k->device_id = PCI_DEVICE_ID_QEMU_VGA;
 364     dc->vmsd = &vmstate_vga_pci;
 365     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 366 }
 367
 368 static const TypeInfo vga_pci_type_info = {
 369     .name = TYPE_PCI_VGA,
 370     .parent = TYPE_PCI_DEVICE,
 371     .instance_size = sizeof(PCIVGAState),
 372     .abstract = true,
 373     .class_init = vga_pci_class_init,
 374     .interfaces = (InterfaceInfo[]) {
 375         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 376         { },
 377     },
 378 };
 379
 380 static void vga_class_init(ObjectClass *klass, void *data)
 381 {
 382     DeviceClass *dc = DEVICE_CLASS(klass);
 383     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 384
 385     k->realize = pci_std_vga_realize;
 386     k->romfile = "vgabios-stdvga.bin";
 387     k->class_id = PCI_CLASS_DISPLAY_VGA;
 388     dc->props = vga_pci_properties;
 389     dc->hotpluggable = false;
 390 }
 391
 392 static void secondary_class_init(ObjectClass *klass, void *data)
 393 {
 394     DeviceClass *dc = DEVICE_CLASS(klass);
 395     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 396
 397     k->realize = pci_secondary_vga_realize;
 398     k->exit = pci_secondary_vga_exit;
 399     k->class_id = PCI_CLASS_DISPLAY_OTHER;
 400     dc->props = secondary_pci_properties;
 401     dc->reset = pci_secondary_vga_reset;
 402 }
 403
 404 static const TypeInfo vga_info = {
 405     .name          = "VGA",
 406     .parent        = TYPE_PCI_VGA,
 407     .instance_init = pci_std_vga_init,
 408     .class_init    = vga_class_init,
 409 };
 410
 411 static const TypeInfo secondary_info = {
 412     .name          = "secondary-vga",
 413     .parent        = TYPE_PCI_VGA,
 414     .instance_init = pci_secondary_vga_init,
 415     .class_init    = secondary_class_init,
 416 };
 417
 418 static void vga_register_types(void)
 419 {
 420     type_register_static(&vga_pci_type_info);
 421     type_register_static(&vga_info);
 422     type_register_static(&secondary_info);
 423 }
 424
 425 type_init(vga_register_types)