hw/display/vga.c

   1 /*
   2  * QEMU VGA Emulator.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "vga.h"
  26 #include "ui/console.h"
  27 #include "hw/i386/pc.h"
  28 #include "hw/pci/pci.h"
  29 #include "vga_int.h"
  30 #include "ui/pixel_ops.h"
  31 #include "qemu/timer.h"
  32 #include "hw/xen/xen.h"
  33 #include "trace.h"
  34
  35 //#define DEBUG_VGA
  36 //#define DEBUG_VGA_MEM
  37 //#define DEBUG_VGA_REG
  38
  39 //#define DEBUG_BOCHS_VBE
  40
  41 /* 16 state changes per vertical frame @60 Hz */
  42 #define VGA_TEXT_CURSOR_PERIOD_MS       (1000 * 2 * 16 / 60)
  43
  44 /*
  45  * Video Graphics Array (VGA)
  46  *
  47  * Chipset docs for original IBM VGA:
  48  * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
  49  *
  50  * FreeVGA site:
  51  * http://www.osdever.net/FreeVGA/home.htm
  52  *
  53  * Standard VGA features and Bochs VBE extensions are implemented.
  54  */
  55
  56 /* force some bits to zero */
  57 const uint8_t sr_mask[8] = {
  58     0x03,
  59     0x3d,
  60     0x0f,
  61     0x3f,
  62     0x0e,
  63     0x00,
  64     0x00,
  65     0xff,
  66 };
  67
  68 const uint8_t gr_mask[16] = {
  69     0x0f, /* 0x00 */
  70     0x0f, /* 0x01 */
  71     0x0f, /* 0x02 */
  72     0x1f, /* 0x03 */
  73     0x03, /* 0x04 */
  74     0x7b, /* 0x05 */
  75     0x0f, /* 0x06 */
  76     0x0f, /* 0x07 */
  77     0xff, /* 0x08 */
  78     0x00, /* 0x09 */
  79     0x00, /* 0x0a */
  80     0x00, /* 0x0b */
  81     0x00, /* 0x0c */
  82     0x00, /* 0x0d */
  83     0x00, /* 0x0e */
  84     0x00, /* 0x0f */
  85 };
  86
  87 #define cbswap_32(__x) \
  88 ((uint32_t)( \
  89                 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
  90                 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) <<  8) | \
  91                 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >>  8) | \
  92                 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
  93
  94 #ifdef HOST_WORDS_BIGENDIAN
  95 #define PAT(x) cbswap_32(x)
  96 #else
  97 #define PAT(x) (x)
  98 #endif
  99
 100 #ifdef HOST_WORDS_BIGENDIAN
 101 #define BIG 1
 102 #else
 103 #define BIG 0
 104 #endif
 105
 106 #ifdef HOST_WORDS_BIGENDIAN
 107 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
 108 #else
 109 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
 110 #endif
 111
 112 static const uint32_t mask16[16] = {
 113     PAT(0x00000000),
 114     PAT(0x000000ff),
 115     PAT(0x0000ff00),
 116     PAT(0x0000ffff),
 117     PAT(0x00ff0000),
 118     PAT(0x00ff00ff),
 119     PAT(0x00ffff00),
 120     PAT(0x00ffffff),
 121     PAT(0xff000000),
 122     PAT(0xff0000ff),
 123     PAT(0xff00ff00),
 124     PAT(0xff00ffff),
 125     PAT(0xffff0000),
 126     PAT(0xffff00ff),
 127     PAT(0xffffff00),
 128     PAT(0xffffffff),
 129 };
 130
 131 #undef PAT
 132
 133 #ifdef HOST_WORDS_BIGENDIAN
 134 #define PAT(x) (x)
 135 #else
 136 #define PAT(x) cbswap_32(x)
 137 #endif
 138
 139 static const uint32_t dmask16[16] = {
 140     PAT(0x00000000),
 141     PAT(0x000000ff),
 142     PAT(0x0000ff00),
 143     PAT(0x0000ffff),
 144     PAT(0x00ff0000),
 145     PAT(0x00ff00ff),
 146     PAT(0x00ffff00),
 147     PAT(0x00ffffff),
 148     PAT(0xff000000),
 149     PAT(0xff0000ff),
 150     PAT(0xff00ff00),
 151     PAT(0xff00ffff),
 152     PAT(0xffff0000),
 153     PAT(0xffff00ff),
 154     PAT(0xffffff00),
 155     PAT(0xffffffff),
 156 };
 157
 158 static const uint32_t dmask4[4] = {
 159     PAT(0x00000000),
 160     PAT(0x0000ffff),
 161     PAT(0xffff0000),
 162     PAT(0xffffffff),
 163 };
 164
 165 static uint32_t expand4[256];
 166 static uint16_t expand2[256];
 167 static uint8_t expand4to8[16];
 168
 169 static void vga_update_memory_access(VGACommonState *s)
 170 {
 171     MemoryRegion *region, *old_region = s->chain4_alias;
 172     hwaddr base, offset, size;
 173
 174     s->chain4_alias = NULL;
 175
 176     if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==
 177         VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
 178         offset = 0;
 179         switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
 180         case 0:
 181             base = 0xa0000;
 182             size = 0x20000;
 183             break;
 184         case 1:
 185             base = 0xa0000;
 186             size = 0x10000;
 187             offset = s->bank_offset;
 188             break;
 189         case 2:
 190             base = 0xb0000;
 191             size = 0x8000;
 192             break;
 193         case 3:
 194         default:
 195             base = 0xb8000;
 196             size = 0x8000;
 197             break;
 198         }
 199         base += isa_mem_base;
 200         region = g_malloc(sizeof(*region));
 201         memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size);
 202         memory_region_add_subregion_overlap(s->legacy_address_space, base,
 203                                             region, 2);
 204         s->chain4_alias = region;
 205     }
 206     if (old_region) {
 207         memory_region_del_subregion(s->legacy_address_space, old_region);
 208         memory_region_destroy(old_region);
 209         g_free(old_region);
 210         s->plane_updated = 0xf;
 211     }
 212 }
 213
 214 static void vga_dumb_update_retrace_info(VGACommonState *s)
 215 {
 216     (void) s;
 217 }
 218
 219 static void vga_precise_update_retrace_info(VGACommonState *s)
 220 {
 221     int htotal_chars;
 222     int hretr_start_char;
 223     int hretr_skew_chars;
 224     int hretr_end_char;
 225
 226     int vtotal_lines;
 227     int vretr_start_line;
 228     int vretr_end_line;
 229
 230     int dots;
 231 #if 0
 232     int div2, sldiv2;
 233 #endif
 234     int clocking_mode;
 235     int clock_sel;
 236     const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
 237     int64_t chars_per_sec;
 238     struct vga_precise_retrace *r = &s->retrace_info.precise;
 239
 240     htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
 241     hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
 242     hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
 243     hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
 244
 245     vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
 246                     (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
 247                       ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
 248     vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
 249         ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
 250           ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
 251     vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
 252
 253     clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1;
 254     clock_sel = (s->msr >> 2) & 3;
 255     dots = (s->msr & 1) ? 8 : 9;
 256
 257     chars_per_sec = clk_hz[clock_sel] / dots;
 258
 259     htotal_chars <<= clocking_mode;
 260
 261     r->total_chars = vtotal_lines * htotal_chars;
 262     if (r->freq) {
 263         r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);
 264     } else {
 265         r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;
 266     }
 267
 268     r->vstart = vretr_start_line;
 269     r->vend = r->vstart + vretr_end_line + 1;
 270
 271     r->hstart = hretr_start_char + hretr_skew_chars;
 272     r->hend = r->hstart + hretr_end_char + 1;
 273     r->htotal = htotal_chars;
 274
 275 #if 0
 276     div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
 277     sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
 278     printf (
 279         "hz=%f\n"
 280         "htotal = %d\n"
 281         "hretr_start = %d\n"
 282         "hretr_skew = %d\n"
 283         "hretr_end = %d\n"
 284         "vtotal = %d\n"
 285         "vretr_start = %d\n"
 286         "vretr_end = %d\n"
 287         "div2 = %d sldiv2 = %d\n"
 288         "clocking_mode = %d\n"
 289         "clock_sel = %d %d\n"
 290         "dots = %d\n"
 291         "ticks/char = %" PRId64 "\n"
 292         "\n",
 293         (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
 294         htotal_chars,
 295         hretr_start_char,
 296         hretr_skew_chars,
 297         hretr_end_char,
 298         vtotal_lines,
 299         vretr_start_line,
 300         vretr_end_line,
 301         div2, sldiv2,
 302         clocking_mode,
 303         clock_sel,
 304         clk_hz[clock_sel],
 305         dots,
 306         r->ticks_per_char
 307         );
 308 #endif
 309 }
 310
 311 static uint8_t vga_precise_retrace(VGACommonState *s)
 312 {
 313     struct vga_precise_retrace *r = &s->retrace_info.precise;
 314     uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
 315
 316     if (r->total_chars) {
 317         int cur_line, cur_line_char, cur_char;
 318         int64_t cur_tick;
 319
 320         cur_tick = qemu_get_clock_ns(vm_clock);
 321
 322         cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
 323         cur_line = cur_char / r->htotal;
 324
 325         if (cur_line >= r->vstart && cur_line <= r->vend) {
 326             val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
 327         } else {
 328             cur_line_char = cur_char % r->htotal;
 329             if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
 330                 val |= ST01_DISP_ENABLE;
 331             }
 332         }
 333
 334         return val;
 335     } else {
 336         return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
 337     }
 338 }
 339
 340 static uint8_t vga_dumb_retrace(VGACommonState *s)
 341 {
 342     return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
 343 }
 344
 345 int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
 346 {
 347     if (s->msr & VGA_MIS_COLOR) {
 348         /* Color */
 349         return (addr >= 0x3b0 && addr <= 0x3bf);
 350     } else {
 351         /* Monochrome */
 352         return (addr >= 0x3d0 && addr <= 0x3df);
 353     }
 354 }
 355
 356 uint32_t vga_ioport_read(void *opaque, uint32_t addr)
 357 {
 358     VGACommonState *s = opaque;
 359     int val, index;
 360
 361     qemu_flush_coalesced_mmio_buffer();
 362
 363     if (vga_ioport_invalid(s, addr)) {
 364         val = 0xff;
 365     } else {
 366         switch(addr) {
 367         case VGA_ATT_W:
 368             if (s->ar_flip_flop == 0) {
 369                 val = s->ar_index;
 370             } else {
 371                 val = 0;
 372             }
 373             break;
 374         case VGA_ATT_R:
 375             index = s->ar_index & 0x1f;
 376             if (index < VGA_ATT_C) {
 377                 val = s->ar[index];
 378             } else {
 379                 val = 0;
 380             }
 381             break;
 382         case VGA_MIS_W:
 383             val = s->st00;
 384             break;
 385         case VGA_SEQ_I:
 386             val = s->sr_index;
 387             break;
 388         case VGA_SEQ_D:
 389             val = s->sr[s->sr_index];
 390 #ifdef DEBUG_VGA_REG
 391             printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
 392 #endif
 393             break;
 394         case VGA_PEL_IR:
 395             val = s->dac_state;
 396             break;
 397         case VGA_PEL_IW:
 398             val = s->dac_write_index;
 399             break;
 400         case VGA_PEL_D:
 401             val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
 402             if (++s->dac_sub_index == 3) {
 403                 s->dac_sub_index = 0;
 404                 s->dac_read_index++;
 405             }
 406             break;
 407         case VGA_FTC_R:
 408             val = s->fcr;
 409             break;
 410         case VGA_MIS_R:
 411             val = s->msr;
 412             break;
 413         case VGA_GFX_I:
 414             val = s->gr_index;
 415             break;
 416         case VGA_GFX_D:
 417             val = s->gr[s->gr_index];
 418 #ifdef DEBUG_VGA_REG
 419             printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
 420 #endif
 421             break;
 422         case VGA_CRT_IM:
 423         case VGA_CRT_IC:
 424             val = s->cr_index;
 425             break;
 426         case VGA_CRT_DM:
 427         case VGA_CRT_DC:
 428             val = s->cr[s->cr_index];
 429 #ifdef DEBUG_VGA_REG
 430             printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
 431 #endif
 432             break;
 433         case VGA_IS1_RM:
 434         case VGA_IS1_RC:
 435             /* just toggle to fool polling */
 436             val = s->st01 = s->retrace(s);
 437             s->ar_flip_flop = 0;
 438             break;
 439         default:
 440             val = 0x00;
 441             break;
 442         }
 443     }
 444 #if defined(DEBUG_VGA)
 445     printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
 446 #endif
 447     return val;
 448 }
 449
 450 void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 451 {
 452     VGACommonState *s = opaque;
 453     int index;
 454
 455     qemu_flush_coalesced_mmio_buffer();
 456
 457     /* check port range access depending on color/monochrome mode */
 458     if (vga_ioport_invalid(s, addr)) {
 459         return;
 460     }
 461 #ifdef DEBUG_VGA
 462     printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
 463 #endif
 464
 465     switch(addr) {
 466     case VGA_ATT_W:
 467         if (s->ar_flip_flop == 0) {
 468             val &= 0x3f;
 469             s->ar_index = val;
 470         } else {
 471             index = s->ar_index & 0x1f;
 472             switch(index) {
 473             case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
 474                 s->ar[index] = val & 0x3f;
 475                 break;
 476             case VGA_ATC_MODE:
 477                 s->ar[index] = val & ~0x10;
 478                 break;
 479             case VGA_ATC_OVERSCAN:
 480                 s->ar[index] = val;
 481                 break;
 482             case VGA_ATC_PLANE_ENABLE:
 483                 s->ar[index] = val & ~0xc0;
 484                 break;
 485             case VGA_ATC_PEL:
 486                 s->ar[index] = val & ~0xf0;
 487                 break;
 488             case VGA_ATC_COLOR_PAGE:
 489                 s->ar[index] = val & ~0xf0;
 490                 break;
 491             default:
 492                 break;
 493             }
 494         }
 495         s->ar_flip_flop ^= 1;
 496         break;
 497     case VGA_MIS_W:
 498         s->msr = val & ~0x10;
 499         s->update_retrace_info(s);
 500         break;
 501     case VGA_SEQ_I:
 502         s->sr_index = val & 7;
 503         break;
 504     case VGA_SEQ_D:
 505 #ifdef DEBUG_VGA_REG
 506         printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
 507 #endif
 508         s->sr[s->sr_index] = val & sr_mask[s->sr_index];
 509         if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
 510             s->update_retrace_info(s);
 511         }
 512         vga_update_memory_access(s);
 513         break;
 514     case VGA_PEL_IR:
 515         s->dac_read_index = val;
 516         s->dac_sub_index = 0;
 517         s->dac_state = 3;
 518         break;
 519     case VGA_PEL_IW:
 520         s->dac_write_index = val;
 521         s->dac_sub_index = 0;
 522         s->dac_state = 0;
 523         break;
 524     case VGA_PEL_D:
 525         s->dac_cache[s->dac_sub_index] = val;
 526         if (++s->dac_sub_index == 3) {
 527             memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
 528             s->dac_sub_index = 0;
 529             s->dac_write_index++;
 530         }
 531         break;
 532     case VGA_GFX_I:
 533         s->gr_index = val & 0x0f;
 534         break;
 535     case VGA_GFX_D:
 536 #ifdef DEBUG_VGA_REG
 537         printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
 538 #endif
 539         s->gr[s->gr_index] = val & gr_mask[s->gr_index];
 540         vga_update_memory_access(s);
 541         break;
 542     case VGA_CRT_IM:
 543     case VGA_CRT_IC:
 544         s->cr_index = val;
 545         break;
 546     case VGA_CRT_DM:
 547     case VGA_CRT_DC:
 548 #ifdef DEBUG_VGA_REG
 549         printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
 550 #endif
 551         /* handle CR0-7 protection */
 552         if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
 553             s->cr_index <= VGA_CRTC_OVERFLOW) {
 554             /* can always write bit 4 of CR7 */
 555             if (s->cr_index == VGA_CRTC_OVERFLOW) {
 556                 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
 557                     (val & 0x10);
 558             }
 559             return;
 560         }
 561         s->cr[s->cr_index] = val;
 562
 563         switch(s->cr_index) {
 564         case VGA_CRTC_H_TOTAL:
 565         case VGA_CRTC_H_SYNC_START:
 566         case VGA_CRTC_H_SYNC_END:
 567         case VGA_CRTC_V_TOTAL:
 568         case VGA_CRTC_OVERFLOW:
 569         case VGA_CRTC_V_SYNC_END:
 570         case VGA_CRTC_MODE:
 571             s->update_retrace_info(s);
 572             break;
 573         }
 574         break;
 575     case VGA_IS1_RM:
 576     case VGA_IS1_RC:
 577         s->fcr = val & 0x10;
 578         break;
 579     }
 580 }
 581
 582 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
 583 {
 584     VGACommonState *s = opaque;
 585     uint32_t val;
 586     val = s->vbe_index;
 587     return val;
 588 }
 589
 590 uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
 591 {
 592     VGACommonState *s = opaque;
 593     uint32_t val;
 594
 595     if (s->vbe_index < VBE_DISPI_INDEX_NB) {
 596         if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
 597             switch(s->vbe_index) {
 598                 /* XXX: do not hardcode ? */
 599             case VBE_DISPI_INDEX_XRES:
 600                 val = VBE_DISPI_MAX_XRES;
 601                 break;
 602             case VBE_DISPI_INDEX_YRES:
 603                 val = VBE_DISPI_MAX_YRES;
 604                 break;
 605             case VBE_DISPI_INDEX_BPP:
 606                 val = VBE_DISPI_MAX_BPP;
 607                 break;
 608             default:
 609                 val = s->vbe_regs[s->vbe_index];
 610                 break;
 611             }
 612         } else {
 613             val = s->vbe_regs[s->vbe_index];
 614         }
 615     } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
 616         val = s->vram_size / (64 * 1024);
 617     } else {
 618         val = 0;
 619     }
 620 #ifdef DEBUG_BOCHS_VBE
 621     printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
 622 #endif
 623     return val;
 624 }
 625
 626 void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
 627 {
 628     VGACommonState *s = opaque;
 629     s->vbe_index = val;
 630 }
 631
 632 void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
 633 {
 634     VGACommonState *s = opaque;
 635
 636     if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
 637 #ifdef DEBUG_BOCHS_VBE
 638         printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
 639 #endif
 640         switch(s->vbe_index) {
 641         case VBE_DISPI_INDEX_ID:
 642             if (val == VBE_DISPI_ID0 ||
 643                 val == VBE_DISPI_ID1 ||
 644                 val == VBE_DISPI_ID2 ||
 645                 val == VBE_DISPI_ID3 ||
 646                 val == VBE_DISPI_ID4) {
 647                 s->vbe_regs[s->vbe_index] = val;
 648             }
 649             break;
 650         case VBE_DISPI_INDEX_XRES:
 651             if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
 652                 s->vbe_regs[s->vbe_index] = val;
 653             }
 654             break;
 655         case VBE_DISPI_INDEX_YRES:
 656             if (val <= VBE_DISPI_MAX_YRES) {
 657                 s->vbe_regs[s->vbe_index] = val;
 658             }
 659             break;
 660         case VBE_DISPI_INDEX_BPP:
 661             if (val == 0)
 662                 val = 8;
 663             if (val == 4 || val == 8 || val == 15 ||
 664                 val == 16 || val == 24 || val == 32) {
 665                 s->vbe_regs[s->vbe_index] = val;
 666             }
 667             break;
 668         case VBE_DISPI_INDEX_BANK:
 669             if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
 670               val &= (s->vbe_bank_mask >> 2);
 671             } else {
 672               val &= s->vbe_bank_mask;
 673             }
 674             s->vbe_regs[s->vbe_index] = val;
 675             s->bank_offset = (val << 16);
 676             vga_update_memory_access(s);
 677             break;
 678         case VBE_DISPI_INDEX_ENABLE:
 679             if ((val & VBE_DISPI_ENABLED) &&
 680                 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
 681                 int h, shift_control;
 682
 683                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
 684                     s->vbe_regs[VBE_DISPI_INDEX_XRES];
 685                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
 686                     s->vbe_regs[VBE_DISPI_INDEX_YRES];
 687                 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
 688                 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
 689
 690                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
 691                     s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
 692                 else
 693                     s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
 694                         ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
 695                 s->vbe_start_addr = 0;
 696
 697                 /* clear the screen (should be done in BIOS) */
 698                 if (!(val & VBE_DISPI_NOCLEARMEM)) {
 699                     memset(s->vram_ptr, 0,
 700                            s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
 701                 }
 702
 703                 /* we initialize the VGA graphic mode (should be done
 704                    in BIOS) */
 705                 /* graphic mode + memory map 1 */
 706                 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
 707                     VGA_GR06_GRAPHICS_MODE;
 708                 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
 709                 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
 710                 /* width */
 711                 s->cr[VGA_CRTC_H_DISP] =
 712                     (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
 713                 /* height (only meaningful if < 1024) */
 714                 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
 715                 s->cr[VGA_CRTC_V_DISP_END] = h;
 716                 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
 717                     ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
 718                 /* line compare to 1023 */
 719                 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
 720                 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
 721                 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
 722
 723                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
 724                     shift_control = 0;
 725                     s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
 726                 } else {
 727                     shift_control = 2;
 728                     /* set chain 4 mode */
 729                     s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
 730                     /* activate all planes */
 731                     s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
 732                 }
 733                 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
 734                     (shift_control << 5);
 735                 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
 736             } else {
 737                 /* XXX: the bios should do that */
 738                 s->bank_offset = 0;
 739             }
 740             s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
 741             s->vbe_regs[s->vbe_index] = val;
 742             vga_update_memory_access(s);
 743             break;
 744         case VBE_DISPI_INDEX_VIRT_WIDTH:
 745             {
 746                 int w, h, line_offset;
 747
 748                 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
 749                     return;
 750                 w = val;
 751                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
 752                     line_offset = w >> 1;
 753                 else
 754                     line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
 755                 h = s->vram_size / line_offset;
 756                 /* XXX: support weird bochs semantics ? */
 757                 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
 758                     return;
 759                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
 760                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
 761                 s->vbe_line_offset = line_offset;
 762             }
 763             break;
 764         case VBE_DISPI_INDEX_X_OFFSET:
 765         case VBE_DISPI_INDEX_Y_OFFSET:
 766             {
 767                 int x;
 768                 s->vbe_regs[s->vbe_index] = val;
 769                 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
 770                 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
 771                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
 772                     s->vbe_start_addr += x >> 1;
 773                 else
 774                     s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
 775                 s->vbe_start_addr >>= 2;
 776             }
 777             break;
 778         default:
 779             break;
 780         }
 781     }
 782 }
 783
 784 /* called for accesses between 0xa0000 and 0xc0000 */
 785 uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
 786 {
 787     int memory_map_mode, plane;
 788     uint32_t ret;
 789
 790     /* convert to VGA memory offset */
 791     memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
 792     addr &= 0x1ffff;
 793     switch(memory_map_mode) {
 794     case 0:
 795         break;
 796     case 1:
 797         if (addr >= 0x10000)
 798             return 0xff;
 799         addr += s->bank_offset;
 800         break;
 801     case 2:
 802         addr -= 0x10000;
 803         if (addr >= 0x8000)
 804             return 0xff;
 805         break;
 806     default:
 807     case 3:
 808         addr -= 0x18000;
 809         if (addr >= 0x8000)
 810             return 0xff;
 811         break;
 812     }
 813
 814     if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
 815         /* chain 4 mode : simplest access */
 816         ret = s->vram_ptr[addr];
 817     } else if (s->gr[VGA_GFX_MODE] & 0x10) {
 818         /* odd/even mode (aka text mode mapping) */
 819         plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
 820         ret = s->vram_ptr[((addr & ~1) << 1) | plane];
 821     } else {
 822         /* standard VGA latched access */
 823         s->latch = ((uint32_t *)s->vram_ptr)[addr];
 824
 825         if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
 826             /* read mode 0 */
 827             plane = s->gr[VGA_GFX_PLANE_READ];
 828             ret = GET_PLANE(s->latch, plane);
 829         } else {
 830             /* read mode 1 */
 831             ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
 832                 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
 833             ret |= ret >> 16;
 834             ret |= ret >> 8;
 835             ret = (~ret) & 0xff;
 836         }
 837     }
 838     return ret;
 839 }
 840
 841 /* called for accesses between 0xa0000 and 0xc0000 */
 842 void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
 843 {
 844     int memory_map_mode, plane, write_mode, b, func_select, mask;
 845     uint32_t write_mask, bit_mask, set_mask;
 846
 847 #ifdef DEBUG_VGA_MEM
 848     printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
 849 #endif
 850     /* convert to VGA memory offset */
 851     memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
 852     addr &= 0x1ffff;
 853     switch(memory_map_mode) {
 854     case 0:
 855         break;
 856     case 1:
 857         if (addr >= 0x10000)
 858             return;
 859         addr += s->bank_offset;
 860         break;
 861     case 2:
 862         addr -= 0x10000;
 863         if (addr >= 0x8000)
 864             return;
 865         break;
 866     default:
 867     case 3:
 868         addr -= 0x18000;
 869         if (addr >= 0x8000)
 870             return;
 871         break;
 872     }
 873
 874     if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
 875         /* chain 4 mode : simplest access */
 876         plane = addr & 3;
 877         mask = (1 << plane);
 878         if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
 879             s->vram_ptr[addr] = val;
 880 #ifdef DEBUG_VGA_MEM
 881             printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
 882 #endif
 883             s->plane_updated |= mask; /* only used to detect font change */
 884             memory_region_set_dirty(&s->vram, addr, 1);
 885         }
 886     } else if (s->gr[VGA_GFX_MODE] & 0x10) {
 887         /* odd/even mode (aka text mode mapping) */
 888         plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
 889         mask = (1 << plane);
 890         if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
 891             addr = ((addr & ~1) << 1) | plane;
 892             s->vram_ptr[addr] = val;
 893 #ifdef DEBUG_VGA_MEM
 894             printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
 895 #endif
 896             s->plane_updated |= mask; /* only used to detect font change */
 897             memory_region_set_dirty(&s->vram, addr, 1);
 898         }
 899     } else {
 900         /* standard VGA latched access */
 901         write_mode = s->gr[VGA_GFX_MODE] & 3;
 902         switch(write_mode) {
 903         default:
 904         case 0:
 905             /* rotate */
 906             b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
 907             val = ((val >> b) | (val << (8 - b))) & 0xff;
 908             val |= val << 8;
 909             val |= val << 16;
 910
 911             /* apply set/reset mask */
 912             set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
 913             val = (val & ~set_mask) |
 914                 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
 915             bit_mask = s->gr[VGA_GFX_BIT_MASK];
 916             break;
 917         case 1:
 918             val = s->latch;
 919             goto do_write;
 920         case 2:
 921             val = mask16[val & 0x0f];
 922             bit_mask = s->gr[VGA_GFX_BIT_MASK];
 923             break;
 924         case 3:
 925             /* rotate */
 926             b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
 927             val = (val >> b) | (val << (8 - b));
 928
 929             bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
 930             val = mask16[s->gr[VGA_GFX_SR_VALUE]];
 931             break;
 932         }
 933
 934         /* apply logical operation */
 935         func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
 936         switch(func_select) {
 937         case 0:
 938         default:
 939             /* nothing to do */
 940             break;
 941         case 1:
 942             /* and */
 943             val &= s->latch;
 944             break;
 945         case 2:
 946             /* or */
 947             val |= s->latch;
 948             break;
 949         case 3:
 950             /* xor */
 951             val ^= s->latch;
 952             break;
 953         }
 954
 955         /* apply bit mask */
 956         bit_mask |= bit_mask << 8;
 957         bit_mask |= bit_mask << 16;
 958         val = (val & bit_mask) | (s->latch & ~bit_mask);
 959
 960     do_write:
 961         /* mask data according to sr[2] */
 962         mask = s->sr[VGA_SEQ_PLANE_WRITE];
 963         s->plane_updated |= mask; /* only used to detect font change */
 964         write_mask = mask16[mask];
 965         ((uint32_t *)s->vram_ptr)[addr] =
 966             (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
 967             (val & write_mask);
 968 #ifdef DEBUG_VGA_MEM
 969         printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
 970                addr * 4, write_mask, val);
 971 #endif
 972         memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
 973     }
 974 }
 975
 976 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
 977                              const uint8_t *font_ptr, int h,
 978                              uint32_t fgcol, uint32_t bgcol);
 979 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
 980                                   const uint8_t *font_ptr, int h,
 981                                   uint32_t fgcol, uint32_t bgcol, int dup9);
 982 typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
 983                                 const uint8_t *s, int width);
 984
 985 #define DEPTH 8
 986 #include "vga_template.h"
 987
 988 #define DEPTH 15
 989 #include "vga_template.h"
 990
 991 #define BGR_FORMAT
 992 #define DEPTH 15
 993 #include "vga_template.h"
 994
 995 #define DEPTH 16
 996 #include "vga_template.h"
 997
 998 #define BGR_FORMAT
 999 #define DEPTH 16
1000 #include "vga_template.h"
1001
1002 #define DEPTH 32
1003 #include "vga_template.h"
1004
1005 #define BGR_FORMAT
1006 #define DEPTH 32
1007 #include "vga_template.h"
1008
1009 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1010 {
1011     unsigned int col;
1012     col = rgb_to_pixel8(r, g, b);
1013     col |= col << 8;
1014     col |= col << 16;
1015     return col;
1016 }
1017
1018 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1019 {
1020     unsigned int col;
1021     col = rgb_to_pixel15(r, g, b);
1022     col |= col << 16;
1023     return col;
1024 }
1025
1026 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1027                                           unsigned int b)
1028 {
1029     unsigned int col;
1030     col = rgb_to_pixel15bgr(r, g, b);
1031     col |= col << 16;
1032     return col;
1033 }
1034
1035 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1036 {
1037     unsigned int col;
1038     col = rgb_to_pixel16(r, g, b);
1039     col |= col << 16;
1040     return col;
1041 }
1042
1043 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1044                                           unsigned int b)
1045 {
1046     unsigned int col;
1047     col = rgb_to_pixel16bgr(r, g, b);
1048     col |= col << 16;
1049     return col;
1050 }
1051
1052 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1053 {
1054     unsigned int col;
1055     col = rgb_to_pixel32(r, g, b);
1056     return col;
1057 }
1058
1059 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1060 {
1061     unsigned int col;
1062     col = rgb_to_pixel32bgr(r, g, b);
1063     return col;
1064 }
1065
1066 /* return true if the palette was modified */
1067 static int update_palette16(VGACommonState *s)
1068 {
1069     int full_update, i;
1070     uint32_t v, col, *palette;
1071
1072     full_update = 0;
1073     palette = s->last_palette;
1074     for(i = 0; i < 16; i++) {
1075         v = s->ar[i];
1076         if (s->ar[VGA_ATC_MODE] & 0x80) {
1077             v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1078         } else {
1079             v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1080         }
1081         v = v * 3;
1082         col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1083                               c6_to_8(s->palette[v + 1]),
1084                               c6_to_8(s->palette[v + 2]));
1085         if (col != palette[i]) {
1086             full_update = 1;
1087             palette[i] = col;
1088         }
1089     }
1090     return full_update;
1091 }
1092
1093 /* return true if the palette was modified */
1094 static int update_palette256(VGACommonState *s)
1095 {
1096     int full_update, i;
1097     uint32_t v, col, *palette;
1098
1099     full_update = 0;
1100     palette = s->last_palette;
1101     v = 0;
1102     for(i = 0; i < 256; i++) {
1103         if (s->dac_8bit) {
1104           col = s->rgb_to_pixel(s->palette[v],
1105                                 s->palette[v + 1],
1106                                 s->palette[v + 2]);
1107         } else {
1108           col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1109                                 c6_to_8(s->palette[v + 1]),
1110                                 c6_to_8(s->palette[v + 2]));
1111         }
1112         if (col != palette[i]) {
1113             full_update = 1;
1114             palette[i] = col;
1115         }
1116         v += 3;
1117     }
1118     return full_update;
1119 }
1120
1121 static void vga_get_offsets(VGACommonState *s,
1122                             uint32_t *pline_offset,
1123                             uint32_t *pstart_addr,
1124                             uint32_t *pline_compare)
1125 {
1126     uint32_t start_addr, line_offset, line_compare;
1127
1128     if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1129         line_offset = s->vbe_line_offset;
1130         start_addr = s->vbe_start_addr;
1131         line_compare = 65535;
1132     } else {
1133         /* compute line_offset in bytes */
1134         line_offset = s->cr[VGA_CRTC_OFFSET];
1135         line_offset <<= 3;
1136
1137         /* starting address */
1138         start_addr = s->cr[VGA_CRTC_START_LO] |
1139             (s->cr[VGA_CRTC_START_HI] << 8);
1140
1141         /* line compare */
1142         line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1143             ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1144             ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
1145     }
1146     *pline_offset = line_offset;
1147     *pstart_addr = start_addr;
1148     *pline_compare = line_compare;
1149 }
1150
1151 /* update start_addr and line_offset. Return TRUE if modified */
1152 static int update_basic_params(VGACommonState *s)
1153 {
1154     int full_update;
1155     uint32_t start_addr, line_offset, line_compare;
1156
1157     full_update = 0;
1158
1159     s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1160
1161     if (line_offset != s->line_offset ||
1162         start_addr != s->start_addr ||
1163         line_compare != s->line_compare) {
1164         s->line_offset = line_offset;
1165         s->start_addr = start_addr;
1166         s->line_compare = line_compare;
1167         full_update = 1;
1168     }
1169     return full_update;
1170 }
1171
1172 #define NB_DEPTHS 7
1173
1174 static inline int get_depth_index(DisplaySurface *s)
1175 {
1176     switch (surface_bits_per_pixel(s)) {
1177     default:
1178     case 8:
1179         return 0;
1180     case 15:
1181         return 1;
1182     case 16:
1183         return 2;
1184     case 32:
1185         if (is_surface_bgr(s)) {
1186             return 4;
1187         } else {
1188             return 3;
1189         }
1190     }
1191 }
1192
1193 static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = {
1194     vga_draw_glyph8_8,
1195     vga_draw_glyph8_16,
1196     vga_draw_glyph8_16,
1197     vga_draw_glyph8_32,
1198     vga_draw_glyph8_32,
1199     vga_draw_glyph8_16,
1200     vga_draw_glyph8_16,
1201 };
1202
1203 static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = {
1204     vga_draw_glyph16_8,
1205     vga_draw_glyph16_16,
1206     vga_draw_glyph16_16,
1207     vga_draw_glyph16_32,
1208     vga_draw_glyph16_32,
1209     vga_draw_glyph16_16,
1210     vga_draw_glyph16_16,
1211 };
1212
1213 static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = {
1214     vga_draw_glyph9_8,
1215     vga_draw_glyph9_16,
1216     vga_draw_glyph9_16,
1217     vga_draw_glyph9_32,
1218     vga_draw_glyph9_32,
1219     vga_draw_glyph9_16,
1220     vga_draw_glyph9_16,
1221 };
1222
1223 static const uint8_t cursor_glyph[32 * 4] = {
1224     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1225     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1226     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1227     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1228     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1229     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1230     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1231     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1232     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1233     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1234     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1235     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1236     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1237     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1238     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1239     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1240 };
1241
1242 static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
1243                                     int *pcwidth, int *pcheight)
1244 {
1245     int width, cwidth, height, cheight;
1246
1247     /* total width & height */
1248     cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1249     cwidth = 8;
1250     if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
1251         cwidth = 9;
1252     }
1253     if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
1254         cwidth = 16; /* NOTE: no 18 pixel wide */
1255     }
1256     width = (s->cr[VGA_CRTC_H_DISP] + 1);
1257     if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1258         /* ugly hack for CGA 160x100x16 - explain me the logic */
1259         height = 100;
1260     } else {
1261         height = s->cr[VGA_CRTC_V_DISP_END] |
1262             ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1263             ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1264         height = (height + 1) / cheight;
1265     }
1266
1267     *pwidth = width;
1268     *pheight = height;
1269     *pcwidth = cwidth;
1270     *pcheight = cheight;
1271 }
1272
1273 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1274
1275 static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = {
1276     rgb_to_pixel8_dup,
1277     rgb_to_pixel15_dup,
1278     rgb_to_pixel16_dup,
1279     rgb_to_pixel32_dup,
1280     rgb_to_pixel32bgr_dup,
1281     rgb_to_pixel15bgr_dup,
1282     rgb_to_pixel16bgr_dup,
1283 };
1284
1285 /*
1286  * Text mode update
1287  * Missing:
1288  * - double scan
1289  * - double width
1290  * - underline
1291  * - flashing
1292  */
1293 static void vga_draw_text(VGACommonState *s, int full_update)
1294 {
1295     DisplaySurface *surface = qemu_console_surface(s->con);
1296     int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1297     int cx_min, cx_max, linesize, x_incr, line, line1;
1298     uint32_t offset, fgcol, bgcol, v, cursor_offset;
1299     uint8_t *d1, *d, *src, *dest, *cursor_ptr;
1300     const uint8_t *font_ptr, *font_base[2];
1301     int dup9, line_offset, depth_index;
1302     uint32_t *palette;
1303     uint32_t *ch_attr_ptr;
1304     vga_draw_glyph8_func *vga_draw_glyph8;
1305     vga_draw_glyph9_func *vga_draw_glyph9;
1306     int64_t now = qemu_get_clock_ms(vm_clock);
1307
1308     /* compute font data address (in plane 2) */
1309     v = s->sr[VGA_SEQ_CHARACTER_MAP];
1310     offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1311     if (offset != s->font_offsets[0]) {
1312         s->font_offsets[0] = offset;
1313         full_update = 1;
1314     }
1315     font_base[0] = s->vram_ptr + offset;
1316
1317     offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1318     font_base[1] = s->vram_ptr + offset;
1319     if (offset != s->font_offsets[1]) {
1320         s->font_offsets[1] = offset;
1321         full_update = 1;
1322     }
1323     if (s->plane_updated & (1 << 2) || s->chain4_alias) {
1324         /* if the plane 2 was modified since the last display, it
1325            indicates the font may have been modified */
1326         s->plane_updated = 0;
1327         full_update = 1;
1328     }
1329     full_update |= update_basic_params(s);
1330
1331     line_offset = s->line_offset;
1332
1333     vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1334     if ((height * width) <= 1) {
1335         /* better than nothing: exit if transient size is too small */
1336         return;
1337     }
1338     if ((height * width) > CH_ATTR_SIZE) {
1339         /* better than nothing: exit if transient size is too big */
1340         return;
1341     }
1342
1343     if (width != s->last_width || height != s->last_height ||
1344         cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1345         s->last_scr_width = width * cw;
1346         s->last_scr_height = height * cheight;
1347         qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
1348         surface = qemu_console_surface(s->con);
1349         dpy_text_resize(s->con, width, height);
1350         s->last_depth = 0;
1351         s->last_width = width;
1352         s->last_height = height;
1353         s->last_ch = cheight;
1354         s->last_cw = cw;
1355         full_update = 1;
1356     }
1357     s->rgb_to_pixel =
1358         rgb_to_pixel_dup_table[get_depth_index(surface)];
1359     full_update |= update_palette16(s);
1360     palette = s->last_palette;
1361     x_incr = cw * surface_bytes_per_pixel(surface);
1362
1363     if (full_update) {
1364         s->full_update_text = 1;
1365     }
1366     if (s->full_update_gfx) {
1367         s->full_update_gfx = 0;
1368         full_update |= 1;
1369     }
1370
1371     cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1372                      s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1373     if (cursor_offset != s->cursor_offset ||
1374         s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1375         s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
1376       /* if the cursor position changed, we update the old and new
1377          chars */
1378         if (s->cursor_offset < CH_ATTR_SIZE)
1379             s->last_ch_attr[s->cursor_offset] = -1;
1380         if (cursor_offset < CH_ATTR_SIZE)
1381             s->last_ch_attr[cursor_offset] = -1;
1382         s->cursor_offset = cursor_offset;
1383         s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1384         s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1385     }
1386     cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1387     if (now >= s->cursor_blink_time) {
1388         s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2;
1389         s->cursor_visible_phase = !s->cursor_visible_phase;
1390     }
1391
1392     depth_index = get_depth_index(surface);
1393     if (cw == 16)
1394         vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1395     else
1396         vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1397     vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1398
1399     dest = surface_data(surface);
1400     linesize = surface_stride(surface);
1401     ch_attr_ptr = s->last_ch_attr;
1402     line = 0;
1403     offset = s->start_addr * 4;
1404     for(cy = 0; cy < height; cy++) {
1405         d1 = dest;
1406         src = s->vram_ptr + offset;
1407         cx_min = width;
1408         cx_max = -1;
1409         for(cx = 0; cx < width; cx++) {
1410             ch_attr = *(uint16_t *)src;
1411             if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) {
1412                 if (cx < cx_min)
1413                     cx_min = cx;
1414                 if (cx > cx_max)
1415                     cx_max = cx;
1416                 *ch_attr_ptr = ch_attr;
1417 #ifdef HOST_WORDS_BIGENDIAN
1418                 ch = ch_attr >> 8;
1419                 cattr = ch_attr & 0xff;
1420 #else
1421                 ch = ch_attr & 0xff;
1422                 cattr = ch_attr >> 8;
1423 #endif
1424                 font_ptr = font_base[(cattr >> 3) & 1];
1425                 font_ptr += 32 * 4 * ch;
1426                 bgcol = palette[cattr >> 4];
1427                 fgcol = palette[cattr & 0x0f];
1428                 if (cw != 9) {
1429                     vga_draw_glyph8(d1, linesize,
1430                                     font_ptr, cheight, fgcol, bgcol);
1431                 } else {
1432                     dup9 = 0;
1433                     if (ch >= 0xb0 && ch <= 0xdf &&
1434                         (s->ar[VGA_ATC_MODE] & 0x04)) {
1435                         dup9 = 1;
1436                     }
1437                     vga_draw_glyph9(d1, linesize,
1438                                     font_ptr, cheight, fgcol, bgcol, dup9);
1439                 }
1440                 if (src == cursor_ptr &&
1441                     !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) &&
1442                     s->cursor_visible_phase) {
1443                     int line_start, line_last, h;
1444                     /* draw the cursor */
1445                     line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1446                     line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
1447                     /* XXX: check that */
1448                     if (line_last > cheight - 1)
1449                         line_last = cheight - 1;
1450                     if (line_last >= line_start && line_start < cheight) {
1451                         h = line_last - line_start + 1;
1452                         d = d1 + linesize * line_start;
1453                         if (cw != 9) {
1454                             vga_draw_glyph8(d, linesize,
1455                                             cursor_glyph, h, fgcol, bgcol);
1456                         } else {
1457                             vga_draw_glyph9(d, linesize,
1458                                             cursor_glyph, h, fgcol, bgcol, 1);
1459                         }
1460                     }
1461                 }
1462             }
1463             d1 += x_incr;
1464             src += 4;
1465             ch_attr_ptr++;
1466         }
1467         if (cx_max != -1) {
1468             dpy_gfx_update(s->con, cx_min * cw, cy * cheight,
1469                            (cx_max - cx_min + 1) * cw, cheight);
1470         }
1471         dest += linesize * cheight;
1472         line1 = line + cheight;
1473         offset += line_offset;
1474         if (line < s->line_compare && line1 >= s->line_compare) {
1475             offset = 0;
1476         }
1477         line = line1;
1478     }
1479 }
1480
1481 enum {
1482     VGA_DRAW_LINE2,
1483     VGA_DRAW_LINE2D2,
1484     VGA_DRAW_LINE4,
1485     VGA_DRAW_LINE4D2,
1486     VGA_DRAW_LINE8D2,
1487     VGA_DRAW_LINE8,
1488     VGA_DRAW_LINE15,
1489     VGA_DRAW_LINE16,
1490     VGA_DRAW_LINE24,
1491     VGA_DRAW_LINE32,
1492     VGA_DRAW_LINE_NB,
1493 };
1494
1495 static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1496     vga_draw_line2_8,
1497     vga_draw_line2_16,
1498     vga_draw_line2_16,
1499     vga_draw_line2_32,
1500     vga_draw_line2_32,
1501     vga_draw_line2_16,
1502     vga_draw_line2_16,
1503
1504     vga_draw_line2d2_8,
1505     vga_draw_line2d2_16,
1506     vga_draw_line2d2_16,
1507     vga_draw_line2d2_32,
1508     vga_draw_line2d2_32,
1509     vga_draw_line2d2_16,
1510     vga_draw_line2d2_16,
1511
1512     vga_draw_line4_8,
1513     vga_draw_line4_16,
1514     vga_draw_line4_16,
1515     vga_draw_line4_32,
1516     vga_draw_line4_32,
1517     vga_draw_line4_16,
1518     vga_draw_line4_16,
1519
1520     vga_draw_line4d2_8,
1521     vga_draw_line4d2_16,
1522     vga_draw_line4d2_16,
1523     vga_draw_line4d2_32,
1524     vga_draw_line4d2_32,
1525     vga_draw_line4d2_16,
1526     vga_draw_line4d2_16,
1527
1528     vga_draw_line8d2_8,
1529     vga_draw_line8d2_16,
1530     vga_draw_line8d2_16,
1531     vga_draw_line8d2_32,
1532     vga_draw_line8d2_32,
1533     vga_draw_line8d2_16,
1534     vga_draw_line8d2_16,
1535
1536     vga_draw_line8_8,
1537     vga_draw_line8_16,
1538     vga_draw_line8_16,
1539     vga_draw_line8_32,
1540     vga_draw_line8_32,
1541     vga_draw_line8_16,
1542     vga_draw_line8_16,
1543
1544     vga_draw_line15_8,
1545     vga_draw_line15_15,
1546     vga_draw_line15_16,
1547     vga_draw_line15_32,
1548     vga_draw_line15_32bgr,
1549     vga_draw_line15_15bgr,
1550     vga_draw_line15_16bgr,
1551
1552     vga_draw_line16_8,
1553     vga_draw_line16_15,
1554     vga_draw_line16_16,
1555     vga_draw_line16_32,
1556     vga_draw_line16_32bgr,
1557     vga_draw_line16_15bgr,
1558     vga_draw_line16_16bgr,
1559
1560     vga_draw_line24_8,
1561     vga_draw_line24_15,
1562     vga_draw_line24_16,
1563     vga_draw_line24_32,
1564     vga_draw_line24_32bgr,
1565     vga_draw_line24_15bgr,
1566     vga_draw_line24_16bgr,
1567
1568     vga_draw_line32_8,
1569     vga_draw_line32_15,
1570     vga_draw_line32_16,
1571     vga_draw_line32_32,
1572     vga_draw_line32_32bgr,
1573     vga_draw_line32_15bgr,
1574     vga_draw_line32_16bgr,
1575 };
1576
1577 static int vga_get_bpp(VGACommonState *s)
1578 {
1579     int ret;
1580
1581     if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1582         ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1583     } else {
1584         ret = 0;
1585     }
1586     return ret;
1587 }
1588
1589 static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1590 {
1591     int width, height;
1592
1593     if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1594         width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1595         height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1596     } else {
1597         width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1598         height = s->cr[VGA_CRTC_V_DISP_END] |
1599             ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1600             ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1601         height = (height + 1);
1602     }
1603     *pwidth = width;
1604     *pheight = height;
1605 }
1606
1607 void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
1608 {
1609     int y;
1610     if (y1 >= VGA_MAX_HEIGHT)
1611         return;
1612     if (y2 >= VGA_MAX_HEIGHT)
1613         y2 = VGA_MAX_HEIGHT;
1614     for(y = y1; y < y2; y++) {
1615         s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1616     }
1617 }
1618
1619 void vga_sync_dirty_bitmap(VGACommonState *s)
1620 {
1621     memory_region_sync_dirty_bitmap(&s->vram);
1622 }
1623
1624 void vga_dirty_log_start(VGACommonState *s)
1625 {
1626     memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
1627 }
1628
1629 void vga_dirty_log_stop(VGACommonState *s)
1630 {
1631     memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
1632 }
1633
1634 /*
1635  * graphic modes
1636  */
1637 static void vga_draw_graphic(VGACommonState *s, int full_update)
1638 {
1639     DisplaySurface *surface = qemu_console_surface(s->con);
1640     int y1, y, update, linesize, y_start, double_scan, mask, depth;
1641     int width, height, shift_control, line_offset, bwidth, bits;
1642     ram_addr_t page0, page1, page_min, page_max;
1643     int disp_width, multi_scan, multi_run;
1644     uint8_t *d;
1645     uint32_t v, addr1, addr;
1646     vga_draw_line_func *vga_draw_line;
1647 #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1648     static const bool byteswap = false;
1649 #else
1650     static const bool byteswap = true;
1651 #endif
1652
1653     full_update |= update_basic_params(s);
1654
1655     if (!full_update)
1656         vga_sync_dirty_bitmap(s);
1657
1658     s->get_resolution(s, &width, &height);
1659     disp_width = width;
1660
1661     shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1662     double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
1663     if (shift_control != 1) {
1664         multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1665             - 1;
1666     } else {
1667         /* in CGA modes, multi_scan is ignored */
1668         /* XXX: is it correct ? */
1669         multi_scan = double_scan;
1670     }
1671     multi_run = multi_scan;
1672     if (shift_control != s->shift_control ||
1673         double_scan != s->double_scan) {
1674         full_update = 1;
1675         s->shift_control = shift_control;
1676         s->double_scan = double_scan;
1677     }
1678
1679     if (shift_control == 0) {
1680         if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1681             disp_width <<= 1;
1682         }
1683     } else if (shift_control == 1) {
1684         if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1685             disp_width <<= 1;
1686         }
1687     }
1688
1689     depth = s->get_bpp(s);
1690     if (s->line_offset != s->last_line_offset ||
1691         disp_width != s->last_width ||
1692         height != s->last_height ||
1693         s->last_depth != depth) {
1694         if (depth == 32 || (depth == 16 && !byteswap)) {
1695             surface = qemu_create_displaysurface_from(disp_width,
1696                     height, depth, s->line_offset,
1697                     s->vram_ptr + (s->start_addr * 4), byteswap);
1698             dpy_gfx_replace_surface(s->con, surface);
1699         } else {
1700             qemu_console_resize(s->con, disp_width, height);
1701             surface = qemu_console_surface(s->con);
1702         }
1703         s->last_scr_width = disp_width;
1704         s->last_scr_height = height;
1705         s->last_width = disp_width;
1706         s->last_height = height;
1707         s->last_line_offset = s->line_offset;
1708         s->last_depth = depth;
1709         full_update = 1;
1710     } else if (is_buffer_shared(surface) &&
1711                (full_update || surface_data(surface) != s->vram_ptr
1712                 + (s->start_addr * 4))) {
1713         DisplaySurface *surface;
1714         surface = qemu_create_displaysurface_from(disp_width,
1715                 height, depth, s->line_offset,
1716                 s->vram_ptr + (s->start_addr * 4), byteswap);
1717         dpy_gfx_replace_surface(s->con, surface);
1718     }
1719
1720     s->rgb_to_pixel =
1721         rgb_to_pixel_dup_table[get_depth_index(surface)];
1722
1723     if (shift_control == 0) {
1724         full_update |= update_palette16(s);
1725         if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1726             v = VGA_DRAW_LINE4D2;
1727         } else {
1728             v = VGA_DRAW_LINE4;
1729         }
1730         bits = 4;
1731     } else if (shift_control == 1) {
1732         full_update |= update_palette16(s);
1733         if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1734             v = VGA_DRAW_LINE2D2;
1735         } else {
1736             v = VGA_DRAW_LINE2;
1737         }
1738         bits = 4;
1739     } else {
1740         switch(s->get_bpp(s)) {
1741         default:
1742         case 0:
1743             full_update |= update_palette256(s);
1744             v = VGA_DRAW_LINE8D2;
1745             bits = 4;
1746             break;
1747         case 8:
1748             full_update |= update_palette256(s);
1749             v = VGA_DRAW_LINE8;
1750             bits = 8;
1751             break;
1752         case 15:
1753             v = VGA_DRAW_LINE15;
1754             bits = 16;
1755             break;
1756         case 16:
1757             v = VGA_DRAW_LINE16;
1758             bits = 16;
1759             break;
1760         case 24:
1761             v = VGA_DRAW_LINE24;
1762             bits = 24;
1763             break;
1764         case 32:
1765             v = VGA_DRAW_LINE32;
1766             bits = 32;
1767             break;
1768         }
1769     }
1770     vga_draw_line = vga_draw_line_table[v * NB_DEPTHS +
1771                                         get_depth_index(surface)];
1772
1773     if (!is_buffer_shared(surface) && s->cursor_invalidate) {
1774         s->cursor_invalidate(s);
1775     }
1776
1777     line_offset = s->line_offset;
1778 #if 0
1779     printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1780            width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1781            s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]);
1782 #endif
1783     addr1 = (s->start_addr * 4);
1784     bwidth = (width * bits + 7) / 8;
1785     y_start = -1;
1786     page_min = -1;
1787     page_max = 0;
1788     d = surface_data(surface);
1789     linesize = surface_stride(surface);
1790     y1 = 0;
1791     for(y = 0; y < height; y++) {
1792         addr = addr1;
1793         if (!(s->cr[VGA_CRTC_MODE] & 1)) {
1794             int shift;
1795             /* CGA compatibility handling */
1796             shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
1797             addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1798         }
1799         if (!(s->cr[VGA_CRTC_MODE] & 2)) {
1800             addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1801         }
1802         update = full_update;
1803         page0 = addr;
1804         page1 = addr + bwidth - 1;
1805         update |= memory_region_get_dirty(&s->vram, page0, page1 - page0,
1806                                           DIRTY_MEMORY_VGA);
1807         /* explicit invalidation for the hardware cursor */
1808         update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1809         if (update) {
1810             if (y_start < 0)
1811                 y_start = y;
1812             if (page0 < page_min)
1813                 page_min = page0;
1814             if (page1 > page_max)
1815                 page_max = page1;
1816             if (!(is_buffer_shared(surface))) {
1817                 vga_draw_line(s, d, s->vram_ptr + addr, width);
1818                 if (s->cursor_draw_line)
1819                     s->cursor_draw_line(s, d, y);
1820             }
1821         } else {
1822             if (y_start >= 0) {
1823                 /* flush to display */
1824                 dpy_gfx_update(s->con, 0, y_start,
1825                                disp_width, y - y_start);
1826                 y_start = -1;
1827             }
1828         }
1829         if (!multi_run) {
1830             mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
1831             if ((y1 & mask) == mask)
1832                 addr1 += line_offset;
1833             y1++;
1834             multi_run = multi_scan;
1835         } else {
1836             multi_run--;
1837         }
1838         /* line compare acts on the displayed lines */
1839         if (y == s->line_compare)
1840             addr1 = 0;
1841         d += linesize;
1842     }
1843     if (y_start >= 0) {
1844         /* flush to display */
1845         dpy_gfx_update(s->con, 0, y_start,
1846                        disp_width, y - y_start);
1847     }
1848     /* reset modified pages */
1849     if (page_max >= page_min) {
1850         memory_region_reset_dirty(&s->vram,
1851                                   page_min,
1852                                   page_max - page_min,
1853                                   DIRTY_MEMORY_VGA);
1854     }
1855     memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1856 }
1857
1858 static void vga_draw_blank(VGACommonState *s, int full_update)
1859 {
1860     DisplaySurface *surface = qemu_console_surface(s->con);
1861     int i, w, val;
1862     uint8_t *d;
1863
1864     if (!full_update)
1865         return;
1866     if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1867         return;
1868
1869     s->rgb_to_pixel =
1870         rgb_to_pixel_dup_table[get_depth_index(surface)];
1871     if (surface_bits_per_pixel(surface) == 8) {
1872         val = s->rgb_to_pixel(0, 0, 0);
1873     } else {
1874         val = 0;
1875     }
1876     w = s->last_scr_width * surface_bytes_per_pixel(surface);
1877     d = surface_data(surface);
1878     for(i = 0; i < s->last_scr_height; i++) {
1879         memset(d, val, w);
1880         d += surface_stride(surface);
1881     }
1882     dpy_gfx_update(s->con, 0, 0,
1883                    s->last_scr_width, s->last_scr_height);
1884 }
1885
1886 #define GMODE_TEXT     0
1887 #define GMODE_GRAPH    1
1888 #define GMODE_BLANK 2
1889
1890 static void vga_update_display(void *opaque)
1891 {
1892     VGACommonState *s = opaque;
1893     DisplaySurface *surface = qemu_console_surface(s->con);
1894     int full_update, graphic_mode;
1895
1896     qemu_flush_coalesced_mmio_buffer();
1897
1898     if (surface_bits_per_pixel(surface) == 0) {
1899         /* nothing to do */
1900     } else {
1901         full_update = 0;
1902         if (!(s->ar_index & 0x20)) {
1903             graphic_mode = GMODE_BLANK;
1904         } else {
1905             graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1906         }
1907         if (graphic_mode != s->graphic_mode) {
1908             s->graphic_mode = graphic_mode;
1909             s->cursor_blink_time = qemu_get_clock_ms(vm_clock);
1910             full_update = 1;
1911         }
1912         switch(graphic_mode) {
1913         case GMODE_TEXT:
1914             vga_draw_text(s, full_update);
1915             break;
1916         case GMODE_GRAPH:
1917             vga_draw_graphic(s, full_update);
1918             break;
1919         case GMODE_BLANK:
1920         default:
1921             vga_draw_blank(s, full_update);
1922             break;
1923         }
1924     }
1925 }
1926
1927 /* force a full display refresh */
1928 static void vga_invalidate_display(void *opaque)
1929 {
1930     VGACommonState *s = opaque;
1931
1932     s->last_width = -1;
1933     s->last_height = -1;
1934 }
1935
1936 void vga_common_reset(VGACommonState *s)
1937 {
1938     s->sr_index = 0;
1939     memset(s->sr, '\0', sizeof(s->sr));
1940     s->gr_index = 0;
1941     memset(s->gr, '\0', sizeof(s->gr));
1942     s->ar_index = 0;
1943     memset(s->ar, '\0', sizeof(s->ar));
1944     s->ar_flip_flop = 0;
1945     s->cr_index = 0;
1946     memset(s->cr, '\0', sizeof(s->cr));
1947     s->msr = 0;
1948     s->fcr = 0;
1949     s->st00 = 0;
1950     s->st01 = 0;
1951     s->dac_state = 0;
1952     s->dac_sub_index = 0;
1953     s->dac_read_index = 0;
1954     s->dac_write_index = 0;
1955     memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1956     s->dac_8bit = 0;
1957     memset(s->palette, '\0', sizeof(s->palette));
1958     s->bank_offset = 0;
1959     s->vbe_index = 0;
1960     memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1961     s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
1962     s->vbe_start_addr = 0;
1963     s->vbe_line_offset = 0;
1964     s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1965     memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1966     s->graphic_mode = -1; /* force full update */
1967     s->shift_control = 0;
1968     s->double_scan = 0;
1969     s->line_offset = 0;
1970     s->line_compare = 0;
1971     s->start_addr = 0;
1972     s->plane_updated = 0;
1973     s->last_cw = 0;
1974     s->last_ch = 0;
1975     s->last_width = 0;
1976     s->last_height = 0;
1977     s->last_scr_width = 0;
1978     s->last_scr_height = 0;
1979     s->cursor_start = 0;
1980     s->cursor_end = 0;
1981     s->cursor_offset = 0;
1982     memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1983     memset(s->last_palette, '\0', sizeof(s->last_palette));
1984     memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1985     switch (vga_retrace_method) {
1986     case VGA_RETRACE_DUMB:
1987         break;
1988     case VGA_RETRACE_PRECISE:
1989         memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1990         break;
1991     }
1992     vga_update_memory_access(s);
1993 }
1994
1995 static void vga_reset(void *opaque)
1996 {
1997     VGACommonState *s =  opaque;
1998     vga_common_reset(s);
1999 }
2000
2001 #define TEXTMODE_X(x)   ((x) % width)
2002 #define TEXTMODE_Y(x)   ((x) / width)
2003 #define VMEM2CHTYPE(v)  ((v & 0xff0007ff) | \
2004         ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
2005 /* relay text rendering to the display driver
2006  * instead of doing a full vga_update_display() */
2007 static void vga_update_text(void *opaque, console_ch_t *chardata)
2008 {
2009     VGACommonState *s =  opaque;
2010     int graphic_mode, i, cursor_offset, cursor_visible;
2011     int cw, cheight, width, height, size, c_min, c_max;
2012     uint32_t *src;
2013     console_ch_t *dst, val;
2014     char msg_buffer[80];
2015     int full_update = 0;
2016
2017     qemu_flush_coalesced_mmio_buffer();
2018
2019     if (!(s->ar_index & 0x20)) {
2020         graphic_mode = GMODE_BLANK;
2021     } else {
2022         graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
2023     }
2024     if (graphic_mode != s->graphic_mode) {
2025         s->graphic_mode = graphic_mode;
2026         full_update = 1;
2027     }
2028     if (s->last_width == -1) {
2029         s->last_width = 0;
2030         full_update = 1;
2031     }
2032
2033     switch (graphic_mode) {
2034     case GMODE_TEXT:
2035         /* TODO: update palette */
2036         full_update |= update_basic_params(s);
2037
2038         /* total width & height */
2039         cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
2040         cw = 8;
2041         if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
2042             cw = 9;
2043         }
2044         if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
2045             cw = 16; /* NOTE: no 18 pixel wide */
2046         }
2047         width = (s->cr[VGA_CRTC_H_DISP] + 1);
2048         if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
2049             /* ugly hack for CGA 160x100x16 - explain me the logic */
2050             height = 100;
2051         } else {
2052             height = s->cr[VGA_CRTC_V_DISP_END] |
2053                 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
2054                 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
2055             height = (height + 1) / cheight;
2056         }
2057
2058         size = (height * width);
2059         if (size > CH_ATTR_SIZE) {
2060             if (!full_update)
2061                 return;
2062
2063             snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2064                      width, height);
2065             break;
2066         }
2067
2068         if (width != s->last_width || height != s->last_height ||
2069             cw != s->last_cw || cheight != s->last_ch) {
2070             s->last_scr_width = width * cw;
2071             s->last_scr_height = height * cheight;
2072             qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
2073             dpy_text_resize(s->con, width, height);
2074             s->last_depth = 0;
2075             s->last_width = width;
2076             s->last_height = height;
2077             s->last_ch = cheight;
2078             s->last_cw = cw;
2079             full_update = 1;
2080         }
2081
2082         if (full_update) {
2083             s->full_update_gfx = 1;
2084         }
2085         if (s->full_update_text) {
2086             s->full_update_text = 0;
2087             full_update |= 1;
2088         }
2089
2090         /* Update "hardware" cursor */
2091         cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
2092                          s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
2093         if (cursor_offset != s->cursor_offset ||
2094             s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
2095             s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
2096             cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
2097             if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
2098                 dpy_text_cursor(s->con,
2099                                 TEXTMODE_X(cursor_offset),
2100                                 TEXTMODE_Y(cursor_offset));
2101             else
2102                 dpy_text_cursor(s->con, -1, -1);
2103             s->cursor_offset = cursor_offset;
2104             s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
2105             s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
2106         }
2107
2108         src = (uint32_t *) s->vram_ptr + s->start_addr;
2109         dst = chardata;
2110
2111         if (full_update) {
2112             for (i = 0; i < size; src ++, dst ++, i ++)
2113                 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
2114
2115             dpy_text_update(s->con, 0, 0, width, height);
2116         } else {
2117             c_max = 0;
2118
2119             for (i = 0; i < size; src ++, dst ++, i ++) {
2120                 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
2121                 if (*dst != val) {
2122                     *dst = val;
2123                     c_max = i;
2124                     break;
2125                 }
2126             }
2127             c_min = i;
2128             for (; i < size; src ++, dst ++, i ++) {
2129                 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
2130                 if (*dst != val) {
2131                     *dst = val;
2132                     c_max = i;
2133                 }
2134             }
2135
2136             if (c_min <= c_max) {
2137                 i = TEXTMODE_Y(c_min);
2138                 dpy_text_update(s->con, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2139             }
2140         }
2141
2142         return;
2143     case GMODE_GRAPH:
2144         if (!full_update)
2145             return;
2146
2147         s->get_resolution(s, &width, &height);
2148         snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2149                  width, height);
2150         break;
2151     case GMODE_BLANK:
2152     default:
2153         if (!full_update)
2154             return;
2155
2156         snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2157         break;
2158     }
2159
2160     /* Display a message */
2161     s->last_width = 60;
2162     s->last_height = height = 3;
2163     dpy_text_cursor(s->con, -1, -1);
2164     dpy_text_resize(s->con, s->last_width, height);
2165
2166     for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2167         console_write_ch(dst ++, ' ');
2168
2169     size = strlen(msg_buffer);
2170     width = (s->last_width - size) / 2;
2171     dst = chardata + s->last_width + width;
2172     for (i = 0; i < size; i ++)
2173         console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2174
2175     dpy_text_update(s->con, 0, 0, s->last_width, height);
2176 }
2177
2178 static uint64_t vga_mem_read(void *opaque, hwaddr addr,
2179                              unsigned size)
2180 {
2181     VGACommonState *s = opaque;
2182
2183     return vga_mem_readb(s, addr);
2184 }
2185
2186 static void vga_mem_write(void *opaque, hwaddr addr,
2187                           uint64_t data, unsigned size)
2188 {
2189     VGACommonState *s = opaque;
2190
2191     return vga_mem_writeb(s, addr, data);
2192 }
2193
2194 const MemoryRegionOps vga_mem_ops = {
2195     .read = vga_mem_read,
2196     .write = vga_mem_write,
2197     .endianness = DEVICE_LITTLE_ENDIAN,
2198     .impl = {
2199         .min_access_size = 1,
2200         .max_access_size = 1,
2201     },
2202 };
2203
2204 static int vga_common_post_load(void *opaque, int version_id)
2205 {
2206     VGACommonState *s = opaque;
2207
2208     /* force refresh */
2209     s->graphic_mode = -1;
2210     return 0;
2211 }
2212
2213 const VMStateDescription vmstate_vga_common = {
2214     .name = "vga",
2215     .version_id = 2,
2216     .minimum_version_id = 2,
2217     .minimum_version_id_old = 2,
2218     .post_load = vga_common_post_load,
2219     .fields      = (VMStateField []) {
2220         VMSTATE_UINT32(latch, VGACommonState),
2221         VMSTATE_UINT8(sr_index, VGACommonState),
2222         VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2223         VMSTATE_UINT8(gr_index, VGACommonState),
2224         VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2225         VMSTATE_UINT8(ar_index, VGACommonState),
2226         VMSTATE_BUFFER(ar, VGACommonState),
2227         VMSTATE_INT32(ar_flip_flop, VGACommonState),
2228         VMSTATE_UINT8(cr_index, VGACommonState),
2229         VMSTATE_BUFFER(cr, VGACommonState),
2230         VMSTATE_UINT8(msr, VGACommonState),
2231         VMSTATE_UINT8(fcr, VGACommonState),
2232         VMSTATE_UINT8(st00, VGACommonState),
2233         VMSTATE_UINT8(st01, VGACommonState),
2234
2235         VMSTATE_UINT8(dac_state, VGACommonState),
2236         VMSTATE_UINT8(dac_sub_index, VGACommonState),
2237         VMSTATE_UINT8(dac_read_index, VGACommonState),
2238         VMSTATE_UINT8(dac_write_index, VGACommonState),
2239         VMSTATE_BUFFER(dac_cache, VGACommonState),
2240         VMSTATE_BUFFER(palette, VGACommonState),
2241
2242         VMSTATE_INT32(bank_offset, VGACommonState),
2243         VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
2244         VMSTATE_UINT16(vbe_index, VGACommonState),
2245         VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2246         VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2247         VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2248         VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
2249         VMSTATE_END_OF_LIST()
2250     }
2251 };
2252
2253 void vga_common_init(VGACommonState *s)
2254 {
2255     int i, j, v, b;
2256
2257     for(i = 0;i < 256; i++) {
2258         v = 0;
2259         for(j = 0; j < 8; j++) {
2260             v |= ((i >> j) & 1) << (j * 4);
2261         }
2262         expand4[i] = v;
2263
2264         v = 0;
2265         for(j = 0; j < 4; j++) {
2266             v |= ((i >> (2 * j)) & 3) << (j * 4);
2267         }
2268         expand2[i] = v;
2269     }
2270     for(i = 0; i < 16; i++) {
2271         v = 0;
2272         for(j = 0; j < 4; j++) {
2273             b = ((i >> j) & 1);
2274             v |= b << (2 * j);
2275             v |= b << (2 * j + 1);
2276         }
2277         expand4to8[i] = v;
2278     }
2279
2280     /* valid range: 1 MB -> 256 MB */
2281     s->vram_size = 1024 * 1024;
2282     while (s->vram_size < (s->vram_size_mb << 20) &&
2283            s->vram_size < (256 << 20)) {
2284         s->vram_size <<= 1;
2285     }
2286     s->vram_size_mb = s->vram_size >> 20;
2287
2288     s->is_vbe_vmstate = 1;
2289     memory_region_init_ram(&s->vram, "vga.vram", s->vram_size);
2290     vmstate_register_ram_global(&s->vram);
2291     xen_register_framebuffer(&s->vram);
2292     s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
2293     s->get_bpp = vga_get_bpp;
2294     s->get_offsets = vga_get_offsets;
2295     s->get_resolution = vga_get_resolution;
2296     s->update = vga_update_display;
2297     s->invalidate = vga_invalidate_display;
2298     s->text_update = vga_update_text;
2299     switch (vga_retrace_method) {
2300     case VGA_RETRACE_DUMB:
2301         s->retrace = vga_dumb_retrace;
2302         s->update_retrace_info = vga_dumb_update_retrace_info;
2303         break;
2304
2305     case VGA_RETRACE_PRECISE:
2306         s->retrace = vga_precise_retrace;
2307         s->update_retrace_info = vga_precise_update_retrace_info;
2308         break;
2309     }
2310     vga_dirty_log_start(s);
2311 }
2312
2313 static const MemoryRegionPortio vga_portio_list[] = {
2314     { 0x04,  2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2315     { 0x0a,  1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2316     { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2317     { 0x24,  2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2318     { 0x2a,  1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2319     PORTIO_END_OF_LIST(),
2320 };
2321
2322 static const MemoryRegionPortio vbe_portio_list[] = {
2323     { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2324 # ifdef TARGET_I386
2325     { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2326 # endif
2327     { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2328     PORTIO_END_OF_LIST(),
2329 };
2330
2331 /* Used by both ISA and PCI */
2332 MemoryRegion *vga_init_io(VGACommonState *s,
2333                           const MemoryRegionPortio **vga_ports,
2334                           const MemoryRegionPortio **vbe_ports)
2335 {
2336     MemoryRegion *vga_mem;
2337
2338     *vga_ports = vga_portio_list;
2339     *vbe_ports = vbe_portio_list;
2340
2341     vga_mem = g_malloc(sizeof(*vga_mem));
2342     memory_region_init_io(vga_mem, &vga_mem_ops, s,
2343                           "vga-lowmem", 0x20000);
2344     memory_region_set_flush_coalesced(vga_mem);
2345
2346     return vga_mem;
2347 }
2348
2349 void vga_init(VGACommonState *s, MemoryRegion *address_space,
2350               MemoryRegion *address_space_io, bool init_vga_ports)
2351 {
2352     MemoryRegion *vga_io_memory;
2353     const MemoryRegionPortio *vga_ports, *vbe_ports;
2354     PortioList *vga_port_list = g_new(PortioList, 1);
2355     PortioList *vbe_port_list = g_new(PortioList, 1);
2356
2357     qemu_register_reset(vga_reset, s);
2358
2359     s->bank_offset = 0;
2360
2361     s->legacy_address_space = address_space;
2362
2363     vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports);
2364     memory_region_add_subregion_overlap(address_space,
2365                                         isa_mem_base + 0x000a0000,
2366                                         vga_io_memory,
2367                                         1);
2368     memory_region_set_coalescing(vga_io_memory);
2369     if (init_vga_ports) {
2370         portio_list_init(vga_port_list, vga_ports, s, "vga");
2371         portio_list_add(vga_port_list, address_space_io, 0x3b0);
2372     }
2373     if (vbe_ports) {
2374         portio_list_init(vbe_port_list, vbe_ports, s, "vbe");
2375         portio_list_add(vbe_port_list, address_space_io, 0x1ce);
2376     }
2377 }
2378
2379 void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
2380 {
2381     /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2382      * so use an alias to avoid double-mapping the same region.
2383      */
2384     memory_region_init_alias(&s->vram_vbe, "vram.vbe",
2385                              &s->vram, 0, memory_region_size(&s->vram));
2386     /* XXX: use optimized standard vga accesses */
2387     memory_region_add_subregion(system_memory,
2388                                 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2389                                 &s->vram_vbe);
2390     s->vbe_mapped = 1;
2391 }