hw/dma/puv3_dma.c

   1 /*
   2  * DMA device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11 #include "hw/hw.h"
  12 #include "hw/sysbus.h"
  13
  14 #undef DEBUG_PUV3
  15 #include "hw/unicore32/puv3.h"
  16
  17 #define PUV3_DMA_CH_NR          (6)
  18 #define PUV3_DMA_CH_MASK        (0xff)
  19 #define PUV3_DMA_CH(offset)     ((offset) >> 8)
  20
  21 typedef struct {
  22     SysBusDevice busdev;
  23     MemoryRegion iomem;
  24     uint32_t reg_CFG[PUV3_DMA_CH_NR];
  25 } PUV3DMAState;
  26
  27 static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
  28         unsigned size)
  29 {
  30     PUV3DMAState *s = opaque;
  31     uint32_t ret = 0;
  32
  33     assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
  34
  35     switch (offset & PUV3_DMA_CH_MASK) {
  36     case 0x10:
  37         ret = s->reg_CFG[PUV3_DMA_CH(offset)];
  38         break;
  39     default:
  40         DPRINTF("Bad offset 0x%x\n", offset);
  41     }
  42     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  43
  44     return ret;
  45 }
  46
  47 static void puv3_dma_write(void *opaque, hwaddr offset,
  48         uint64_t value, unsigned size)
  49 {
  50     PUV3DMAState *s = opaque;
  51
  52     assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
  53
  54     switch (offset & PUV3_DMA_CH_MASK) {
  55     case 0x10:
  56         s->reg_CFG[PUV3_DMA_CH(offset)] = value;
  57         break;
  58     default:
  59         DPRINTF("Bad offset 0x%x\n", offset);
  60     }
  61     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  62 }
  63
  64 static const MemoryRegionOps puv3_dma_ops = {
  65     .read = puv3_dma_read,
  66     .write = puv3_dma_write,
  67     .impl = {
  68         .min_access_size = 4,
  69         .max_access_size = 4,
  70     },
  71     .endianness = DEVICE_NATIVE_ENDIAN,
  72 };
  73
  74 static int puv3_dma_init(SysBusDevice *dev)
  75 {
  76     PUV3DMAState *s = FROM_SYSBUS(PUV3DMAState, dev);
  77     int i;
  78
  79     for (i = 0; i < PUV3_DMA_CH_NR; i++) {
  80         s->reg_CFG[i] = 0x0;
  81     }
  82
  83     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma",
  84             PUV3_REGS_OFFSET);
  85     sysbus_init_mmio(dev, &s->iomem);
  86
  87     return 0;
  88 }
  89
  90 static void puv3_dma_class_init(ObjectClass *klass, void *data)
  91 {
  92     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
  93
  94     sdc->init = puv3_dma_init;
  95 }
  96
  97 static const TypeInfo puv3_dma_info = {
  98     .name = "puv3_dma",
  99     .parent = TYPE_SYS_BUS_DEVICE,
 100     .instance_size = sizeof(PUV3DMAState),
 101     .class_init = puv3_dma_class_init,
 102 };
 103
 104 static void puv3_dma_register_type(void)
 105 {
 106     type_register_static(&puv3_dma_info);
 107 }
 108
 109 type_init(puv3_dma_register_type)