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e1000: move reset function earlier in file
[qemu.git] / hw / e1000.c
1 /*
2 * QEMU e1000 emulation
3 *
4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 */
26
27
28 #include "hw.h"
29 #include "pci.h"
30 #include "net.h"
31 #include "net/checksum.h"
32 #include "loader.h"
33 #include "sysemu.h"
34 #include "dma.h"
35
36 #include "e1000_hw.h"
37
38 #define E1000_DEBUG
39
40 #ifdef E1000_DEBUG
41 enum {
42 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
43 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
44 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
45 DEBUG_RXFILTER, DEBUG_NOTYET,
46 };
47 #define DBGBIT(x) (1<<DEBUG_##x)
48 static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
49
50 #define DBGOUT(what, fmt, ...) do { \
51 if (debugflags & DBGBIT(what)) \
52 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
53 } while (0)
54 #else
55 #define DBGOUT(what, fmt, ...) do {} while (0)
56 #endif
57
58 #define IOPORT_SIZE 0x40
59 #define PNPMMIO_SIZE 0x20000
60 #define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
61
62 /*
63 * HW models:
64 * E1000_DEV_ID_82540EM works with Windows and Linux
65 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
66 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
67 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
68 * Others never tested
69 */
70 enum { E1000_DEVID = E1000_DEV_ID_82540EM };
71
72 /*
73 * May need to specify additional MAC-to-PHY entries --
74 * Intel's Windows driver refuses to initialize unless they match
75 */
76 enum {
77 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
78 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
79 /* default to E1000_DEV_ID_82540EM */ 0xc20
80 };
81
82 typedef struct E1000State_st {
83 PCIDevice dev;
84 NICState *nic;
85 NICConf conf;
86 MemoryRegion mmio;
87 MemoryRegion io;
88
89 uint32_t mac_reg[0x8000];
90 uint16_t phy_reg[0x20];
91 uint16_t eeprom_data[64];
92
93 uint32_t rxbuf_size;
94 uint32_t rxbuf_min_shift;
95 int check_rxov;
96 struct e1000_tx {
97 unsigned char header[256];
98 unsigned char vlan_header[4];
99 /* Fields vlan and data must not be reordered or separated. */
100 unsigned char vlan[4];
101 unsigned char data[0x10000];
102 uint16_t size;
103 unsigned char sum_needed;
104 unsigned char vlan_needed;
105 uint8_t ipcss;
106 uint8_t ipcso;
107 uint16_t ipcse;
108 uint8_t tucss;
109 uint8_t tucso;
110 uint16_t tucse;
111 uint8_t hdr_len;
112 uint16_t mss;
113 uint32_t paylen;
114 uint16_t tso_frames;
115 char tse;
116 int8_t ip;
117 int8_t tcp;
118 char cptse; // current packet tse bit
119 } tx;
120
121 struct {
122 uint32_t val_in; // shifted in from guest driver
123 uint16_t bitnum_in;
124 uint16_t bitnum_out;
125 uint16_t reading;
126 uint32_t old_eecd;
127 } eecd_state;
128 } E1000State;
129
130 #define defreg(x) x = (E1000_##x>>2)
131 enum {
132 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
133 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
134 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
135 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
136 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
137 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
138 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
139 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
140 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
141 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
142 defreg(VET),
143 };
144
145 enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
146 static const char phy_regcap[0x20] = {
147 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
148 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
149 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
150 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
151 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
152 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
153 };
154
155 static const uint16_t phy_reg_init[] = {
156 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
157 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
158 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
159 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
160 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
161 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
162 };
163
164 static const uint32_t mac_reg_init[] = {
165 [PBA] = 0x00100030,
166 [LEDCTL] = 0x602,
167 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
168 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
169 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
170 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
171 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
172 E1000_STATUS_LU,
173 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
174 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
175 E1000_MANC_RMCP_EN,
176 };
177
178 static void
179 set_interrupt_cause(E1000State *s, int index, uint32_t val)
180 {
181 if (val)
182 val |= E1000_ICR_INT_ASSERTED;
183 s->mac_reg[ICR] = val;
184 s->mac_reg[ICS] = val;
185 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
186 }
187
188 static void
189 set_ics(E1000State *s, int index, uint32_t val)
190 {
191 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
192 s->mac_reg[IMS]);
193 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
194 }
195
196 static int
197 rxbufsize(uint32_t v)
198 {
199 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
200 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
201 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
202 switch (v) {
203 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
204 return 16384;
205 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
206 return 8192;
207 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
208 return 4096;
209 case E1000_RCTL_SZ_1024:
210 return 1024;
211 case E1000_RCTL_SZ_512:
212 return 512;
213 case E1000_RCTL_SZ_256:
214 return 256;
215 }
216 return 2048;
217 }
218
219 static void e1000_reset(void *opaque)
220 {
221 E1000State *d = opaque;
222
223 memset(d->phy_reg, 0, sizeof d->phy_reg);
224 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
225 memset(d->mac_reg, 0, sizeof d->mac_reg);
226 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
227 d->rxbuf_min_shift = 1;
228 memset(&d->tx, 0, sizeof d->tx);
229
230 if (d->nic->nc.link_down) {
231 d->mac_reg[STATUS] &= ~E1000_STATUS_LU;
232 d->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
233 }
234 }
235
236 static void
237 set_ctrl(E1000State *s, int index, uint32_t val)
238 {
239 /* RST is self clearing */
240 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
241 }
242
243 static void
244 set_rx_control(E1000State *s, int index, uint32_t val)
245 {
246 s->mac_reg[RCTL] = val;
247 s->rxbuf_size = rxbufsize(val);
248 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
249 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
250 s->mac_reg[RCTL]);
251 }
252
253 static void
254 set_mdic(E1000State *s, int index, uint32_t val)
255 {
256 uint32_t data = val & E1000_MDIC_DATA_MASK;
257 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
258
259 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
260 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
261 else if (val & E1000_MDIC_OP_READ) {
262 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
263 if (!(phy_regcap[addr] & PHY_R)) {
264 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
265 val |= E1000_MDIC_ERROR;
266 } else
267 val = (val ^ data) | s->phy_reg[addr];
268 } else if (val & E1000_MDIC_OP_WRITE) {
269 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
270 if (!(phy_regcap[addr] & PHY_W)) {
271 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
272 val |= E1000_MDIC_ERROR;
273 } else
274 s->phy_reg[addr] = data;
275 }
276 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
277 set_ics(s, 0, E1000_ICR_MDAC);
278 }
279
280 static uint32_t
281 get_eecd(E1000State *s, int index)
282 {
283 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
284
285 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
286 s->eecd_state.bitnum_out, s->eecd_state.reading);
287 if (!s->eecd_state.reading ||
288 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
289 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
290 ret |= E1000_EECD_DO;
291 return ret;
292 }
293
294 static void
295 set_eecd(E1000State *s, int index, uint32_t val)
296 {
297 uint32_t oldval = s->eecd_state.old_eecd;
298
299 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
300 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
301 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
302 return;
303 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
304 s->eecd_state.val_in = 0;
305 s->eecd_state.bitnum_in = 0;
306 s->eecd_state.bitnum_out = 0;
307 s->eecd_state.reading = 0;
308 }
309 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
310 return;
311 if (!(E1000_EECD_SK & val)) { // falling edge
312 s->eecd_state.bitnum_out++;
313 return;
314 }
315 s->eecd_state.val_in <<= 1;
316 if (val & E1000_EECD_DI)
317 s->eecd_state.val_in |= 1;
318 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
319 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
320 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
321 EEPROM_READ_OPCODE_MICROWIRE);
322 }
323 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
324 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
325 s->eecd_state.reading);
326 }
327
328 static uint32_t
329 flash_eerd_read(E1000State *s, int x)
330 {
331 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
332
333 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
334 return (s->mac_reg[EERD]);
335
336 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
337 return (E1000_EEPROM_RW_REG_DONE | r);
338
339 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
340 E1000_EEPROM_RW_REG_DONE | r);
341 }
342
343 static void
344 putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
345 {
346 uint32_t sum;
347
348 if (cse && cse < n)
349 n = cse + 1;
350 if (sloc < n-1) {
351 sum = net_checksum_add(n-css, data+css);
352 cpu_to_be16wu((uint16_t *)(data + sloc),
353 net_checksum_finish(sum));
354 }
355 }
356
357 static inline int
358 vlan_enabled(E1000State *s)
359 {
360 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
361 }
362
363 static inline int
364 vlan_rx_filter_enabled(E1000State *s)
365 {
366 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
367 }
368
369 static inline int
370 is_vlan_packet(E1000State *s, const uint8_t *buf)
371 {
372 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
373 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
374 }
375
376 static inline int
377 is_vlan_txd(uint32_t txd_lower)
378 {
379 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
380 }
381
382 /* FCS aka Ethernet CRC-32. We don't get it from backends and can't
383 * fill it in, just pad descriptor length by 4 bytes unless guest
384 * told us to strip it off the packet. */
385 static inline int
386 fcs_len(E1000State *s)
387 {
388 return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
389 }
390
391 static void
392 xmit_seg(E1000State *s)
393 {
394 uint16_t len, *sp;
395 unsigned int frames = s->tx.tso_frames, css, sofar, n;
396 struct e1000_tx *tp = &s->tx;
397
398 if (tp->tse && tp->cptse) {
399 css = tp->ipcss;
400 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
401 frames, tp->size, css);
402 if (tp->ip) { // IPv4
403 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
404 tp->size - css);
405 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
406 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
407 } else // IPv6
408 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
409 tp->size - css);
410 css = tp->tucss;
411 len = tp->size - css;
412 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
413 if (tp->tcp) {
414 sofar = frames * tp->mss;
415 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
416 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
417 if (tp->paylen - sofar > tp->mss)
418 tp->data[css + 13] &= ~9; // PSH, FIN
419 } else // UDP
420 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
421 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
422 unsigned int phsum;
423 // add pseudo-header length before checksum calculation
424 sp = (uint16_t *)(tp->data + tp->tucso);
425 phsum = be16_to_cpup(sp) + len;
426 phsum = (phsum >> 16) + (phsum & 0xffff);
427 cpu_to_be16wu(sp, phsum);
428 }
429 tp->tso_frames++;
430 }
431
432 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
433 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
434 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
435 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
436 if (tp->vlan_needed) {
437 memmove(tp->vlan, tp->data, 4);
438 memmove(tp->data, tp->data + 4, 8);
439 memcpy(tp->data + 8, tp->vlan_header, 4);
440 qemu_send_packet(&s->nic->nc, tp->vlan, tp->size + 4);
441 } else
442 qemu_send_packet(&s->nic->nc, tp->data, tp->size);
443 s->mac_reg[TPT]++;
444 s->mac_reg[GPTC]++;
445 n = s->mac_reg[TOTL];
446 if ((s->mac_reg[TOTL] += s->tx.size) < n)
447 s->mac_reg[TOTH]++;
448 }
449
450 static void
451 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
452 {
453 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
454 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
455 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
456 unsigned int msh = 0xfffff, hdr = 0;
457 uint64_t addr;
458 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
459 struct e1000_tx *tp = &s->tx;
460
461 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
462 op = le32_to_cpu(xp->cmd_and_length);
463 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
464 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
465 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
466 tp->tucss = xp->upper_setup.tcp_fields.tucss;
467 tp->tucso = xp->upper_setup.tcp_fields.tucso;
468 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
469 tp->paylen = op & 0xfffff;
470 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
471 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
472 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
473 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
474 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
475 tp->tso_frames = 0;
476 if (tp->tucso == 0) { // this is probably wrong
477 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
478 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
479 }
480 return;
481 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
482 // data descriptor
483 if (tp->size == 0) {
484 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
485 }
486 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
487 } else {
488 // legacy descriptor
489 tp->cptse = 0;
490 }
491
492 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
493 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
494 tp->vlan_needed = 1;
495 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
496 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
497 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
498 le16_to_cpu(dp->upper.fields.special));
499 }
500
501 addr = le64_to_cpu(dp->buffer_addr);
502 if (tp->tse && tp->cptse) {
503 hdr = tp->hdr_len;
504 msh = hdr + tp->mss;
505 do {
506 bytes = split_size;
507 if (tp->size + bytes > msh)
508 bytes = msh - tp->size;
509
510 bytes = MIN(sizeof(tp->data) - tp->size, bytes);
511 pci_dma_read(&s->dev, addr, tp->data + tp->size, bytes);
512 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
513 memmove(tp->header, tp->data, hdr);
514 tp->size = sz;
515 addr += bytes;
516 if (sz == msh) {
517 xmit_seg(s);
518 memmove(tp->data, tp->header, hdr);
519 tp->size = hdr;
520 }
521 } while (split_size -= bytes);
522 } else if (!tp->tse && tp->cptse) {
523 // context descriptor TSE is not set, while data descriptor TSE is set
524 DBGOUT(TXERR, "TCP segmentation error\n");
525 } else {
526 split_size = MIN(sizeof(tp->data) - tp->size, split_size);
527 pci_dma_read(&s->dev, addr, tp->data + tp->size, split_size);
528 tp->size += split_size;
529 }
530
531 if (!(txd_lower & E1000_TXD_CMD_EOP))
532 return;
533 if (!(tp->tse && tp->cptse && tp->size < hdr))
534 xmit_seg(s);
535 tp->tso_frames = 0;
536 tp->sum_needed = 0;
537 tp->vlan_needed = 0;
538 tp->size = 0;
539 tp->cptse = 0;
540 }
541
542 static uint32_t
543 txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
544 {
545 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
546
547 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
548 return 0;
549 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
550 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
551 dp->upper.data = cpu_to_le32(txd_upper);
552 pci_dma_write(&s->dev, base + ((char *)&dp->upper - (char *)dp),
553 &dp->upper, sizeof(dp->upper));
554 return E1000_ICR_TXDW;
555 }
556
557 static uint64_t tx_desc_base(E1000State *s)
558 {
559 uint64_t bah = s->mac_reg[TDBAH];
560 uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
561
562 return (bah << 32) + bal;
563 }
564
565 static void
566 start_xmit(E1000State *s)
567 {
568 dma_addr_t base;
569 struct e1000_tx_desc desc;
570 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
571
572 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
573 DBGOUT(TX, "tx disabled\n");
574 return;
575 }
576
577 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
578 base = tx_desc_base(s) +
579 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
580 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
581
582 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
583 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
584 desc.upper.data);
585
586 process_tx_desc(s, &desc);
587 cause |= txdesc_writeback(s, base, &desc);
588
589 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
590 s->mac_reg[TDH] = 0;
591 /*
592 * the following could happen only if guest sw assigns
593 * bogus values to TDT/TDLEN.
594 * there's nothing too intelligent we could do about this.
595 */
596 if (s->mac_reg[TDH] == tdh_start) {
597 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
598 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
599 break;
600 }
601 }
602 set_ics(s, 0, cause);
603 }
604
605 static int
606 receive_filter(E1000State *s, const uint8_t *buf, int size)
607 {
608 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
609 static const int mta_shift[] = {4, 3, 2, 0};
610 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
611
612 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
613 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
614 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
615 ((vid >> 5) & 0x7f));
616 if ((vfta & (1 << (vid & 0x1f))) == 0)
617 return 0;
618 }
619
620 if (rctl & E1000_RCTL_UPE) // promiscuous
621 return 1;
622
623 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
624 return 1;
625
626 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
627 return 1;
628
629 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
630 if (!(rp[1] & E1000_RAH_AV))
631 continue;
632 ra[0] = cpu_to_le32(rp[0]);
633 ra[1] = cpu_to_le32(rp[1]);
634 if (!memcmp(buf, (uint8_t *)ra, 6)) {
635 DBGOUT(RXFILTER,
636 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
637 (int)(rp - s->mac_reg - RA)/2,
638 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
639 return 1;
640 }
641 }
642 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
643 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
644
645 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
646 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
647 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
648 return 1;
649 DBGOUT(RXFILTER,
650 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
651 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
652 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
653 s->mac_reg[MTA + (f >> 5)]);
654
655 return 0;
656 }
657
658 static void
659 e1000_set_link_status(VLANClientState *nc)
660 {
661 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
662 uint32_t old_status = s->mac_reg[STATUS];
663
664 if (nc->link_down) {
665 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
666 s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
667 } else {
668 s->mac_reg[STATUS] |= E1000_STATUS_LU;
669 s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS;
670 }
671
672 if (s->mac_reg[STATUS] != old_status)
673 set_ics(s, 0, E1000_ICR_LSC);
674 }
675
676 static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
677 {
678 int bufs;
679 /* Fast-path short packets */
680 if (total_size <= s->rxbuf_size) {
681 return s->mac_reg[RDH] != s->mac_reg[RDT] || !s->check_rxov;
682 }
683 if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
684 bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
685 } else if (s->mac_reg[RDH] > s->mac_reg[RDT] || !s->check_rxov) {
686 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
687 s->mac_reg[RDT] - s->mac_reg[RDH];
688 } else {
689 return false;
690 }
691 return total_size <= bufs * s->rxbuf_size;
692 }
693
694 static int
695 e1000_can_receive(VLANClientState *nc)
696 {
697 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
698
699 return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1);
700 }
701
702 static uint64_t rx_desc_base(E1000State *s)
703 {
704 uint64_t bah = s->mac_reg[RDBAH];
705 uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
706
707 return (bah << 32) + bal;
708 }
709
710 static ssize_t
711 e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
712 {
713 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
714 struct e1000_rx_desc desc;
715 dma_addr_t base;
716 unsigned int n, rdt;
717 uint32_t rdh_start;
718 uint16_t vlan_special = 0;
719 uint8_t vlan_status = 0, vlan_offset = 0;
720 uint8_t min_buf[MIN_BUF_SIZE];
721 size_t desc_offset;
722 size_t desc_size;
723 size_t total_size;
724
725 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
726 return -1;
727
728 /* Pad to minimum Ethernet frame length */
729 if (size < sizeof(min_buf)) {
730 memcpy(min_buf, buf, size);
731 memset(&min_buf[size], 0, sizeof(min_buf) - size);
732 buf = min_buf;
733 size = sizeof(min_buf);
734 }
735
736 if (!receive_filter(s, buf, size))
737 return size;
738
739 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
740 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
741 memmove((uint8_t *)buf + 4, buf, 12);
742 vlan_status = E1000_RXD_STAT_VP;
743 vlan_offset = 4;
744 size -= 4;
745 }
746
747 rdh_start = s->mac_reg[RDH];
748 desc_offset = 0;
749 total_size = size + fcs_len(s);
750 if (!e1000_has_rxbufs(s, total_size)) {
751 set_ics(s, 0, E1000_ICS_RXO);
752 return -1;
753 }
754 do {
755 desc_size = total_size - desc_offset;
756 if (desc_size > s->rxbuf_size) {
757 desc_size = s->rxbuf_size;
758 }
759 base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
760 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
761 desc.special = vlan_special;
762 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
763 if (desc.buffer_addr) {
764 if (desc_offset < size) {
765 size_t copy_size = size - desc_offset;
766 if (copy_size > s->rxbuf_size) {
767 copy_size = s->rxbuf_size;
768 }
769 pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr),
770 buf + desc_offset + vlan_offset, copy_size);
771 }
772 desc_offset += desc_size;
773 desc.length = cpu_to_le16(desc_size);
774 if (desc_offset >= total_size) {
775 desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
776 } else {
777 /* Guest zeroing out status is not a hardware requirement.
778 Clear EOP in case guest didn't do it. */
779 desc.status &= ~E1000_RXD_STAT_EOP;
780 }
781 } else { // as per intel docs; skip descriptors with null buf addr
782 DBGOUT(RX, "Null RX descriptor!!\n");
783 }
784 pci_dma_write(&s->dev, base, &desc, sizeof(desc));
785
786 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
787 s->mac_reg[RDH] = 0;
788 s->check_rxov = 1;
789 /* see comment in start_xmit; same here */
790 if (s->mac_reg[RDH] == rdh_start) {
791 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
792 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
793 set_ics(s, 0, E1000_ICS_RXO);
794 return -1;
795 }
796 } while (desc_offset < total_size);
797
798 s->mac_reg[GPRC]++;
799 s->mac_reg[TPR]++;
800 /* TOR - Total Octets Received:
801 * This register includes bytes received in a packet from the <Destination
802 * Address> field through the <CRC> field, inclusively.
803 */
804 n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
805 if (n < s->mac_reg[TORL])
806 s->mac_reg[TORH]++;
807 s->mac_reg[TORL] = n;
808
809 n = E1000_ICS_RXT0;
810 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
811 rdt += s->mac_reg[RDLEN] / sizeof(desc);
812 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
813 s->rxbuf_min_shift)
814 n |= E1000_ICS_RXDMT0;
815
816 set_ics(s, 0, n);
817
818 return size;
819 }
820
821 static uint32_t
822 mac_readreg(E1000State *s, int index)
823 {
824 return s->mac_reg[index];
825 }
826
827 static uint32_t
828 mac_icr_read(E1000State *s, int index)
829 {
830 uint32_t ret = s->mac_reg[ICR];
831
832 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
833 set_interrupt_cause(s, 0, 0);
834 return ret;
835 }
836
837 static uint32_t
838 mac_read_clr4(E1000State *s, int index)
839 {
840 uint32_t ret = s->mac_reg[index];
841
842 s->mac_reg[index] = 0;
843 return ret;
844 }
845
846 static uint32_t
847 mac_read_clr8(E1000State *s, int index)
848 {
849 uint32_t ret = s->mac_reg[index];
850
851 s->mac_reg[index] = 0;
852 s->mac_reg[index-1] = 0;
853 return ret;
854 }
855
856 static void
857 mac_writereg(E1000State *s, int index, uint32_t val)
858 {
859 s->mac_reg[index] = val;
860 }
861
862 static void
863 set_rdt(E1000State *s, int index, uint32_t val)
864 {
865 s->check_rxov = 0;
866 s->mac_reg[index] = val & 0xffff;
867 }
868
869 static void
870 set_16bit(E1000State *s, int index, uint32_t val)
871 {
872 s->mac_reg[index] = val & 0xffff;
873 }
874
875 static void
876 set_dlen(E1000State *s, int index, uint32_t val)
877 {
878 s->mac_reg[index] = val & 0xfff80;
879 }
880
881 static void
882 set_tctl(E1000State *s, int index, uint32_t val)
883 {
884 s->mac_reg[index] = val;
885 s->mac_reg[TDT] &= 0xffff;
886 start_xmit(s);
887 }
888
889 static void
890 set_icr(E1000State *s, int index, uint32_t val)
891 {
892 DBGOUT(INTERRUPT, "set_icr %x\n", val);
893 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
894 }
895
896 static void
897 set_imc(E1000State *s, int index, uint32_t val)
898 {
899 s->mac_reg[IMS] &= ~val;
900 set_ics(s, 0, 0);
901 }
902
903 static void
904 set_ims(E1000State *s, int index, uint32_t val)
905 {
906 s->mac_reg[IMS] |= val;
907 set_ics(s, 0, 0);
908 }
909
910 #define getreg(x) [x] = mac_readreg
911 static uint32_t (*macreg_readops[])(E1000State *, int) = {
912 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
913 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
914 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
915 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
916 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
917 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
918 getreg(TDLEN), getreg(RDLEN),
919
920 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
921 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
922 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
923 [CRCERRS ... MPC] = &mac_readreg,
924 [RA ... RA+31] = &mac_readreg,
925 [MTA ... MTA+127] = &mac_readreg,
926 [VFTA ... VFTA+127] = &mac_readreg,
927 };
928 enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
929
930 #define putreg(x) [x] = mac_writereg
931 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
932 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
933 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
934 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
935 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
936 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
937 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
938 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
939 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
940 [RA ... RA+31] = &mac_writereg,
941 [MTA ... MTA+127] = &mac_writereg,
942 [VFTA ... VFTA+127] = &mac_writereg,
943 };
944 enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
945
946 static void
947 e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
948 unsigned size)
949 {
950 E1000State *s = opaque;
951 unsigned int index = (addr & 0x1ffff) >> 2;
952
953 if (index < NWRITEOPS && macreg_writeops[index]) {
954 macreg_writeops[index](s, index, val);
955 } else if (index < NREADOPS && macreg_readops[index]) {
956 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val);
957 } else {
958 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
959 index<<2, val);
960 }
961 }
962
963 static uint64_t
964 e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
965 {
966 E1000State *s = opaque;
967 unsigned int index = (addr & 0x1ffff) >> 2;
968
969 if (index < NREADOPS && macreg_readops[index])
970 {
971 return macreg_readops[index](s, index);
972 }
973 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
974 return 0;
975 }
976
977 static const MemoryRegionOps e1000_mmio_ops = {
978 .read = e1000_mmio_read,
979 .write = e1000_mmio_write,
980 .endianness = DEVICE_LITTLE_ENDIAN,
981 .impl = {
982 .min_access_size = 4,
983 .max_access_size = 4,
984 },
985 };
986
987 static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
988 unsigned size)
989 {
990 E1000State *s = opaque;
991
992 (void)s;
993 return 0;
994 }
995
996 static void e1000_io_write(void *opaque, target_phys_addr_t addr,
997 uint64_t val, unsigned size)
998 {
999 E1000State *s = opaque;
1000
1001 (void)s;
1002 }
1003
1004 static const MemoryRegionOps e1000_io_ops = {
1005 .read = e1000_io_read,
1006 .write = e1000_io_write,
1007 .endianness = DEVICE_LITTLE_ENDIAN,
1008 };
1009
1010 static bool is_version_1(void *opaque, int version_id)
1011 {
1012 return version_id == 1;
1013 }
1014
1015 static const VMStateDescription vmstate_e1000 = {
1016 .name = "e1000",
1017 .version_id = 2,
1018 .minimum_version_id = 1,
1019 .minimum_version_id_old = 1,
1020 .fields = (VMStateField []) {
1021 VMSTATE_PCI_DEVICE(dev, E1000State),
1022 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
1023 VMSTATE_UNUSED(4), /* Was mmio_base. */
1024 VMSTATE_UINT32(rxbuf_size, E1000State),
1025 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
1026 VMSTATE_UINT32(eecd_state.val_in, E1000State),
1027 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
1028 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
1029 VMSTATE_UINT16(eecd_state.reading, E1000State),
1030 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
1031 VMSTATE_UINT8(tx.ipcss, E1000State),
1032 VMSTATE_UINT8(tx.ipcso, E1000State),
1033 VMSTATE_UINT16(tx.ipcse, E1000State),
1034 VMSTATE_UINT8(tx.tucss, E1000State),
1035 VMSTATE_UINT8(tx.tucso, E1000State),
1036 VMSTATE_UINT16(tx.tucse, E1000State),
1037 VMSTATE_UINT32(tx.paylen, E1000State),
1038 VMSTATE_UINT8(tx.hdr_len, E1000State),
1039 VMSTATE_UINT16(tx.mss, E1000State),
1040 VMSTATE_UINT16(tx.size, E1000State),
1041 VMSTATE_UINT16(tx.tso_frames, E1000State),
1042 VMSTATE_UINT8(tx.sum_needed, E1000State),
1043 VMSTATE_INT8(tx.ip, E1000State),
1044 VMSTATE_INT8(tx.tcp, E1000State),
1045 VMSTATE_BUFFER(tx.header, E1000State),
1046 VMSTATE_BUFFER(tx.data, E1000State),
1047 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
1048 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
1049 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
1050 VMSTATE_UINT32(mac_reg[EECD], E1000State),
1051 VMSTATE_UINT32(mac_reg[EERD], E1000State),
1052 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
1053 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
1054 VMSTATE_UINT32(mac_reg[ICR], E1000State),
1055 VMSTATE_UINT32(mac_reg[ICS], E1000State),
1056 VMSTATE_UINT32(mac_reg[IMC], E1000State),
1057 VMSTATE_UINT32(mac_reg[IMS], E1000State),
1058 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
1059 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1060 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1061 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1062 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1063 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1064 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1065 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1066 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1067 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1068 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1069 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1070 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1071 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1072 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1073 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1074 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1075 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1076 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1077 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1078 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1079 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1080 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1081 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1082 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1083 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1084 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1085 VMSTATE_UINT32(mac_reg[VET], E1000State),
1086 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1087 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
1088 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
1089 VMSTATE_END_OF_LIST()
1090 }
1091 };
1092
1093 static const uint16_t e1000_eeprom_template[64] = {
1094 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1095 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
1096 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1097 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1098 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1099 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1100 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1101 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1102 };
1103
1104 /* PCI interface */
1105
1106 static void
1107 e1000_mmio_setup(E1000State *d)
1108 {
1109 int i;
1110 const uint32_t excluded_regs[] = {
1111 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1112 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1113 };
1114
1115 memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
1116 PNPMMIO_SIZE);
1117 memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);
1118 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1119 memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
1120 excluded_regs[i+1] - excluded_regs[i] - 4);
1121 memory_region_init_io(&d->io, &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
1122 }
1123
1124 static void
1125 e1000_cleanup(VLANClientState *nc)
1126 {
1127 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1128
1129 s->nic = NULL;
1130 }
1131
1132 static int
1133 pci_e1000_uninit(PCIDevice *dev)
1134 {
1135 E1000State *d = DO_UPCAST(E1000State, dev, dev);
1136
1137 memory_region_destroy(&d->mmio);
1138 memory_region_destroy(&d->io);
1139 qemu_del_vlan_client(&d->nic->nc);
1140 return 0;
1141 }
1142
1143 static NetClientInfo net_e1000_info = {
1144 .type = NET_CLIENT_TYPE_NIC,
1145 .size = sizeof(NICState),
1146 .can_receive = e1000_can_receive,
1147 .receive = e1000_receive,
1148 .cleanup = e1000_cleanup,
1149 .link_status_changed = e1000_set_link_status,
1150 };
1151
1152 static int pci_e1000_init(PCIDevice *pci_dev)
1153 {
1154 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
1155 uint8_t *pci_conf;
1156 uint16_t checksum = 0;
1157 int i;
1158 uint8_t *macaddr;
1159
1160 pci_conf = d->dev.config;
1161
1162 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1163 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
1164
1165 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
1166
1167 e1000_mmio_setup(d);
1168
1169 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
1170
1171 pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
1172
1173 memmove(d->eeprom_data, e1000_eeprom_template,
1174 sizeof e1000_eeprom_template);
1175 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1176 macaddr = d->conf.macaddr.a;
1177 for (i = 0; i < 3; i++)
1178 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
1179 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1180 checksum += d->eeprom_data[i];
1181 checksum = (uint16_t) EEPROM_SUM - checksum;
1182 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1183
1184 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
1185 object_get_typename(OBJECT(d)), d->dev.qdev.id, d);
1186
1187 qemu_format_nic_info_str(&d->nic->nc, macaddr);
1188
1189 add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1190
1191 return 0;
1192 }
1193
1194 static void qdev_e1000_reset(DeviceState *dev)
1195 {
1196 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1197 e1000_reset(d);
1198 }
1199
1200 static Property e1000_properties[] = {
1201 DEFINE_NIC_PROPERTIES(E1000State, conf),
1202 DEFINE_PROP_END_OF_LIST(),
1203 };
1204
1205 static void e1000_class_init(ObjectClass *klass, void *data)
1206 {
1207 DeviceClass *dc = DEVICE_CLASS(klass);
1208 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1209
1210 k->init = pci_e1000_init;
1211 k->exit = pci_e1000_uninit;
1212 k->romfile = "pxe-e1000.rom";
1213 k->vendor_id = PCI_VENDOR_ID_INTEL;
1214 k->device_id = E1000_DEVID;
1215 k->revision = 0x03;
1216 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
1217 dc->desc = "Intel Gigabit Ethernet";
1218 dc->reset = qdev_e1000_reset;
1219 dc->vmsd = &vmstate_e1000;
1220 dc->props = e1000_properties;
1221 }
1222
1223 static TypeInfo e1000_info = {
1224 .name = "e1000",
1225 .parent = TYPE_PCI_DEVICE,
1226 .instance_size = sizeof(E1000State),
1227 .class_init = e1000_class_init,
1228 };
1229
1230 static void e1000_register_types(void)
1231 {
1232 type_register_static(&e1000_info);
1233 }
1234
1235 type_init(e1000_register_types)
Qemu copy for testing