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e1000: link auto-negotiation emulation
[qemu.git] / hw / e1000.c
1 /*
2 * QEMU e1000 emulation
3 *
4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 */
26
27
28 #include "hw.h"
29 #include "pci.h"
30 #include "net.h"
31 #include "net/checksum.h"
32 #include "loader.h"
33 #include "sysemu.h"
34 #include "dma.h"
35
36 #include "e1000_hw.h"
37
38 #define E1000_DEBUG
39
40 #ifdef E1000_DEBUG
41 enum {
42 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
43 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
44 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
45 DEBUG_RXFILTER, DEBUG_PHY, DEBUG_NOTYET,
46 };
47 #define DBGBIT(x) (1<<DEBUG_##x)
48 static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
49
50 #define DBGOUT(what, fmt, ...) do { \
51 if (debugflags & DBGBIT(what)) \
52 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
53 } while (0)
54 #else
55 #define DBGOUT(what, fmt, ...) do {} while (0)
56 #endif
57
58 #define IOPORT_SIZE 0x40
59 #define PNPMMIO_SIZE 0x20000
60 #define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
61
62 /*
63 * HW models:
64 * E1000_DEV_ID_82540EM works with Windows and Linux
65 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
66 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
67 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
68 * Others never tested
69 */
70 enum { E1000_DEVID = E1000_DEV_ID_82540EM };
71
72 /*
73 * May need to specify additional MAC-to-PHY entries --
74 * Intel's Windows driver refuses to initialize unless they match
75 */
76 enum {
77 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
78 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
79 /* default to E1000_DEV_ID_82540EM */ 0xc20
80 };
81
82 typedef struct E1000State_st {
83 PCIDevice dev;
84 NICState *nic;
85 NICConf conf;
86 MemoryRegion mmio;
87 MemoryRegion io;
88
89 uint32_t mac_reg[0x8000];
90 uint16_t phy_reg[0x20];
91 uint16_t eeprom_data[64];
92
93 uint32_t rxbuf_size;
94 uint32_t rxbuf_min_shift;
95 int check_rxov;
96 struct e1000_tx {
97 unsigned char header[256];
98 unsigned char vlan_header[4];
99 /* Fields vlan and data must not be reordered or separated. */
100 unsigned char vlan[4];
101 unsigned char data[0x10000];
102 uint16_t size;
103 unsigned char sum_needed;
104 unsigned char vlan_needed;
105 uint8_t ipcss;
106 uint8_t ipcso;
107 uint16_t ipcse;
108 uint8_t tucss;
109 uint8_t tucso;
110 uint16_t tucse;
111 uint8_t hdr_len;
112 uint16_t mss;
113 uint32_t paylen;
114 uint16_t tso_frames;
115 char tse;
116 int8_t ip;
117 int8_t tcp;
118 char cptse; // current packet tse bit
119 } tx;
120
121 struct {
122 uint32_t val_in; // shifted in from guest driver
123 uint16_t bitnum_in;
124 uint16_t bitnum_out;
125 uint16_t reading;
126 uint32_t old_eecd;
127 } eecd_state;
128
129 QEMUTimer *autoneg_timer;
130 } E1000State;
131
132 #define defreg(x) x = (E1000_##x>>2)
133 enum {
134 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
135 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
136 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
137 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
138 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
139 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
140 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
141 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
142 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
143 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
144 defreg(VET),
145 };
146
147 static void
148 e1000_link_down(E1000State *s)
149 {
150 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
151 s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
152 }
153
154 static void
155 e1000_link_up(E1000State *s)
156 {
157 s->mac_reg[STATUS] |= E1000_STATUS_LU;
158 s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS;
159 }
160
161 static void
162 set_phy_ctrl(E1000State *s, int index, uint16_t val)
163 {
164 if ((val & MII_CR_AUTO_NEG_EN) && (val & MII_CR_RESTART_AUTO_NEG)) {
165 s->nic->nc.link_down = true;
166 e1000_link_down(s);
167 s->phy_reg[PHY_STATUS] &= ~MII_SR_AUTONEG_COMPLETE;
168 DBGOUT(PHY, "Start link auto negotiation\n");
169 qemu_mod_timer(s->autoneg_timer, qemu_get_clock_ms(vm_clock) + 500);
170 }
171 }
172
173 static void
174 e1000_autoneg_timer(void *opaque)
175 {
176 E1000State *s = opaque;
177 s->nic->nc.link_down = false;
178 e1000_link_up(s);
179 s->phy_reg[PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
180 DBGOUT(PHY, "Auto negotiation is completed\n");
181 }
182
183 static void (*phyreg_writeops[])(E1000State *, int, uint16_t) = {
184 [PHY_CTRL] = set_phy_ctrl,
185 };
186
187 enum { NPHYWRITEOPS = ARRAY_SIZE(phyreg_writeops) };
188
189 enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
190 static const char phy_regcap[0x20] = {
191 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
192 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
193 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
194 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
195 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
196 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
197 };
198
199 static const uint16_t phy_reg_init[] = {
200 [PHY_CTRL] = 0x1140,
201 [PHY_STATUS] = 0x794d, /* link initially up with not completed autoneg */
202 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
203 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
204 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
205 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
206 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
207 };
208
209 static const uint32_t mac_reg_init[] = {
210 [PBA] = 0x00100030,
211 [LEDCTL] = 0x602,
212 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
213 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
214 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
215 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
216 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
217 E1000_STATUS_LU,
218 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
219 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
220 E1000_MANC_RMCP_EN,
221 };
222
223 static void
224 set_interrupt_cause(E1000State *s, int index, uint32_t val)
225 {
226 if (val)
227 val |= E1000_ICR_INT_ASSERTED;
228 s->mac_reg[ICR] = val;
229 s->mac_reg[ICS] = val;
230 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
231 }
232
233 static void
234 set_ics(E1000State *s, int index, uint32_t val)
235 {
236 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
237 s->mac_reg[IMS]);
238 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
239 }
240
241 static int
242 rxbufsize(uint32_t v)
243 {
244 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
245 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
246 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
247 switch (v) {
248 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
249 return 16384;
250 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
251 return 8192;
252 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
253 return 4096;
254 case E1000_RCTL_SZ_1024:
255 return 1024;
256 case E1000_RCTL_SZ_512:
257 return 512;
258 case E1000_RCTL_SZ_256:
259 return 256;
260 }
261 return 2048;
262 }
263
264 static void e1000_reset(void *opaque)
265 {
266 E1000State *d = opaque;
267
268 qemu_del_timer(d->autoneg_timer);
269 memset(d->phy_reg, 0, sizeof d->phy_reg);
270 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
271 memset(d->mac_reg, 0, sizeof d->mac_reg);
272 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
273 d->rxbuf_min_shift = 1;
274 memset(&d->tx, 0, sizeof d->tx);
275
276 if (d->nic->nc.link_down) {
277 e1000_link_down(d);
278 }
279 }
280
281 static void
282 set_ctrl(E1000State *s, int index, uint32_t val)
283 {
284 /* RST is self clearing */
285 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
286 }
287
288 static void
289 set_rx_control(E1000State *s, int index, uint32_t val)
290 {
291 s->mac_reg[RCTL] = val;
292 s->rxbuf_size = rxbufsize(val);
293 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
294 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
295 s->mac_reg[RCTL]);
296 }
297
298 static void
299 set_mdic(E1000State *s, int index, uint32_t val)
300 {
301 uint32_t data = val & E1000_MDIC_DATA_MASK;
302 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
303
304 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
305 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
306 else if (val & E1000_MDIC_OP_READ) {
307 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
308 if (!(phy_regcap[addr] & PHY_R)) {
309 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
310 val |= E1000_MDIC_ERROR;
311 } else
312 val = (val ^ data) | s->phy_reg[addr];
313 } else if (val & E1000_MDIC_OP_WRITE) {
314 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
315 if (!(phy_regcap[addr] & PHY_W)) {
316 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
317 val |= E1000_MDIC_ERROR;
318 } else {
319 if (addr < NPHYWRITEOPS && phyreg_writeops[addr]) {
320 phyreg_writeops[addr](s, index, data);
321 }
322 s->phy_reg[addr] = data;
323 }
324 }
325 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
326
327 if (val & E1000_MDIC_INT_EN) {
328 set_ics(s, 0, E1000_ICR_MDAC);
329 }
330 }
331
332 static uint32_t
333 get_eecd(E1000State *s, int index)
334 {
335 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
336
337 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
338 s->eecd_state.bitnum_out, s->eecd_state.reading);
339 if (!s->eecd_state.reading ||
340 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
341 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
342 ret |= E1000_EECD_DO;
343 return ret;
344 }
345
346 static void
347 set_eecd(E1000State *s, int index, uint32_t val)
348 {
349 uint32_t oldval = s->eecd_state.old_eecd;
350
351 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
352 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
353 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
354 return;
355 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
356 s->eecd_state.val_in = 0;
357 s->eecd_state.bitnum_in = 0;
358 s->eecd_state.bitnum_out = 0;
359 s->eecd_state.reading = 0;
360 }
361 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
362 return;
363 if (!(E1000_EECD_SK & val)) { // falling edge
364 s->eecd_state.bitnum_out++;
365 return;
366 }
367 s->eecd_state.val_in <<= 1;
368 if (val & E1000_EECD_DI)
369 s->eecd_state.val_in |= 1;
370 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
371 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
372 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
373 EEPROM_READ_OPCODE_MICROWIRE);
374 }
375 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
376 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
377 s->eecd_state.reading);
378 }
379
380 static uint32_t
381 flash_eerd_read(E1000State *s, int x)
382 {
383 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
384
385 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
386 return (s->mac_reg[EERD]);
387
388 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
389 return (E1000_EEPROM_RW_REG_DONE | r);
390
391 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
392 E1000_EEPROM_RW_REG_DONE | r);
393 }
394
395 static void
396 putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
397 {
398 uint32_t sum;
399
400 if (cse && cse < n)
401 n = cse + 1;
402 if (sloc < n-1) {
403 sum = net_checksum_add(n-css, data+css);
404 cpu_to_be16wu((uint16_t *)(data + sloc),
405 net_checksum_finish(sum));
406 }
407 }
408
409 static inline int
410 vlan_enabled(E1000State *s)
411 {
412 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
413 }
414
415 static inline int
416 vlan_rx_filter_enabled(E1000State *s)
417 {
418 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
419 }
420
421 static inline int
422 is_vlan_packet(E1000State *s, const uint8_t *buf)
423 {
424 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
425 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
426 }
427
428 static inline int
429 is_vlan_txd(uint32_t txd_lower)
430 {
431 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
432 }
433
434 /* FCS aka Ethernet CRC-32. We don't get it from backends and can't
435 * fill it in, just pad descriptor length by 4 bytes unless guest
436 * told us to strip it off the packet. */
437 static inline int
438 fcs_len(E1000State *s)
439 {
440 return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
441 }
442
443 static void
444 e1000_send_packet(E1000State *s, const uint8_t *buf, int size)
445 {
446 if (s->phy_reg[PHY_CTRL] & MII_CR_LOOPBACK) {
447 s->nic->nc.info->receive(&s->nic->nc, buf, size);
448 } else {
449 qemu_send_packet(&s->nic->nc, buf, size);
450 }
451 }
452
453 static void
454 xmit_seg(E1000State *s)
455 {
456 uint16_t len, *sp;
457 unsigned int frames = s->tx.tso_frames, css, sofar, n;
458 struct e1000_tx *tp = &s->tx;
459
460 if (tp->tse && tp->cptse) {
461 css = tp->ipcss;
462 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
463 frames, tp->size, css);
464 if (tp->ip) { // IPv4
465 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
466 tp->size - css);
467 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
468 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
469 } else // IPv6
470 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
471 tp->size - css);
472 css = tp->tucss;
473 len = tp->size - css;
474 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
475 if (tp->tcp) {
476 sofar = frames * tp->mss;
477 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
478 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
479 if (tp->paylen - sofar > tp->mss)
480 tp->data[css + 13] &= ~9; // PSH, FIN
481 } else // UDP
482 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
483 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
484 unsigned int phsum;
485 // add pseudo-header length before checksum calculation
486 sp = (uint16_t *)(tp->data + tp->tucso);
487 phsum = be16_to_cpup(sp) + len;
488 phsum = (phsum >> 16) + (phsum & 0xffff);
489 cpu_to_be16wu(sp, phsum);
490 }
491 tp->tso_frames++;
492 }
493
494 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
495 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
496 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
497 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
498 if (tp->vlan_needed) {
499 memmove(tp->vlan, tp->data, 4);
500 memmove(tp->data, tp->data + 4, 8);
501 memcpy(tp->data + 8, tp->vlan_header, 4);
502 e1000_send_packet(s, tp->vlan, tp->size + 4);
503 } else
504 e1000_send_packet(s, tp->data, tp->size);
505 s->mac_reg[TPT]++;
506 s->mac_reg[GPTC]++;
507 n = s->mac_reg[TOTL];
508 if ((s->mac_reg[TOTL] += s->tx.size) < n)
509 s->mac_reg[TOTH]++;
510 }
511
512 static void
513 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
514 {
515 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
516 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
517 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
518 unsigned int msh = 0xfffff, hdr = 0;
519 uint64_t addr;
520 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
521 struct e1000_tx *tp = &s->tx;
522
523 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
524 op = le32_to_cpu(xp->cmd_and_length);
525 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
526 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
527 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
528 tp->tucss = xp->upper_setup.tcp_fields.tucss;
529 tp->tucso = xp->upper_setup.tcp_fields.tucso;
530 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
531 tp->paylen = op & 0xfffff;
532 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
533 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
534 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
535 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
536 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
537 tp->tso_frames = 0;
538 if (tp->tucso == 0) { // this is probably wrong
539 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
540 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
541 }
542 return;
543 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
544 // data descriptor
545 if (tp->size == 0) {
546 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
547 }
548 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
549 } else {
550 // legacy descriptor
551 tp->cptse = 0;
552 }
553
554 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
555 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
556 tp->vlan_needed = 1;
557 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
558 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
559 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
560 le16_to_cpu(dp->upper.fields.special));
561 }
562
563 addr = le64_to_cpu(dp->buffer_addr);
564 if (tp->tse && tp->cptse) {
565 hdr = tp->hdr_len;
566 msh = hdr + tp->mss;
567 do {
568 bytes = split_size;
569 if (tp->size + bytes > msh)
570 bytes = msh - tp->size;
571
572 bytes = MIN(sizeof(tp->data) - tp->size, bytes);
573 pci_dma_read(&s->dev, addr, tp->data + tp->size, bytes);
574 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
575 memmove(tp->header, tp->data, hdr);
576 tp->size = sz;
577 addr += bytes;
578 if (sz == msh) {
579 xmit_seg(s);
580 memmove(tp->data, tp->header, hdr);
581 tp->size = hdr;
582 }
583 } while (split_size -= bytes);
584 } else if (!tp->tse && tp->cptse) {
585 // context descriptor TSE is not set, while data descriptor TSE is set
586 DBGOUT(TXERR, "TCP segmentation error\n");
587 } else {
588 split_size = MIN(sizeof(tp->data) - tp->size, split_size);
589 pci_dma_read(&s->dev, addr, tp->data + tp->size, split_size);
590 tp->size += split_size;
591 }
592
593 if (!(txd_lower & E1000_TXD_CMD_EOP))
594 return;
595 if (!(tp->tse && tp->cptse && tp->size < hdr))
596 xmit_seg(s);
597 tp->tso_frames = 0;
598 tp->sum_needed = 0;
599 tp->vlan_needed = 0;
600 tp->size = 0;
601 tp->cptse = 0;
602 }
603
604 static uint32_t
605 txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
606 {
607 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
608
609 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
610 return 0;
611 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
612 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
613 dp->upper.data = cpu_to_le32(txd_upper);
614 pci_dma_write(&s->dev, base + ((char *)&dp->upper - (char *)dp),
615 &dp->upper, sizeof(dp->upper));
616 return E1000_ICR_TXDW;
617 }
618
619 static uint64_t tx_desc_base(E1000State *s)
620 {
621 uint64_t bah = s->mac_reg[TDBAH];
622 uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
623
624 return (bah << 32) + bal;
625 }
626
627 static void
628 start_xmit(E1000State *s)
629 {
630 dma_addr_t base;
631 struct e1000_tx_desc desc;
632 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
633
634 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
635 DBGOUT(TX, "tx disabled\n");
636 return;
637 }
638
639 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
640 base = tx_desc_base(s) +
641 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
642 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
643
644 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
645 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
646 desc.upper.data);
647
648 process_tx_desc(s, &desc);
649 cause |= txdesc_writeback(s, base, &desc);
650
651 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
652 s->mac_reg[TDH] = 0;
653 /*
654 * the following could happen only if guest sw assigns
655 * bogus values to TDT/TDLEN.
656 * there's nothing too intelligent we could do about this.
657 */
658 if (s->mac_reg[TDH] == tdh_start) {
659 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
660 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
661 break;
662 }
663 }
664 set_ics(s, 0, cause);
665 }
666
667 static int
668 receive_filter(E1000State *s, const uint8_t *buf, int size)
669 {
670 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
671 static const int mta_shift[] = {4, 3, 2, 0};
672 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
673
674 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
675 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
676 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
677 ((vid >> 5) & 0x7f));
678 if ((vfta & (1 << (vid & 0x1f))) == 0)
679 return 0;
680 }
681
682 if (rctl & E1000_RCTL_UPE) // promiscuous
683 return 1;
684
685 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
686 return 1;
687
688 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
689 return 1;
690
691 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
692 if (!(rp[1] & E1000_RAH_AV))
693 continue;
694 ra[0] = cpu_to_le32(rp[0]);
695 ra[1] = cpu_to_le32(rp[1]);
696 if (!memcmp(buf, (uint8_t *)ra, 6)) {
697 DBGOUT(RXFILTER,
698 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
699 (int)(rp - s->mac_reg - RA)/2,
700 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
701 return 1;
702 }
703 }
704 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
705 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
706
707 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
708 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
709 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
710 return 1;
711 DBGOUT(RXFILTER,
712 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
713 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
714 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
715 s->mac_reg[MTA + (f >> 5)]);
716
717 return 0;
718 }
719
720 static void
721 e1000_set_link_status(VLANClientState *nc)
722 {
723 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
724 uint32_t old_status = s->mac_reg[STATUS];
725
726 if (nc->link_down) {
727 e1000_link_down(s);
728 } else {
729 e1000_link_up(s);
730 }
731
732 if (s->mac_reg[STATUS] != old_status)
733 set_ics(s, 0, E1000_ICR_LSC);
734 }
735
736 static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
737 {
738 int bufs;
739 /* Fast-path short packets */
740 if (total_size <= s->rxbuf_size) {
741 return s->mac_reg[RDH] != s->mac_reg[RDT] || !s->check_rxov;
742 }
743 if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
744 bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
745 } else if (s->mac_reg[RDH] > s->mac_reg[RDT] || !s->check_rxov) {
746 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
747 s->mac_reg[RDT] - s->mac_reg[RDH];
748 } else {
749 return false;
750 }
751 return total_size <= bufs * s->rxbuf_size;
752 }
753
754 static int
755 e1000_can_receive(VLANClientState *nc)
756 {
757 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
758
759 return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1);
760 }
761
762 static uint64_t rx_desc_base(E1000State *s)
763 {
764 uint64_t bah = s->mac_reg[RDBAH];
765 uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
766
767 return (bah << 32) + bal;
768 }
769
770 static ssize_t
771 e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
772 {
773 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
774 struct e1000_rx_desc desc;
775 dma_addr_t base;
776 unsigned int n, rdt;
777 uint32_t rdh_start;
778 uint16_t vlan_special = 0;
779 uint8_t vlan_status = 0, vlan_offset = 0;
780 uint8_t min_buf[MIN_BUF_SIZE];
781 size_t desc_offset;
782 size_t desc_size;
783 size_t total_size;
784
785 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
786 return -1;
787
788 /* Pad to minimum Ethernet frame length */
789 if (size < sizeof(min_buf)) {
790 memcpy(min_buf, buf, size);
791 memset(&min_buf[size], 0, sizeof(min_buf) - size);
792 buf = min_buf;
793 size = sizeof(min_buf);
794 }
795
796 if (!receive_filter(s, buf, size))
797 return size;
798
799 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
800 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
801 memmove((uint8_t *)buf + 4, buf, 12);
802 vlan_status = E1000_RXD_STAT_VP;
803 vlan_offset = 4;
804 size -= 4;
805 }
806
807 rdh_start = s->mac_reg[RDH];
808 desc_offset = 0;
809 total_size = size + fcs_len(s);
810 if (!e1000_has_rxbufs(s, total_size)) {
811 set_ics(s, 0, E1000_ICS_RXO);
812 return -1;
813 }
814 do {
815 desc_size = total_size - desc_offset;
816 if (desc_size > s->rxbuf_size) {
817 desc_size = s->rxbuf_size;
818 }
819 base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
820 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
821 desc.special = vlan_special;
822 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
823 if (desc.buffer_addr) {
824 if (desc_offset < size) {
825 size_t copy_size = size - desc_offset;
826 if (copy_size > s->rxbuf_size) {
827 copy_size = s->rxbuf_size;
828 }
829 pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr),
830 buf + desc_offset + vlan_offset, copy_size);
831 }
832 desc_offset += desc_size;
833 desc.length = cpu_to_le16(desc_size);
834 if (desc_offset >= total_size) {
835 desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
836 } else {
837 /* Guest zeroing out status is not a hardware requirement.
838 Clear EOP in case guest didn't do it. */
839 desc.status &= ~E1000_RXD_STAT_EOP;
840 }
841 } else { // as per intel docs; skip descriptors with null buf addr
842 DBGOUT(RX, "Null RX descriptor!!\n");
843 }
844 pci_dma_write(&s->dev, base, &desc, sizeof(desc));
845
846 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
847 s->mac_reg[RDH] = 0;
848 s->check_rxov = 1;
849 /* see comment in start_xmit; same here */
850 if (s->mac_reg[RDH] == rdh_start) {
851 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
852 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
853 set_ics(s, 0, E1000_ICS_RXO);
854 return -1;
855 }
856 } while (desc_offset < total_size);
857
858 s->mac_reg[GPRC]++;
859 s->mac_reg[TPR]++;
860 /* TOR - Total Octets Received:
861 * This register includes bytes received in a packet from the <Destination
862 * Address> field through the <CRC> field, inclusively.
863 */
864 n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
865 if (n < s->mac_reg[TORL])
866 s->mac_reg[TORH]++;
867 s->mac_reg[TORL] = n;
868
869 n = E1000_ICS_RXT0;
870 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
871 rdt += s->mac_reg[RDLEN] / sizeof(desc);
872 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
873 s->rxbuf_min_shift)
874 n |= E1000_ICS_RXDMT0;
875
876 set_ics(s, 0, n);
877
878 return size;
879 }
880
881 static uint32_t
882 mac_readreg(E1000State *s, int index)
883 {
884 return s->mac_reg[index];
885 }
886
887 static uint32_t
888 mac_icr_read(E1000State *s, int index)
889 {
890 uint32_t ret = s->mac_reg[ICR];
891
892 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
893 set_interrupt_cause(s, 0, 0);
894 return ret;
895 }
896
897 static uint32_t
898 mac_read_clr4(E1000State *s, int index)
899 {
900 uint32_t ret = s->mac_reg[index];
901
902 s->mac_reg[index] = 0;
903 return ret;
904 }
905
906 static uint32_t
907 mac_read_clr8(E1000State *s, int index)
908 {
909 uint32_t ret = s->mac_reg[index];
910
911 s->mac_reg[index] = 0;
912 s->mac_reg[index-1] = 0;
913 return ret;
914 }
915
916 static void
917 mac_writereg(E1000State *s, int index, uint32_t val)
918 {
919 s->mac_reg[index] = val;
920 }
921
922 static void
923 set_rdt(E1000State *s, int index, uint32_t val)
924 {
925 s->check_rxov = 0;
926 s->mac_reg[index] = val & 0xffff;
927 }
928
929 static void
930 set_16bit(E1000State *s, int index, uint32_t val)
931 {
932 s->mac_reg[index] = val & 0xffff;
933 }
934
935 static void
936 set_dlen(E1000State *s, int index, uint32_t val)
937 {
938 s->mac_reg[index] = val & 0xfff80;
939 }
940
941 static void
942 set_tctl(E1000State *s, int index, uint32_t val)
943 {
944 s->mac_reg[index] = val;
945 s->mac_reg[TDT] &= 0xffff;
946 start_xmit(s);
947 }
948
949 static void
950 set_icr(E1000State *s, int index, uint32_t val)
951 {
952 DBGOUT(INTERRUPT, "set_icr %x\n", val);
953 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
954 }
955
956 static void
957 set_imc(E1000State *s, int index, uint32_t val)
958 {
959 s->mac_reg[IMS] &= ~val;
960 set_ics(s, 0, 0);
961 }
962
963 static void
964 set_ims(E1000State *s, int index, uint32_t val)
965 {
966 s->mac_reg[IMS] |= val;
967 set_ics(s, 0, 0);
968 }
969
970 #define getreg(x) [x] = mac_readreg
971 static uint32_t (*macreg_readops[])(E1000State *, int) = {
972 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
973 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
974 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
975 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
976 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
977 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
978 getreg(TDLEN), getreg(RDLEN),
979
980 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
981 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
982 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
983 [CRCERRS ... MPC] = &mac_readreg,
984 [RA ... RA+31] = &mac_readreg,
985 [MTA ... MTA+127] = &mac_readreg,
986 [VFTA ... VFTA+127] = &mac_readreg,
987 };
988 enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
989
990 #define putreg(x) [x] = mac_writereg
991 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
992 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
993 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
994 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
995 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
996 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
997 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
998 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
999 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
1000 [RA ... RA+31] = &mac_writereg,
1001 [MTA ... MTA+127] = &mac_writereg,
1002 [VFTA ... VFTA+127] = &mac_writereg,
1003 };
1004
1005 enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
1006
1007 static void
1008 e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
1009 unsigned size)
1010 {
1011 E1000State *s = opaque;
1012 unsigned int index = (addr & 0x1ffff) >> 2;
1013
1014 if (index < NWRITEOPS && macreg_writeops[index]) {
1015 macreg_writeops[index](s, index, val);
1016 } else if (index < NREADOPS && macreg_readops[index]) {
1017 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val);
1018 } else {
1019 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
1020 index<<2, val);
1021 }
1022 }
1023
1024 static uint64_t
1025 e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
1026 {
1027 E1000State *s = opaque;
1028 unsigned int index = (addr & 0x1ffff) >> 2;
1029
1030 if (index < NREADOPS && macreg_readops[index])
1031 {
1032 return macreg_readops[index](s, index);
1033 }
1034 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
1035 return 0;
1036 }
1037
1038 static const MemoryRegionOps e1000_mmio_ops = {
1039 .read = e1000_mmio_read,
1040 .write = e1000_mmio_write,
1041 .endianness = DEVICE_LITTLE_ENDIAN,
1042 .impl = {
1043 .min_access_size = 4,
1044 .max_access_size = 4,
1045 },
1046 };
1047
1048 static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
1049 unsigned size)
1050 {
1051 E1000State *s = opaque;
1052
1053 (void)s;
1054 return 0;
1055 }
1056
1057 static void e1000_io_write(void *opaque, target_phys_addr_t addr,
1058 uint64_t val, unsigned size)
1059 {
1060 E1000State *s = opaque;
1061
1062 (void)s;
1063 }
1064
1065 static const MemoryRegionOps e1000_io_ops = {
1066 .read = e1000_io_read,
1067 .write = e1000_io_write,
1068 .endianness = DEVICE_LITTLE_ENDIAN,
1069 };
1070
1071 static bool is_version_1(void *opaque, int version_id)
1072 {
1073 return version_id == 1;
1074 }
1075
1076 static const VMStateDescription vmstate_e1000 = {
1077 .name = "e1000",
1078 .version_id = 2,
1079 .minimum_version_id = 1,
1080 .minimum_version_id_old = 1,
1081 .fields = (VMStateField []) {
1082 VMSTATE_PCI_DEVICE(dev, E1000State),
1083 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
1084 VMSTATE_UNUSED(4), /* Was mmio_base. */
1085 VMSTATE_UINT32(rxbuf_size, E1000State),
1086 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
1087 VMSTATE_UINT32(eecd_state.val_in, E1000State),
1088 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
1089 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
1090 VMSTATE_UINT16(eecd_state.reading, E1000State),
1091 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
1092 VMSTATE_UINT8(tx.ipcss, E1000State),
1093 VMSTATE_UINT8(tx.ipcso, E1000State),
1094 VMSTATE_UINT16(tx.ipcse, E1000State),
1095 VMSTATE_UINT8(tx.tucss, E1000State),
1096 VMSTATE_UINT8(tx.tucso, E1000State),
1097 VMSTATE_UINT16(tx.tucse, E1000State),
1098 VMSTATE_UINT32(tx.paylen, E1000State),
1099 VMSTATE_UINT8(tx.hdr_len, E1000State),
1100 VMSTATE_UINT16(tx.mss, E1000State),
1101 VMSTATE_UINT16(tx.size, E1000State),
1102 VMSTATE_UINT16(tx.tso_frames, E1000State),
1103 VMSTATE_UINT8(tx.sum_needed, E1000State),
1104 VMSTATE_INT8(tx.ip, E1000State),
1105 VMSTATE_INT8(tx.tcp, E1000State),
1106 VMSTATE_BUFFER(tx.header, E1000State),
1107 VMSTATE_BUFFER(tx.data, E1000State),
1108 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
1109 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
1110 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
1111 VMSTATE_UINT32(mac_reg[EECD], E1000State),
1112 VMSTATE_UINT32(mac_reg[EERD], E1000State),
1113 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
1114 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
1115 VMSTATE_UINT32(mac_reg[ICR], E1000State),
1116 VMSTATE_UINT32(mac_reg[ICS], E1000State),
1117 VMSTATE_UINT32(mac_reg[IMC], E1000State),
1118 VMSTATE_UINT32(mac_reg[IMS], E1000State),
1119 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
1120 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1121 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1122 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1123 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1124 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1125 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1126 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1127 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1128 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1129 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1130 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1131 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1132 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1133 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1134 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1135 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1136 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1137 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1138 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1139 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1140 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1141 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1142 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1143 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1144 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1145 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1146 VMSTATE_UINT32(mac_reg[VET], E1000State),
1147 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1148 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
1149 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
1150 VMSTATE_END_OF_LIST()
1151 }
1152 };
1153
1154 static const uint16_t e1000_eeprom_template[64] = {
1155 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1156 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
1157 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1158 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1159 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1160 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1161 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1162 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1163 };
1164
1165 /* PCI interface */
1166
1167 static void
1168 e1000_mmio_setup(E1000State *d)
1169 {
1170 int i;
1171 const uint32_t excluded_regs[] = {
1172 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1173 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1174 };
1175
1176 memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
1177 PNPMMIO_SIZE);
1178 memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);
1179 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1180 memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
1181 excluded_regs[i+1] - excluded_regs[i] - 4);
1182 memory_region_init_io(&d->io, &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
1183 }
1184
1185 static void
1186 e1000_cleanup(VLANClientState *nc)
1187 {
1188 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1189
1190 s->nic = NULL;
1191 }
1192
1193 static int
1194 pci_e1000_uninit(PCIDevice *dev)
1195 {
1196 E1000State *d = DO_UPCAST(E1000State, dev, dev);
1197
1198 qemu_del_timer(d->autoneg_timer);
1199 qemu_free_timer(d->autoneg_timer);
1200 memory_region_destroy(&d->mmio);
1201 memory_region_destroy(&d->io);
1202 qemu_del_vlan_client(&d->nic->nc);
1203 return 0;
1204 }
1205
1206 static NetClientInfo net_e1000_info = {
1207 .type = NET_CLIENT_TYPE_NIC,
1208 .size = sizeof(NICState),
1209 .can_receive = e1000_can_receive,
1210 .receive = e1000_receive,
1211 .cleanup = e1000_cleanup,
1212 .link_status_changed = e1000_set_link_status,
1213 };
1214
1215 static int pci_e1000_init(PCIDevice *pci_dev)
1216 {
1217 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
1218 uint8_t *pci_conf;
1219 uint16_t checksum = 0;
1220 int i;
1221 uint8_t *macaddr;
1222
1223 pci_conf = d->dev.config;
1224
1225 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1226 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
1227
1228 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
1229
1230 e1000_mmio_setup(d);
1231
1232 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
1233
1234 pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
1235
1236 memmove(d->eeprom_data, e1000_eeprom_template,
1237 sizeof e1000_eeprom_template);
1238 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1239 macaddr = d->conf.macaddr.a;
1240 for (i = 0; i < 3; i++)
1241 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
1242 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1243 checksum += d->eeprom_data[i];
1244 checksum = (uint16_t) EEPROM_SUM - checksum;
1245 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1246
1247 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
1248 object_get_typename(OBJECT(d)), d->dev.qdev.id, d);
1249
1250 qemu_format_nic_info_str(&d->nic->nc, macaddr);
1251
1252 add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1253
1254 d->autoneg_timer = qemu_new_timer_ms(vm_clock, e1000_autoneg_timer, d);
1255
1256 return 0;
1257 }
1258
1259 static void qdev_e1000_reset(DeviceState *dev)
1260 {
1261 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1262 e1000_reset(d);
1263 }
1264
1265 static Property e1000_properties[] = {
1266 DEFINE_NIC_PROPERTIES(E1000State, conf),
1267 DEFINE_PROP_END_OF_LIST(),
1268 };
1269
1270 static void e1000_class_init(ObjectClass *klass, void *data)
1271 {
1272 DeviceClass *dc = DEVICE_CLASS(klass);
1273 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1274
1275 k->init = pci_e1000_init;
1276 k->exit = pci_e1000_uninit;
1277 k->romfile = "pxe-e1000.rom";
1278 k->vendor_id = PCI_VENDOR_ID_INTEL;
1279 k->device_id = E1000_DEVID;
1280 k->revision = 0x03;
1281 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
1282 dc->desc = "Intel Gigabit Ethernet";
1283 dc->reset = qdev_e1000_reset;
1284 dc->vmsd = &vmstate_e1000;
1285 dc->props = e1000_properties;
1286 }
1287
1288 static TypeInfo e1000_info = {
1289 .name = "e1000",
1290 .parent = TYPE_PCI_DEVICE,
1291 .instance_size = sizeof(E1000State),
1292 .class_init = e1000_class_init,
1293 };
1294
1295 static void e1000_register_types(void)
1296 {
1297 type_register_static(&e1000_info);
1298 }
1299
1300 type_init(e1000_register_types)
Qemu copy for testing