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eepro100: Use symbolic names and BIT macros in binary operations
[qemu.git] / hw / eepro100.c
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2010 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 *
35 * TODO:
36 * * PHY emulation should be separated from nic emulation.
37 * Most nic emulations could share the same phy code.
38 * * i82550 is untested. It is programmed like the i82559.
39 * * i82562 is untested. It is programmed like the i82559.
40 * * Power management (i82558 and later) is not implemented.
41 * * Wake-on-LAN is not implemented.
42 */
43
44 #include <stddef.h> /* offsetof */
45 #include <stdbool.h>
46 #include "hw.h"
47 #include "pci.h"
48 #include "net.h"
49 #include "eeprom93xx.h"
50
51 /* Common declarations for all PCI devices. */
52
53 #define PCI_CONFIG_8(offset, value) \
54 (pci_conf[offset] = (value))
55 #define PCI_CONFIG_16(offset, value) \
56 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
57 #define PCI_CONFIG_32(offset, value) \
58 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
59
60 #define KiB 1024
61
62 /* Debug EEPRO100 card. */
63 #if 0
64 # define DEBUG_EEPRO100
65 #endif
66
67 #ifdef DEBUG_EEPRO100
68 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
69 #else
70 #define logout(fmt, ...) ((void)0)
71 #endif
72
73 /* Set flags to 0 to disable debug output. */
74 #define INT 1 /* interrupt related actions */
75 #define MDI 1 /* mdi related actions */
76 #define OTHER 1
77 #define RXTX 1
78 #define EEPROM 1 /* eeprom related actions */
79
80 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
81
82 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
83
84 #define MAX_ETH_FRAME_SIZE 1514
85
86 /* This driver supports several different devices which are declared here. */
87 #define i82550 0x82550
88 #define i82551 0x82551
89 #define i82557A 0x82557a
90 #define i82557B 0x82557b
91 #define i82557C 0x82557c
92 #define i82558A 0x82558a
93 #define i82558B 0x82558b
94 #define i82559A 0x82559a
95 #define i82559B 0x82559b
96 #define i82559C 0x82559c
97 #define i82559ER 0x82559e
98 #define i82562 0x82562
99
100 /* Use 64 word EEPROM. TODO: could be a runtime option. */
101 #define EEPROM_SIZE 64
102
103 #define PCI_MEM_SIZE (4 * KiB)
104 #define PCI_IO_SIZE 64
105 #define PCI_FLASH_SIZE (128 * KiB)
106
107 #define BIT(n) (1 << (n))
108 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
109
110 /* The SCB accepts the following controls for the Tx and Rx units: */
111 #define CU_NOP 0x0000 /* No operation. */
112 #define CU_START 0x0010 /* CU start. */
113 #define CU_RESUME 0x0020 /* CU resume. */
114 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
115 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
116 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
117 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
118 #define CU_SRESUME 0x00a0 /* CU static resume. */
119
120 #define RU_NOP 0x0000
121 #define RX_START 0x0001
122 #define RX_RESUME 0x0002
123 #define RX_ABORT 0x0004
124 #define RX_ADDR_LOAD 0x0006
125 #define RX_RESUMENR 0x0007
126 #define INT_MASK 0x0100
127 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
128
129 /* Offsets to the various registers.
130 All accesses need not be longword aligned. */
131 enum speedo_offsets {
132 SCBStatus = 0, /* Status Word. */
133 SCBAck = 1,
134 SCBCmd = 2, /* Rx/Command Unit command and status. */
135 SCBIntmask = 3,
136 SCBPointer = 4, /* General purpose pointer. */
137 SCBPort = 8, /* Misc. commands and operands. */
138 SCBflash = 12, /* Flash memory control. */
139 SCBeeprom = 14, /* EEPROM control. */
140 SCBCtrlMDI = 16, /* MDI interface control. */
141 SCBEarlyRx = 20, /* Early receive byte count. */
142 SCBFlow = 24, /* Flow Control. */
143 SCBpmdr = 27, /* Power Management Driver. */
144 SCBgctrl = 28, /* General Control. */
145 SCBgstat = 29, /* General Status. */
146 };
147
148 /* A speedo3 transmit buffer descriptor with two buffers... */
149 typedef struct {
150 uint16_t status;
151 uint16_t command;
152 uint32_t link; /* void * */
153 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
154 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
155 uint8_t tx_threshold; /* transmit threshold */
156 uint8_t tbd_count; /* TBD number */
157 //~ /* This constitutes two "TBD" entries: hdr and data */
158 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
159 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
160 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
161 //~ int32_t tx_buf_size1; /* Length of Tx data. */
162 } eepro100_tx_t;
163
164 /* Receive frame descriptor. */
165 typedef struct {
166 int16_t status;
167 uint16_t command;
168 uint32_t link; /* struct RxFD * */
169 uint32_t rx_buf_addr; /* void * */
170 uint16_t count;
171 uint16_t size;
172 char packet[MAX_ETH_FRAME_SIZE + 4];
173 } eepro100_rx_t;
174
175 typedef enum {
176 COMMAND_EL = BIT(15),
177 COMMAND_S = BIT(14),
178 COMMAND_I = BIT(13),
179 COMMAND_NC = BIT(4),
180 COMMAND_SF = BIT(3),
181 COMMAND_CMD = BITS(2, 0),
182 } scb_command_bit;
183
184 typedef enum {
185 STATUS_C = BIT(15),
186 STATUS_OK = BIT(13),
187 } scb_status_bit;
188
189 typedef struct {
190 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
191 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
192 tx_multiple_collisions, tx_total_collisions;
193 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
194 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
195 rx_short_frame_errors;
196 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
197 uint16_t xmt_tco_frames, rcv_tco_frames;
198 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
199 uint32_t reserved[4];
200 } eepro100_stats_t;
201
202 typedef enum {
203 cu_idle = 0,
204 cu_suspended = 1,
205 cu_active = 2,
206 cu_lpq_active = 2,
207 cu_hqp_active = 3
208 } cu_state_t;
209
210 typedef enum {
211 ru_idle = 0,
212 ru_suspended = 1,
213 ru_no_resources = 2,
214 ru_ready = 4
215 } ru_state_t;
216
217 typedef struct {
218 PCIDevice dev;
219 uint8_t mult[8]; /* multicast mask array */
220 int mmio_index;
221 NICState *nic;
222 NICConf conf;
223 uint8_t scb_stat; /* SCB stat/ack byte */
224 uint8_t int_stat; /* PCI interrupt status */
225 /* region must not be saved by nic_save. */
226 uint32_t region[3]; /* PCI region addresses */
227 uint16_t mdimem[32];
228 eeprom_t *eeprom;
229 uint32_t device; /* device variant */
230 uint32_t pointer;
231 /* (cu_base + cu_offset) address the next command block in the command block list. */
232 uint32_t cu_base; /* CU base address */
233 uint32_t cu_offset; /* CU address offset */
234 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
235 uint32_t ru_base; /* RU base address */
236 uint32_t ru_offset; /* RU address offset */
237 uint32_t statsaddr; /* pointer to eepro100_stats_t */
238
239 /* Temporary status information (no need to save these values),
240 * used while processing CU commands. */
241 eepro100_tx_t tx; /* transmit buffer descriptor */
242 uint32_t cb_address; /* = cu_base + cu_offset */
243
244 /* Statistical counters. Also used for wake-up packet (i82559). */
245 eepro100_stats_t statistics;
246
247 #if 0
248 uint16_t status;
249 #endif
250
251 /* Configuration bytes. */
252 uint8_t configuration[22];
253
254 /* Data in mem is always in the byte order of the controller (le). */
255 uint8_t mem[PCI_MEM_SIZE];
256 /* vmstate for each particular nic */
257 VMStateDescription *vmstate;
258
259 /* Quasi static device properties (no need to save them). */
260 uint16_t stats_size;
261 bool has_extended_tcb_support;
262 } EEPRO100State;
263
264 /* Word indices in EEPROM. */
265 typedef enum {
266 EEPROM_CNFG_MDIX = 0x03,
267 EEPROM_ID = 0x05,
268 EEPROM_PHY_ID = 0x06,
269 EEPROM_VENDOR_ID = 0x0c,
270 EEPROM_CONFIG_ASF = 0x0d,
271 EEPROM_DEVICE_ID = 0x23,
272 EEPROM_SMBUS_ADDR = 0x90,
273 } EEPROMOffset;
274
275 /* Default values for MDI (PHY) registers */
276 static const uint16_t eepro100_mdi_default[] = {
277 /* MDI Registers 0 - 6, 7 */
278 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
279 /* MDI Registers 8 - 15 */
280 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
281 /* MDI Registers 16 - 31 */
282 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
283 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
284 };
285
286 /* Readonly mask for MDI (PHY) registers */
287 static const uint16_t eepro100_mdi_mask[] = {
288 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
289 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
290 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
291 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
292 };
293
294 /* XXX: optimize */
295 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
296 {
297 val = cpu_to_le32(val);
298 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
299 }
300
301 #define POLYNOMIAL 0x04c11db6
302
303 /* From FreeBSD */
304 /* XXX: optimize */
305 static unsigned compute_mcast_idx(const uint8_t * ep)
306 {
307 uint32_t crc;
308 int carry, i, j;
309 uint8_t b;
310
311 crc = 0xffffffff;
312 for (i = 0; i < 6; i++) {
313 b = *ep++;
314 for (j = 0; j < 8; j++) {
315 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
316 crc <<= 1;
317 b >>= 1;
318 if (carry) {
319 crc = ((crc ^ POLYNOMIAL) | carry);
320 }
321 }
322 }
323 return (crc & BITS(7, 2)) >> 2;
324 }
325
326 #if defined(DEBUG_EEPRO100)
327 static const char *nic_dump(const uint8_t * buf, unsigned size)
328 {
329 static char dump[3 * 16 + 1];
330 char *p = &dump[0];
331 if (size > 16) {
332 size = 16;
333 }
334 while (size-- > 0) {
335 p += sprintf(p, " %02x", *buf++);
336 }
337 return dump;
338 }
339 #endif /* DEBUG_EEPRO100 */
340
341 enum scb_stat_ack {
342 stat_ack_not_ours = 0x00,
343 stat_ack_sw_gen = 0x04,
344 stat_ack_rnr = 0x10,
345 stat_ack_cu_idle = 0x20,
346 stat_ack_frame_rx = 0x40,
347 stat_ack_cu_cmd_done = 0x80,
348 stat_ack_not_present = 0xFF,
349 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
350 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
351 };
352
353 static void disable_interrupt(EEPRO100State * s)
354 {
355 if (s->int_stat) {
356 TRACE(INT, logout("interrupt disabled\n"));
357 qemu_irq_lower(s->dev.irq[0]);
358 s->int_stat = 0;
359 }
360 }
361
362 static void enable_interrupt(EEPRO100State * s)
363 {
364 if (!s->int_stat) {
365 TRACE(INT, logout("interrupt enabled\n"));
366 qemu_irq_raise(s->dev.irq[0]);
367 s->int_stat = 1;
368 }
369 }
370
371 static void eepro100_acknowledge(EEPRO100State * s)
372 {
373 s->scb_stat &= ~s->mem[SCBAck];
374 s->mem[SCBAck] = s->scb_stat;
375 if (s->scb_stat == 0) {
376 disable_interrupt(s);
377 }
378 }
379
380 static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
381 {
382 uint8_t mask = ~s->mem[SCBIntmask];
383 s->mem[SCBAck] |= stat;
384 stat = s->scb_stat = s->mem[SCBAck];
385 stat &= (mask | 0x0f);
386 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
387 if (stat && (mask & 0x01)) {
388 /* SCB mask and SCB Bit M do not disable interrupt. */
389 enable_interrupt(s);
390 } else if (s->int_stat) {
391 disable_interrupt(s);
392 }
393 }
394
395 static void eepro100_cx_interrupt(EEPRO100State * s)
396 {
397 /* CU completed action command. */
398 /* Transmit not ok (82557 only, not in emulation). */
399 eepro100_interrupt(s, 0x80);
400 }
401
402 static void eepro100_cna_interrupt(EEPRO100State * s)
403 {
404 /* CU left the active state. */
405 eepro100_interrupt(s, 0x20);
406 }
407
408 static void eepro100_fr_interrupt(EEPRO100State * s)
409 {
410 /* RU received a complete frame. */
411 eepro100_interrupt(s, 0x40);
412 }
413
414 #if 0
415 static void eepro100_rnr_interrupt(EEPRO100State * s)
416 {
417 /* RU is not ready. */
418 eepro100_interrupt(s, 0x10);
419 }
420 #endif
421
422 static void eepro100_mdi_interrupt(EEPRO100State * s)
423 {
424 /* MDI completed read or write cycle. */
425 eepro100_interrupt(s, 0x08);
426 }
427
428 static void eepro100_swi_interrupt(EEPRO100State * s)
429 {
430 /* Software has requested an interrupt. */
431 eepro100_interrupt(s, 0x04);
432 }
433
434 #if 0
435 static void eepro100_fcp_interrupt(EEPRO100State * s)
436 {
437 /* Flow control pause interrupt (82558 and later). */
438 eepro100_interrupt(s, 0x01);
439 }
440 #endif
441
442 static void pci_reset(EEPRO100State * s)
443 {
444 uint32_t device = s->device;
445 uint8_t *pci_conf = s->dev.config;
446 bool power_management = 1;
447
448 TRACE(OTHER, logout("%p\n", s));
449
450 /* PCI Vendor ID */
451 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
452 /* PCI Device ID depends on device and is set below. */
453 /* PCI Command */
454 /* TODO: this is the default, do not override. */
455 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
456 /* PCI Status */
457 /* TODO: Value at RST# should be 0. */
458 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
459 /* PCI Revision ID */
460 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
461 /* TODO: this is the default, do not override. */
462 /* PCI Class Code */
463 PCI_CONFIG_8(PCI_CLASS_PROG, 0x00);
464 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
465 /* PCI Cache Line Size */
466 /* check cache line size!!! */
467 //~ PCI_CONFIG_8(0x0c, 0x00);
468 /* PCI Latency Timer */
469 PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks
470 /* PCI Header Type */
471 /* BIST (built-in self test) */
472 #if defined(TARGET_I386)
473 // !!! workaround for buggy bios
474 //~ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0
475 #endif
476 #if 0
477 /* PCI Base Address Registers */
478 /* CSR Memory Mapped Base Address */
479 PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
480 PCI_BASE_ADDRESS_SPACE_MEMORY |
481 PCI_BASE_ADDRESS_MEM_PREFETCH);
482 /* CSR I/O Mapped Base Address */
483 PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_SPACE_IO);
484 #if 0
485 /* Flash Memory Mapped Base Address */
486 PCI_CONFIG_32(PCI_BASE_ADDRESS_2,
487 0xfffe0000 | PCI_BASE_ADDRESS_SPACE_MEMORY);
488 #endif
489 #endif
490 /* Expansion ROM Base Address (depends on boot disable!!!) */
491 /* TODO: not needed, set when BAR is registered */
492 PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY);
493 /* Capability Pointer */
494 /* TODO: revisions with power_management 1 use this but
495 * do not set new capability list bit in status register. */
496 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc);
497 /* Interrupt Line */
498 /* Interrupt Pin */
499 /* TODO: RST# value should be 0 */
500 PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0
501 /* Minimum Grant */
502 PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
503 /* Maximum Latency */
504 PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
505
506 switch (device) {
507 case i82550:
508 // TODO: check device id.
509 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
510 /* Revision ID: 0x0c, 0x0d, 0x0e. */
511 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
512 // TODO: check size of statistical counters.
513 s->stats_size = 80;
514 // TODO: check extended tcb support.
515 s->has_extended_tcb_support = 1;
516 break;
517 case i82551:
518 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
519 /* Revision ID: 0x0f, 0x10. */
520 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
521 // TODO: check size of statistical counters.
522 s->stats_size = 80;
523 s->has_extended_tcb_support = 1;
524 break;
525 case i82557A:
526 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
527 PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
528 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
529 power_management = 0;
530 break;
531 case i82557B:
532 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
533 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
534 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
535 power_management = 0;
536 break;
537 case i82557C:
538 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
539 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
540 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
541 power_management = 0;
542 break;
543 case i82558A:
544 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
545 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
546 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
547 PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
548 s->stats_size = 76;
549 s->has_extended_tcb_support = 1;
550 break;
551 case i82558B:
552 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
553 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
554 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
555 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
556 s->stats_size = 76;
557 s->has_extended_tcb_support = 1;
558 break;
559 case i82559A:
560 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
561 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
562 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
563 PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
564 s->stats_size = 80;
565 s->has_extended_tcb_support = 1;
566 break;
567 case i82559B:
568 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
569 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
570 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
571 PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
572 s->stats_size = 80;
573 s->has_extended_tcb_support = 1;
574 break;
575 case i82559C:
576 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
577 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
578 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
579 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
580 // TODO: Windows wants revision id 0x0c.
581 PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
582 #if EEPROM_SIZE > 0
583 PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
584 PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
585 #endif
586 s->stats_size = 80;
587 s->has_extended_tcb_support = 1;
588 break;
589 case i82559ER:
590 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
591 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
592 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
593 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
594 s->stats_size = 80;
595 s->has_extended_tcb_support = 1;
596 break;
597 case i82562:
598 // TODO: check device id.
599 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
600 /* TODO: wrong revision id. */
601 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
602 s->stats_size = 80;
603 s->has_extended_tcb_support = 1;
604 break;
605 default:
606 logout("Device %X is undefined!\n", device);
607 }
608
609 s->configuration[6] |= BIT(5);
610
611 if (s->stats_size == 80) {
612 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
613 if (s->configuration[6] & BIT(2)) {
614 /* TCO statistical counters. */
615 assert(s->configuration[6] & BIT(5));
616 } else {
617 if (s->configuration[6] & BIT(5)) {
618 /* No extended statistical counters, i82557 compatible. */
619 s->stats_size = 64;
620 } else {
621 /* i82558 compatible. */
622 s->stats_size = 76;
623 }
624 }
625 } else {
626 if (s->configuration[6] & BIT(5)) {
627 /* No extended statistical counters. */
628 s->stats_size = 64;
629 }
630 }
631 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
632
633 if (power_management) {
634 /* Power Management Capabilities */
635 PCI_CONFIG_8(0xdc, 0x01);
636 /* Next Item Pointer */
637 /* Capability ID */
638 PCI_CONFIG_16(0xde, 0x7e21);
639 /* TODO: Power Management Control / Status. */
640 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
641 }
642
643 #if EEPROM_SIZE > 0
644 if (device == i82557C || device == i82558B || device == i82559C) {
645 // TODO: get vendor id from EEPROM for i82557C or later.
646 // TODO: get device id from EEPROM for i82557C or later.
647 // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
648 // TODO: header type is determined by EEPROM for i82559.
649 // TODO: get subsystem id from EEPROM for i82557C or later.
650 // TODO: get subsystem vendor id from EEPROM for i82557C or later.
651 // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
652 // TODO: capability pointer depends on EEPROM for i82558.
653 logout("Get device id and revision from EEPROM!!!\n");
654 }
655 #endif /* EEPROM_SIZE > 0 */
656 }
657
658 static void nic_selective_reset(EEPRO100State * s)
659 {
660 size_t i;
661 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
662 //~ eeprom93xx_reset(s->eeprom);
663 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
664 eeprom_contents[EEPROM_ID] = 0x4000;
665 if (s->device == i82557B || s->device == i82557C)
666 eeprom_contents[5] = 0x0100;
667 eeprom_contents[EEPROM_PHY_ID] = 1;
668 uint16_t sum = 0;
669 for (i = 0; i < EEPROM_SIZE - 1; i++) {
670 sum += eeprom_contents[i];
671 }
672 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
673 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
674
675 memset(s->mem, 0, sizeof(s->mem));
676 uint32_t val = BIT(21);
677 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
678
679 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
680 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
681 }
682
683 static void nic_reset(void *opaque)
684 {
685 EEPRO100State *s = opaque;
686 TRACE(OTHER, logout("%p\n", s));
687 /* TODO: Clearing of multicast table for selective reset, too? */
688 memset(&s->mult[0], 0, sizeof(s->mult));
689 nic_selective_reset(s);
690 }
691
692 #if defined(DEBUG_EEPRO100)
693 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
694 "Command/Status",
695 "General Pointer",
696 "Port",
697 "EEPROM/Flash Control",
698 "MDI Control",
699 "Receive DMA Byte Count",
700 "Flow Control",
701 "General Status/Control"
702 };
703
704 static char *regname(uint32_t addr)
705 {
706 static char buf[32];
707 if (addr < PCI_IO_SIZE) {
708 const char *r = e100_reg[addr / 4];
709 if (r != 0) {
710 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
711 } else {
712 snprintf(buf, sizeof(buf), "0x%02x", addr);
713 }
714 } else {
715 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
716 }
717 return buf;
718 }
719 #endif /* DEBUG_EEPRO100 */
720
721 #if 0
722 static uint16_t eepro100_read_status(EEPRO100State * s)
723 {
724 uint16_t val = s->status;
725 TRACE(OTHER, logout("val=0x%04x\n", val));
726 return val;
727 }
728
729 static void eepro100_write_status(EEPRO100State * s, uint16_t val)
730 {
731 TRACE(OTHER, logout("val=0x%04x\n", val));
732 s->status = val;
733 }
734 #endif
735
736 /*****************************************************************************
737 *
738 * Command emulation.
739 *
740 ****************************************************************************/
741
742 #if 0
743 static uint16_t eepro100_read_command(EEPRO100State * s)
744 {
745 uint16_t val = 0xffff;
746 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
747 return val;
748 }
749 #endif
750
751 /* Commands that can be put in a command list entry. */
752 enum commands {
753 CmdNOp = 0,
754 CmdIASetup = 1,
755 CmdConfigure = 2,
756 CmdMulticastList = 3,
757 CmdTx = 4,
758 CmdTDR = 5, /* load microcode */
759 CmdDump = 6,
760 CmdDiagnose = 7,
761
762 /* And some extra flags: */
763 CmdSuspend = 0x4000, /* Suspend after completion. */
764 CmdIntr = 0x2000, /* Interrupt after completion. */
765 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
766 };
767
768 static cu_state_t get_cu_state(EEPRO100State * s)
769 {
770 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
771 }
772
773 static void set_cu_state(EEPRO100State * s, cu_state_t state)
774 {
775 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
776 }
777
778 static ru_state_t get_ru_state(EEPRO100State * s)
779 {
780 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
781 }
782
783 static void set_ru_state(EEPRO100State * s, ru_state_t state)
784 {
785 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
786 }
787
788 static void dump_statistics(EEPRO100State * s)
789 {
790 /* Dump statistical data. Most data is never changed by the emulation
791 * and always 0, so we first just copy the whole block and then those
792 * values which really matter.
793 * Number of data should check configuration!!!
794 */
795 cpu_physical_memory_write(s->statsaddr,
796 (uint8_t *) & s->statistics, s->stats_size);
797 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
798 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
799 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
800 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
801 //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
802 //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
803 //~ missing("CU dump statistical counters");
804 }
805
806 static void tx_command(EEPRO100State *s)
807 {
808 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
809 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
810 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
811 uint8_t buf[2600];
812 uint16_t size = 0;
813 uint32_t tbd_address = s->cb_address + 0x10;
814 TRACE(RXTX, logout
815 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
816 tbd_array, tcb_bytes, s->tx.tbd_count));
817
818 if (tcb_bytes > 2600) {
819 logout("TCB byte count too large, using 2600\n");
820 tcb_bytes = 2600;
821 }
822 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
823 logout
824 ("illegal values of TBD array address and TCB byte count!\n");
825 }
826 assert(tcb_bytes <= sizeof(buf));
827 while (size < tcb_bytes) {
828 uint32_t tx_buffer_address = ldl_phys(tbd_address);
829 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
830 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
831 tbd_address += 8;
832 TRACE(RXTX, logout
833 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
834 tx_buffer_address, tx_buffer_size));
835 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
836 cpu_physical_memory_read(tx_buffer_address, &buf[size],
837 tx_buffer_size);
838 size += tx_buffer_size;
839 }
840 if (tbd_array == 0xffffffff) {
841 /* Simplified mode. Was already handled by code above. */
842 } else {
843 /* Flexible mode. */
844 uint8_t tbd_count = 0;
845 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
846 /* Extended Flexible TCB. */
847 for (; tbd_count < 2; tbd_count++) {
848 uint32_t tx_buffer_address = ldl_phys(tbd_address);
849 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
850 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
851 tbd_address += 8;
852 TRACE(RXTX, logout
853 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
854 tx_buffer_address, tx_buffer_size));
855 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
856 cpu_physical_memory_read(tx_buffer_address, &buf[size],
857 tx_buffer_size);
858 size += tx_buffer_size;
859 if (tx_buffer_el & 1) {
860 break;
861 }
862 }
863 }
864 tbd_address = tbd_array;
865 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
866 uint32_t tx_buffer_address = ldl_phys(tbd_address);
867 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
868 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
869 tbd_address += 8;
870 TRACE(RXTX, logout
871 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
872 tx_buffer_address, tx_buffer_size));
873 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
874 cpu_physical_memory_read(tx_buffer_address, &buf[size],
875 tx_buffer_size);
876 size += tx_buffer_size;
877 if (tx_buffer_el & 1) {
878 break;
879 }
880 }
881 }
882 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
883 qemu_send_packet(&s->nic->nc, buf, size);
884 s->statistics.tx_good_frames++;
885 /* Transmit with bad status would raise an CX/TNO interrupt.
886 * (82557 only). Emulation never has bad status. */
887 //~ eepro100_cx_interrupt(s);
888 }
889
890 static void set_multicast_list(EEPRO100State *s)
891 {
892 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
893 uint16_t i;
894 memset(&s->mult[0], 0, sizeof(s->mult));
895 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
896 for (i = 0; i < multicast_count; i += 6) {
897 uint8_t multicast_addr[6];
898 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
899 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
900 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
901 assert(mcast_idx < 64);
902 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
903 }
904 }
905
906 static void action_command(EEPRO100State *s)
907 {
908 for (;;) {
909 s->cb_address = s->cu_base + s->cu_offset;
910 cpu_physical_memory_read(s->cb_address, (uint8_t *)&s->tx, sizeof(s->tx));
911 uint16_t status = le16_to_cpu(s->tx.status);
912 uint16_t command = le16_to_cpu(s->tx.command);
913 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
914 status, command, s->tx.link);
915 bool bit_el = ((command & COMMAND_EL) != 0);
916 bool bit_s = ((command & COMMAND_S) != 0);
917 bool bit_i = ((command & COMMAND_I) != 0);
918 bool bit_nc = ((command & COMMAND_NC) != 0);
919 bool success = true;
920 //~ bool bit_sf = ((command & COMMAND_SF) != 0);
921 uint16_t cmd = command & COMMAND_CMD;
922 s->cu_offset = le32_to_cpu(s->tx.link);
923 switch (cmd) {
924 case CmdNOp:
925 /* Do nothing. */
926 break;
927 case CmdIASetup:
928 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
929 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
930 break;
931 case CmdConfigure:
932 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
933 sizeof(s->configuration));
934 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
935 break;
936 case CmdMulticastList:
937 set_multicast_list(s);
938 break;
939 case CmdTx:
940 if (bit_nc) {
941 missing("CmdTx: NC = 0");
942 success = false;
943 break;
944 }
945 tx_command(s);
946 break;
947 case CmdTDR:
948 TRACE(OTHER, logout("load microcode\n"));
949 /* Starting with offset 8, the command contains
950 * 64 dwords microcode which we just ignore here. */
951 break;
952 default:
953 missing("undefined command");
954 success = false;
955 break;
956 }
957 /* Write new status. */
958 stw_phys(s->cb_address, status | STATUS_C | (success ? STATUS_OK : 0));
959 if (bit_i) {
960 /* CU completed action. */
961 eepro100_cx_interrupt(s);
962 }
963 if (bit_el) {
964 /* CU becomes idle. Terminate command loop. */
965 set_cu_state(s, cu_idle);
966 eepro100_cna_interrupt(s);
967 break;
968 } else if (bit_s) {
969 /* CU becomes suspended. Terminate command loop. */
970 set_cu_state(s, cu_suspended);
971 eepro100_cna_interrupt(s);
972 break;
973 } else {
974 /* More entries in list. */
975 TRACE(OTHER, logout("CU list with at least one more entry\n"));
976 }
977 }
978 TRACE(OTHER, logout("CU list empty\n"));
979 /* List is empty. Now CU is idle or suspended. */
980 }
981
982 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
983 {
984 switch (val) {
985 case CU_NOP:
986 /* No operation. */
987 break;
988 case CU_START:
989 if (get_cu_state(s) != cu_idle) {
990 /* Intel documentation says that CU must be idle for the CU
991 * start command. Intel driver for Linux also starts the CU
992 * from suspended state. */
993 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
994 //~ assert(!"wrong CU state");
995 }
996 set_cu_state(s, cu_active);
997 s->cu_offset = s->pointer;
998 action_command(s);
999 break;
1000 case CU_RESUME:
1001 if (get_cu_state(s) != cu_suspended) {
1002 logout("bad CU resume from CU state %u\n", get_cu_state(s));
1003 /* Workaround for bad Linux eepro100 driver which resumes
1004 * from idle state. */
1005 //~ missing("cu resume");
1006 set_cu_state(s, cu_suspended);
1007 }
1008 if (get_cu_state(s) == cu_suspended) {
1009 TRACE(OTHER, logout("CU resuming\n"));
1010 set_cu_state(s, cu_active);
1011 action_command(s);
1012 }
1013 break;
1014 case CU_STATSADDR:
1015 /* Load dump counters address. */
1016 s->statsaddr = s->pointer;
1017 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
1018 break;
1019 case CU_SHOWSTATS:
1020 /* Dump statistical counters. */
1021 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
1022 dump_statistics(s);
1023 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
1024 break;
1025 case CU_CMD_BASE:
1026 /* Load CU base. */
1027 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
1028 s->cu_base = s->pointer;
1029 break;
1030 case CU_DUMPSTATS:
1031 /* Dump and reset statistical counters. */
1032 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1033 dump_statistics(s);
1034 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
1035 memset(&s->statistics, 0, sizeof(s->statistics));
1036 break;
1037 case CU_SRESUME:
1038 /* CU static resume. */
1039 missing("CU static resume");
1040 break;
1041 default:
1042 missing("Undefined CU command");
1043 }
1044 }
1045
1046 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1047 {
1048 switch (val) {
1049 case RU_NOP:
1050 /* No operation. */
1051 break;
1052 case RX_START:
1053 /* RU start. */
1054 if (get_ru_state(s) != ru_idle) {
1055 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1056 //~ assert(!"wrong RU state");
1057 }
1058 set_ru_state(s, ru_ready);
1059 s->ru_offset = s->pointer;
1060 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1061 break;
1062 case RX_RESUME:
1063 /* Restart RU. */
1064 if (get_ru_state(s) != ru_suspended) {
1065 logout("RU state is %u, should be %u\n", get_ru_state(s),
1066 ru_suspended);
1067 //~ assert(!"wrong RU state");
1068 }
1069 set_ru_state(s, ru_ready);
1070 break;
1071 case RX_ADDR_LOAD:
1072 /* Load RU base. */
1073 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1074 s->ru_base = s->pointer;
1075 break;
1076 default:
1077 logout("val=0x%02x (undefined RU command)\n", val);
1078 missing("Undefined SU command");
1079 }
1080 }
1081
1082 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1083 {
1084 eepro100_ru_command(s, val & 0x0f);
1085 eepro100_cu_command(s, val & 0xf0);
1086 if ((val) == 0) {
1087 TRACE(OTHER, logout("val=0x%02x\n", val));
1088 }
1089 /* Clear command byte after command was accepted. */
1090 s->mem[SCBCmd] = 0;
1091 }
1092
1093 /*****************************************************************************
1094 *
1095 * EEPROM emulation.
1096 *
1097 ****************************************************************************/
1098
1099 #define EEPROM_CS 0x02
1100 #define EEPROM_SK 0x01
1101 #define EEPROM_DI 0x04
1102 #define EEPROM_DO 0x08
1103
1104 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1105 {
1106 uint16_t val;
1107 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1108 if (eeprom93xx_read(s->eeprom)) {
1109 val |= EEPROM_DO;
1110 } else {
1111 val &= ~EEPROM_DO;
1112 }
1113 TRACE(EEPROM, logout("val=0x%04x\n", val));
1114 return val;
1115 }
1116
1117 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1118 {
1119 TRACE(EEPROM, logout("val=0x%02x\n", val));
1120
1121 /* mask unwriteable bits */
1122 //~ val = SET_MASKED(val, 0x31, eeprom->value);
1123
1124 int eecs = ((val & EEPROM_CS) != 0);
1125 int eesk = ((val & EEPROM_SK) != 0);
1126 int eedi = ((val & EEPROM_DI) != 0);
1127 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1128 }
1129
1130 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1131 {
1132 s->pointer = le32_to_cpu(val);
1133 TRACE(OTHER, logout("val=0x%08x\n", val));
1134 }
1135
1136 /*****************************************************************************
1137 *
1138 * MDI emulation.
1139 *
1140 ****************************************************************************/
1141
1142 #if defined(DEBUG_EEPRO100)
1143 static const char * const mdi_op_name[] = {
1144 "opcode 0",
1145 "write",
1146 "read",
1147 "opcode 3"
1148 };
1149
1150 static const char * const mdi_reg_name[] = {
1151 "Control",
1152 "Status",
1153 "PHY Identification (Word 1)",
1154 "PHY Identification (Word 2)",
1155 "Auto-Negotiation Advertisement",
1156 "Auto-Negotiation Link Partner Ability",
1157 "Auto-Negotiation Expansion"
1158 };
1159
1160 static const char *reg2name(uint8_t reg)
1161 {
1162 static char buffer[10];
1163 const char *p = buffer;
1164 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1165 p = mdi_reg_name[reg];
1166 } else {
1167 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1168 }
1169 return p;
1170 }
1171 #endif /* DEBUG_EEPRO100 */
1172
1173 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1174 {
1175 uint32_t val;
1176 memcpy(&val, &s->mem[0x10], sizeof(val));
1177
1178 #ifdef DEBUG_EEPRO100
1179 uint8_t raiseint = (val & BIT(29)) >> 29;
1180 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1181 uint8_t phy = (val & BITS(25, 21)) >> 21;
1182 uint8_t reg = (val & BITS(20, 16)) >> 16;
1183 uint16_t data = (val & BITS(15, 0));
1184 #endif
1185 /* Emulation takes no time to finish MDI transaction. */
1186 val |= BIT(28);
1187 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1188 val, raiseint, mdi_op_name[opcode], phy,
1189 reg2name(reg), data));
1190 return val;
1191 }
1192
1193 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1194 {
1195 uint8_t raiseint = (val & BIT(29)) >> 29;
1196 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1197 uint8_t phy = (val & BITS(25, 21)) >> 21;
1198 uint8_t reg = (val & BITS(20, 16)) >> 16;
1199 uint16_t data = (val & BITS(15, 0));
1200 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1201 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1202 if (phy != 1) {
1203 /* Unsupported PHY address. */
1204 //~ logout("phy must be 1 but is %u\n", phy);
1205 data = 0;
1206 } else if (opcode != 1 && opcode != 2) {
1207 /* Unsupported opcode. */
1208 logout("opcode must be 1 or 2 but is %u\n", opcode);
1209 data = 0;
1210 } else if (reg > 6) {
1211 /* Unsupported register. */
1212 logout("register must be 0...6 but is %u\n", reg);
1213 data = 0;
1214 } else {
1215 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1216 val, raiseint, mdi_op_name[opcode], phy,
1217 reg2name(reg), data));
1218 if (opcode == 1) {
1219 /* MDI write */
1220 switch (reg) {
1221 case 0: /* Control Register */
1222 if (data & 0x8000) {
1223 /* Reset status and control registers to default. */
1224 s->mdimem[0] = eepro100_mdi_default[0];
1225 s->mdimem[1] = eepro100_mdi_default[1];
1226 data = s->mdimem[reg];
1227 } else {
1228 /* Restart Auto Configuration = Normal Operation */
1229 data &= ~0x0200;
1230 }
1231 break;
1232 case 1: /* Status Register */
1233 missing("not writable");
1234 data = s->mdimem[reg];
1235 break;
1236 case 2: /* PHY Identification Register (Word 1) */
1237 case 3: /* PHY Identification Register (Word 2) */
1238 missing("not implemented");
1239 break;
1240 case 4: /* Auto-Negotiation Advertisement Register */
1241 case 5: /* Auto-Negotiation Link Partner Ability Register */
1242 break;
1243 case 6: /* Auto-Negotiation Expansion Register */
1244 default:
1245 missing("not implemented");
1246 }
1247 s->mdimem[reg] = data;
1248 } else if (opcode == 2) {
1249 /* MDI read */
1250 switch (reg) {
1251 case 0: /* Control Register */
1252 if (data & 0x8000) {
1253 /* Reset status and control registers to default. */
1254 s->mdimem[0] = eepro100_mdi_default[0];
1255 s->mdimem[1] = eepro100_mdi_default[1];
1256 }
1257 break;
1258 case 1: /* Status Register */
1259 s->mdimem[reg] |= 0x0020;
1260 break;
1261 case 2: /* PHY Identification Register (Word 1) */
1262 case 3: /* PHY Identification Register (Word 2) */
1263 case 4: /* Auto-Negotiation Advertisement Register */
1264 break;
1265 case 5: /* Auto-Negotiation Link Partner Ability Register */
1266 s->mdimem[reg] = 0x41fe;
1267 break;
1268 case 6: /* Auto-Negotiation Expansion Register */
1269 s->mdimem[reg] = 0x0001;
1270 break;
1271 }
1272 data = s->mdimem[reg];
1273 }
1274 /* Emulation takes no time to finish MDI transaction.
1275 * Set MDI bit in SCB status register. */
1276 s->mem[SCBAck] |= 0x08;
1277 val |= BIT(28);
1278 if (raiseint) {
1279 eepro100_mdi_interrupt(s);
1280 }
1281 }
1282 val = (val & 0xffff0000) + data;
1283 memcpy(&s->mem[0x10], &val, sizeof(val));
1284 }
1285
1286 /*****************************************************************************
1287 *
1288 * Port emulation.
1289 *
1290 ****************************************************************************/
1291
1292 #define PORT_SOFTWARE_RESET 0
1293 #define PORT_SELFTEST 1
1294 #define PORT_SELECTIVE_RESET 2
1295 #define PORT_DUMP 3
1296 #define PORT_SELECTION_MASK 3
1297
1298 typedef struct {
1299 uint32_t st_sign; /* Self Test Signature */
1300 uint32_t st_result; /* Self Test Results */
1301 } eepro100_selftest_t;
1302
1303 static uint32_t eepro100_read_port(EEPRO100State * s)
1304 {
1305 return 0;
1306 }
1307
1308 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1309 {
1310 val = le32_to_cpu(val);
1311 uint32_t address = (val & ~PORT_SELECTION_MASK);
1312 uint8_t selection = (val & PORT_SELECTION_MASK);
1313 switch (selection) {
1314 case PORT_SOFTWARE_RESET:
1315 nic_reset(s);
1316 break;
1317 case PORT_SELFTEST:
1318 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1319 eepro100_selftest_t data;
1320 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1321 data.st_sign = 0xffffffff;
1322 data.st_result = 0;
1323 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1324 break;
1325 case PORT_SELECTIVE_RESET:
1326 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1327 nic_selective_reset(s);
1328 break;
1329 default:
1330 logout("val=0x%08x\n", val);
1331 missing("unknown port selection");
1332 }
1333 }
1334
1335 /*****************************************************************************
1336 *
1337 * General hardware emulation.
1338 *
1339 ****************************************************************************/
1340
1341 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1342 {
1343 uint8_t val;
1344 if (addr <= sizeof(s->mem) - sizeof(val)) {
1345 memcpy(&val, &s->mem[addr], sizeof(val));
1346 }
1347
1348 switch (addr) {
1349 case SCBStatus:
1350 //~ val = eepro100_read_status(s);
1351 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1352 break;
1353 case SCBAck:
1354 //~ val = eepro100_read_status(s);
1355 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1356 break;
1357 case SCBCmd:
1358 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1359 //~ val = eepro100_read_command(s);
1360 break;
1361 case SCBIntmask:
1362 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1363 break;
1364 case SCBPort + 3:
1365 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1366 break;
1367 case SCBeeprom:
1368 val = eepro100_read_eeprom(s);
1369 break;
1370 case SCBpmdr: /* Power Management Driver Register */
1371 val = 0;
1372 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1373 break;
1374 case SCBgstat: /* General Status Register */
1375 /* 100 Mbps full duplex, valid link */
1376 val = 0x07;
1377 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1378 break;
1379 default:
1380 logout("addr=%s val=0x%02x\n", regname(addr), val);
1381 missing("unknown byte read");
1382 }
1383 return val;
1384 }
1385
1386 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1387 {
1388 uint16_t val;
1389 if (addr <= sizeof(s->mem) - sizeof(val)) {
1390 memcpy(&val, &s->mem[addr], sizeof(val));
1391 }
1392
1393 switch (addr) {
1394 case SCBStatus:
1395 //~ val = eepro100_read_status(s);
1396 case SCBCmd:
1397 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1398 break;
1399 case SCBeeprom:
1400 val = eepro100_read_eeprom(s);
1401 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1402 break;
1403 default:
1404 logout("addr=%s val=0x%04x\n", regname(addr), val);
1405 missing("unknown word read");
1406 }
1407 return val;
1408 }
1409
1410 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1411 {
1412 uint32_t val;
1413 if (addr <= sizeof(s->mem) - sizeof(val)) {
1414 memcpy(&val, &s->mem[addr], sizeof(val));
1415 }
1416
1417 switch (addr) {
1418 case SCBStatus:
1419 //~ val = eepro100_read_status(s);
1420 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1421 break;
1422 case SCBPointer:
1423 //~ val = eepro100_read_pointer(s);
1424 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1425 break;
1426 case SCBPort:
1427 val = eepro100_read_port(s);
1428 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1429 break;
1430 case SCBCtrlMDI:
1431 val = eepro100_read_mdi(s);
1432 break;
1433 default:
1434 logout("addr=%s val=0x%08x\n", regname(addr), val);
1435 missing("unknown longword read");
1436 }
1437 return val;
1438 }
1439
1440 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1441 {
1442 if (addr <= sizeof(s->mem) - sizeof(val)) {
1443 memcpy(&s->mem[addr], &val, sizeof(val));
1444 }
1445
1446 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1447
1448 switch (addr) {
1449 case SCBStatus:
1450 //~ eepro100_write_status(s, val);
1451 break;
1452 case SCBAck:
1453 eepro100_acknowledge(s);
1454 break;
1455 case SCBCmd:
1456 eepro100_write_command(s, val);
1457 break;
1458 case SCBIntmask:
1459 if (val & BIT(1)) {
1460 eepro100_swi_interrupt(s);
1461 }
1462 eepro100_interrupt(s, 0);
1463 break;
1464 case SCBPort + 3:
1465 case SCBFlow: /* does not exist on 82557 */
1466 case SCBFlow + 1:
1467 case SCBFlow + 2:
1468 case SCBpmdr: /* does not exist on 82557 */
1469 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1470 break;
1471 case SCBeeprom:
1472 eepro100_write_eeprom(s->eeprom, val);
1473 break;
1474 default:
1475 logout("addr=%s val=0x%02x\n", regname(addr), val);
1476 missing("unknown byte write");
1477 }
1478 }
1479
1480 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1481 {
1482 if (addr <= sizeof(s->mem) - sizeof(val)) {
1483 memcpy(&s->mem[addr], &val, sizeof(val));
1484 }
1485
1486 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1487
1488 switch (addr) {
1489 case SCBStatus:
1490 //~ eepro100_write_status(s, val);
1491 eepro100_acknowledge(s);
1492 break;
1493 case SCBCmd:
1494 eepro100_write_command(s, val);
1495 eepro100_write1(s, SCBIntmask, val >> 8);
1496 break;
1497 case SCBeeprom:
1498 eepro100_write_eeprom(s->eeprom, val);
1499 break;
1500 default:
1501 logout("addr=%s val=0x%04x\n", regname(addr), val);
1502 missing("unknown word write");
1503 }
1504 }
1505
1506 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1507 {
1508 if (addr <= sizeof(s->mem) - sizeof(val)) {
1509 memcpy(&s->mem[addr], &val, sizeof(val));
1510 }
1511
1512 switch (addr) {
1513 case SCBPointer:
1514 eepro100_write_pointer(s, val);
1515 break;
1516 case SCBPort:
1517 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1518 eepro100_write_port(s, val);
1519 break;
1520 case SCBCtrlMDI:
1521 eepro100_write_mdi(s, val);
1522 break;
1523 default:
1524 logout("addr=%s val=0x%08x\n", regname(addr), val);
1525 missing("unknown longword write");
1526 }
1527 }
1528
1529 /*****************************************************************************
1530 *
1531 * Port mapped I/O.
1532 *
1533 ****************************************************************************/
1534
1535 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1536 {
1537 EEPRO100State *s = opaque;
1538 //~ logout("addr=%s\n", regname(addr));
1539 return eepro100_read1(s, addr - s->region[1]);
1540 }
1541
1542 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1543 {
1544 EEPRO100State *s = opaque;
1545 return eepro100_read2(s, addr - s->region[1]);
1546 }
1547
1548 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1549 {
1550 EEPRO100State *s = opaque;
1551 return eepro100_read4(s, addr - s->region[1]);
1552 }
1553
1554 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1555 {
1556 EEPRO100State *s = opaque;
1557 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1558 eepro100_write1(s, addr - s->region[1], val);
1559 }
1560
1561 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1562 {
1563 EEPRO100State *s = opaque;
1564 eepro100_write2(s, addr - s->region[1], val);
1565 }
1566
1567 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1568 {
1569 EEPRO100State *s = opaque;
1570 eepro100_write4(s, addr - s->region[1], val);
1571 }
1572
1573 /***********************************************************/
1574 /* PCI EEPRO100 definitions */
1575
1576 static void pci_map(PCIDevice * pci_dev, int region_num,
1577 pcibus_t addr, pcibus_t size, int type)
1578 {
1579 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1580
1581 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1582 "size=0x%08"FMT_PCIBUS", type=%d\n",
1583 region_num, addr, size, type));
1584
1585 assert(region_num == 1);
1586 register_ioport_write(addr, size, 1, ioport_write1, s);
1587 register_ioport_read(addr, size, 1, ioport_read1, s);
1588 register_ioport_write(addr, size, 2, ioport_write2, s);
1589 register_ioport_read(addr, size, 2, ioport_read2, s);
1590 register_ioport_write(addr, size, 4, ioport_write4, s);
1591 register_ioport_read(addr, size, 4, ioport_read4, s);
1592
1593 s->region[region_num] = addr;
1594 }
1595
1596 /*****************************************************************************
1597 *
1598 * Memory mapped I/O.
1599 *
1600 ****************************************************************************/
1601
1602 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1603 {
1604 EEPRO100State *s = opaque;
1605 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1606 eepro100_write1(s, addr, val);
1607 }
1608
1609 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1610 {
1611 EEPRO100State *s = opaque;
1612 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1613 eepro100_write2(s, addr, val);
1614 }
1615
1616 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1617 {
1618 EEPRO100State *s = opaque;
1619 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1620 eepro100_write4(s, addr, val);
1621 }
1622
1623 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1624 {
1625 EEPRO100State *s = opaque;
1626 //~ logout("addr=%s\n", regname(addr));
1627 return eepro100_read1(s, addr);
1628 }
1629
1630 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1631 {
1632 EEPRO100State *s = opaque;
1633 //~ logout("addr=%s\n", regname(addr));
1634 return eepro100_read2(s, addr);
1635 }
1636
1637 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1638 {
1639 EEPRO100State *s = opaque;
1640 //~ logout("addr=%s\n", regname(addr));
1641 return eepro100_read4(s, addr);
1642 }
1643
1644 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1645 pci_mmio_writeb,
1646 pci_mmio_writew,
1647 pci_mmio_writel
1648 };
1649
1650 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1651 pci_mmio_readb,
1652 pci_mmio_readw,
1653 pci_mmio_readl
1654 };
1655
1656 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1657 pcibus_t addr, pcibus_t size, int type)
1658 {
1659 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1660
1661 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1662 "size=0x%08"FMT_PCIBUS", type=%d\n",
1663 region_num, addr, size, type));
1664
1665 if (region_num == 0) {
1666 /* Map control / status registers. */
1667 cpu_register_physical_memory(addr, size, s->mmio_index);
1668 s->region[region_num] = addr;
1669 }
1670 }
1671
1672 static int nic_can_receive(VLANClientState *nc)
1673 {
1674 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1675 TRACE(RXTX, logout("%p\n", s));
1676 return get_ru_state(s) == ru_ready;
1677 //~ return !eepro100_buffer_full(s);
1678 }
1679
1680 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1681 {
1682 /* TODO:
1683 * - Magic packets should set bit 30 in power management driver register.
1684 * - Interesting packets should set bit 29 in power management driver register.
1685 */
1686 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1687 uint16_t rfd_status = 0xa000;
1688 static const uint8_t broadcast_macaddr[6] =
1689 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1690
1691 /* TODO: check multiple IA bit. */
1692 if (s->configuration[20] & BIT(6)) {
1693 missing("Multiple IA bit");
1694 return -1;
1695 }
1696
1697 if (s->configuration[8] & 0x80) {
1698 /* CSMA is disabled. */
1699 logout("%p received while CSMA is disabled\n", s);
1700 return -1;
1701 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1702 /* Short frame and configuration byte 7/0 (discard short receive) set:
1703 * Short frame is discarded */
1704 logout("%p received short frame (%zu byte)\n", s, size);
1705 s->statistics.rx_short_frame_errors++;
1706 //~ return -1;
1707 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1708 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1709 * Long frames are discarded. */
1710 logout("%p received long frame (%zu byte), ignored\n", s, size);
1711 return -1;
1712 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!!
1713 /* Frame matches individual address. */
1714 /* TODO: check configuration byte 15/4 (ignore U/L). */
1715 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1716 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1717 /* Broadcast frame. */
1718 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1719 rfd_status |= 0x0002;
1720 } else if (buf[0] & 0x01) {
1721 /* Multicast frame. */
1722 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1723 if (s->configuration[21] & BIT(3)) {
1724 /* Multicast all bit is set, receive all multicast frames. */
1725 } else {
1726 unsigned mcast_idx = compute_mcast_idx(buf);
1727 assert(mcast_idx < 64);
1728 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1729 /* Multicast frame is allowed in hash table. */
1730 } else if (s->configuration[15] & BIT(0)) {
1731 /* Promiscuous: receive all. */
1732 rfd_status |= 0x0004;
1733 } else {
1734 TRACE(RXTX, logout("%p multicast ignored\n", s));
1735 return -1;
1736 }
1737 }
1738 /* TODO: Next not for promiscuous mode? */
1739 rfd_status |= 0x0002;
1740 } else if (s->configuration[15] & BIT(0)) {
1741 /* Promiscuous: receive all. */
1742 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1743 rfd_status |= 0x0004;
1744 } else {
1745 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1746 nic_dump(buf, size)));
1747 return size;
1748 }
1749
1750 if (get_ru_state(s) != ru_ready) {
1751 /* No resources available. */
1752 logout("no resources, state=%u\n", get_ru_state(s));
1753 s->statistics.rx_resource_errors++;
1754 //~ assert(!"no resources");
1755 return -1;
1756 }
1757 //~ !!!
1758 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1759 eepro100_rx_t rx;
1760 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1761 offsetof(eepro100_rx_t, packet));
1762 uint16_t rfd_command = le16_to_cpu(rx.command);
1763 uint16_t rfd_size = le16_to_cpu(rx.size);
1764
1765 if (size > rfd_size) {
1766 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1767 "(%zu bytes); data truncated\n", rfd_size, size);
1768 size = rfd_size;
1769 }
1770 if (size < 64) {
1771 rfd_status |= 0x0080;
1772 }
1773 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1774 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1775 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1776 rfd_status);
1777 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1778 /* Early receive interrupt not supported. */
1779 //~ eepro100_er_interrupt(s);
1780 /* Receive CRC Transfer not supported. */
1781 if (s->configuration[18] & BIT(2)) {
1782 missing("Receive CRC Transfer");
1783 return -1;
1784 }
1785 /* TODO: check stripping enable bit. */
1786 //~ assert(!(s->configuration[17] & BIT(0)));
1787 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1788 offsetof(eepro100_rx_t, packet), buf, size);
1789 s->statistics.rx_good_frames++;
1790 eepro100_fr_interrupt(s);
1791 s->ru_offset = le32_to_cpu(rx.link);
1792 if (rfd_command & COMMAND_EL) {
1793 /* EL bit is set, so this was the last frame. */
1794 logout("receive: Running out of frames\n");
1795 set_ru_state(s, ru_suspended);
1796 }
1797 if (rfd_command & COMMAND_S) {
1798 /* S bit is set. */
1799 set_ru_state(s, ru_suspended);
1800 }
1801 return size;
1802 }
1803
1804 static const VMStateDescription vmstate_eepro100 = {
1805 .version_id = 3,
1806 .minimum_version_id = 2,
1807 .minimum_version_id_old = 2,
1808 .fields = (VMStateField []) {
1809 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1810 VMSTATE_UNUSED(32),
1811 VMSTATE_BUFFER(mult, EEPRO100State),
1812 VMSTATE_BUFFER(mem, EEPRO100State),
1813 /* Save all members of struct between scb_stat and mem. */
1814 VMSTATE_UINT8(scb_stat, EEPRO100State),
1815 VMSTATE_UINT8(int_stat, EEPRO100State),
1816 VMSTATE_UNUSED(3*4),
1817 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1818 VMSTATE_UNUSED(19*4),
1819 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1820 /* The eeprom should be saved and restored by its own routines. */
1821 VMSTATE_UINT32(device, EEPRO100State),
1822 /* TODO check device. */
1823 VMSTATE_UINT32(pointer, EEPRO100State),
1824 VMSTATE_UINT32(cu_base, EEPRO100State),
1825 VMSTATE_UINT32(cu_offset, EEPRO100State),
1826 VMSTATE_UINT32(ru_base, EEPRO100State),
1827 VMSTATE_UINT32(ru_offset, EEPRO100State),
1828 VMSTATE_UINT32(statsaddr, EEPRO100State),
1829 /* Save eepro100_stats_t statistics. */
1830 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1831 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1832 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1833 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1834 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1835 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1836 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1837 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1838 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1839 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1840 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1841 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1842 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1843 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1844 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1845 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1846 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1847 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1848 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1849 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1850 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1851 #if 0
1852 VMSTATE_UINT16(status, EEPRO100State),
1853 #endif
1854 /* Configuration bytes. */
1855 VMSTATE_BUFFER(configuration, EEPRO100State),
1856 VMSTATE_END_OF_LIST()
1857 }
1858 };
1859
1860 static void nic_cleanup(VLANClientState *nc)
1861 {
1862 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1863
1864 s->nic = NULL;
1865 }
1866
1867 static int pci_nic_uninit(PCIDevice *pci_dev)
1868 {
1869 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1870
1871 cpu_unregister_io_memory(s->mmio_index);
1872 vmstate_unregister(s->vmstate, s);
1873 eeprom93xx_free(s->eeprom);
1874 qemu_del_vlan_client(&s->nic->nc);
1875 return 0;
1876 }
1877
1878 static NetClientInfo net_eepro100_info = {
1879 .type = NET_CLIENT_TYPE_NIC,
1880 .size = sizeof(NICState),
1881 .can_receive = nic_can_receive,
1882 .receive = nic_receive,
1883 .cleanup = nic_cleanup,
1884 };
1885
1886 static int nic_init(PCIDevice *pci_dev, uint32_t device)
1887 {
1888 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1889
1890 TRACE(OTHER, logout("\n"));
1891
1892 s->device = device;
1893
1894 pci_reset(s);
1895
1896 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1897 * i82559 and later support 64 or 256 word EEPROM. */
1898 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1899
1900 /* Handler for memory-mapped I/O */
1901 s->mmio_index =
1902 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1903
1904 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1905 PCI_BASE_ADDRESS_SPACE_MEMORY |
1906 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1907 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1908 pci_map);
1909 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1910 pci_mmio_map);
1911
1912 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1913 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1914 assert(s->region[1] == 0);
1915
1916 nic_reset(s);
1917
1918 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1919 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1920
1921 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1922 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1923
1924 qemu_register_reset(nic_reset, s);
1925
1926 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1927 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1928 s->vmstate->name = s->nic->nc.model;
1929 vmstate_register(-1, s->vmstate, s);
1930
1931 return 0;
1932 }
1933
1934 static int pci_i82550_init(PCIDevice *pci_dev)
1935 {
1936 return nic_init(pci_dev, i82550);
1937 }
1938
1939 static int pci_i82551_init(PCIDevice *pci_dev)
1940 {
1941 return nic_init(pci_dev, i82551);
1942 }
1943
1944 static int pci_i82557a_init(PCIDevice *pci_dev)
1945 {
1946 return nic_init(pci_dev, i82557A);
1947 }
1948
1949 static int pci_i82557b_init(PCIDevice *pci_dev)
1950 {
1951 return nic_init(pci_dev, i82557B);
1952 }
1953
1954 static int pci_i82557c_init(PCIDevice *pci_dev)
1955 {
1956 return nic_init(pci_dev, i82557C);
1957 }
1958
1959 static int pci_i82558a_init(PCIDevice *pci_dev)
1960 {
1961 return nic_init(pci_dev, i82558A);
1962 }
1963
1964 static int pci_i82558b_init(PCIDevice *pci_dev)
1965 {
1966 return nic_init(pci_dev, i82558B);
1967 }
1968
1969 static int pci_i82559a_init(PCIDevice *pci_dev)
1970 {
1971 return nic_init(pci_dev, i82559A);
1972 }
1973
1974 static int pci_i82559b_init(PCIDevice *pci_dev)
1975 {
1976 return nic_init(pci_dev, i82559B);
1977 }
1978
1979 static int pci_i82559c_init(PCIDevice *pci_dev)
1980 {
1981 return nic_init(pci_dev, i82559C);
1982 }
1983
1984 static int pci_i82559er_init(PCIDevice *pci_dev)
1985 {
1986 return nic_init(pci_dev, i82559ER);
1987 }
1988
1989 static int pci_i82562_init(PCIDevice *pci_dev)
1990 {
1991 return nic_init(pci_dev, i82562);
1992 }
1993
1994 static PCIDeviceInfo eepro100_info[] = {
1995 {
1996 .qdev.name = "i82550",
1997 .qdev.desc = "Intel i82550 Ethernet",
1998 .qdev.size = sizeof(EEPRO100State),
1999 .init = pci_i82550_init,
2000 .exit = pci_nic_uninit,
2001 .romfile = "gpxe-eepro100-80861209.rom",
2002 .qdev.props = (Property[]) {
2003 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2004 DEFINE_PROP_END_OF_LIST(),
2005 },
2006 },{
2007 .qdev.name = "i82551",
2008 .qdev.desc = "Intel i82551 Ethernet",
2009 .qdev.size = sizeof(EEPRO100State),
2010 .init = pci_i82551_init,
2011 .exit = pci_nic_uninit,
2012 .romfile = "gpxe-eepro100-80861209.rom",
2013 .qdev.props = (Property[]) {
2014 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2015 DEFINE_PROP_END_OF_LIST(),
2016 },
2017 },{
2018 .qdev.name = "i82557a",
2019 .qdev.desc = "Intel i82557A Ethernet",
2020 .qdev.size = sizeof(EEPRO100State),
2021 .init = pci_i82557a_init,
2022 .exit = pci_nic_uninit,
2023 .romfile = "gpxe-eepro100-80861229.rom",
2024 .qdev.props = (Property[]) {
2025 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2026 DEFINE_PROP_END_OF_LIST(),
2027 },
2028 },{
2029 .qdev.name = "i82557b",
2030 .qdev.desc = "Intel i82557B Ethernet",
2031 .qdev.size = sizeof(EEPRO100State),
2032 .init = pci_i82557b_init,
2033 .exit = pci_nic_uninit,
2034 .romfile = "gpxe-eepro100-80861229.rom",
2035 .qdev.props = (Property[]) {
2036 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2037 DEFINE_PROP_END_OF_LIST(),
2038 },
2039 },{
2040 .qdev.name = "i82557c",
2041 .qdev.desc = "Intel i82557C Ethernet",
2042 .qdev.size = sizeof(EEPRO100State),
2043 .init = pci_i82557c_init,
2044 .exit = pci_nic_uninit,
2045 .romfile = "gpxe-eepro100-80861229.rom",
2046 .qdev.props = (Property[]) {
2047 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2048 DEFINE_PROP_END_OF_LIST(),
2049 },
2050 },{
2051 .qdev.name = "i82558a",
2052 .qdev.desc = "Intel i82558A Ethernet",
2053 .qdev.size = sizeof(EEPRO100State),
2054 .init = pci_i82558a_init,
2055 .exit = pci_nic_uninit,
2056 .romfile = "gpxe-eepro100-80861229.rom",
2057 .qdev.props = (Property[]) {
2058 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2059 DEFINE_PROP_END_OF_LIST(),
2060 },
2061 },{
2062 .qdev.name = "i82558b",
2063 .qdev.desc = "Intel i82558B Ethernet",
2064 .qdev.size = sizeof(EEPRO100State),
2065 .init = pci_i82558b_init,
2066 .exit = pci_nic_uninit,
2067 .romfile = "gpxe-eepro100-80861229.rom",
2068 .qdev.props = (Property[]) {
2069 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2070 DEFINE_PROP_END_OF_LIST(),
2071 },
2072 },{
2073 .qdev.name = "i82559a",
2074 .qdev.desc = "Intel i82559A Ethernet",
2075 .qdev.size = sizeof(EEPRO100State),
2076 .init = pci_i82559a_init,
2077 .exit = pci_nic_uninit,
2078 .romfile = "gpxe-eepro100-80861229.rom",
2079 .qdev.props = (Property[]) {
2080 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2081 DEFINE_PROP_END_OF_LIST(),
2082 },
2083 },{
2084 .qdev.name = "i82559b",
2085 .qdev.desc = "Intel i82559B Ethernet",
2086 .qdev.size = sizeof(EEPRO100State),
2087 .init = pci_i82559b_init,
2088 .exit = pci_nic_uninit,
2089 .romfile = "gpxe-eepro100-80861229.rom",
2090 .qdev.props = (Property[]) {
2091 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2092 DEFINE_PROP_END_OF_LIST(),
2093 },
2094 },{
2095 .qdev.name = "i82559c",
2096 .qdev.desc = "Intel i82559C Ethernet",
2097 .qdev.size = sizeof(EEPRO100State),
2098 .init = pci_i82559c_init,
2099 .exit = pci_nic_uninit,
2100 .romfile = "gpxe-eepro100-80861229.rom",
2101 .qdev.props = (Property[]) {
2102 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2103 DEFINE_PROP_END_OF_LIST(),
2104 },
2105 },{
2106 .qdev.name = "i82559er",
2107 .qdev.desc = "Intel i82559ER Ethernet",
2108 .qdev.size = sizeof(EEPRO100State),
2109 .init = pci_i82559er_init,
2110 .exit = pci_nic_uninit,
2111 .romfile = "gpxe-eepro100-80861209.rom",
2112 .qdev.props = (Property[]) {
2113 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2114 DEFINE_PROP_END_OF_LIST(),
2115 },
2116 },{
2117 .qdev.name = "i82562",
2118 .qdev.desc = "Intel i82562 Ethernet",
2119 .qdev.size = sizeof(EEPRO100State),
2120 .init = pci_i82562_init,
2121 .exit = pci_nic_uninit,
2122 .romfile = "gpxe-eepro100-80861209.rom",
2123 .qdev.props = (Property[]) {
2124 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2125 DEFINE_PROP_END_OF_LIST(),
2126 },
2127 },{
2128 /* end of list */
2129 }
2130 };
2131
2132 static void eepro100_register_devices(void)
2133 {
2134 pci_qdev_register_many(eepro100_info);
2135 }
2136
2137 device_init(eepro100_register_devices)
Qemu copy for testing