hw/esp.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "scsi.h"
  27 #include "esp.h"
  28 #include "trace.h"
  29
  30 /*
  31  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  32  * also produced as NCR89C100. See
  33  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  34  * and
  35  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  36  */
  37
  38 #define ESP_ERROR(fmt, ...)                                             \
  39     do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  40
  41 #define ESP_REGS 16
  42 #define TI_BUFSZ 16
  43
  44 typedef struct ESPState ESPState;
  45
  46 struct ESPState {
  47     SysBusDevice busdev;
  48     MemoryRegion iomem;
  49     uint8_t rregs[ESP_REGS];
  50     uint8_t wregs[ESP_REGS];
  51     qemu_irq irq;
  52     uint32_t it_shift;
  53     uint8_t chip_id;
  54     int32_t ti_size;
  55     uint32_t ti_rptr, ti_wptr;
  56     uint32_t status;
  57     uint32_t dma;
  58     uint8_t ti_buf[TI_BUFSZ];
  59     SCSIBus bus;
  60     SCSIDevice *current_dev;
  61     SCSIRequest *current_req;
  62     uint8_t cmdbuf[TI_BUFSZ];
  63     uint32_t cmdlen;
  64     uint32_t do_cmd;
  65
  66     /* The amount of data left in the current DMA transfer.  */
  67     uint32_t dma_left;
  68     /* The size of the current DMA transfer.  Zero if no transfer is in
  69        progress.  */
  70     uint32_t dma_counter;
  71     int dma_enabled;
  72
  73     uint32_t async_len;
  74     uint8_t *async_buf;
  75
  76     ESPDMAMemoryReadWriteFunc dma_memory_read;
  77     ESPDMAMemoryReadWriteFunc dma_memory_write;
  78     void *dma_opaque;
  79     void (*dma_cb)(ESPState *s);
  80 };
  81
  82 #define ESP_TCLO   0x0
  83 #define ESP_TCMID  0x1
  84 #define ESP_FIFO   0x2
  85 #define ESP_CMD    0x3
  86 #define ESP_RSTAT  0x4
  87 #define ESP_WBUSID 0x4
  88 #define ESP_RINTR  0x5
  89 #define ESP_WSEL   0x5
  90 #define ESP_RSEQ   0x6
  91 #define ESP_WSYNTP 0x6
  92 #define ESP_RFLAGS 0x7
  93 #define ESP_WSYNO  0x7
  94 #define ESP_CFG1   0x8
  95 #define ESP_RRES1  0x9
  96 #define ESP_WCCF   0x9
  97 #define ESP_RRES2  0xa
  98 #define ESP_WTEST  0xa
  99 #define ESP_CFG2   0xb
 100 #define ESP_CFG3   0xc
 101 #define ESP_RES3   0xd
 102 #define ESP_TCHI   0xe
 103 #define ESP_RES4   0xf
 104
 105 #define CMD_DMA 0x80
 106 #define CMD_CMD 0x7f
 107
 108 #define CMD_NOP      0x00
 109 #define CMD_FLUSH    0x01
 110 #define CMD_RESET    0x02
 111 #define CMD_BUSRESET 0x03
 112 #define CMD_TI       0x10
 113 #define CMD_ICCS     0x11
 114 #define CMD_MSGACC   0x12
 115 #define CMD_PAD      0x18
 116 #define CMD_SATN     0x1a
 117 #define CMD_RSTATN   0x1b
 118 #define CMD_SEL      0x41
 119 #define CMD_SELATN   0x42
 120 #define CMD_SELATNS  0x43
 121 #define CMD_ENSEL    0x44
 122 #define CMD_DISSEL   0x45
 123
 124 #define STAT_DO 0x00
 125 #define STAT_DI 0x01
 126 #define STAT_CD 0x02
 127 #define STAT_ST 0x03
 128 #define STAT_MO 0x06
 129 #define STAT_MI 0x07
 130 #define STAT_PIO_MASK 0x06
 131
 132 #define STAT_TC 0x10
 133 #define STAT_PE 0x20
 134 #define STAT_GE 0x40
 135 #define STAT_INT 0x80
 136
 137 #define BUSID_DID 0x07
 138
 139 #define INTR_FC 0x08
 140 #define INTR_BS 0x10
 141 #define INTR_DC 0x20
 142 #define INTR_RST 0x80
 143
 144 #define SEQ_0 0x0
 145 #define SEQ_CD 0x4
 146
 147 #define CFG1_RESREPT 0x40
 148
 149 #define TCHI_FAS100A 0x4
 150
 151 static void esp_raise_irq(ESPState *s)
 152 {
 153     if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
 154         s->rregs[ESP_RSTAT] |= STAT_INT;
 155         qemu_irq_raise(s->irq);
 156         trace_esp_raise_irq();
 157     }
 158 }
 159
 160 static void esp_lower_irq(ESPState *s)
 161 {
 162     if (s->rregs[ESP_RSTAT] & STAT_INT) {
 163         s->rregs[ESP_RSTAT] &= ~STAT_INT;
 164         qemu_irq_lower(s->irq);
 165         trace_esp_lower_irq();
 166     }
 167 }
 168
 169 static void esp_dma_enable(void *opaque, int irq, int level)
 170 {
 171     DeviceState *d = opaque;
 172     ESPState *s = container_of(d, ESPState, busdev.qdev);
 173
 174     if (level) {
 175         s->dma_enabled = 1;
 176         trace_esp_dma_enable();
 177         if (s->dma_cb) {
 178             s->dma_cb(s);
 179             s->dma_cb = NULL;
 180         }
 181     } else {
 182         trace_esp_dma_disable();
 183         s->dma_enabled = 0;
 184     }
 185 }
 186
 187 static void esp_request_cancelled(SCSIRequest *req)
 188 {
 189     ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
 190
 191     if (req == s->current_req) {
 192         scsi_req_unref(s->current_req);
 193         s->current_req = NULL;
 194         s->current_dev = NULL;
 195     }
 196 }
 197
 198 static uint32_t get_cmd(ESPState *s, uint8_t *buf)
 199 {
 200     uint32_t dmalen;
 201     int target;
 202
 203     target = s->wregs[ESP_WBUSID] & BUSID_DID;
 204     if (s->dma) {
 205         dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
 206         s->dma_memory_read(s->dma_opaque, buf, dmalen);
 207     } else {
 208         dmalen = s->ti_size;
 209         memcpy(buf, s->ti_buf, dmalen);
 210         buf[0] = buf[2] >> 5;
 211     }
 212     trace_esp_get_cmd(dmalen, target);
 213
 214     s->ti_size = 0;
 215     s->ti_rptr = 0;
 216     s->ti_wptr = 0;
 217
 218     if (s->current_req) {
 219         /* Started a new command before the old one finished.  Cancel it.  */
 220         scsi_req_cancel(s->current_req);
 221         s->async_len = 0;
 222     }
 223
 224     s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
 225     if (!s->current_dev) {
 226         // No such drive
 227         s->rregs[ESP_RSTAT] = 0;
 228         s->rregs[ESP_RINTR] = INTR_DC;
 229         s->rregs[ESP_RSEQ] = SEQ_0;
 230         esp_raise_irq(s);
 231         return 0;
 232     }
 233     return dmalen;
 234 }
 235
 236 static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
 237 {
 238     int32_t datalen;
 239     int lun;
 240     SCSIDevice *current_lun;
 241
 242     trace_esp_do_busid_cmd(busid);
 243     lun = busid & 7;
 244     current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
 245     s->current_req = scsi_req_new(current_lun, 0, lun, buf, NULL);
 246     datalen = scsi_req_enqueue(s->current_req);
 247     s->ti_size = datalen;
 248     if (datalen != 0) {
 249         s->rregs[ESP_RSTAT] = STAT_TC;
 250         s->dma_left = 0;
 251         s->dma_counter = 0;
 252         if (datalen > 0) {
 253             s->rregs[ESP_RSTAT] |= STAT_DI;
 254         } else {
 255             s->rregs[ESP_RSTAT] |= STAT_DO;
 256         }
 257         scsi_req_continue(s->current_req);
 258     }
 259     s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 260     s->rregs[ESP_RSEQ] = SEQ_CD;
 261     esp_raise_irq(s);
 262 }
 263
 264 static void do_cmd(ESPState *s, uint8_t *buf)
 265 {
 266     uint8_t busid = buf[0];
 267
 268     do_busid_cmd(s, &buf[1], busid);
 269 }
 270
 271 static void handle_satn(ESPState *s)
 272 {
 273     uint8_t buf[32];
 274     int len;
 275
 276     if (s->dma && !s->dma_enabled) {
 277         s->dma_cb = handle_satn;
 278         return;
 279     }
 280     len = get_cmd(s, buf);
 281     if (len)
 282         do_cmd(s, buf);
 283 }
 284
 285 static void handle_s_without_atn(ESPState *s)
 286 {
 287     uint8_t buf[32];
 288     int len;
 289
 290     if (s->dma && !s->dma_enabled) {
 291         s->dma_cb = handle_s_without_atn;
 292         return;
 293     }
 294     len = get_cmd(s, buf);
 295     if (len) {
 296         do_busid_cmd(s, buf, 0);
 297     }
 298 }
 299
 300 static void handle_satn_stop(ESPState *s)
 301 {
 302     if (s->dma && !s->dma_enabled) {
 303         s->dma_cb = handle_satn_stop;
 304         return;
 305     }
 306     s->cmdlen = get_cmd(s, s->cmdbuf);
 307     if (s->cmdlen) {
 308         trace_esp_handle_satn_stop(s->cmdlen);
 309         s->do_cmd = 1;
 310         s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 311         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 312         s->rregs[ESP_RSEQ] = SEQ_CD;
 313         esp_raise_irq(s);
 314     }
 315 }
 316
 317 static void write_response(ESPState *s)
 318 {
 319     trace_esp_write_response(s->status);
 320     s->ti_buf[0] = s->status;
 321     s->ti_buf[1] = 0;
 322     if (s->dma) {
 323         s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
 324         s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 325         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 326         s->rregs[ESP_RSEQ] = SEQ_CD;
 327     } else {
 328         s->ti_size = 2;
 329         s->ti_rptr = 0;
 330         s->ti_wptr = 0;
 331         s->rregs[ESP_RFLAGS] = 2;
 332     }
 333     esp_raise_irq(s);
 334 }
 335
 336 static void esp_dma_done(ESPState *s)
 337 {
 338     s->rregs[ESP_RSTAT] |= STAT_TC;
 339     s->rregs[ESP_RINTR] = INTR_BS;
 340     s->rregs[ESP_RSEQ] = 0;
 341     s->rregs[ESP_RFLAGS] = 0;
 342     s->rregs[ESP_TCLO] = 0;
 343     s->rregs[ESP_TCMID] = 0;
 344     esp_raise_irq(s);
 345 }
 346
 347 static void esp_do_dma(ESPState *s)
 348 {
 349     uint32_t len;
 350     int to_device;
 351
 352     to_device = (s->ti_size < 0);
 353     len = s->dma_left;
 354     if (s->do_cmd) {
 355         trace_esp_do_dma(s->cmdlen, len);
 356         s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
 357         s->ti_size = 0;
 358         s->cmdlen = 0;
 359         s->do_cmd = 0;
 360         do_cmd(s, s->cmdbuf);
 361         return;
 362     }
 363     if (s->async_len == 0) {
 364         /* Defer until data is available.  */
 365         return;
 366     }
 367     if (len > s->async_len) {
 368         len = s->async_len;
 369     }
 370     if (to_device) {
 371         s->dma_memory_read(s->dma_opaque, s->async_buf, len);
 372     } else {
 373         s->dma_memory_write(s->dma_opaque, s->async_buf, len);
 374     }
 375     s->dma_left -= len;
 376     s->async_buf += len;
 377     s->async_len -= len;
 378     if (to_device)
 379         s->ti_size += len;
 380     else
 381         s->ti_size -= len;
 382     if (s->async_len == 0) {
 383         scsi_req_continue(s->current_req);
 384         /* If there is still data to be read from the device then
 385            complete the DMA operation immediately.  Otherwise defer
 386            until the scsi layer has completed.  */
 387         if (to_device || s->dma_left != 0 || s->ti_size == 0) {
 388             return;
 389         }
 390     }
 391
 392     /* Partially filled a scsi buffer. Complete immediately.  */
 393     esp_dma_done(s);
 394 }
 395
 396 static void esp_command_complete(SCSIRequest *req, uint32_t status,
 397                                  size_t resid)
 398 {
 399     ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
 400
 401     trace_esp_command_complete();
 402     if (s->ti_size != 0) {
 403         trace_esp_command_complete_unexpected();
 404     }
 405     s->ti_size = 0;
 406     s->dma_left = 0;
 407     s->async_len = 0;
 408     if (status) {
 409         trace_esp_command_complete_fail();
 410     }
 411     s->status = status;
 412     s->rregs[ESP_RSTAT] = STAT_ST;
 413     esp_dma_done(s);
 414     if (s->current_req) {
 415         scsi_req_unref(s->current_req);
 416         s->current_req = NULL;
 417         s->current_dev = NULL;
 418     }
 419 }
 420
 421 static void esp_transfer_data(SCSIRequest *req, uint32_t len)
 422 {
 423     ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
 424
 425     trace_esp_transfer_data(s->dma_left, s->ti_size);
 426     s->async_len = len;
 427     s->async_buf = scsi_req_get_buf(req);
 428     if (s->dma_left) {
 429         esp_do_dma(s);
 430     } else if (s->dma_counter != 0 && s->ti_size <= 0) {
 431         /* If this was the last part of a DMA transfer then the
 432            completion interrupt is deferred to here.  */
 433         esp_dma_done(s);
 434     }
 435 }
 436
 437 static void handle_ti(ESPState *s)
 438 {
 439     uint32_t dmalen, minlen;
 440
 441     if (s->dma && !s->dma_enabled) {
 442         s->dma_cb = handle_ti;
 443         return;
 444     }
 445
 446     dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
 447     if (dmalen==0) {
 448       dmalen=0x10000;
 449     }
 450     s->dma_counter = dmalen;
 451
 452     if (s->do_cmd)
 453         minlen = (dmalen < 32) ? dmalen : 32;
 454     else if (s->ti_size < 0)
 455         minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
 456     else
 457         minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
 458     trace_esp_handle_ti(minlen);
 459     if (s->dma) {
 460         s->dma_left = minlen;
 461         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 462         esp_do_dma(s);
 463     } else if (s->do_cmd) {
 464         trace_esp_handle_ti_cmd(s->cmdlen);
 465         s->ti_size = 0;
 466         s->cmdlen = 0;
 467         s->do_cmd = 0;
 468         do_cmd(s, s->cmdbuf);
 469         return;
 470     }
 471 }
 472
 473 static void esp_hard_reset(DeviceState *d)
 474 {
 475     ESPState *s = container_of(d, ESPState, busdev.qdev);
 476
 477     memset(s->rregs, 0, ESP_REGS);
 478     memset(s->wregs, 0, ESP_REGS);
 479     s->rregs[ESP_TCHI] = s->chip_id;
 480     s->ti_size = 0;
 481     s->ti_rptr = 0;
 482     s->ti_wptr = 0;
 483     s->dma = 0;
 484     s->do_cmd = 0;
 485     s->dma_cb = NULL;
 486
 487     s->rregs[ESP_CFG1] = 7;
 488 }
 489
 490 static void esp_soft_reset(DeviceState *d)
 491 {
 492     ESPState *s = container_of(d, ESPState, busdev.qdev);
 493
 494     qemu_irq_lower(s->irq);
 495     esp_hard_reset(d);
 496 }
 497
 498 static void parent_esp_reset(void *opaque, int irq, int level)
 499 {
 500     if (level) {
 501         esp_soft_reset(opaque);
 502     }
 503 }
 504
 505 static void esp_gpio_demux(void *opaque, int irq, int level)
 506 {
 507     switch (irq) {
 508     case 0:
 509         parent_esp_reset(opaque, irq, level);
 510         break;
 511     case 1:
 512         esp_dma_enable(opaque, irq, level);
 513         break;
 514     }
 515 }
 516
 517 static uint64_t esp_mem_read(void *opaque, target_phys_addr_t addr,
 518                              unsigned size)
 519 {
 520     ESPState *s = opaque;
 521     uint32_t saddr, old_val;
 522
 523     saddr = addr >> s->it_shift;
 524     trace_esp_mem_readb(saddr, s->rregs[saddr]);
 525     switch (saddr) {
 526     case ESP_FIFO:
 527         if (s->ti_size > 0) {
 528             s->ti_size--;
 529             if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
 530                 /* Data out.  */
 531                 ESP_ERROR("PIO data read not implemented\n");
 532                 s->rregs[ESP_FIFO] = 0;
 533             } else {
 534                 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
 535             }
 536             esp_raise_irq(s);
 537         }
 538         if (s->ti_size == 0) {
 539             s->ti_rptr = 0;
 540             s->ti_wptr = 0;
 541         }
 542         break;
 543     case ESP_RINTR:
 544         /* Clear sequence step, interrupt register and all status bits
 545            except TC */
 546         old_val = s->rregs[ESP_RINTR];
 547         s->rregs[ESP_RINTR] = 0;
 548         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 549         s->rregs[ESP_RSEQ] = SEQ_CD;
 550         esp_lower_irq(s);
 551
 552         return old_val;
 553     default:
 554         break;
 555     }
 556     return s->rregs[saddr];
 557 }
 558
 559 static void esp_mem_write(void *opaque, target_phys_addr_t addr,
 560                           uint64_t val, unsigned size)
 561 {
 562     ESPState *s = opaque;
 563     uint32_t saddr;
 564
 565     saddr = addr >> s->it_shift;
 566     trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
 567     switch (saddr) {
 568     case ESP_TCLO:
 569     case ESP_TCMID:
 570         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 571         break;
 572     case ESP_FIFO:
 573         if (s->do_cmd) {
 574             s->cmdbuf[s->cmdlen++] = val & 0xff;
 575         } else if (s->ti_size == TI_BUFSZ - 1) {
 576             ESP_ERROR("fifo overrun\n");
 577         } else {
 578             s->ti_size++;
 579             s->ti_buf[s->ti_wptr++] = val & 0xff;
 580         }
 581         break;
 582     case ESP_CMD:
 583         s->rregs[saddr] = val;
 584         if (val & CMD_DMA) {
 585             s->dma = 1;
 586             /* Reload DMA counter.  */
 587             s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
 588             s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
 589         } else {
 590             s->dma = 0;
 591         }
 592         switch(val & CMD_CMD) {
 593         case CMD_NOP:
 594             trace_esp_mem_writeb_cmd_nop(val);
 595             break;
 596         case CMD_FLUSH:
 597             trace_esp_mem_writeb_cmd_flush(val);
 598             //s->ti_size = 0;
 599             s->rregs[ESP_RINTR] = INTR_FC;
 600             s->rregs[ESP_RSEQ] = 0;
 601             s->rregs[ESP_RFLAGS] = 0;
 602             break;
 603         case CMD_RESET:
 604             trace_esp_mem_writeb_cmd_reset(val);
 605             esp_soft_reset(&s->busdev.qdev);
 606             break;
 607         case CMD_BUSRESET:
 608             trace_esp_mem_writeb_cmd_bus_reset(val);
 609             s->rregs[ESP_RINTR] = INTR_RST;
 610             if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
 611                 esp_raise_irq(s);
 612             }
 613             break;
 614         case CMD_TI:
 615             handle_ti(s);
 616             break;
 617         case CMD_ICCS:
 618             trace_esp_mem_writeb_cmd_iccs(val);
 619             write_response(s);
 620             s->rregs[ESP_RINTR] = INTR_FC;
 621             s->rregs[ESP_RSTAT] |= STAT_MI;
 622             break;
 623         case CMD_MSGACC:
 624             trace_esp_mem_writeb_cmd_msgacc(val);
 625             s->rregs[ESP_RINTR] = INTR_DC;
 626             s->rregs[ESP_RSEQ] = 0;
 627             s->rregs[ESP_RFLAGS] = 0;
 628             esp_raise_irq(s);
 629             break;
 630         case CMD_PAD:
 631             trace_esp_mem_writeb_cmd_pad(val);
 632             s->rregs[ESP_RSTAT] = STAT_TC;
 633             s->rregs[ESP_RINTR] = INTR_FC;
 634             s->rregs[ESP_RSEQ] = 0;
 635             break;
 636         case CMD_SATN:
 637             trace_esp_mem_writeb_cmd_satn(val);
 638             break;
 639         case CMD_RSTATN:
 640             trace_esp_mem_writeb_cmd_rstatn(val);
 641             break;
 642         case CMD_SEL:
 643             trace_esp_mem_writeb_cmd_sel(val);
 644             handle_s_without_atn(s);
 645             break;
 646         case CMD_SELATN:
 647             trace_esp_mem_writeb_cmd_selatn(val);
 648             handle_satn(s);
 649             break;
 650         case CMD_SELATNS:
 651             trace_esp_mem_writeb_cmd_selatns(val);
 652             handle_satn_stop(s);
 653             break;
 654         case CMD_ENSEL:
 655             trace_esp_mem_writeb_cmd_ensel(val);
 656             s->rregs[ESP_RINTR] = 0;
 657             break;
 658         case CMD_DISSEL:
 659             trace_esp_mem_writeb_cmd_dissel(val);
 660             s->rregs[ESP_RINTR] = 0;
 661             esp_raise_irq(s);
 662             break;
 663         default:
 664             ESP_ERROR("Unhandled ESP command (%2.2x)\n", (unsigned)val);
 665             break;
 666         }
 667         break;
 668     case ESP_WBUSID ... ESP_WSYNO:
 669         break;
 670     case ESP_CFG1:
 671         s->rregs[saddr] = val;
 672         break;
 673     case ESP_WCCF ... ESP_WTEST:
 674         break;
 675     case ESP_CFG2 ... ESP_RES4:
 676         s->rregs[saddr] = val;
 677         break;
 678     default:
 679         ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", (unsigned)val, saddr);
 680         return;
 681     }
 682     s->wregs[saddr] = val;
 683 }
 684
 685 static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
 686                             unsigned size, bool is_write)
 687 {
 688     return (size == 1) || (is_write && size == 4);
 689 }
 690
 691 static const MemoryRegionOps esp_mem_ops = {
 692     .read = esp_mem_read,
 693     .write = esp_mem_write,
 694     .endianness = DEVICE_NATIVE_ENDIAN,
 695     .valid.accepts = esp_mem_accepts,
 696 };
 697
 698 static const VMStateDescription vmstate_esp = {
 699     .name ="esp",
 700     .version_id = 3,
 701     .minimum_version_id = 3,
 702     .minimum_version_id_old = 3,
 703     .fields      = (VMStateField []) {
 704         VMSTATE_BUFFER(rregs, ESPState),
 705         VMSTATE_BUFFER(wregs, ESPState),
 706         VMSTATE_INT32(ti_size, ESPState),
 707         VMSTATE_UINT32(ti_rptr, ESPState),
 708         VMSTATE_UINT32(ti_wptr, ESPState),
 709         VMSTATE_BUFFER(ti_buf, ESPState),
 710         VMSTATE_UINT32(status, ESPState),
 711         VMSTATE_UINT32(dma, ESPState),
 712         VMSTATE_BUFFER(cmdbuf, ESPState),
 713         VMSTATE_UINT32(cmdlen, ESPState),
 714         VMSTATE_UINT32(do_cmd, ESPState),
 715         VMSTATE_UINT32(dma_left, ESPState),
 716         VMSTATE_END_OF_LIST()
 717     }
 718 };
 719
 720 void esp_init(target_phys_addr_t espaddr, int it_shift,
 721               ESPDMAMemoryReadWriteFunc dma_memory_read,
 722               ESPDMAMemoryReadWriteFunc dma_memory_write,
 723               void *dma_opaque, qemu_irq irq, qemu_irq *reset,
 724               qemu_irq *dma_enable)
 725 {
 726     DeviceState *dev;
 727     SysBusDevice *s;
 728     ESPState *esp;
 729
 730     dev = qdev_create(NULL, "esp");
 731     esp = DO_UPCAST(ESPState, busdev.qdev, dev);
 732     esp->dma_memory_read = dma_memory_read;
 733     esp->dma_memory_write = dma_memory_write;
 734     esp->dma_opaque = dma_opaque;
 735     esp->it_shift = it_shift;
 736     /* XXX for now until rc4030 has been changed to use DMA enable signal */
 737     esp->dma_enabled = 1;
 738     qdev_init_nofail(dev);
 739     s = sysbus_from_qdev(dev);
 740     sysbus_connect_irq(s, 0, irq);
 741     sysbus_mmio_map(s, 0, espaddr);
 742     *reset = qdev_get_gpio_in(dev, 0);
 743     *dma_enable = qdev_get_gpio_in(dev, 1);
 744 }
 745
 746 static const struct SCSIBusInfo esp_scsi_info = {
 747     .tcq = false,
 748     .max_target = ESP_MAX_DEVS,
 749     .max_lun = 7,
 750
 751     .transfer_data = esp_transfer_data,
 752     .complete = esp_command_complete,
 753     .cancel = esp_request_cancelled
 754 };
 755
 756 static int esp_init1(SysBusDevice *dev)
 757 {
 758     ESPState *s = FROM_SYSBUS(ESPState, dev);
 759
 760     sysbus_init_irq(dev, &s->irq);
 761     assert(s->it_shift != -1);
 762
 763     s->chip_id = TCHI_FAS100A;
 764     memory_region_init_io(&s->iomem, &esp_mem_ops, s,
 765                           "esp", ESP_REGS << s->it_shift);
 766     sysbus_init_mmio(dev, &s->iomem);
 767
 768     qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
 769
 770     scsi_bus_new(&s->bus, &dev->qdev, &esp_scsi_info);
 771     return scsi_bus_legacy_handle_cmdline(&s->bus);
 772 }
 773
 774 static Property esp_properties[] = {
 775     {.name = NULL},
 776 };
 777
 778 static void esp_class_init(ObjectClass *klass, void *data)
 779 {
 780     DeviceClass *dc = DEVICE_CLASS(klass);
 781     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 782
 783     k->init = esp_init1;
 784     dc->reset = esp_hard_reset;
 785     dc->vmsd = &vmstate_esp;
 786     dc->props = esp_properties;
 787 }
 788
 789 static TypeInfo esp_info = {
 790     .name          = "esp",
 791     .parent        = TYPE_SYS_BUS_DEVICE,
 792     .instance_size = sizeof(ESPState),
 793     .class_init    = esp_class_init,
 794 };
 795
 796 static void esp_register_types(void)
 797 {
 798     type_register_static(&esp_info);
 799 }
 800
 801 type_init(esp_register_types)