hw/esp.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "scsi.h"
  27 #include "esp.h"
  28 #include "trace.h"
  29
  30 /*
  31  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  32  * also produced as NCR89C100. See
  33  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  34  * and
  35  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  36  */
  37
  38 #define ESP_ERROR(fmt, ...)                                             \
  39     do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  40
  41 #define ESP_REGS 16
  42 #define TI_BUFSZ 16
  43
  44 typedef struct ESPState ESPState;
  45
  46 struct ESPState {
  47     SysBusDevice busdev;
  48     MemoryRegion iomem;
  49     uint8_t rregs[ESP_REGS];
  50     uint8_t wregs[ESP_REGS];
  51     qemu_irq irq;
  52     uint32_t it_shift;
  53     int32_t ti_size;
  54     uint32_t ti_rptr, ti_wptr;
  55     uint32_t status;
  56     uint32_t dma;
  57     uint8_t ti_buf[TI_BUFSZ];
  58     SCSIBus bus;
  59     SCSIDevice *current_dev;
  60     SCSIRequest *current_req;
  61     uint8_t cmdbuf[TI_BUFSZ];
  62     uint32_t cmdlen;
  63     uint32_t do_cmd;
  64
  65     /* The amount of data left in the current DMA transfer.  */
  66     uint32_t dma_left;
  67     /* The size of the current DMA transfer.  Zero if no transfer is in
  68        progress.  */
  69     uint32_t dma_counter;
  70     int dma_enabled;
  71
  72     uint32_t async_len;
  73     uint8_t *async_buf;
  74
  75     ESPDMAMemoryReadWriteFunc dma_memory_read;
  76     ESPDMAMemoryReadWriteFunc dma_memory_write;
  77     void *dma_opaque;
  78     void (*dma_cb)(ESPState *s);
  79 };
  80
  81 #define ESP_TCLO   0x0
  82 #define ESP_TCMID  0x1
  83 #define ESP_FIFO   0x2
  84 #define ESP_CMD    0x3
  85 #define ESP_RSTAT  0x4
  86 #define ESP_WBUSID 0x4
  87 #define ESP_RINTR  0x5
  88 #define ESP_WSEL   0x5
  89 #define ESP_RSEQ   0x6
  90 #define ESP_WSYNTP 0x6
  91 #define ESP_RFLAGS 0x7
  92 #define ESP_WSYNO  0x7
  93 #define ESP_CFG1   0x8
  94 #define ESP_RRES1  0x9
  95 #define ESP_WCCF   0x9
  96 #define ESP_RRES2  0xa
  97 #define ESP_WTEST  0xa
  98 #define ESP_CFG2   0xb
  99 #define ESP_CFG3   0xc
 100 #define ESP_RES3   0xd
 101 #define ESP_TCHI   0xe
 102 #define ESP_RES4   0xf
 103
 104 #define CMD_DMA 0x80
 105 #define CMD_CMD 0x7f
 106
 107 #define CMD_NOP      0x00
 108 #define CMD_FLUSH    0x01
 109 #define CMD_RESET    0x02
 110 #define CMD_BUSRESET 0x03
 111 #define CMD_TI       0x10
 112 #define CMD_ICCS     0x11
 113 #define CMD_MSGACC   0x12
 114 #define CMD_PAD      0x18
 115 #define CMD_SATN     0x1a
 116 #define CMD_SEL      0x41
 117 #define CMD_SELATN   0x42
 118 #define CMD_SELATNS  0x43
 119 #define CMD_ENSEL    0x44
 120 #define CMD_DISSEL   0x45
 121
 122 #define STAT_DO 0x00
 123 #define STAT_DI 0x01
 124 #define STAT_CD 0x02
 125 #define STAT_ST 0x03
 126 #define STAT_MO 0x06
 127 #define STAT_MI 0x07
 128 #define STAT_PIO_MASK 0x06
 129
 130 #define STAT_TC 0x10
 131 #define STAT_PE 0x20
 132 #define STAT_GE 0x40
 133 #define STAT_INT 0x80
 134
 135 #define BUSID_DID 0x07
 136
 137 #define INTR_FC 0x08
 138 #define INTR_BS 0x10
 139 #define INTR_DC 0x20
 140 #define INTR_RST 0x80
 141
 142 #define SEQ_0 0x0
 143 #define SEQ_CD 0x4
 144
 145 #define CFG1_RESREPT 0x40
 146
 147 #define TCHI_FAS100A 0x4
 148
 149 static void esp_raise_irq(ESPState *s)
 150 {
 151     if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
 152         s->rregs[ESP_RSTAT] |= STAT_INT;
 153         qemu_irq_raise(s->irq);
 154         trace_esp_raise_irq();
 155     }
 156 }
 157
 158 static void esp_lower_irq(ESPState *s)
 159 {
 160     if (s->rregs[ESP_RSTAT] & STAT_INT) {
 161         s->rregs[ESP_RSTAT] &= ~STAT_INT;
 162         qemu_irq_lower(s->irq);
 163         trace_esp_lower_irq();
 164     }
 165 }
 166
 167 static void esp_dma_enable(void *opaque, int irq, int level)
 168 {
 169     DeviceState *d = opaque;
 170     ESPState *s = container_of(d, ESPState, busdev.qdev);
 171
 172     if (level) {
 173         s->dma_enabled = 1;
 174         trace_esp_dma_enable();
 175         if (s->dma_cb) {
 176             s->dma_cb(s);
 177             s->dma_cb = NULL;
 178         }
 179     } else {
 180         trace_esp_dma_disable();
 181         s->dma_enabled = 0;
 182     }
 183 }
 184
 185 static void esp_request_cancelled(SCSIRequest *req)
 186 {
 187     ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
 188
 189     if (req == s->current_req) {
 190         scsi_req_unref(s->current_req);
 191         s->current_req = NULL;
 192         s->current_dev = NULL;
 193     }
 194 }
 195
 196 static uint32_t get_cmd(ESPState *s, uint8_t *buf)
 197 {
 198     uint32_t dmalen;
 199     int target;
 200
 201     target = s->wregs[ESP_WBUSID] & BUSID_DID;
 202     if (s->dma) {
 203         dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
 204         s->dma_memory_read(s->dma_opaque, buf, dmalen);
 205     } else {
 206         dmalen = s->ti_size;
 207         memcpy(buf, s->ti_buf, dmalen);
 208         buf[0] = buf[2] >> 5;
 209     }
 210     trace_esp_get_cmd(dmalen, target);
 211
 212     s->ti_size = 0;
 213     s->ti_rptr = 0;
 214     s->ti_wptr = 0;
 215
 216     if (s->current_req) {
 217         /* Started a new command before the old one finished.  Cancel it.  */
 218         scsi_req_cancel(s->current_req);
 219         s->async_len = 0;
 220     }
 221
 222     s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
 223     if (!s->current_dev) {
 224         // No such drive
 225         s->rregs[ESP_RSTAT] = 0;
 226         s->rregs[ESP_RINTR] = INTR_DC;
 227         s->rregs[ESP_RSEQ] = SEQ_0;
 228         esp_raise_irq(s);
 229         return 0;
 230     }
 231     return dmalen;
 232 }
 233
 234 static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
 235 {
 236     int32_t datalen;
 237     int lun;
 238     SCSIDevice *current_lun;
 239
 240     trace_esp_do_busid_cmd(busid);
 241     lun = busid & 7;
 242     current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
 243     s->current_req = scsi_req_new(current_lun, 0, lun, buf, NULL);
 244     datalen = scsi_req_enqueue(s->current_req);
 245     s->ti_size = datalen;
 246     if (datalen != 0) {
 247         s->rregs[ESP_RSTAT] = STAT_TC;
 248         s->dma_left = 0;
 249         s->dma_counter = 0;
 250         if (datalen > 0) {
 251             s->rregs[ESP_RSTAT] |= STAT_DI;
 252         } else {
 253             s->rregs[ESP_RSTAT] |= STAT_DO;
 254         }
 255         scsi_req_continue(s->current_req);
 256     }
 257     s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 258     s->rregs[ESP_RSEQ] = SEQ_CD;
 259     esp_raise_irq(s);
 260 }
 261
 262 static void do_cmd(ESPState *s, uint8_t *buf)
 263 {
 264     uint8_t busid = buf[0];
 265
 266     do_busid_cmd(s, &buf[1], busid);
 267 }
 268
 269 static void handle_satn(ESPState *s)
 270 {
 271     uint8_t buf[32];
 272     int len;
 273
 274     if (s->dma && !s->dma_enabled) {
 275         s->dma_cb = handle_satn;
 276         return;
 277     }
 278     len = get_cmd(s, buf);
 279     if (len)
 280         do_cmd(s, buf);
 281 }
 282
 283 static void handle_s_without_atn(ESPState *s)
 284 {
 285     uint8_t buf[32];
 286     int len;
 287
 288     if (s->dma && !s->dma_enabled) {
 289         s->dma_cb = handle_s_without_atn;
 290         return;
 291     }
 292     len = get_cmd(s, buf);
 293     if (len) {
 294         do_busid_cmd(s, buf, 0);
 295     }
 296 }
 297
 298 static void handle_satn_stop(ESPState *s)
 299 {
 300     if (s->dma && !s->dma_enabled) {
 301         s->dma_cb = handle_satn_stop;
 302         return;
 303     }
 304     s->cmdlen = get_cmd(s, s->cmdbuf);
 305     if (s->cmdlen) {
 306         trace_esp_handle_satn_stop(s->cmdlen);
 307         s->do_cmd = 1;
 308         s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 309         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 310         s->rregs[ESP_RSEQ] = SEQ_CD;
 311         esp_raise_irq(s);
 312     }
 313 }
 314
 315 static void write_response(ESPState *s)
 316 {
 317     trace_esp_write_response(s->status);
 318     s->ti_buf[0] = s->status;
 319     s->ti_buf[1] = 0;
 320     if (s->dma) {
 321         s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
 322         s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 323         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 324         s->rregs[ESP_RSEQ] = SEQ_CD;
 325     } else {
 326         s->ti_size = 2;
 327         s->ti_rptr = 0;
 328         s->ti_wptr = 0;
 329         s->rregs[ESP_RFLAGS] = 2;
 330     }
 331     esp_raise_irq(s);
 332 }
 333
 334 static void esp_dma_done(ESPState *s)
 335 {
 336     s->rregs[ESP_RSTAT] |= STAT_TC;
 337     s->rregs[ESP_RINTR] = INTR_BS;
 338     s->rregs[ESP_RSEQ] = 0;
 339     s->rregs[ESP_RFLAGS] = 0;
 340     s->rregs[ESP_TCLO] = 0;
 341     s->rregs[ESP_TCMID] = 0;
 342     esp_raise_irq(s);
 343 }
 344
 345 static void esp_do_dma(ESPState *s)
 346 {
 347     uint32_t len;
 348     int to_device;
 349
 350     to_device = (s->ti_size < 0);
 351     len = s->dma_left;
 352     if (s->do_cmd) {
 353         trace_esp_do_dma(s->cmdlen, len);
 354         s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
 355         s->ti_size = 0;
 356         s->cmdlen = 0;
 357         s->do_cmd = 0;
 358         do_cmd(s, s->cmdbuf);
 359         return;
 360     }
 361     if (s->async_len == 0) {
 362         /* Defer until data is available.  */
 363         return;
 364     }
 365     if (len > s->async_len) {
 366         len = s->async_len;
 367     }
 368     if (to_device) {
 369         s->dma_memory_read(s->dma_opaque, s->async_buf, len);
 370     } else {
 371         s->dma_memory_write(s->dma_opaque, s->async_buf, len);
 372     }
 373     s->dma_left -= len;
 374     s->async_buf += len;
 375     s->async_len -= len;
 376     if (to_device)
 377         s->ti_size += len;
 378     else
 379         s->ti_size -= len;
 380     if (s->async_len == 0) {
 381         scsi_req_continue(s->current_req);
 382         /* If there is still data to be read from the device then
 383            complete the DMA operation immediately.  Otherwise defer
 384            until the scsi layer has completed.  */
 385         if (to_device || s->dma_left != 0 || s->ti_size == 0) {
 386             return;
 387         }
 388     }
 389
 390     /* Partially filled a scsi buffer. Complete immediately.  */
 391     esp_dma_done(s);
 392 }
 393
 394 static void esp_command_complete(SCSIRequest *req, uint32_t status,
 395                                  size_t resid)
 396 {
 397     ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
 398
 399     trace_esp_command_complete();
 400     if (s->ti_size != 0) {
 401         trace_esp_command_complete_unexpected();
 402     }
 403     s->ti_size = 0;
 404     s->dma_left = 0;
 405     s->async_len = 0;
 406     if (status) {
 407         trace_esp_command_complete_fail();
 408     }
 409     s->status = status;
 410     s->rregs[ESP_RSTAT] = STAT_ST;
 411     esp_dma_done(s);
 412     if (s->current_req) {
 413         scsi_req_unref(s->current_req);
 414         s->current_req = NULL;
 415         s->current_dev = NULL;
 416     }
 417 }
 418
 419 static void esp_transfer_data(SCSIRequest *req, uint32_t len)
 420 {
 421     ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
 422
 423     trace_esp_transfer_data(s->dma_left, s->ti_size);
 424     s->async_len = len;
 425     s->async_buf = scsi_req_get_buf(req);
 426     if (s->dma_left) {
 427         esp_do_dma(s);
 428     } else if (s->dma_counter != 0 && s->ti_size <= 0) {
 429         /* If this was the last part of a DMA transfer then the
 430            completion interrupt is deferred to here.  */
 431         esp_dma_done(s);
 432     }
 433 }
 434
 435 static void handle_ti(ESPState *s)
 436 {
 437     uint32_t dmalen, minlen;
 438
 439     if (s->dma && !s->dma_enabled) {
 440         s->dma_cb = handle_ti;
 441         return;
 442     }
 443
 444     dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
 445     if (dmalen==0) {
 446       dmalen=0x10000;
 447     }
 448     s->dma_counter = dmalen;
 449
 450     if (s->do_cmd)
 451         minlen = (dmalen < 32) ? dmalen : 32;
 452     else if (s->ti_size < 0)
 453         minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
 454     else
 455         minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
 456     trace_esp_handle_ti(minlen);
 457     if (s->dma) {
 458         s->dma_left = minlen;
 459         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 460         esp_do_dma(s);
 461     } else if (s->do_cmd) {
 462         trace_esp_handle_ti_cmd(s->cmdlen);
 463         s->ti_size = 0;
 464         s->cmdlen = 0;
 465         s->do_cmd = 0;
 466         do_cmd(s, s->cmdbuf);
 467         return;
 468     }
 469 }
 470
 471 static void esp_hard_reset(DeviceState *d)
 472 {
 473     ESPState *s = container_of(d, ESPState, busdev.qdev);
 474
 475     memset(s->rregs, 0, ESP_REGS);
 476     memset(s->wregs, 0, ESP_REGS);
 477     s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
 478     s->ti_size = 0;
 479     s->ti_rptr = 0;
 480     s->ti_wptr = 0;
 481     s->dma = 0;
 482     s->do_cmd = 0;
 483     s->dma_cb = NULL;
 484
 485     s->rregs[ESP_CFG1] = 7;
 486 }
 487
 488 static void esp_soft_reset(DeviceState *d)
 489 {
 490     ESPState *s = container_of(d, ESPState, busdev.qdev);
 491
 492     qemu_irq_lower(s->irq);
 493     esp_hard_reset(d);
 494 }
 495
 496 static void parent_esp_reset(void *opaque, int irq, int level)
 497 {
 498     if (level) {
 499         esp_soft_reset(opaque);
 500     }
 501 }
 502
 503 static void esp_gpio_demux(void *opaque, int irq, int level)
 504 {
 505     switch (irq) {
 506     case 0:
 507         parent_esp_reset(opaque, irq, level);
 508         break;
 509     case 1:
 510         esp_dma_enable(opaque, irq, level);
 511         break;
 512     }
 513 }
 514
 515 static uint64_t esp_mem_read(void *opaque, target_phys_addr_t addr,
 516                              unsigned size)
 517 {
 518     ESPState *s = opaque;
 519     uint32_t saddr, old_val;
 520
 521     saddr = addr >> s->it_shift;
 522     trace_esp_mem_readb(saddr, s->rregs[saddr]);
 523     switch (saddr) {
 524     case ESP_FIFO:
 525         if (s->ti_size > 0) {
 526             s->ti_size--;
 527             if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
 528                 /* Data out.  */
 529                 ESP_ERROR("PIO data read not implemented\n");
 530                 s->rregs[ESP_FIFO] = 0;
 531             } else {
 532                 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
 533             }
 534             esp_raise_irq(s);
 535         }
 536         if (s->ti_size == 0) {
 537             s->ti_rptr = 0;
 538             s->ti_wptr = 0;
 539         }
 540         break;
 541     case ESP_RINTR:
 542         /* Clear sequence step, interrupt register and all status bits
 543            except TC */
 544         old_val = s->rregs[ESP_RINTR];
 545         s->rregs[ESP_RINTR] = 0;
 546         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 547         s->rregs[ESP_RSEQ] = SEQ_CD;
 548         esp_lower_irq(s);
 549
 550         return old_val;
 551     default:
 552         break;
 553     }
 554     return s->rregs[saddr];
 555 }
 556
 557 static void esp_mem_write(void *opaque, target_phys_addr_t addr,
 558                           uint64_t val, unsigned size)
 559 {
 560     ESPState *s = opaque;
 561     uint32_t saddr;
 562
 563     saddr = addr >> s->it_shift;
 564     trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
 565     switch (saddr) {
 566     case ESP_TCLO:
 567     case ESP_TCMID:
 568         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 569         break;
 570     case ESP_FIFO:
 571         if (s->do_cmd) {
 572             s->cmdbuf[s->cmdlen++] = val & 0xff;
 573         } else if (s->ti_size == TI_BUFSZ - 1) {
 574             ESP_ERROR("fifo overrun\n");
 575         } else {
 576             s->ti_size++;
 577             s->ti_buf[s->ti_wptr++] = val & 0xff;
 578         }
 579         break;
 580     case ESP_CMD:
 581         s->rregs[saddr] = val;
 582         if (val & CMD_DMA) {
 583             s->dma = 1;
 584             /* Reload DMA counter.  */
 585             s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
 586             s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
 587         } else {
 588             s->dma = 0;
 589         }
 590         switch(val & CMD_CMD) {
 591         case CMD_NOP:
 592             trace_esp_mem_writeb_cmd_nop(val);
 593             break;
 594         case CMD_FLUSH:
 595             trace_esp_mem_writeb_cmd_flush(val);
 596             //s->ti_size = 0;
 597             s->rregs[ESP_RINTR] = INTR_FC;
 598             s->rregs[ESP_RSEQ] = 0;
 599             s->rregs[ESP_RFLAGS] = 0;
 600             break;
 601         case CMD_RESET:
 602             trace_esp_mem_writeb_cmd_reset(val);
 603             esp_soft_reset(&s->busdev.qdev);
 604             break;
 605         case CMD_BUSRESET:
 606             trace_esp_mem_writeb_cmd_bus_reset(val);
 607             s->rregs[ESP_RINTR] = INTR_RST;
 608             if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
 609                 esp_raise_irq(s);
 610             }
 611             break;
 612         case CMD_TI:
 613             handle_ti(s);
 614             break;
 615         case CMD_ICCS:
 616             trace_esp_mem_writeb_cmd_iccs(val);
 617             write_response(s);
 618             s->rregs[ESP_RINTR] = INTR_FC;
 619             s->rregs[ESP_RSTAT] |= STAT_MI;
 620             break;
 621         case CMD_MSGACC:
 622             trace_esp_mem_writeb_cmd_msgacc(val);
 623             s->rregs[ESP_RINTR] = INTR_DC;
 624             s->rregs[ESP_RSEQ] = 0;
 625             s->rregs[ESP_RFLAGS] = 0;
 626             esp_raise_irq(s);
 627             break;
 628         case CMD_PAD:
 629             trace_esp_mem_writeb_cmd_pad(val);
 630             s->rregs[ESP_RSTAT] = STAT_TC;
 631             s->rregs[ESP_RINTR] = INTR_FC;
 632             s->rregs[ESP_RSEQ] = 0;
 633             break;
 634         case CMD_SATN:
 635             trace_esp_mem_writeb_cmd_satn(val);
 636             break;
 637         case CMD_SEL:
 638             trace_esp_mem_writeb_cmd_sel(val);
 639             handle_s_without_atn(s);
 640             break;
 641         case CMD_SELATN:
 642             trace_esp_mem_writeb_cmd_selatn(val);
 643             handle_satn(s);
 644             break;
 645         case CMD_SELATNS:
 646             trace_esp_mem_writeb_cmd_selatns(val);
 647             handle_satn_stop(s);
 648             break;
 649         case CMD_ENSEL:
 650             trace_esp_mem_writeb_cmd_ensel(val);
 651             s->rregs[ESP_RINTR] = 0;
 652             break;
 653         case CMD_DISSEL:
 654             trace_esp_mem_writeb_cmd_dissel(val);
 655             s->rregs[ESP_RINTR] = 0;
 656             esp_raise_irq(s);
 657             break;
 658         default:
 659             ESP_ERROR("Unhandled ESP command (%2.2x)\n", (unsigned)val);
 660             break;
 661         }
 662         break;
 663     case ESP_WBUSID ... ESP_WSYNO:
 664         break;
 665     case ESP_CFG1:
 666         s->rregs[saddr] = val;
 667         break;
 668     case ESP_WCCF ... ESP_WTEST:
 669         break;
 670     case ESP_CFG2 ... ESP_RES4:
 671         s->rregs[saddr] = val;
 672         break;
 673     default:
 674         ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", (unsigned)val, saddr);
 675         return;
 676     }
 677     s->wregs[saddr] = val;
 678 }
 679
 680 static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
 681                             unsigned size, bool is_write)
 682 {
 683     return (size == 1) || (is_write && size == 4);
 684 }
 685
 686 static const MemoryRegionOps esp_mem_ops = {
 687     .read = esp_mem_read,
 688     .write = esp_mem_write,
 689     .endianness = DEVICE_NATIVE_ENDIAN,
 690     .valid.accepts = esp_mem_accepts,
 691 };
 692
 693 static const VMStateDescription vmstate_esp = {
 694     .name ="esp",
 695     .version_id = 3,
 696     .minimum_version_id = 3,
 697     .minimum_version_id_old = 3,
 698     .fields      = (VMStateField []) {
 699         VMSTATE_BUFFER(rregs, ESPState),
 700         VMSTATE_BUFFER(wregs, ESPState),
 701         VMSTATE_INT32(ti_size, ESPState),
 702         VMSTATE_UINT32(ti_rptr, ESPState),
 703         VMSTATE_UINT32(ti_wptr, ESPState),
 704         VMSTATE_BUFFER(ti_buf, ESPState),
 705         VMSTATE_UINT32(status, ESPState),
 706         VMSTATE_UINT32(dma, ESPState),
 707         VMSTATE_BUFFER(cmdbuf, ESPState),
 708         VMSTATE_UINT32(cmdlen, ESPState),
 709         VMSTATE_UINT32(do_cmd, ESPState),
 710         VMSTATE_UINT32(dma_left, ESPState),
 711         VMSTATE_END_OF_LIST()
 712     }
 713 };
 714
 715 void esp_init(target_phys_addr_t espaddr, int it_shift,
 716               ESPDMAMemoryReadWriteFunc dma_memory_read,
 717               ESPDMAMemoryReadWriteFunc dma_memory_write,
 718               void *dma_opaque, qemu_irq irq, qemu_irq *reset,
 719               qemu_irq *dma_enable)
 720 {
 721     DeviceState *dev;
 722     SysBusDevice *s;
 723     ESPState *esp;
 724
 725     dev = qdev_create(NULL, "esp");
 726     esp = DO_UPCAST(ESPState, busdev.qdev, dev);
 727     esp->dma_memory_read = dma_memory_read;
 728     esp->dma_memory_write = dma_memory_write;
 729     esp->dma_opaque = dma_opaque;
 730     esp->it_shift = it_shift;
 731     /* XXX for now until rc4030 has been changed to use DMA enable signal */
 732     esp->dma_enabled = 1;
 733     qdev_init_nofail(dev);
 734     s = sysbus_from_qdev(dev);
 735     sysbus_connect_irq(s, 0, irq);
 736     sysbus_mmio_map(s, 0, espaddr);
 737     *reset = qdev_get_gpio_in(dev, 0);
 738     *dma_enable = qdev_get_gpio_in(dev, 1);
 739 }
 740
 741 static const struct SCSIBusInfo esp_scsi_info = {
 742     .tcq = false,
 743     .max_target = ESP_MAX_DEVS,
 744     .max_lun = 7,
 745
 746     .transfer_data = esp_transfer_data,
 747     .complete = esp_command_complete,
 748     .cancel = esp_request_cancelled
 749 };
 750
 751 static int esp_init1(SysBusDevice *dev)
 752 {
 753     ESPState *s = FROM_SYSBUS(ESPState, dev);
 754
 755     sysbus_init_irq(dev, &s->irq);
 756     assert(s->it_shift != -1);
 757
 758     memory_region_init_io(&s->iomem, &esp_mem_ops, s,
 759                           "esp", ESP_REGS << s->it_shift);
 760     sysbus_init_mmio(dev, &s->iomem);
 761
 762     qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
 763
 764     scsi_bus_new(&s->bus, &dev->qdev, &esp_scsi_info);
 765     return scsi_bus_legacy_handle_cmdline(&s->bus);
 766 }
 767
 768 static Property esp_properties[] = {
 769     {.name = NULL},
 770 };
 771
 772 static void esp_class_init(ObjectClass *klass, void *data)
 773 {
 774     DeviceClass *dc = DEVICE_CLASS(klass);
 775     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 776
 777     k->init = esp_init1;
 778     dc->reset = esp_hard_reset;
 779     dc->vmsd = &vmstate_esp;
 780     dc->props = esp_properties;
 781 }
 782
 783 static TypeInfo esp_info = {
 784     .name          = "esp",
 785     .parent        = TYPE_SYS_BUS_DEVICE,
 786     .instance_size = sizeof(ESPState),
 787     .class_init    = esp_class_init,
 788 };
 789
 790 static void esp_register_types(void)
 791 {
 792     type_register_static(&esp_info);
 793 }
 794
 795 type_init(esp_register_types)