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ETRAX-FS: Process outgoing DMA channels until EOL.
[qemu.git] / hw / etraxfs_dma.c
1 /*
2 * QEMU ETRAX DMA Controller.
3 *
4 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include <stdio.h>
25 #include <sys/time.h>
26 #include "hw.h"
27
28 #include "etraxfs_dma.h"
29
30 #define D(x)
31
32 #define RW_DATA 0x0
33 #define RW_SAVED_DATA 0x58
34 #define RW_SAVED_DATA_BUF 0x5c
35 #define RW_GROUP 0x60
36 #define RW_GROUP_DOWN 0x7c
37 #define RW_CMD 0x80
38 #define RW_CFG 0x84
39 #define RW_STAT 0x88
40 #define RW_INTR_MASK 0x8c
41 #define RW_ACK_INTR 0x90
42 #define R_INTR 0x94
43 #define R_MASKED_INTR 0x98
44 #define RW_STREAM_CMD 0x9c
45
46 #define DMA_REG_MAX 0x100
47
48 /* descriptors */
49
50 // ------------------------------------------------------------ dma_descr_group
51 typedef struct dma_descr_group {
52 struct dma_descr_group *next;
53 unsigned eol : 1;
54 unsigned tol : 1;
55 unsigned bol : 1;
56 unsigned : 1;
57 unsigned intr : 1;
58 unsigned : 2;
59 unsigned en : 1;
60 unsigned : 7;
61 unsigned dis : 1;
62 unsigned md : 16;
63 struct dma_descr_group *up;
64 union {
65 struct dma_descr_context *context;
66 struct dma_descr_group *group;
67 } down;
68 } dma_descr_group;
69
70 // ---------------------------------------------------------- dma_descr_context
71 typedef struct dma_descr_context {
72 struct dma_descr_context *next;
73 unsigned eol : 1;
74 unsigned : 3;
75 unsigned intr : 1;
76 unsigned : 1;
77 unsigned store_mode : 1;
78 unsigned en : 1;
79 unsigned : 7;
80 unsigned dis : 1;
81 unsigned md0 : 16;
82 unsigned md1;
83 unsigned md2;
84 unsigned md3;
85 unsigned md4;
86 struct dma_descr_data *saved_data;
87 char *saved_data_buf;
88 } dma_descr_context;
89
90 // ------------------------------------------------------------- dma_descr_data
91 typedef struct dma_descr_data {
92 struct dma_descr_data *next;
93 char *buf;
94 unsigned eol : 1;
95 unsigned : 2;
96 unsigned out_eop : 1;
97 unsigned intr : 1;
98 unsigned wait : 1;
99 unsigned : 2;
100 unsigned : 3;
101 unsigned in_eop : 1;
102 unsigned : 4;
103 unsigned md : 16;
104 char *after;
105 } dma_descr_data;
106
107 /* Constants */
108 enum {
109 regk_dma_ack_pkt = 0x00000100,
110 regk_dma_anytime = 0x00000001,
111 regk_dma_array = 0x00000008,
112 regk_dma_burst = 0x00000020,
113 regk_dma_client = 0x00000002,
114 regk_dma_copy_next = 0x00000010,
115 regk_dma_copy_up = 0x00000020,
116 regk_dma_data_at_eol = 0x00000001,
117 regk_dma_dis_c = 0x00000010,
118 regk_dma_dis_g = 0x00000020,
119 regk_dma_idle = 0x00000001,
120 regk_dma_intern = 0x00000004,
121 regk_dma_load_c = 0x00000200,
122 regk_dma_load_c_n = 0x00000280,
123 regk_dma_load_c_next = 0x00000240,
124 regk_dma_load_d = 0x00000140,
125 regk_dma_load_g = 0x00000300,
126 regk_dma_load_g_down = 0x000003c0,
127 regk_dma_load_g_next = 0x00000340,
128 regk_dma_load_g_up = 0x00000380,
129 regk_dma_next_en = 0x00000010,
130 regk_dma_next_pkt = 0x00000010,
131 regk_dma_no = 0x00000000,
132 regk_dma_only_at_wait = 0x00000000,
133 regk_dma_restore = 0x00000020,
134 regk_dma_rst = 0x00000001,
135 regk_dma_running = 0x00000004,
136 regk_dma_rw_cfg_default = 0x00000000,
137 regk_dma_rw_cmd_default = 0x00000000,
138 regk_dma_rw_intr_mask_default = 0x00000000,
139 regk_dma_rw_stat_default = 0x00000101,
140 regk_dma_rw_stream_cmd_default = 0x00000000,
141 regk_dma_save_down = 0x00000020,
142 regk_dma_save_up = 0x00000020,
143 regk_dma_set_reg = 0x00000050,
144 regk_dma_set_w_size1 = 0x00000190,
145 regk_dma_set_w_size2 = 0x000001a0,
146 regk_dma_set_w_size4 = 0x000001c0,
147 regk_dma_stopped = 0x00000002,
148 regk_dma_store_c = 0x00000002,
149 regk_dma_store_descr = 0x00000000,
150 regk_dma_store_g = 0x00000004,
151 regk_dma_store_md = 0x00000001,
152 regk_dma_sw = 0x00000008,
153 regk_dma_update_down = 0x00000020,
154 regk_dma_yes = 0x00000001
155 };
156
157 enum dma_ch_state
158 {
159 RST = 1,
160 STOPPED = 2,
161 RUNNING = 4
162 };
163
164 struct fs_dma_channel
165 {
166 int regmap;
167 qemu_irq *irq;
168 struct etraxfs_dma_client *client;
169
170
171 /* Internal status. */
172 int stream_cmd_src;
173 enum dma_ch_state state;
174
175 unsigned int input : 1;
176 unsigned int eol : 1;
177
178 struct dma_descr_group current_g;
179 struct dma_descr_context current_c;
180 struct dma_descr_data current_d;
181
182 /* Controll registers. */
183 uint32_t regs[DMA_REG_MAX];
184 };
185
186 struct fs_dma_ctrl
187 {
188 CPUState *env;
189 target_phys_addr_t base;
190
191 int nr_channels;
192 struct fs_dma_channel *channels;
193 };
194
195 static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg)
196 {
197 return ctrl->channels[c].regs[reg];
198 }
199
200 static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c)
201 {
202 return channel_reg(ctrl, c, RW_CFG) & 2;
203 }
204
205 static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
206 {
207 return (channel_reg(ctrl, c, RW_CFG) & 1)
208 && ctrl->channels[c].client;
209 }
210
211 static inline int fs_channel(target_phys_addr_t base, target_phys_addr_t addr)
212 {
213 /* Every channel has a 0x2000 ctrl register map. */
214 return (addr - base) >> 13;
215 }
216
217 #ifdef USE_THIS_DEAD_CODE
218 static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
219 {
220 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
221
222 /* Load and decode. FIXME: handle endianness. */
223 cpu_physical_memory_read (addr,
224 (void *) &ctrl->channels[c].current_g,
225 sizeof ctrl->channels[c].current_g);
226 }
227
228 static void dump_c(int ch, struct dma_descr_context *c)
229 {
230 printf("%s ch=%d\n", __func__, ch);
231 printf("next=%p\n", c->next);
232 printf("saved_data=%p\n", c->saved_data);
233 printf("saved_data_buf=%p\n", c->saved_data_buf);
234 printf("eol=%x\n", (uint32_t) c->eol);
235 }
236
237 static void dump_d(int ch, struct dma_descr_data *d)
238 {
239 printf("%s ch=%d\n", __func__, ch);
240 printf("next=%p\n", d->next);
241 printf("buf=%p\n", d->buf);
242 printf("after=%p\n", d->after);
243 printf("intr=%x\n", (uint32_t) d->intr);
244 printf("out_eop=%x\n", (uint32_t) d->out_eop);
245 printf("in_eop=%x\n", (uint32_t) d->in_eop);
246 printf("eol=%x\n", (uint32_t) d->eol);
247 }
248 #endif
249
250 static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
251 {
252 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
253
254 /* Load and decode. FIXME: handle endianness. */
255 cpu_physical_memory_read (addr,
256 (void *) &ctrl->channels[c].current_c,
257 sizeof ctrl->channels[c].current_c);
258
259 D(dump_c(c, &ctrl->channels[c].current_c));
260 /* I guess this should update the current pos. */
261 ctrl->channels[c].regs[RW_SAVED_DATA] =
262 (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data;
263 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
264 (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf;
265 }
266
267 static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
268 {
269 target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
270
271 /* Load and decode. FIXME: handle endianness. */
272 D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
273 cpu_physical_memory_read (addr,
274 (void *) &ctrl->channels[c].current_d,
275 sizeof ctrl->channels[c].current_d);
276
277 D(dump_d(c, &ctrl->channels[c].current_d));
278 ctrl->channels[c].regs[RW_DATA] = addr;
279 }
280
281 static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
282 {
283 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
284
285 /* Encode and store. FIXME: handle endianness. */
286 D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
287 D(dump_d(c, &ctrl->channels[c].current_d));
288 cpu_physical_memory_write (addr,
289 (void *) &ctrl->channels[c].current_c,
290 sizeof ctrl->channels[c].current_c);
291 }
292
293 static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
294 {
295 target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
296
297 /* Encode and store. FIXME: handle endianness. */
298 D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
299 cpu_physical_memory_write (addr,
300 (void *) &ctrl->channels[c].current_d,
301 sizeof ctrl->channels[c].current_d);
302 }
303
304 static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c)
305 {
306 /* FIXME: */
307 }
308
309 static inline void channel_start(struct fs_dma_ctrl *ctrl, int c)
310 {
311 if (ctrl->channels[c].client)
312 {
313 ctrl->channels[c].eol = 0;
314 ctrl->channels[c].state = RUNNING;
315 } else
316 printf("WARNING: starting DMA ch %d with no client\n", c);
317 }
318
319 static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
320 {
321 if (!channel_en(ctrl, c)
322 || channel_stopped(ctrl, c)
323 || ctrl->channels[c].state != RUNNING
324 /* Only reload the current data descriptor if it has eol set. */
325 || !ctrl->channels[c].current_d.eol) {
326 D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
327 c, ctrl->channels[c].state,
328 channel_stopped(ctrl, c),
329 channel_en(ctrl,c),
330 ctrl->channels[c].eol));
331 D(dump_d(c, &ctrl->channels[c].current_d));
332 return;
333 }
334
335 /* Reload the current descriptor. */
336 channel_load_d(ctrl, c);
337
338 /* If the current descriptor cleared the eol flag and we had already
339 reached eol state, do the continue. */
340 if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
341 D(printf("continue %d ok %p\n", c,
342 ctrl->channels[c].current_d.next));
343 ctrl->channels[c].regs[RW_SAVED_DATA] =
344 (uint32_t)(unsigned long)ctrl->channels[c].current_d.next;
345 channel_load_d(ctrl, c);
346 channel_start(ctrl, c);
347 }
348 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
349 (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf;
350 }
351
352 static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v)
353 {
354 unsigned int cmd = v & ((1 << 10) - 1);
355
356 D(printf("%s ch=%d cmd=%x\n",
357 __func__, c, cmd));
358 if (cmd & regk_dma_load_d) {
359 channel_load_d(ctrl, c);
360 if (cmd & regk_dma_burst)
361 channel_start(ctrl, c);
362 }
363
364 if (cmd & regk_dma_load_c) {
365 channel_load_c(ctrl, c);
366 channel_start(ctrl, c);
367 }
368 }
369
370 static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c)
371 {
372 D(printf("%s %d\n", __func__, c));
373 ctrl->channels[c].regs[R_INTR] &=
374 ~(ctrl->channels[c].regs[RW_ACK_INTR]);
375
376 ctrl->channels[c].regs[R_MASKED_INTR] =
377 ctrl->channels[c].regs[R_INTR]
378 & ctrl->channels[c].regs[RW_INTR_MASK];
379
380 D(printf("%s: chan=%d masked_intr=%x\n", __func__,
381 c,
382 ctrl->channels[c].regs[R_MASKED_INTR]));
383
384 if (ctrl->channels[c].regs[R_MASKED_INTR])
385 qemu_irq_raise(ctrl->channels[c].irq[0]);
386 else
387 qemu_irq_lower(ctrl->channels[c].irq[0]);
388 }
389
390 static void channel_out_run(struct fs_dma_ctrl *ctrl, int c)
391 {
392 uint32_t len;
393 uint32_t saved_data_buf;
394 unsigned char buf[2 * 1024];
395
396 while (ctrl->channels[c].eol != 1) {
397 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
398
399 D(printf("ch=%d buf=%x after=%x saved_data_buf=%x\n",
400 c,
401 (uint32_t)ctrl->channels[c].current_d.buf,
402 (uint32_t)ctrl->channels[c].current_d.after,
403 saved_data_buf));
404
405 len = (uint32_t)ctrl->channels[c].current_d.after;
406 len -= saved_data_buf;
407
408 if (len > sizeof buf)
409 len = sizeof buf;
410 cpu_physical_memory_read (saved_data_buf, buf, len);
411
412 D(printf("channel %d pushes %x %u bytes\n", c,
413 saved_data_buf, len));
414
415 if (ctrl->channels[c].client->client.push)
416 ctrl->channels[c].client->client.push(
417 ctrl->channels[c].client->client.opaque,
418 buf, len);
419 else
420 printf("WARNING: DMA ch%d dataloss,"
421 " no attached client.\n", c);
422
423 saved_data_buf += len;
424
425 if (saved_data_buf ==
426 (uint32_t)ctrl->channels[c].current_d.after) {
427 /* Done. Step to next. */
428 if (ctrl->channels[c].current_d.out_eop) {
429 /* TODO: signal eop to the client. */
430 D(printf("signal eop\n"));
431 }
432 if (ctrl->channels[c].current_d.intr) {
433 /* TODO: signal eop to the client. */
434 /* data intr. */
435 D(printf("signal intr\n"));
436 ctrl->channels[c].regs[R_INTR] |= (1 << 2);
437 channel_update_irq(ctrl, c);
438 }
439 if (ctrl->channels[c].current_d.eol) {
440 D(printf("channel %d EOL\n", c));
441 ctrl->channels[c].eol = 1;
442
443 /* Mark the context as disabled. */
444 ctrl->channels[c].current_c.dis = 1;
445 channel_store_c(ctrl, c);
446
447 channel_stop(ctrl, c);
448 } else {
449 ctrl->channels[c].regs[RW_SAVED_DATA] =
450 (uint32_t)ctrl->channels[c].current_d.next;
451 /* Load new descriptor. */
452 channel_load_d(ctrl, c);
453 saved_data_buf = (uint32_t)(unsigned long)
454 ctrl->channels[c].current_d.buf;
455 }
456
457 channel_store_d(ctrl, c);
458 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
459 saved_data_buf;
460 D(dump_d(c, &ctrl->channels[c].current_d));
461 }
462 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
463 }
464 }
465
466 static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
467 unsigned char *buf, int buflen, int eop)
468 {
469 uint32_t len;
470 uint32_t saved_data_buf;
471
472 if (ctrl->channels[c].eol == 1)
473 return 0;
474
475 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
476 len = (uint32_t)ctrl->channels[c].current_d.after;
477 len -= saved_data_buf;
478
479 if (len > buflen)
480 len = buflen;
481
482 cpu_physical_memory_write (saved_data_buf, buf, len);
483 saved_data_buf += len;
484
485 if (saved_data_buf ==
486 (uint32_t)ctrl->channels[c].current_d.after
487 || eop) {
488 uint32_t r_intr = ctrl->channels[c].regs[R_INTR];
489
490 D(printf("in dscr end len=%d\n",
491 ctrl->channels[c].current_d.after
492 - ctrl->channels[c].current_d.buf));
493 ctrl->channels[c].current_d.after =
494 (void *)(unsigned long) saved_data_buf;
495
496 /* Done. Step to next. */
497 if (ctrl->channels[c].current_d.intr) {
498 /* TODO: signal eop to the client. */
499 /* data intr. */
500 ctrl->channels[c].regs[R_INTR] |= 3;
501 }
502 if (eop) {
503 ctrl->channels[c].current_d.in_eop = 1;
504 ctrl->channels[c].regs[R_INTR] |= 8;
505 }
506 if (r_intr != ctrl->channels[c].regs[R_INTR])
507 channel_update_irq(ctrl, c);
508
509 channel_store_d(ctrl, c);
510 D(dump_d(c, &ctrl->channels[c].current_d));
511
512 if (ctrl->channels[c].current_d.eol) {
513 D(printf("channel %d EOL\n", c));
514 ctrl->channels[c].eol = 1;
515
516 /* Mark the context as disabled. */
517 ctrl->channels[c].current_c.dis = 1;
518 channel_store_c(ctrl, c);
519
520 channel_stop(ctrl, c);
521 } else {
522 ctrl->channels[c].regs[RW_SAVED_DATA] =
523 (uint32_t)ctrl->channels[c].current_d.next;
524 /* Load new descriptor. */
525 channel_load_d(ctrl, c);
526 saved_data_buf = (uint32_t)
527 ctrl->channels[c].current_d.buf;
528 }
529 }
530
531 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
532 return len;
533 }
534
535 static inline void channel_in_run(struct fs_dma_ctrl *ctrl, int c)
536 {
537 if (ctrl->channels[c].client->client.pull)
538 ctrl->channels[c].client->client.pull(
539 ctrl->channels[c].client->client.opaque);
540 }
541
542 static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
543 {
544 struct fs_dma_ctrl *ctrl = opaque;
545 CPUState *env = ctrl->env;
546 cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
547 addr);
548 return 0;
549 }
550
551 static uint32_t
552 dma_readl (void *opaque, target_phys_addr_t addr)
553 {
554 struct fs_dma_ctrl *ctrl = opaque;
555 int c;
556 uint32_t r = 0;
557
558 /* Make addr relative to this instances base. */
559 c = fs_channel(ctrl->base, addr);
560 addr &= 0x1fff;
561 switch (addr)
562 {
563 case RW_STAT:
564 r = ctrl->channels[c].state & 7;
565 r |= ctrl->channels[c].eol << 5;
566 r |= ctrl->channels[c].stream_cmd_src << 8;
567 break;
568
569 default:
570 r = ctrl->channels[c].regs[addr];
571 D(printf ("%s c=%d addr=%x\n",
572 __func__, c, addr));
573 break;
574 }
575 return r;
576 }
577
578 static void
579 dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
580 {
581 struct fs_dma_ctrl *ctrl = opaque;
582 CPUState *env = ctrl->env;
583 cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n",
584 addr);
585 }
586
587 static void
588 dma_update_state(struct fs_dma_ctrl *ctrl, int c)
589 {
590 if ((ctrl->channels[c].regs[RW_CFG] & 1) != 3) {
591 if (ctrl->channels[c].regs[RW_CFG] & 2)
592 ctrl->channels[c].state = STOPPED;
593 if (!(ctrl->channels[c].regs[RW_CFG] & 1))
594 ctrl->channels[c].state = RST;
595 }
596 }
597
598 static void
599 dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
600 {
601 struct fs_dma_ctrl *ctrl = opaque;
602 int c;
603
604 /* Make addr relative to this instances base. */
605 c = fs_channel(ctrl->base, addr);
606 addr &= 0x1fff;
607 switch (addr)
608 {
609 case RW_DATA:
610 ctrl->channels[c].regs[addr] = value;
611 break;
612
613 case RW_CFG:
614 ctrl->channels[c].regs[addr] = value;
615 dma_update_state(ctrl, c);
616 break;
617 case RW_CMD:
618 /* continue. */
619 if (value & ~1)
620 printf("Invalid store to ch=%d RW_CMD %x\n",
621 c, value);
622 ctrl->channels[c].regs[addr] = value;
623 channel_continue(ctrl, c);
624 break;
625
626 case RW_SAVED_DATA:
627 case RW_SAVED_DATA_BUF:
628 case RW_GROUP:
629 case RW_GROUP_DOWN:
630 ctrl->channels[c].regs[addr] = value;
631 break;
632
633 case RW_ACK_INTR:
634 case RW_INTR_MASK:
635 ctrl->channels[c].regs[addr] = value;
636 channel_update_irq(ctrl, c);
637 if (addr == RW_ACK_INTR)
638 ctrl->channels[c].regs[RW_ACK_INTR] = 0;
639 break;
640
641 case RW_STREAM_CMD:
642 if (value & ~1023)
643 printf("Invalid store to ch=%d "
644 "RW_STREAMCMD %x\n",
645 c, value);
646 ctrl->channels[c].regs[addr] = value;
647 D(printf("stream_cmd ch=%d\n", c));
648 channel_stream_cmd(ctrl, c, value);
649 break;
650
651 default:
652 D(printf ("%s c=%d %x %x\n", __func__, c, addr));
653 break;
654 }
655 }
656
657 static CPUReadMemoryFunc *dma_read[] = {
658 &dma_rinvalid,
659 &dma_rinvalid,
660 &dma_readl,
661 };
662
663 static CPUWriteMemoryFunc *dma_write[] = {
664 &dma_winvalid,
665 &dma_winvalid,
666 &dma_writel,
667 };
668
669 void etraxfs_dmac_run(void *opaque)
670 {
671 struct fs_dma_ctrl *ctrl = opaque;
672 int i;
673 int p = 0;
674
675 for (i = 0;
676 i < ctrl->nr_channels;
677 i++)
678 {
679 if (ctrl->channels[i].state == RUNNING)
680 {
681 p++;
682 if (ctrl->channels[i].input)
683 channel_in_run(ctrl, i);
684 else
685 channel_out_run(ctrl, i);
686 }
687 }
688 }
689
690 int etraxfs_dmac_input(struct etraxfs_dma_client *client,
691 void *buf, int len, int eop)
692 {
693 return channel_in_process(client->ctrl, client->channel,
694 buf, len, eop);
695 }
696
697 /* Connect an IRQ line with a channel. */
698 void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input)
699 {
700 struct fs_dma_ctrl *ctrl = opaque;
701 ctrl->channels[c].irq = line;
702 ctrl->channels[c].input = input;
703 }
704
705 void etraxfs_dmac_connect_client(void *opaque, int c,
706 struct etraxfs_dma_client *cl)
707 {
708 struct fs_dma_ctrl *ctrl = opaque;
709 cl->ctrl = ctrl;
710 cl->channel = c;
711 ctrl->channels[c].client = cl;
712 }
713
714
715 static void *etraxfs_dmac;
716 void DMA_run(void)
717 {
718 if (etraxfs_dmac)
719 etraxfs_dmac_run(etraxfs_dmac);
720 }
721
722 void *etraxfs_dmac_init(CPUState *env,
723 target_phys_addr_t base, int nr_channels)
724 {
725 struct fs_dma_ctrl *ctrl = NULL;
726 int i;
727
728 ctrl = qemu_mallocz(sizeof *ctrl);
729 if (!ctrl)
730 return NULL;
731
732 ctrl->base = base;
733 ctrl->env = env;
734 ctrl->nr_channels = nr_channels;
735 ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
736 if (!ctrl->channels)
737 goto err;
738
739 for (i = 0; i < nr_channels; i++)
740 {
741 ctrl->channels[i].regmap = cpu_register_io_memory(0,
742 dma_read,
743 dma_write,
744 ctrl);
745 cpu_register_physical_memory (base + i * 0x2000,
746 sizeof ctrl->channels[i].regs,
747 ctrl->channels[i].regmap);
748 }
749
750 /* Hax, we only support one DMA controller at a time. */
751 etraxfs_dmac = ctrl;
752 return ctrl;
753 err:
754 qemu_free(ctrl->channels);
755 qemu_free(ctrl);
756 return NULL;
757 }
Qemu copy for testing