hw/exynos4210_gic.c

   1 /*
   2  * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
   3  *
   4  * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Evgeny Voevodin <e.voevodin@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the
  11  * Free Software Foundation; either version 2 of the License, or (at your
  12  * option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  17  * See the GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "sysbus.h"
  24 #include "qemu-common.h"
  25 #include "irq.h"
  26 #include "exynos4210.h"
  27
  28 enum ExtGicId {
  29     EXT_GIC_ID_MDMA_LCD0 = 66,
  30     EXT_GIC_ID_PDMA0,
  31     EXT_GIC_ID_PDMA1,
  32     EXT_GIC_ID_TIMER0,
  33     EXT_GIC_ID_TIMER1,
  34     EXT_GIC_ID_TIMER2,
  35     EXT_GIC_ID_TIMER3,
  36     EXT_GIC_ID_TIMER4,
  37     EXT_GIC_ID_MCT_L0,
  38     EXT_GIC_ID_WDT,
  39     EXT_GIC_ID_RTC_ALARM,
  40     EXT_GIC_ID_RTC_TIC,
  41     EXT_GIC_ID_GPIO_XB,
  42     EXT_GIC_ID_GPIO_XA,
  43     EXT_GIC_ID_MCT_L1,
  44     EXT_GIC_ID_IEM_APC,
  45     EXT_GIC_ID_IEM_IEC,
  46     EXT_GIC_ID_NFC,
  47     EXT_GIC_ID_UART0,
  48     EXT_GIC_ID_UART1,
  49     EXT_GIC_ID_UART2,
  50     EXT_GIC_ID_UART3,
  51     EXT_GIC_ID_UART4,
  52     EXT_GIC_ID_MCT_G0,
  53     EXT_GIC_ID_I2C0,
  54     EXT_GIC_ID_I2C1,
  55     EXT_GIC_ID_I2C2,
  56     EXT_GIC_ID_I2C3,
  57     EXT_GIC_ID_I2C4,
  58     EXT_GIC_ID_I2C5,
  59     EXT_GIC_ID_I2C6,
  60     EXT_GIC_ID_I2C7,
  61     EXT_GIC_ID_SPI0,
  62     EXT_GIC_ID_SPI1,
  63     EXT_GIC_ID_SPI2,
  64     EXT_GIC_ID_MCT_G1,
  65     EXT_GIC_ID_USB_HOST,
  66     EXT_GIC_ID_USB_DEVICE,
  67     EXT_GIC_ID_MODEMIF,
  68     EXT_GIC_ID_HSMMC0,
  69     EXT_GIC_ID_HSMMC1,
  70     EXT_GIC_ID_HSMMC2,
  71     EXT_GIC_ID_HSMMC3,
  72     EXT_GIC_ID_SDMMC,
  73     EXT_GIC_ID_MIPI_CSI_4LANE,
  74     EXT_GIC_ID_MIPI_DSI_4LANE,
  75     EXT_GIC_ID_MIPI_CSI_2LANE,
  76     EXT_GIC_ID_MIPI_DSI_2LANE,
  77     EXT_GIC_ID_ONENAND_AUDI,
  78     EXT_GIC_ID_ROTATOR,
  79     EXT_GIC_ID_FIMC0,
  80     EXT_GIC_ID_FIMC1,
  81     EXT_GIC_ID_FIMC2,
  82     EXT_GIC_ID_FIMC3,
  83     EXT_GIC_ID_JPEG,
  84     EXT_GIC_ID_2D,
  85     EXT_GIC_ID_PCIe,
  86     EXT_GIC_ID_MIXER,
  87     EXT_GIC_ID_HDMI,
  88     EXT_GIC_ID_HDMI_I2C,
  89     EXT_GIC_ID_MFC,
  90     EXT_GIC_ID_TVENC,
  91 };
  92
  93 enum ExtInt {
  94     EXT_GIC_ID_EXTINT0 = 48,
  95     EXT_GIC_ID_EXTINT1,
  96     EXT_GIC_ID_EXTINT2,
  97     EXT_GIC_ID_EXTINT3,
  98     EXT_GIC_ID_EXTINT4,
  99     EXT_GIC_ID_EXTINT5,
 100     EXT_GIC_ID_EXTINT6,
 101     EXT_GIC_ID_EXTINT7,
 102     EXT_GIC_ID_EXTINT8,
 103     EXT_GIC_ID_EXTINT9,
 104     EXT_GIC_ID_EXTINT10,
 105     EXT_GIC_ID_EXTINT11,
 106     EXT_GIC_ID_EXTINT12,
 107     EXT_GIC_ID_EXTINT13,
 108     EXT_GIC_ID_EXTINT14,
 109     EXT_GIC_ID_EXTINT15
 110 };
 111
 112 /*
 113  * External GIC sources which are not from External Interrupt Combiner or
 114  * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
 115  * which is INTG16 in Internal Interrupt Combiner.
 116  */
 117
 118 static uint32_t
 119 combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
 120     /* int combiner groups 16-19 */
 121     { }, { }, { }, { },
 122     /* int combiner group 20 */
 123     { 0, EXT_GIC_ID_MDMA_LCD0 },
 124     /* int combiner group 21 */
 125     { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
 126     /* int combiner group 22 */
 127     { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
 128             EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
 129     /* int combiner group 23 */
 130     { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
 131     /* int combiner group 24 */
 132     { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
 133     /* int combiner group 25 */
 134     { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
 135     /* int combiner group 26 */
 136     { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
 137             EXT_GIC_ID_UART4 },
 138     /* int combiner group 27 */
 139     { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
 140             EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
 141             EXT_GIC_ID_I2C7 },
 142     /* int combiner group 28 */
 143     { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 },
 144     /* int combiner group 29 */
 145     { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
 146      EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
 147     /* int combiner group 30 */
 148     { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
 149     /* int combiner group 31 */
 150     { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
 151     /* int combiner group 32 */
 152     { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
 153     /* int combiner group 33 */
 154     { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
 155     /* int combiner group 34 */
 156     { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
 157     /* int combiner group 35 */
 158     { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
 159     /* int combiner group 36 */
 160     { EXT_GIC_ID_MIXER },
 161     /* int combiner group 37 */
 162     { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
 163      EXT_GIC_ID_EXTINT7 },
 164     /* groups 38-50 */
 165     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
 166     /* int combiner group 51 */
 167     { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
 168     /* group 52 */
 169     { },
 170     /* int combiner group 53 */
 171     { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
 172     /* groups 54-63 */
 173     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
 174 };
 175
 176 #define EXYNOS4210_GIC_NIRQ 160
 177 #define NCPU                EXYNOS4210_NCPUS
 178
 179 #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE     0x10000
 180 #define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE    0x10000
 181
 182 #define EXYNOS4210_EXT_GIC_PER_CPU_OFFSET      0x8000
 183 #define EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(n) \
 184     ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET)
 185 #define EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(n) \
 186     ((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET)
 187
 188 #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
 189 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
 190
 191 static void exynos4210_irq_handler(void *opaque, int irq, int level)
 192 {
 193     Exynos4210Irq *s = (Exynos4210Irq *)opaque;
 194
 195     /* Bypass */
 196     qemu_set_irq(s->board_irqs[irq], level);
 197
 198     return;
 199 }
 200
 201 /*
 202  * Initialize exynos4210 IRQ subsystem stub.
 203  */
 204 qemu_irq *exynos4210_init_irq(Exynos4210Irq *s)
 205 {
 206     return qemu_allocate_irqs(exynos4210_irq_handler, s,
 207             EXYNOS4210_MAX_INT_COMBINER_IN_IRQ);
 208 }
 209
 210 /*
 211  * Initialize board IRQs.
 212  * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
 213  */
 214 void exynos4210_init_board_irqs(Exynos4210Irq *s)
 215 {
 216     uint32_t grp, bit, irq_id, n;
 217
 218     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
 219         s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
 220                 s->ext_combiner_irq[n]);
 221
 222         irq_id = 0;
 223         if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
 224                 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
 225             /* MCT_G0 is passed to External GIC */
 226             irq_id = EXT_GIC_ID_MCT_G0;
 227         }
 228         if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
 229                 n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
 230             /* MCT_G1 is passed to External and GIC */
 231             irq_id = EXT_GIC_ID_MCT_G1;
 232         }
 233         if (irq_id) {
 234             s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
 235                     s->ext_gic_irq[irq_id-32]);
 236         }
 237
 238     }
 239     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
 240         /* these IDs are passed to Internal Combiner and External GIC */
 241         grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
 242         bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
 243         irq_id = combiner_grp_to_gic_id[grp -
 244                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
 245
 246         if (irq_id) {
 247             s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
 248                     s->ext_gic_irq[irq_id-32]);
 249         }
 250     }
 251 }
 252
 253 /*
 254  * Get IRQ number from exynos4210 IRQ subsystem stub.
 255  * To identify IRQ source use internal combiner group and bit number
 256  *  grp - group number
 257  *  bit - bit number inside group
 258  */
 259 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
 260 {
 261     return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
 262 }
 263
 264 /********* GIC part *********/
 265
 266 static inline int
 267 gic_get_current_cpu(void)
 268 {
 269     return cpu_single_env->cpu_index;
 270 }
 271
 272 #include "arm_gic.c"
 273
 274 typedef struct {
 275     gic_state gic;
 276     MemoryRegion cpu_container;
 277     MemoryRegion dist_container;
 278     MemoryRegion cpu_alias[NCPU];
 279     MemoryRegion dist_alias[NCPU];
 280     uint32_t num_cpu;
 281 } Exynos4210GicState;
 282
 283 static int exynos4210_gic_init(SysBusDevice *dev)
 284 {
 285     Exynos4210GicState *s = FROM_SYSBUSGIC(Exynos4210GicState, dev);
 286     uint32_t i;
 287     const char cpu_prefix[] = "exynos4210-gic-alias_cpu";
 288     const char dist_prefix[] = "exynos4210-gic-alias_dist";
 289     char cpu_alias_name[sizeof(cpu_prefix) + 3];
 290     char dist_alias_name[sizeof(cpu_prefix) + 3];
 291
 292     gic_init(&s->gic, s->num_cpu, EXYNOS4210_GIC_NIRQ);
 293
 294     memory_region_init(&s->cpu_container, "exynos4210-cpu-container",
 295             EXYNOS4210_EXT_GIC_CPU_REGION_SIZE);
 296     memory_region_init(&s->dist_container, "exynos4210-dist-container",
 297             EXYNOS4210_EXT_GIC_DIST_REGION_SIZE);
 298
 299     for (i = 0; i < s->num_cpu; i++) {
 300         /* Map CPU interface per SMP Core */
 301         sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
 302         memory_region_init_alias(&s->cpu_alias[i],
 303                                  cpu_alias_name,
 304                                  &s->gic.cpuiomem[0],
 305                                  0,
 306                                  EXYNOS4210_GIC_CPU_REGION_SIZE);
 307         memory_region_add_subregion(&s->cpu_container,
 308                 EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]);
 309
 310         /* Map Distributor per SMP Core */
 311         sprintf(dist_alias_name, "%s%x", dist_prefix, i);
 312         memory_region_init_alias(&s->dist_alias[i],
 313                                  dist_alias_name,
 314                                  &s->gic.iomem,
 315                                  0,
 316                                  EXYNOS4210_GIC_DIST_REGION_SIZE);
 317         memory_region_add_subregion(&s->dist_container,
 318                 EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]);
 319     }
 320
 321     sysbus_init_mmio(dev, &s->cpu_container);
 322     sysbus_init_mmio(dev, &s->dist_container);
 323
 324     gic_cpu_write(&s->gic, 1, 0, 1);
 325
 326     return 0;
 327 }
 328
 329 static Property exynos4210_gic_properties[] = {
 330     DEFINE_PROP_UINT32("num-cpu", Exynos4210GicState, num_cpu, 1),
 331     DEFINE_PROP_END_OF_LIST(),
 332 };
 333
 334 static void exynos4210_gic_class_init(ObjectClass *klass, void *data)
 335 {
 336     DeviceClass *dc = DEVICE_CLASS(klass);
 337     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 338
 339     k->init = exynos4210_gic_init;
 340     dc->props = exynos4210_gic_properties;
 341 }
 342
 343 static TypeInfo exynos4210_gic_info = {
 344     .name          = "exynos4210.gic",
 345     .parent        = TYPE_SYS_BUS_DEVICE,
 346     .instance_size = sizeof(Exynos4210GicState),
 347     .class_init    = exynos4210_gic_class_init,
 348 };
 349
 350 static void exynos4210_gic_register_types(void)
 351 {
 352     type_register_static(&exynos4210_gic_info);
 353 }
 354
 355 type_init(exynos4210_gic_register_types)
 356
 357 /*
 358  * IRQGate struct.
 359  * IRQ Gate represents OR gate between GICs to pass IRQ to PIC.
 360  */
 361 typedef struct {
 362     SysBusDevice busdev;
 363
 364     qemu_irq pic_irq[NCPU]; /* output IRQs to PICs */
 365     uint32_t gpio_level[EXYNOS4210_IRQ_GATE_NINPUTS]; /* Input levels */
 366 } Exynos4210IRQGateState;
 367
 368 static const VMStateDescription vmstate_exynos4210_irq_gate = {
 369     .name = "exynos4210.irq_gate",
 370     .version_id = 1,
 371     .minimum_version_id = 1,
 372     .minimum_version_id_old = 1,
 373     .fields = (VMStateField[]) {
 374         VMSTATE_UINT32_ARRAY(gpio_level, Exynos4210IRQGateState,
 375                 EXYNOS4210_IRQ_GATE_NINPUTS),
 376         VMSTATE_END_OF_LIST()
 377     }
 378 };
 379
 380 /* Process a change in an external IRQ input.  */
 381 static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
 382 {
 383     Exynos4210IRQGateState *s =
 384             (Exynos4210IRQGateState *)opaque;
 385     uint32_t odd, even;
 386
 387     if (irq & 1) {
 388         odd = irq;
 389         even = irq & ~1;
 390     } else {
 391         even = irq;
 392         odd = irq | 1;
 393     }
 394
 395     assert(irq < EXYNOS4210_IRQ_GATE_NINPUTS);
 396     s->gpio_level[irq] = level;
 397
 398     if (s->gpio_level[odd] >= 1 || s->gpio_level[even] >= 1) {
 399         qemu_irq_raise(s->pic_irq[even >> 1]);
 400     } else {
 401         qemu_irq_lower(s->pic_irq[even >> 1]);
 402     }
 403
 404     return;
 405 }
 406
 407 static void exynos4210_irq_gate_reset(DeviceState *d)
 408 {
 409     Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)d;
 410
 411     memset(&s->gpio_level, 0, sizeof(s->gpio_level));
 412 }
 413
 414 /*
 415  * IRQ Gate initialization.
 416  */
 417 static int exynos4210_irq_gate_init(SysBusDevice *dev)
 418 {
 419     unsigned int i;
 420     Exynos4210IRQGateState *s =
 421             FROM_SYSBUS(Exynos4210IRQGateState, dev);
 422
 423     /* Allocate general purpose input signals and connect a handler to each of
 424      * them */
 425     qdev_init_gpio_in(&s->busdev.qdev, exynos4210_irq_gate_handler,
 426             EXYNOS4210_IRQ_GATE_NINPUTS);
 427
 428     /* Connect SysBusDev irqs to device specific irqs */
 429     for (i = 0; i < NCPU; i++) {
 430         sysbus_init_irq(dev, &s->pic_irq[i]);
 431     }
 432
 433     return 0;
 434 }
 435
 436 static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
 437 {
 438     DeviceClass *dc = DEVICE_CLASS(klass);
 439     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 440
 441     k->init = exynos4210_irq_gate_init;
 442     dc->reset = exynos4210_irq_gate_reset;
 443     dc->vmsd = &vmstate_exynos4210_irq_gate;
 444 }
 445
 446 static TypeInfo exynos4210_irq_gate_info = {
 447     .name          = "exynos4210.irq_gate",
 448     .parent        = TYPE_SYS_BUS_DEVICE,
 449     .instance_size = sizeof(Exynos4210IRQGateState),
 450     .class_init    = exynos4210_irq_gate_class_init,
 451 };
 452
 453 static void exynos4210_irq_gate_register_types(void)
 454 {
 455     type_register_static(&exynos4210_irq_gate_info);
 456 }
 457
 458 type_init(exynos4210_irq_gate_register_types)