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[qemu.git] / hw / fdc.c
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "block.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37
38 /********************************************************/
39 /* debug Floppy devices */
40 //#define DEBUG_FLOPPY
41
42 #ifdef DEBUG_FLOPPY
43 #define FLOPPY_DPRINTF(fmt, ...) \
44 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
45 #else
46 #define FLOPPY_DPRINTF(fmt, ...)
47 #endif
48
49 #define FLOPPY_ERROR(fmt, ...) \
50 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
51
52 /********************************************************/
53 /* Floppy drive emulation */
54
55 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
56 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
57
58 /* Will always be a fixed parameter for us */
59 #define FD_SECTOR_LEN 512
60 #define FD_SECTOR_SC 2 /* Sector size code */
61 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
62
63 /* Floppy disk drive emulation */
64 typedef enum fdisk_type_t {
65 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
66 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
67 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
68 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
69 FDRIVE_DISK_NONE = 0x05, /* No disk */
70 } fdisk_type_t;
71
72 typedef enum fdrive_type_t {
73 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
74 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
75 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
76 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
77 } fdrive_type_t;
78
79 typedef enum fdisk_flags_t {
80 FDISK_DBL_SIDES = 0x01,
81 } fdisk_flags_t;
82
83 typedef struct fdrive_t {
84 DriveInfo *dinfo;
85 BlockDriverState *bs;
86 /* Drive status */
87 fdrive_type_t drive;
88 uint8_t perpendicular; /* 2.88 MB access mode */
89 /* Position */
90 uint8_t head;
91 uint8_t track;
92 uint8_t sect;
93 /* Media */
94 fdisk_flags_t flags;
95 uint8_t last_sect; /* Nb sector per track */
96 uint8_t max_track; /* Nb of tracks */
97 uint16_t bps; /* Bytes per sector */
98 uint8_t ro; /* Is read-only */
99 } fdrive_t;
100
101 static void fd_init (fdrive_t *drv)
102 {
103 /* Drive */
104 drv->bs = drv->dinfo ? drv->dinfo->bdrv : NULL;
105 drv->drive = FDRIVE_DRV_NONE;
106 drv->perpendicular = 0;
107 /* Disk */
108 drv->last_sect = 0;
109 drv->max_track = 0;
110 }
111
112 static int _fd_sector (uint8_t head, uint8_t track,
113 uint8_t sect, uint8_t last_sect)
114 {
115 return (((track * 2) + head) * last_sect) + sect - 1;
116 }
117
118 /* Returns current position, in sectors, for given drive */
119 static int fd_sector (fdrive_t *drv)
120 {
121 return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
122 }
123
124 /* Seek to a new position:
125 * returns 0 if already on right track
126 * returns 1 if track changed
127 * returns 2 if track is invalid
128 * returns 3 if sector is invalid
129 * returns 4 if seek is disabled
130 */
131 static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
132 int enable_seek)
133 {
134 uint32_t sector;
135 int ret;
136
137 if (track > drv->max_track ||
138 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
139 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
140 head, track, sect, 1,
141 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
142 drv->max_track, drv->last_sect);
143 return 2;
144 }
145 if (sect > drv->last_sect) {
146 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
147 head, track, sect, 1,
148 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
149 drv->max_track, drv->last_sect);
150 return 3;
151 }
152 sector = _fd_sector(head, track, sect, drv->last_sect);
153 ret = 0;
154 if (sector != fd_sector(drv)) {
155 #if 0
156 if (!enable_seek) {
157 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
158 head, track, sect, 1, drv->max_track, drv->last_sect);
159 return 4;
160 }
161 #endif
162 drv->head = head;
163 if (drv->track != track)
164 ret = 1;
165 drv->track = track;
166 drv->sect = sect;
167 }
168
169 return ret;
170 }
171
172 /* Set drive back to track 0 */
173 static void fd_recalibrate (fdrive_t *drv)
174 {
175 FLOPPY_DPRINTF("recalibrate\n");
176 drv->head = 0;
177 drv->track = 0;
178 drv->sect = 1;
179 }
180
181 /* Recognize floppy formats */
182 typedef struct fd_format_t {
183 fdrive_type_t drive;
184 fdisk_type_t disk;
185 uint8_t last_sect;
186 uint8_t max_track;
187 uint8_t max_head;
188 const char *str;
189 } fd_format_t;
190
191 static const fd_format_t fd_formats[] = {
192 /* First entry is default format */
193 /* 1.44 MB 3"1/2 floppy disks */
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
197 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
198 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
199 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
200 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
201 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
202 /* 2.88 MB 3"1/2 floppy disks */
203 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
204 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
205 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
206 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
207 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
208 /* 720 kB 3"1/2 floppy disks */
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
210 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
211 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
212 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
213 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
214 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
215 /* 1.2 MB 5"1/4 floppy disks */
216 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
219 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
220 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
221 /* 720 kB 5"1/4 floppy disks */
222 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
224 /* 360 kB 5"1/4 floppy disks */
225 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
226 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
227 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
228 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
229 /* 320 kB 5"1/4 floppy disks */
230 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
231 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
232 /* 360 kB must match 5"1/4 better than 3"1/2... */
233 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
234 /* end */
235 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
236 };
237
238 /* Revalidate a disk drive after a disk change */
239 static void fd_revalidate (fdrive_t *drv)
240 {
241 const fd_format_t *parse;
242 uint64_t nb_sectors, size;
243 int i, first_match, match;
244 int nb_heads, max_track, last_sect, ro;
245
246 FLOPPY_DPRINTF("revalidate\n");
247 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
248 ro = bdrv_is_read_only(drv->bs);
249 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
250 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
251 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
252 nb_heads - 1, max_track, last_sect);
253 } else {
254 bdrv_get_geometry(drv->bs, &nb_sectors);
255 match = -1;
256 first_match = -1;
257 for (i = 0;; i++) {
258 parse = &fd_formats[i];
259 if (parse->drive == FDRIVE_DRV_NONE)
260 break;
261 if (drv->drive == parse->drive ||
262 drv->drive == FDRIVE_DRV_NONE) {
263 size = (parse->max_head + 1) * parse->max_track *
264 parse->last_sect;
265 if (nb_sectors == size) {
266 match = i;
267 break;
268 }
269 if (first_match == -1)
270 first_match = i;
271 }
272 }
273 if (match == -1) {
274 if (first_match == -1)
275 match = 1;
276 else
277 match = first_match;
278 parse = &fd_formats[match];
279 }
280 nb_heads = parse->max_head + 1;
281 max_track = parse->max_track;
282 last_sect = parse->last_sect;
283 drv->drive = parse->drive;
284 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
285 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
286 }
287 if (nb_heads == 1) {
288 drv->flags &= ~FDISK_DBL_SIDES;
289 } else {
290 drv->flags |= FDISK_DBL_SIDES;
291 }
292 drv->max_track = max_track;
293 drv->last_sect = last_sect;
294 drv->ro = ro;
295 } else {
296 FLOPPY_DPRINTF("No disk in drive\n");
297 drv->last_sect = 0;
298 drv->max_track = 0;
299 drv->flags &= ~FDISK_DBL_SIDES;
300 }
301 }
302
303 /********************************************************/
304 /* Intel 82078 floppy disk controller emulation */
305
306 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
307 static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
308 static int fdctrl_transfer_handler (void *opaque, int nchan,
309 int dma_pos, int dma_len);
310 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
311
312 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
313 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
314 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
315 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
316 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
317 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
318 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
319 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
320 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
321 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
322 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
323
324 enum {
325 FD_DIR_WRITE = 0,
326 FD_DIR_READ = 1,
327 FD_DIR_SCANE = 2,
328 FD_DIR_SCANL = 3,
329 FD_DIR_SCANH = 4,
330 };
331
332 enum {
333 FD_STATE_MULTI = 0x01, /* multi track flag */
334 FD_STATE_FORMAT = 0x02, /* format flag */
335 FD_STATE_SEEK = 0x04, /* seek flag */
336 };
337
338 enum {
339 FD_REG_SRA = 0x00,
340 FD_REG_SRB = 0x01,
341 FD_REG_DOR = 0x02,
342 FD_REG_TDR = 0x03,
343 FD_REG_MSR = 0x04,
344 FD_REG_DSR = 0x04,
345 FD_REG_FIFO = 0x05,
346 FD_REG_DIR = 0x07,
347 };
348
349 enum {
350 FD_CMD_READ_TRACK = 0x02,
351 FD_CMD_SPECIFY = 0x03,
352 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
353 FD_CMD_WRITE = 0x05,
354 FD_CMD_READ = 0x06,
355 FD_CMD_RECALIBRATE = 0x07,
356 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
357 FD_CMD_WRITE_DELETED = 0x09,
358 FD_CMD_READ_ID = 0x0a,
359 FD_CMD_READ_DELETED = 0x0c,
360 FD_CMD_FORMAT_TRACK = 0x0d,
361 FD_CMD_DUMPREG = 0x0e,
362 FD_CMD_SEEK = 0x0f,
363 FD_CMD_VERSION = 0x10,
364 FD_CMD_SCAN_EQUAL = 0x11,
365 FD_CMD_PERPENDICULAR_MODE = 0x12,
366 FD_CMD_CONFIGURE = 0x13,
367 FD_CMD_LOCK = 0x14,
368 FD_CMD_VERIFY = 0x16,
369 FD_CMD_POWERDOWN_MODE = 0x17,
370 FD_CMD_PART_ID = 0x18,
371 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
372 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
373 FD_CMD_SAVE = 0x2c,
374 FD_CMD_OPTION = 0x33,
375 FD_CMD_RESTORE = 0x4c,
376 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
377 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
378 FD_CMD_FORMAT_AND_WRITE = 0xcd,
379 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
380 };
381
382 enum {
383 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
384 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
385 FD_CONFIG_POLL = 0x10, /* Poll enabled */
386 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
387 FD_CONFIG_EIS = 0x40, /* No implied seeks */
388 };
389
390 enum {
391 FD_SR0_EQPMT = 0x10,
392 FD_SR0_SEEK = 0x20,
393 FD_SR0_ABNTERM = 0x40,
394 FD_SR0_INVCMD = 0x80,
395 FD_SR0_RDYCHG = 0xc0,
396 };
397
398 enum {
399 FD_SR1_EC = 0x80, /* End of cylinder */
400 };
401
402 enum {
403 FD_SR2_SNS = 0x04, /* Scan not satisfied */
404 FD_SR2_SEH = 0x08, /* Scan equal hit */
405 };
406
407 enum {
408 FD_SRA_DIR = 0x01,
409 FD_SRA_nWP = 0x02,
410 FD_SRA_nINDX = 0x04,
411 FD_SRA_HDSEL = 0x08,
412 FD_SRA_nTRK0 = 0x10,
413 FD_SRA_STEP = 0x20,
414 FD_SRA_nDRV2 = 0x40,
415 FD_SRA_INTPEND = 0x80,
416 };
417
418 enum {
419 FD_SRB_MTR0 = 0x01,
420 FD_SRB_MTR1 = 0x02,
421 FD_SRB_WGATE = 0x04,
422 FD_SRB_RDATA = 0x08,
423 FD_SRB_WDATA = 0x10,
424 FD_SRB_DR0 = 0x20,
425 };
426
427 enum {
428 #if MAX_FD == 4
429 FD_DOR_SELMASK = 0x03,
430 #else
431 FD_DOR_SELMASK = 0x01,
432 #endif
433 FD_DOR_nRESET = 0x04,
434 FD_DOR_DMAEN = 0x08,
435 FD_DOR_MOTEN0 = 0x10,
436 FD_DOR_MOTEN1 = 0x20,
437 FD_DOR_MOTEN2 = 0x40,
438 FD_DOR_MOTEN3 = 0x80,
439 };
440
441 enum {
442 #if MAX_FD == 4
443 FD_TDR_BOOTSEL = 0x0c,
444 #else
445 FD_TDR_BOOTSEL = 0x04,
446 #endif
447 };
448
449 enum {
450 FD_DSR_DRATEMASK= 0x03,
451 FD_DSR_PWRDOWN = 0x40,
452 FD_DSR_SWRESET = 0x80,
453 };
454
455 enum {
456 FD_MSR_DRV0BUSY = 0x01,
457 FD_MSR_DRV1BUSY = 0x02,
458 FD_MSR_DRV2BUSY = 0x04,
459 FD_MSR_DRV3BUSY = 0x08,
460 FD_MSR_CMDBUSY = 0x10,
461 FD_MSR_NONDMA = 0x20,
462 FD_MSR_DIO = 0x40,
463 FD_MSR_RQM = 0x80,
464 };
465
466 enum {
467 FD_DIR_DSKCHG = 0x80,
468 };
469
470 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
471 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
472 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
473
474 struct fdctrl_t {
475 /* Controller's identification */
476 uint8_t version;
477 /* HW */
478 qemu_irq irq;
479 int dma_chann;
480 /* Controller state */
481 QEMUTimer *result_timer;
482 uint8_t sra;
483 uint8_t srb;
484 uint8_t dor;
485 uint8_t dor_vmstate; /* only used as temp during vmstate */
486 uint8_t tdr;
487 uint8_t dsr;
488 uint8_t msr;
489 uint8_t cur_drv;
490 uint8_t status0;
491 uint8_t status1;
492 uint8_t status2;
493 /* Command FIFO */
494 uint8_t *fifo;
495 int32_t fifo_size;
496 uint32_t data_pos;
497 uint32_t data_len;
498 uint8_t data_state;
499 uint8_t data_dir;
500 uint8_t eot; /* last wanted sector */
501 /* States kept only to be returned back */
502 /* Timers state */
503 uint8_t timer0;
504 uint8_t timer1;
505 /* precompensation */
506 uint8_t precomp_trk;
507 uint8_t config;
508 uint8_t lock;
509 /* Power down config (also with status regB access mode */
510 uint8_t pwrd;
511 /* Sun4m quirks? */
512 int sun4m;
513 /* Floppy drives */
514 uint8_t num_floppies;
515 fdrive_t drives[MAX_FD];
516 int reset_sensei;
517 };
518
519 typedef struct fdctrl_sysbus_t {
520 SysBusDevice busdev;
521 struct fdctrl_t state;
522 } fdctrl_sysbus_t;
523
524 typedef struct fdctrl_isabus_t {
525 ISADevice busdev;
526 struct fdctrl_t state;
527 } fdctrl_isabus_t;
528
529 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
530 {
531 fdctrl_t *fdctrl = opaque;
532 uint32_t retval;
533
534 switch (reg) {
535 case FD_REG_SRA:
536 retval = fdctrl_read_statusA(fdctrl);
537 break;
538 case FD_REG_SRB:
539 retval = fdctrl_read_statusB(fdctrl);
540 break;
541 case FD_REG_DOR:
542 retval = fdctrl_read_dor(fdctrl);
543 break;
544 case FD_REG_TDR:
545 retval = fdctrl_read_tape(fdctrl);
546 break;
547 case FD_REG_MSR:
548 retval = fdctrl_read_main_status(fdctrl);
549 break;
550 case FD_REG_FIFO:
551 retval = fdctrl_read_data(fdctrl);
552 break;
553 case FD_REG_DIR:
554 retval = fdctrl_read_dir(fdctrl);
555 break;
556 default:
557 retval = (uint32_t)(-1);
558 break;
559 }
560 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
561
562 return retval;
563 }
564
565 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
566 {
567 fdctrl_t *fdctrl = opaque;
568
569 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
570
571 switch (reg) {
572 case FD_REG_DOR:
573 fdctrl_write_dor(fdctrl, value);
574 break;
575 case FD_REG_TDR:
576 fdctrl_write_tape(fdctrl, value);
577 break;
578 case FD_REG_DSR:
579 fdctrl_write_rate(fdctrl, value);
580 break;
581 case FD_REG_FIFO:
582 fdctrl_write_data(fdctrl, value);
583 break;
584 default:
585 break;
586 }
587 }
588
589 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
590 {
591 return fdctrl_read(opaque, reg & 7);
592 }
593
594 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
595 {
596 fdctrl_write(opaque, reg & 7, value);
597 }
598
599 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
600 {
601 return fdctrl_read(opaque, (uint32_t)reg);
602 }
603
604 static void fdctrl_write_mem (void *opaque,
605 target_phys_addr_t reg, uint32_t value)
606 {
607 fdctrl_write(opaque, (uint32_t)reg, value);
608 }
609
610 static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
611 fdctrl_read_mem,
612 fdctrl_read_mem,
613 fdctrl_read_mem,
614 };
615
616 static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
617 fdctrl_write_mem,
618 fdctrl_write_mem,
619 fdctrl_write_mem,
620 };
621
622 static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
623 fdctrl_read_mem,
624 NULL,
625 NULL,
626 };
627
628 static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
629 fdctrl_write_mem,
630 NULL,
631 NULL,
632 };
633
634 static const VMStateDescription vmstate_fdrive = {
635 .name = "fdrive",
636 .version_id = 1,
637 .minimum_version_id = 1,
638 .minimum_version_id_old = 1,
639 .fields = (VMStateField []) {
640 VMSTATE_UINT8(head, fdrive_t),
641 VMSTATE_UINT8(track, fdrive_t),
642 VMSTATE_UINT8(sect, fdrive_t),
643 VMSTATE_END_OF_LIST()
644 }
645 };
646
647 static void fdc_pre_save(void *opaque)
648 {
649 fdctrl_t *s = opaque;
650
651 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
652 }
653
654 static int fdc_post_load(void *opaque, int version_id)
655 {
656 fdctrl_t *s = opaque;
657
658 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
659 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
660 return 0;
661 }
662
663 static const VMStateDescription vmstate_fdc = {
664 .name = "fdc",
665 .version_id = 2,
666 .minimum_version_id = 2,
667 .minimum_version_id_old = 2,
668 .pre_save = fdc_pre_save,
669 .post_load = fdc_post_load,
670 .fields = (VMStateField []) {
671 /* Controller State */
672 VMSTATE_UINT8(sra, fdctrl_t),
673 VMSTATE_UINT8(srb, fdctrl_t),
674 VMSTATE_UINT8(dor_vmstate, fdctrl_t),
675 VMSTATE_UINT8(tdr, fdctrl_t),
676 VMSTATE_UINT8(dsr, fdctrl_t),
677 VMSTATE_UINT8(msr, fdctrl_t),
678 VMSTATE_UINT8(status0, fdctrl_t),
679 VMSTATE_UINT8(status1, fdctrl_t),
680 VMSTATE_UINT8(status2, fdctrl_t),
681 /* Command FIFO */
682 VMSTATE_VARRAY_INT32(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8),
683 VMSTATE_UINT32(data_pos, fdctrl_t),
684 VMSTATE_UINT32(data_len, fdctrl_t),
685 VMSTATE_UINT8(data_state, fdctrl_t),
686 VMSTATE_UINT8(data_dir, fdctrl_t),
687 VMSTATE_UINT8(eot, fdctrl_t),
688 /* States kept only to be returned back */
689 VMSTATE_UINT8(timer0, fdctrl_t),
690 VMSTATE_UINT8(timer1, fdctrl_t),
691 VMSTATE_UINT8(precomp_trk, fdctrl_t),
692 VMSTATE_UINT8(config, fdctrl_t),
693 VMSTATE_UINT8(lock, fdctrl_t),
694 VMSTATE_UINT8(pwrd, fdctrl_t),
695 VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t),
696 VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1,
697 vmstate_fdrive, fdrive_t),
698 VMSTATE_END_OF_LIST()
699 }
700 };
701
702 static void fdctrl_external_reset_sysbus(DeviceState *d)
703 {
704 fdctrl_sysbus_t *sys = container_of(d, fdctrl_sysbus_t, busdev.qdev);
705 fdctrl_t *s = &sys->state;
706
707 fdctrl_reset(s, 0);
708 }
709
710 static void fdctrl_external_reset_isa(DeviceState *d)
711 {
712 fdctrl_isabus_t *isa = container_of(d, fdctrl_isabus_t, busdev.qdev);
713 fdctrl_t *s = &isa->state;
714
715 fdctrl_reset(s, 0);
716 }
717
718 static void fdctrl_handle_tc(void *opaque, int irq, int level)
719 {
720 //fdctrl_t *s = opaque;
721
722 if (level) {
723 // XXX
724 FLOPPY_DPRINTF("TC pulsed\n");
725 }
726 }
727
728 /* XXX: may change if moved to bdrv */
729 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
730 {
731 return fdctrl->drives[drive_num].drive;
732 }
733
734 /* Change IRQ state */
735 static void fdctrl_reset_irq (fdctrl_t *fdctrl)
736 {
737 if (!(fdctrl->sra & FD_SRA_INTPEND))
738 return;
739 FLOPPY_DPRINTF("Reset interrupt\n");
740 qemu_set_irq(fdctrl->irq, 0);
741 fdctrl->sra &= ~FD_SRA_INTPEND;
742 }
743
744 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
745 {
746 /* Sparc mutation */
747 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
748 /* XXX: not sure */
749 fdctrl->msr &= ~FD_MSR_CMDBUSY;
750 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
751 fdctrl->status0 = status0;
752 return;
753 }
754 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
755 qemu_set_irq(fdctrl->irq, 1);
756 fdctrl->sra |= FD_SRA_INTPEND;
757 }
758 fdctrl->reset_sensei = 0;
759 fdctrl->status0 = status0;
760 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
761 }
762
763 /* Reset controller */
764 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
765 {
766 int i;
767
768 FLOPPY_DPRINTF("reset controller\n");
769 fdctrl_reset_irq(fdctrl);
770 /* Initialise controller */
771 fdctrl->sra = 0;
772 fdctrl->srb = 0xc0;
773 if (!fdctrl->drives[1].bs)
774 fdctrl->sra |= FD_SRA_nDRV2;
775 fdctrl->cur_drv = 0;
776 fdctrl->dor = FD_DOR_nRESET;
777 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
778 fdctrl->msr = FD_MSR_RQM;
779 /* FIFO state */
780 fdctrl->data_pos = 0;
781 fdctrl->data_len = 0;
782 fdctrl->data_state = 0;
783 fdctrl->data_dir = FD_DIR_WRITE;
784 for (i = 0; i < MAX_FD; i++)
785 fd_recalibrate(&fdctrl->drives[i]);
786 fdctrl_reset_fifo(fdctrl);
787 if (do_irq) {
788 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
789 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
790 }
791 }
792
793 static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
794 {
795 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
796 }
797
798 static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
799 {
800 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
801 return &fdctrl->drives[1];
802 else
803 return &fdctrl->drives[0];
804 }
805
806 #if MAX_FD == 4
807 static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
808 {
809 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
810 return &fdctrl->drives[2];
811 else
812 return &fdctrl->drives[1];
813 }
814
815 static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
816 {
817 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
818 return &fdctrl->drives[3];
819 else
820 return &fdctrl->drives[2];
821 }
822 #endif
823
824 static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
825 {
826 switch (fdctrl->cur_drv) {
827 case 0: return drv0(fdctrl);
828 case 1: return drv1(fdctrl);
829 #if MAX_FD == 4
830 case 2: return drv2(fdctrl);
831 case 3: return drv3(fdctrl);
832 #endif
833 default: return NULL;
834 }
835 }
836
837 /* Status A register : 0x00 (read-only) */
838 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
839 {
840 uint32_t retval = fdctrl->sra;
841
842 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
843
844 return retval;
845 }
846
847 /* Status B register : 0x01 (read-only) */
848 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
849 {
850 uint32_t retval = fdctrl->srb;
851
852 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
853
854 return retval;
855 }
856
857 /* Digital output register : 0x02 */
858 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
859 {
860 uint32_t retval = fdctrl->dor;
861
862 /* Selected drive */
863 retval |= fdctrl->cur_drv;
864 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
865
866 return retval;
867 }
868
869 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
870 {
871 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
872
873 /* Motors */
874 if (value & FD_DOR_MOTEN0)
875 fdctrl->srb |= FD_SRB_MTR0;
876 else
877 fdctrl->srb &= ~FD_SRB_MTR0;
878 if (value & FD_DOR_MOTEN1)
879 fdctrl->srb |= FD_SRB_MTR1;
880 else
881 fdctrl->srb &= ~FD_SRB_MTR1;
882
883 /* Drive */
884 if (value & 1)
885 fdctrl->srb |= FD_SRB_DR0;
886 else
887 fdctrl->srb &= ~FD_SRB_DR0;
888
889 /* Reset */
890 if (!(value & FD_DOR_nRESET)) {
891 if (fdctrl->dor & FD_DOR_nRESET) {
892 FLOPPY_DPRINTF("controller enter RESET state\n");
893 }
894 } else {
895 if (!(fdctrl->dor & FD_DOR_nRESET)) {
896 FLOPPY_DPRINTF("controller out of RESET state\n");
897 fdctrl_reset(fdctrl, 1);
898 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
899 }
900 }
901 /* Selected drive */
902 fdctrl->cur_drv = value & FD_DOR_SELMASK;
903
904 fdctrl->dor = value;
905 }
906
907 /* Tape drive register : 0x03 */
908 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
909 {
910 uint32_t retval = fdctrl->tdr;
911
912 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
913
914 return retval;
915 }
916
917 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
918 {
919 /* Reset mode */
920 if (!(fdctrl->dor & FD_DOR_nRESET)) {
921 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
922 return;
923 }
924 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
925 /* Disk boot selection indicator */
926 fdctrl->tdr = value & FD_TDR_BOOTSEL;
927 /* Tape indicators: never allow */
928 }
929
930 /* Main status register : 0x04 (read) */
931 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
932 {
933 uint32_t retval = fdctrl->msr;
934
935 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
936 fdctrl->dor |= FD_DOR_nRESET;
937
938 /* Sparc mutation */
939 if (fdctrl->sun4m) {
940 retval |= FD_MSR_DIO;
941 fdctrl_reset_irq(fdctrl);
942 };
943
944 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
945
946 return retval;
947 }
948
949 /* Data select rate register : 0x04 (write) */
950 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
951 {
952 /* Reset mode */
953 if (!(fdctrl->dor & FD_DOR_nRESET)) {
954 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
955 return;
956 }
957 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
958 /* Reset: autoclear */
959 if (value & FD_DSR_SWRESET) {
960 fdctrl->dor &= ~FD_DOR_nRESET;
961 fdctrl_reset(fdctrl, 1);
962 fdctrl->dor |= FD_DOR_nRESET;
963 }
964 if (value & FD_DSR_PWRDOWN) {
965 fdctrl_reset(fdctrl, 1);
966 }
967 fdctrl->dsr = value;
968 }
969
970 static int fdctrl_media_changed(fdrive_t *drv)
971 {
972 int ret;
973
974 if (!drv->bs)
975 return 0;
976 ret = bdrv_media_changed(drv->bs);
977 if (ret) {
978 fd_revalidate(drv);
979 }
980 return ret;
981 }
982
983 /* Digital input register : 0x07 (read-only) */
984 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
985 {
986 uint32_t retval = 0;
987
988 if (fdctrl_media_changed(drv0(fdctrl))
989 || fdctrl_media_changed(drv1(fdctrl))
990 #if MAX_FD == 4
991 || fdctrl_media_changed(drv2(fdctrl))
992 || fdctrl_media_changed(drv3(fdctrl))
993 #endif
994 )
995 retval |= FD_DIR_DSKCHG;
996 if (retval != 0)
997 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
998
999 return retval;
1000 }
1001
1002 /* FIFO state control */
1003 static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
1004 {
1005 fdctrl->data_dir = FD_DIR_WRITE;
1006 fdctrl->data_pos = 0;
1007 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1008 }
1009
1010 /* Set FIFO status for the host to read */
1011 static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
1012 {
1013 fdctrl->data_dir = FD_DIR_READ;
1014 fdctrl->data_len = fifo_len;
1015 fdctrl->data_pos = 0;
1016 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1017 if (do_irq)
1018 fdctrl_raise_irq(fdctrl, 0x00);
1019 }
1020
1021 /* Set an error: unimplemented/unknown command */
1022 static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1023 {
1024 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1025 fdctrl->fifo[0] = FD_SR0_INVCMD;
1026 fdctrl_set_fifo(fdctrl, 1, 0);
1027 }
1028
1029 /* Seek to next sector */
1030 static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1031 {
1032 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1033 cur_drv->head, cur_drv->track, cur_drv->sect,
1034 fd_sector(cur_drv));
1035 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1036 error in fact */
1037 if (cur_drv->sect >= cur_drv->last_sect ||
1038 cur_drv->sect == fdctrl->eot) {
1039 cur_drv->sect = 1;
1040 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1041 if (cur_drv->head == 0 &&
1042 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1043 cur_drv->head = 1;
1044 } else {
1045 cur_drv->head = 0;
1046 cur_drv->track++;
1047 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1048 return 0;
1049 }
1050 } else {
1051 cur_drv->track++;
1052 return 0;
1053 }
1054 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1055 cur_drv->head, cur_drv->track,
1056 cur_drv->sect, fd_sector(cur_drv));
1057 } else {
1058 cur_drv->sect++;
1059 }
1060 return 1;
1061 }
1062
1063 /* Callback for transfer end (stop or abort) */
1064 static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1065 uint8_t status1, uint8_t status2)
1066 {
1067 fdrive_t *cur_drv;
1068
1069 cur_drv = get_cur_drv(fdctrl);
1070 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1071 status0, status1, status2,
1072 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1073 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1074 fdctrl->fifo[1] = status1;
1075 fdctrl->fifo[2] = status2;
1076 fdctrl->fifo[3] = cur_drv->track;
1077 fdctrl->fifo[4] = cur_drv->head;
1078 fdctrl->fifo[5] = cur_drv->sect;
1079 fdctrl->fifo[6] = FD_SECTOR_SC;
1080 fdctrl->data_dir = FD_DIR_READ;
1081 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1082 DMA_release_DREQ(fdctrl->dma_chann);
1083 }
1084 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1085 fdctrl->msr &= ~FD_MSR_NONDMA;
1086 fdctrl_set_fifo(fdctrl, 7, 1);
1087 }
1088
1089 /* Prepare a data transfer (either DMA or FIFO) */
1090 static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1091 {
1092 fdrive_t *cur_drv;
1093 uint8_t kh, kt, ks;
1094 int did_seek = 0;
1095
1096 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1097 cur_drv = get_cur_drv(fdctrl);
1098 kt = fdctrl->fifo[2];
1099 kh = fdctrl->fifo[3];
1100 ks = fdctrl->fifo[4];
1101 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1102 GET_CUR_DRV(fdctrl), kh, kt, ks,
1103 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1104 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1105 case 2:
1106 /* sect too big */
1107 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1108 fdctrl->fifo[3] = kt;
1109 fdctrl->fifo[4] = kh;
1110 fdctrl->fifo[5] = ks;
1111 return;
1112 case 3:
1113 /* track too big */
1114 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1115 fdctrl->fifo[3] = kt;
1116 fdctrl->fifo[4] = kh;
1117 fdctrl->fifo[5] = ks;
1118 return;
1119 case 4:
1120 /* No seek enabled */
1121 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1122 fdctrl->fifo[3] = kt;
1123 fdctrl->fifo[4] = kh;
1124 fdctrl->fifo[5] = ks;
1125 return;
1126 case 1:
1127 did_seek = 1;
1128 break;
1129 default:
1130 break;
1131 }
1132
1133 /* Set the FIFO state */
1134 fdctrl->data_dir = direction;
1135 fdctrl->data_pos = 0;
1136 fdctrl->msr |= FD_MSR_CMDBUSY;
1137 if (fdctrl->fifo[0] & 0x80)
1138 fdctrl->data_state |= FD_STATE_MULTI;
1139 else
1140 fdctrl->data_state &= ~FD_STATE_MULTI;
1141 if (did_seek)
1142 fdctrl->data_state |= FD_STATE_SEEK;
1143 else
1144 fdctrl->data_state &= ~FD_STATE_SEEK;
1145 if (fdctrl->fifo[5] == 00) {
1146 fdctrl->data_len = fdctrl->fifo[8];
1147 } else {
1148 int tmp;
1149 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1150 tmp = (fdctrl->fifo[6] - ks + 1);
1151 if (fdctrl->fifo[0] & 0x80)
1152 tmp += fdctrl->fifo[6];
1153 fdctrl->data_len *= tmp;
1154 }
1155 fdctrl->eot = fdctrl->fifo[6];
1156 if (fdctrl->dor & FD_DOR_DMAEN) {
1157 int dma_mode;
1158 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1159 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1160 dma_mode = (dma_mode >> 2) & 3;
1161 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1162 dma_mode, direction,
1163 (128 << fdctrl->fifo[5]) *
1164 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1165 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1166 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1167 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1168 (direction == FD_DIR_READ && dma_mode == 1)) {
1169 /* No access is allowed until DMA transfer has completed */
1170 fdctrl->msr &= ~FD_MSR_RQM;
1171 /* Now, we just have to wait for the DMA controller to
1172 * recall us...
1173 */
1174 DMA_hold_DREQ(fdctrl->dma_chann);
1175 DMA_schedule(fdctrl->dma_chann);
1176 return;
1177 } else {
1178 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1179 }
1180 }
1181 FLOPPY_DPRINTF("start non-DMA transfer\n");
1182 fdctrl->msr |= FD_MSR_NONDMA;
1183 if (direction != FD_DIR_WRITE)
1184 fdctrl->msr |= FD_MSR_DIO;
1185 /* IO based transfer: calculate len */
1186 fdctrl_raise_irq(fdctrl, 0x00);
1187
1188 return;
1189 }
1190
1191 /* Prepare a transfer of deleted data */
1192 static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1193 {
1194 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1195
1196 /* We don't handle deleted data,
1197 * so we don't return *ANYTHING*
1198 */
1199 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1200 }
1201
1202 /* handlers for DMA transfers */
1203 static int fdctrl_transfer_handler (void *opaque, int nchan,
1204 int dma_pos, int dma_len)
1205 {
1206 fdctrl_t *fdctrl;
1207 fdrive_t *cur_drv;
1208 int len, start_pos, rel_pos;
1209 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1210
1211 fdctrl = opaque;
1212 if (fdctrl->msr & FD_MSR_RQM) {
1213 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1214 return 0;
1215 }
1216 cur_drv = get_cur_drv(fdctrl);
1217 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1218 fdctrl->data_dir == FD_DIR_SCANH)
1219 status2 = FD_SR2_SNS;
1220 if (dma_len > fdctrl->data_len)
1221 dma_len = fdctrl->data_len;
1222 if (cur_drv->bs == NULL) {
1223 if (fdctrl->data_dir == FD_DIR_WRITE)
1224 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1225 else
1226 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1227 len = 0;
1228 goto transfer_error;
1229 }
1230 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1231 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1232 len = dma_len - fdctrl->data_pos;
1233 if (len + rel_pos > FD_SECTOR_LEN)
1234 len = FD_SECTOR_LEN - rel_pos;
1235 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1236 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1237 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1238 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1239 fd_sector(cur_drv) * FD_SECTOR_LEN);
1240 if (fdctrl->data_dir != FD_DIR_WRITE ||
1241 len < FD_SECTOR_LEN || rel_pos != 0) {
1242 /* READ & SCAN commands and realign to a sector for WRITE */
1243 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1244 fdctrl->fifo, 1) < 0) {
1245 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1246 fd_sector(cur_drv));
1247 /* Sure, image size is too small... */
1248 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1249 }
1250 }
1251 switch (fdctrl->data_dir) {
1252 case FD_DIR_READ:
1253 /* READ commands */
1254 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1255 fdctrl->data_pos, len);
1256 break;
1257 case FD_DIR_WRITE:
1258 /* WRITE commands */
1259 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1260 fdctrl->data_pos, len);
1261 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1262 fdctrl->fifo, 1) < 0) {
1263 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1264 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1265 goto transfer_error;
1266 }
1267 break;
1268 default:
1269 /* SCAN commands */
1270 {
1271 uint8_t tmpbuf[FD_SECTOR_LEN];
1272 int ret;
1273 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1274 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1275 if (ret == 0) {
1276 status2 = FD_SR2_SEH;
1277 goto end_transfer;
1278 }
1279 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1280 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1281 status2 = 0x00;
1282 goto end_transfer;
1283 }
1284 }
1285 break;
1286 }
1287 fdctrl->data_pos += len;
1288 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1289 if (rel_pos == 0) {
1290 /* Seek to next sector */
1291 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1292 break;
1293 }
1294 }
1295 end_transfer:
1296 len = fdctrl->data_pos - start_pos;
1297 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1298 fdctrl->data_pos, len, fdctrl->data_len);
1299 if (fdctrl->data_dir == FD_DIR_SCANE ||
1300 fdctrl->data_dir == FD_DIR_SCANL ||
1301 fdctrl->data_dir == FD_DIR_SCANH)
1302 status2 = FD_SR2_SEH;
1303 if (FD_DID_SEEK(fdctrl->data_state))
1304 status0 |= FD_SR0_SEEK;
1305 fdctrl->data_len -= len;
1306 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1307 transfer_error:
1308
1309 return len;
1310 }
1311
1312 /* Data register : 0x05 */
1313 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1314 {
1315 fdrive_t *cur_drv;
1316 uint32_t retval = 0;
1317 int pos;
1318
1319 cur_drv = get_cur_drv(fdctrl);
1320 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1321 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1322 FLOPPY_ERROR("controller not ready for reading\n");
1323 return 0;
1324 }
1325 pos = fdctrl->data_pos;
1326 if (fdctrl->msr & FD_MSR_NONDMA) {
1327 pos %= FD_SECTOR_LEN;
1328 if (pos == 0) {
1329 if (fdctrl->data_pos != 0)
1330 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1331 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1332 fd_sector(cur_drv));
1333 return 0;
1334 }
1335 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1336 FLOPPY_DPRINTF("error getting sector %d\n",
1337 fd_sector(cur_drv));
1338 /* Sure, image size is too small... */
1339 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1340 }
1341 }
1342 }
1343 retval = fdctrl->fifo[pos];
1344 if (++fdctrl->data_pos == fdctrl->data_len) {
1345 fdctrl->data_pos = 0;
1346 /* Switch from transfer mode to status mode
1347 * then from status mode to command mode
1348 */
1349 if (fdctrl->msr & FD_MSR_NONDMA) {
1350 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1351 } else {
1352 fdctrl_reset_fifo(fdctrl);
1353 fdctrl_reset_irq(fdctrl);
1354 }
1355 }
1356 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1357
1358 return retval;
1359 }
1360
1361 static void fdctrl_format_sector (fdctrl_t *fdctrl)
1362 {
1363 fdrive_t *cur_drv;
1364 uint8_t kh, kt, ks;
1365
1366 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1367 cur_drv = get_cur_drv(fdctrl);
1368 kt = fdctrl->fifo[6];
1369 kh = fdctrl->fifo[7];
1370 ks = fdctrl->fifo[8];
1371 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1372 GET_CUR_DRV(fdctrl), kh, kt, ks,
1373 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1374 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1375 case 2:
1376 /* sect too big */
1377 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1378 fdctrl->fifo[3] = kt;
1379 fdctrl->fifo[4] = kh;
1380 fdctrl->fifo[5] = ks;
1381 return;
1382 case 3:
1383 /* track too big */
1384 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1385 fdctrl->fifo[3] = kt;
1386 fdctrl->fifo[4] = kh;
1387 fdctrl->fifo[5] = ks;
1388 return;
1389 case 4:
1390 /* No seek enabled */
1391 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1392 fdctrl->fifo[3] = kt;
1393 fdctrl->fifo[4] = kh;
1394 fdctrl->fifo[5] = ks;
1395 return;
1396 case 1:
1397 fdctrl->data_state |= FD_STATE_SEEK;
1398 break;
1399 default:
1400 break;
1401 }
1402 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1403 if (cur_drv->bs == NULL ||
1404 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1405 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1406 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1407 } else {
1408 if (cur_drv->sect == cur_drv->last_sect) {
1409 fdctrl->data_state &= ~FD_STATE_FORMAT;
1410 /* Last sector done */
1411 if (FD_DID_SEEK(fdctrl->data_state))
1412 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1413 else
1414 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1415 } else {
1416 /* More to do */
1417 fdctrl->data_pos = 0;
1418 fdctrl->data_len = 4;
1419 }
1420 }
1421 }
1422
1423 static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1424 {
1425 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1426 fdctrl->fifo[0] = fdctrl->lock << 4;
1427 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1428 }
1429
1430 static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1431 {
1432 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1433
1434 /* Drives position */
1435 fdctrl->fifo[0] = drv0(fdctrl)->track;
1436 fdctrl->fifo[1] = drv1(fdctrl)->track;
1437 #if MAX_FD == 4
1438 fdctrl->fifo[2] = drv2(fdctrl)->track;
1439 fdctrl->fifo[3] = drv3(fdctrl)->track;
1440 #else
1441 fdctrl->fifo[2] = 0;
1442 fdctrl->fifo[3] = 0;
1443 #endif
1444 /* timers */
1445 fdctrl->fifo[4] = fdctrl->timer0;
1446 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1447 fdctrl->fifo[6] = cur_drv->last_sect;
1448 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1449 (cur_drv->perpendicular << 2);
1450 fdctrl->fifo[8] = fdctrl->config;
1451 fdctrl->fifo[9] = fdctrl->precomp_trk;
1452 fdctrl_set_fifo(fdctrl, 10, 0);
1453 }
1454
1455 static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1456 {
1457 /* Controller's version */
1458 fdctrl->fifo[0] = fdctrl->version;
1459 fdctrl_set_fifo(fdctrl, 1, 1);
1460 }
1461
1462 static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1463 {
1464 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1465 fdctrl_set_fifo(fdctrl, 1, 0);
1466 }
1467
1468 static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1469 {
1470 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1471
1472 /* Drives position */
1473 drv0(fdctrl)->track = fdctrl->fifo[3];
1474 drv1(fdctrl)->track = fdctrl->fifo[4];
1475 #if MAX_FD == 4
1476 drv2(fdctrl)->track = fdctrl->fifo[5];
1477 drv3(fdctrl)->track = fdctrl->fifo[6];
1478 #endif
1479 /* timers */
1480 fdctrl->timer0 = fdctrl->fifo[7];
1481 fdctrl->timer1 = fdctrl->fifo[8];
1482 cur_drv->last_sect = fdctrl->fifo[9];
1483 fdctrl->lock = fdctrl->fifo[10] >> 7;
1484 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1485 fdctrl->config = fdctrl->fifo[11];
1486 fdctrl->precomp_trk = fdctrl->fifo[12];
1487 fdctrl->pwrd = fdctrl->fifo[13];
1488 fdctrl_reset_fifo(fdctrl);
1489 }
1490
1491 static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1492 {
1493 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1494
1495 fdctrl->fifo[0] = 0;
1496 fdctrl->fifo[1] = 0;
1497 /* Drives position */
1498 fdctrl->fifo[2] = drv0(fdctrl)->track;
1499 fdctrl->fifo[3] = drv1(fdctrl)->track;
1500 #if MAX_FD == 4
1501 fdctrl->fifo[4] = drv2(fdctrl)->track;
1502 fdctrl->fifo[5] = drv3(fdctrl)->track;
1503 #else
1504 fdctrl->fifo[4] = 0;
1505 fdctrl->fifo[5] = 0;
1506 #endif
1507 /* timers */
1508 fdctrl->fifo[6] = fdctrl->timer0;
1509 fdctrl->fifo[7] = fdctrl->timer1;
1510 fdctrl->fifo[8] = cur_drv->last_sect;
1511 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1512 (cur_drv->perpendicular << 2);
1513 fdctrl->fifo[10] = fdctrl->config;
1514 fdctrl->fifo[11] = fdctrl->precomp_trk;
1515 fdctrl->fifo[12] = fdctrl->pwrd;
1516 fdctrl->fifo[13] = 0;
1517 fdctrl->fifo[14] = 0;
1518 fdctrl_set_fifo(fdctrl, 15, 1);
1519 }
1520
1521 static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1522 {
1523 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1524
1525 /* XXX: should set main status register to busy */
1526 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1527 qemu_mod_timer(fdctrl->result_timer,
1528 qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
1529 }
1530
1531 static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1532 {
1533 fdrive_t *cur_drv;
1534
1535 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1536 cur_drv = get_cur_drv(fdctrl);
1537 fdctrl->data_state |= FD_STATE_FORMAT;
1538 if (fdctrl->fifo[0] & 0x80)
1539 fdctrl->data_state |= FD_STATE_MULTI;
1540 else
1541 fdctrl->data_state &= ~FD_STATE_MULTI;
1542 fdctrl->data_state &= ~FD_STATE_SEEK;
1543 cur_drv->bps =
1544 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1545 #if 0
1546 cur_drv->last_sect =
1547 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1548 fdctrl->fifo[3] / 2;
1549 #else
1550 cur_drv->last_sect = fdctrl->fifo[3];
1551 #endif
1552 /* TODO: implement format using DMA expected by the Bochs BIOS
1553 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1554 * the sector with the specified fill byte
1555 */
1556 fdctrl->data_state &= ~FD_STATE_FORMAT;
1557 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1558 }
1559
1560 static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1561 {
1562 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1563 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1564 if (fdctrl->fifo[2] & 1)
1565 fdctrl->dor &= ~FD_DOR_DMAEN;
1566 else
1567 fdctrl->dor |= FD_DOR_DMAEN;
1568 /* No result back */
1569 fdctrl_reset_fifo(fdctrl);
1570 }
1571
1572 static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1573 {
1574 fdrive_t *cur_drv;
1575
1576 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1577 cur_drv = get_cur_drv(fdctrl);
1578 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1579 /* 1 Byte status back */
1580 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1581 (cur_drv->track == 0 ? 0x10 : 0x00) |
1582 (cur_drv->head << 2) |
1583 GET_CUR_DRV(fdctrl) |
1584 0x28;
1585 fdctrl_set_fifo(fdctrl, 1, 0);
1586 }
1587
1588 static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1589 {
1590 fdrive_t *cur_drv;
1591
1592 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1593 cur_drv = get_cur_drv(fdctrl);
1594 fd_recalibrate(cur_drv);
1595 fdctrl_reset_fifo(fdctrl);
1596 /* Raise Interrupt */
1597 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1598 }
1599
1600 static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1601 {
1602 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1603
1604 if(fdctrl->reset_sensei > 0) {
1605 fdctrl->fifo[0] =
1606 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1607 fdctrl->reset_sensei--;
1608 } else {
1609 /* XXX: status0 handling is broken for read/write
1610 commands, so we do this hack. It should be suppressed
1611 ASAP */
1612 fdctrl->fifo[0] =
1613 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1614 }
1615
1616 fdctrl->fifo[1] = cur_drv->track;
1617 fdctrl_set_fifo(fdctrl, 2, 0);
1618 fdctrl_reset_irq(fdctrl);
1619 fdctrl->status0 = FD_SR0_RDYCHG;
1620 }
1621
1622 static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1623 {
1624 fdrive_t *cur_drv;
1625
1626 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1627 cur_drv = get_cur_drv(fdctrl);
1628 fdctrl_reset_fifo(fdctrl);
1629 if (fdctrl->fifo[2] > cur_drv->max_track) {
1630 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1631 } else {
1632 cur_drv->track = fdctrl->fifo[2];
1633 /* Raise Interrupt */
1634 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1635 }
1636 }
1637
1638 static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1639 {
1640 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1641
1642 if (fdctrl->fifo[1] & 0x80)
1643 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1644 /* No result back */
1645 fdctrl_reset_fifo(fdctrl);
1646 }
1647
1648 static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1649 {
1650 fdctrl->config = fdctrl->fifo[2];
1651 fdctrl->precomp_trk = fdctrl->fifo[3];
1652 /* No result back */
1653 fdctrl_reset_fifo(fdctrl);
1654 }
1655
1656 static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1657 {
1658 fdctrl->pwrd = fdctrl->fifo[1];
1659 fdctrl->fifo[0] = fdctrl->fifo[1];
1660 fdctrl_set_fifo(fdctrl, 1, 1);
1661 }
1662
1663 static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1664 {
1665 /* No result back */
1666 fdctrl_reset_fifo(fdctrl);
1667 }
1668
1669 static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1670 {
1671 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1672
1673 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1674 /* Command parameters done */
1675 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1676 fdctrl->fifo[0] = fdctrl->fifo[1];
1677 fdctrl->fifo[2] = 0;
1678 fdctrl->fifo[3] = 0;
1679 fdctrl_set_fifo(fdctrl, 4, 1);
1680 } else {
1681 fdctrl_reset_fifo(fdctrl);
1682 }
1683 } else if (fdctrl->data_len > 7) {
1684 /* ERROR */
1685 fdctrl->fifo[0] = 0x80 |
1686 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1687 fdctrl_set_fifo(fdctrl, 1, 1);
1688 }
1689 }
1690
1691 static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1692 {
1693 fdrive_t *cur_drv;
1694
1695 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1696 cur_drv = get_cur_drv(fdctrl);
1697 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1698 cur_drv->track = cur_drv->max_track - 1;
1699 } else {
1700 cur_drv->track += fdctrl->fifo[2];
1701 }
1702 fdctrl_reset_fifo(fdctrl);
1703 /* Raise Interrupt */
1704 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1705 }
1706
1707 static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1708 {
1709 fdrive_t *cur_drv;
1710
1711 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1712 cur_drv = get_cur_drv(fdctrl);
1713 if (fdctrl->fifo[2] > cur_drv->track) {
1714 cur_drv->track = 0;
1715 } else {
1716 cur_drv->track -= fdctrl->fifo[2];
1717 }
1718 fdctrl_reset_fifo(fdctrl);
1719 /* Raise Interrupt */
1720 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1721 }
1722
1723 static const struct {
1724 uint8_t value;
1725 uint8_t mask;
1726 const char* name;
1727 int parameters;
1728 void (*handler)(fdctrl_t *fdctrl, int direction);
1729 int direction;
1730 } handlers[] = {
1731 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1732 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1733 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1734 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1735 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1736 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1737 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1738 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1739 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1740 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1741 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1742 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1743 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1744 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1745 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1746 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1747 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1748 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1749 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1750 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1751 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1752 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1753 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1754 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1755 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1756 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1757 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1758 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1759 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1760 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1761 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1762 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1763 };
1764 /* Associate command to an index in the 'handlers' array */
1765 static uint8_t command_to_handler[256];
1766
1767 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1768 {
1769 fdrive_t *cur_drv;
1770 int pos;
1771
1772 /* Reset mode */
1773 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1774 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1775 return;
1776 }
1777 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1778 FLOPPY_ERROR("controller not ready for writing\n");
1779 return;
1780 }
1781 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1782 /* Is it write command time ? */
1783 if (fdctrl->msr & FD_MSR_NONDMA) {
1784 /* FIFO data write */
1785 pos = fdctrl->data_pos++;
1786 pos %= FD_SECTOR_LEN;
1787 fdctrl->fifo[pos] = value;
1788 if (pos == FD_SECTOR_LEN - 1 ||
1789 fdctrl->data_pos == fdctrl->data_len) {
1790 cur_drv = get_cur_drv(fdctrl);
1791 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1792 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1793 return;
1794 }
1795 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1796 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1797 fd_sector(cur_drv));
1798 return;
1799 }
1800 }
1801 /* Switch from transfer mode to status mode
1802 * then from status mode to command mode
1803 */
1804 if (fdctrl->data_pos == fdctrl->data_len)
1805 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1806 return;
1807 }
1808 if (fdctrl->data_pos == 0) {
1809 /* Command */
1810 pos = command_to_handler[value & 0xff];
1811 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1812 fdctrl->data_len = handlers[pos].parameters + 1;
1813 }
1814
1815 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1816 fdctrl->fifo[fdctrl->data_pos++] = value;
1817 if (fdctrl->data_pos == fdctrl->data_len) {
1818 /* We now have all parameters
1819 * and will be able to treat the command
1820 */
1821 if (fdctrl->data_state & FD_STATE_FORMAT) {
1822 fdctrl_format_sector(fdctrl);
1823 return;
1824 }
1825
1826 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1827 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1828 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1829 }
1830 }
1831
1832 static void fdctrl_result_timer(void *opaque)
1833 {
1834 fdctrl_t *fdctrl = opaque;
1835 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1836
1837 /* Pretend we are spinning.
1838 * This is needed for Coherent, which uses READ ID to check for
1839 * sector interleaving.
1840 */
1841 if (cur_drv->last_sect != 0) {
1842 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1843 }
1844 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1845 }
1846
1847 /* Init functions */
1848 static void fdctrl_connect_drives(fdctrl_t *fdctrl)
1849 {
1850 unsigned int i;
1851
1852 for (i = 0; i < MAX_FD; i++) {
1853 fd_init(&fdctrl->drives[i]);
1854 fd_revalidate(&fdctrl->drives[i]);
1855 }
1856 }
1857
1858 fdctrl_t *fdctrl_init_isa(DriveInfo **fds)
1859 {
1860 ISADevice *dev;
1861
1862 dev = isa_create("isa-fdc");
1863 qdev_prop_set_drive(&dev->qdev, "driveA", fds[0]);
1864 qdev_prop_set_drive(&dev->qdev, "driveB", fds[1]);
1865 if (qdev_init(&dev->qdev) < 0)
1866 return NULL;
1867 return &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state);
1868 }
1869
1870 fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1871 target_phys_addr_t mmio_base,
1872 DriveInfo **fds)
1873 {
1874 fdctrl_t *fdctrl;
1875 DeviceState *dev;
1876 fdctrl_sysbus_t *sys;
1877
1878 dev = qdev_create(NULL, "sysbus-fdc");
1879 sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1880 fdctrl = &sys->state;
1881 fdctrl->dma_chann = dma_chann; /* FIXME */
1882 qdev_prop_set_drive(dev, "driveA", fds[0]);
1883 qdev_prop_set_drive(dev, "driveB", fds[1]);
1884 qdev_init_nofail(dev);
1885 sysbus_connect_irq(&sys->busdev, 0, irq);
1886 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1887
1888 return fdctrl;
1889 }
1890
1891 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1892 DriveInfo **fds, qemu_irq *fdc_tc)
1893 {
1894 DeviceState *dev;
1895 fdctrl_sysbus_t *sys;
1896 fdctrl_t *fdctrl;
1897
1898 dev = qdev_create(NULL, "SUNW,fdtwo");
1899 qdev_prop_set_drive(dev, "drive", fds[0]);
1900 qdev_init_nofail(dev);
1901 sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1902 fdctrl = &sys->state;
1903 sysbus_connect_irq(&sys->busdev, 0, irq);
1904 sysbus_mmio_map(&sys->busdev, 0, io_base);
1905 *fdc_tc = qdev_get_gpio_in(dev, 0);
1906
1907 return fdctrl;
1908 }
1909
1910 static int fdctrl_init_common(fdctrl_t *fdctrl, target_phys_addr_t io_base)
1911 {
1912 int i, j;
1913 static int command_tables_inited = 0;
1914
1915 /* Fill 'command_to_handler' lookup table */
1916 if (!command_tables_inited) {
1917 command_tables_inited = 1;
1918 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1919 for (j = 0; j < sizeof(command_to_handler); j++) {
1920 if ((j & handlers[i].mask) == handlers[i].value) {
1921 command_to_handler[j] = i;
1922 }
1923 }
1924 }
1925 }
1926
1927 FLOPPY_DPRINTF("init controller\n");
1928 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1929 fdctrl->fifo_size = 512;
1930 fdctrl->result_timer = qemu_new_timer(vm_clock,
1931 fdctrl_result_timer, fdctrl);
1932
1933 fdctrl->version = 0x90; /* Intel 82078 controller */
1934 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1935 fdctrl->num_floppies = MAX_FD;
1936
1937 if (fdctrl->dma_chann != -1)
1938 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1939 fdctrl_connect_drives(fdctrl);
1940
1941 vmstate_register(io_base, &vmstate_fdc, fdctrl);
1942 return 0;
1943 }
1944
1945 static int isabus_fdc_init1(ISADevice *dev)
1946 {
1947 fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev);
1948 fdctrl_t *fdctrl = &isa->state;
1949 int iobase = 0x3f0;
1950 int isairq = 6;
1951 int dma_chann = 2;
1952 int ret;
1953
1954 register_ioport_read(iobase + 0x01, 5, 1,
1955 &fdctrl_read_port, fdctrl);
1956 register_ioport_read(iobase + 0x07, 1, 1,
1957 &fdctrl_read_port, fdctrl);
1958 register_ioport_write(iobase + 0x01, 5, 1,
1959 &fdctrl_write_port, fdctrl);
1960 register_ioport_write(iobase + 0x07, 1, 1,
1961 &fdctrl_write_port, fdctrl);
1962 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1963 fdctrl->dma_chann = dma_chann;
1964
1965 ret = fdctrl_init_common(fdctrl, iobase);
1966
1967 return ret;
1968 }
1969
1970 static int sysbus_fdc_init1(SysBusDevice *dev)
1971 {
1972 fdctrl_sysbus_t *sys = DO_UPCAST(fdctrl_sysbus_t, busdev, dev);
1973 fdctrl_t *fdctrl = &sys->state;
1974 int io;
1975 int ret;
1976
1977 io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
1978 sysbus_init_mmio(dev, 0x08, io);
1979 sysbus_init_irq(dev, &fdctrl->irq);
1980 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1981 fdctrl->dma_chann = -1;
1982
1983 ret = fdctrl_init_common(fdctrl, io);
1984
1985 return ret;
1986 }
1987
1988 static int sun4m_fdc_init1(SysBusDevice *dev)
1989 {
1990 fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
1991 int io;
1992
1993 io = cpu_register_io_memory(fdctrl_mem_read_strict,
1994 fdctrl_mem_write_strict, fdctrl);
1995 sysbus_init_mmio(dev, 0x08, io);
1996 sysbus_init_irq(dev, &fdctrl->irq);
1997 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1998
1999 fdctrl->sun4m = 1;
2000 return fdctrl_init_common(fdctrl, io);
2001 }
2002
2003 static ISADeviceInfo isa_fdc_info = {
2004 .init = isabus_fdc_init1,
2005 .qdev.name = "isa-fdc",
2006 .qdev.size = sizeof(fdctrl_isabus_t),
2007 .qdev.no_user = 1,
2008 .qdev.reset = fdctrl_external_reset_isa,
2009 .qdev.props = (Property[]) {
2010 DEFINE_PROP_DRIVE("driveA", fdctrl_isabus_t, state.drives[0].dinfo),
2011 DEFINE_PROP_DRIVE("driveB", fdctrl_isabus_t, state.drives[1].dinfo),
2012 DEFINE_PROP_END_OF_LIST(),
2013 },
2014 };
2015
2016 static SysBusDeviceInfo sysbus_fdc_info = {
2017 .init = sysbus_fdc_init1,
2018 .qdev.name = "sysbus-fdc",
2019 .qdev.size = sizeof(fdctrl_sysbus_t),
2020 .qdev.reset = fdctrl_external_reset_sysbus,
2021 .qdev.props = (Property[]) {
2022 DEFINE_PROP_DRIVE("driveA", fdctrl_sysbus_t, state.drives[0].dinfo),
2023 DEFINE_PROP_DRIVE("driveB", fdctrl_sysbus_t, state.drives[1].dinfo),
2024 DEFINE_PROP_END_OF_LIST(),
2025 },
2026 };
2027
2028 static SysBusDeviceInfo sun4m_fdc_info = {
2029 .init = sun4m_fdc_init1,
2030 .qdev.name = "SUNW,fdtwo",
2031 .qdev.size = sizeof(fdctrl_sysbus_t),
2032 .qdev.reset = fdctrl_external_reset_sysbus,
2033 .qdev.props = (Property[]) {
2034 DEFINE_PROP_DRIVE("drive", fdctrl_sysbus_t, state.drives[0].dinfo),
2035 DEFINE_PROP_END_OF_LIST(),
2036 },
2037 };
2038
2039 static void fdc_register_devices(void)
2040 {
2041 isa_qdev_register(&isa_fdc_info);
2042 sysbus_register_withprop(&sysbus_fdc_info);
2043 sysbus_register_withprop(&sun4m_fdc_info);
2044 }
2045
2046 device_init(fdc_register_devices)
Qemu copy for testing