]> git.proxmox.com Git - qemu.git/blob - hw/fdc.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
sun4u: implement interrupt clearing registers
[qemu.git] / hw / fdc.c
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37 #include "blockdev.h"
38 #include "sysemu.h"
39
40 /********************************************************/
41 /* debug Floppy devices */
42 //#define DEBUG_FLOPPY
43
44 #ifdef DEBUG_FLOPPY
45 #define FLOPPY_DPRINTF(fmt, ...) \
46 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
47 #else
48 #define FLOPPY_DPRINTF(fmt, ...)
49 #endif
50
51 #define FLOPPY_ERROR(fmt, ...) \
52 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
53
54 /********************************************************/
55 /* Floppy drive emulation */
56
57 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
58 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
59
60 /* Will always be a fixed parameter for us */
61 #define FD_SECTOR_LEN 512
62 #define FD_SECTOR_SC 2 /* Sector size code */
63 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
64
65 typedef struct FDCtrl FDCtrl;
66
67 /* Floppy disk drive emulation */
68 typedef enum FDiskFlags {
69 FDISK_DBL_SIDES = 0x01,
70 } FDiskFlags;
71
72 typedef struct FDrive {
73 FDCtrl *fdctrl;
74 BlockDriverState *bs;
75 /* Drive status */
76 FDriveType drive;
77 uint8_t perpendicular; /* 2.88 MB access mode */
78 /* Position */
79 uint8_t head;
80 uint8_t track;
81 uint8_t sect;
82 /* Media */
83 FDiskFlags flags;
84 uint8_t last_sect; /* Nb sector per track */
85 uint8_t max_track; /* Nb of tracks */
86 uint16_t bps; /* Bytes per sector */
87 uint8_t ro; /* Is read-only */
88 uint8_t media_changed; /* Is media changed */
89 uint8_t media_rate; /* Data rate of medium */
90 } FDrive;
91
92 static void fd_init(FDrive *drv)
93 {
94 /* Drive */
95 drv->drive = FDRIVE_DRV_NONE;
96 drv->perpendicular = 0;
97 /* Disk */
98 drv->last_sect = 0;
99 drv->max_track = 0;
100 }
101
102 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
103
104 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
105 uint8_t last_sect, uint8_t num_sides)
106 {
107 return (((track * num_sides) + head) * last_sect) + sect - 1;
108 }
109
110 /* Returns current position, in sectors, for given drive */
111 static int fd_sector(FDrive *drv)
112 {
113 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
114 NUM_SIDES(drv));
115 }
116
117 /* Seek to a new position:
118 * returns 0 if already on right track
119 * returns 1 if track changed
120 * returns 2 if track is invalid
121 * returns 3 if sector is invalid
122 * returns 4 if seek is disabled
123 */
124 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
125 int enable_seek)
126 {
127 uint32_t sector;
128 int ret;
129
130 if (track > drv->max_track ||
131 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
132 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
133 head, track, sect, 1,
134 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
135 drv->max_track, drv->last_sect);
136 return 2;
137 }
138 if (sect > drv->last_sect) {
139 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
140 head, track, sect, 1,
141 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
142 drv->max_track, drv->last_sect);
143 return 3;
144 }
145 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
146 ret = 0;
147 if (sector != fd_sector(drv)) {
148 #if 0
149 if (!enable_seek) {
150 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
151 head, track, sect, 1, drv->max_track, drv->last_sect);
152 return 4;
153 }
154 #endif
155 drv->head = head;
156 if (drv->track != track)
157 ret = 1;
158 drv->track = track;
159 drv->sect = sect;
160 }
161
162 return ret;
163 }
164
165 /* Set drive back to track 0 */
166 static void fd_recalibrate(FDrive *drv)
167 {
168 FLOPPY_DPRINTF("recalibrate\n");
169 drv->head = 0;
170 drv->track = 0;
171 drv->sect = 1;
172 }
173
174 /* Revalidate a disk drive after a disk change */
175 static void fd_revalidate(FDrive *drv)
176 {
177 int nb_heads, max_track, last_sect, ro;
178 FDriveType drive;
179 FDriveRate rate;
180
181 FLOPPY_DPRINTF("revalidate\n");
182 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
183 ro = bdrv_is_read_only(drv->bs);
184 bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,
185 &last_sect, drv->drive, &drive, &rate);
186 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
187 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
188 nb_heads - 1, max_track, last_sect);
189 } else {
190 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
191 max_track, last_sect, ro ? "ro" : "rw");
192 }
193 if (nb_heads == 1) {
194 drv->flags &= ~FDISK_DBL_SIDES;
195 } else {
196 drv->flags |= FDISK_DBL_SIDES;
197 }
198 drv->max_track = max_track;
199 drv->last_sect = last_sect;
200 drv->ro = ro;
201 drv->drive = drive;
202 drv->media_rate = rate;
203 } else {
204 FLOPPY_DPRINTF("No disk in drive\n");
205 drv->last_sect = 0;
206 drv->max_track = 0;
207 drv->flags &= ~FDISK_DBL_SIDES;
208 }
209 }
210
211 /********************************************************/
212 /* Intel 82078 floppy disk controller emulation */
213
214 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
215 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
216 static int fdctrl_transfer_handler (void *opaque, int nchan,
217 int dma_pos, int dma_len);
218 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
219 static FDrive *get_cur_drv(FDCtrl *fdctrl);
220
221 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
222 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
223 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
224 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
225 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
226 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
227 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
228 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
229 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
230 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
231 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
232 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
233
234 enum {
235 FD_DIR_WRITE = 0,
236 FD_DIR_READ = 1,
237 FD_DIR_SCANE = 2,
238 FD_DIR_SCANL = 3,
239 FD_DIR_SCANH = 4,
240 };
241
242 enum {
243 FD_STATE_MULTI = 0x01, /* multi track flag */
244 FD_STATE_FORMAT = 0x02, /* format flag */
245 FD_STATE_SEEK = 0x04, /* seek flag */
246 };
247
248 enum {
249 FD_REG_SRA = 0x00,
250 FD_REG_SRB = 0x01,
251 FD_REG_DOR = 0x02,
252 FD_REG_TDR = 0x03,
253 FD_REG_MSR = 0x04,
254 FD_REG_DSR = 0x04,
255 FD_REG_FIFO = 0x05,
256 FD_REG_DIR = 0x07,
257 FD_REG_CCR = 0x07,
258 };
259
260 enum {
261 FD_CMD_READ_TRACK = 0x02,
262 FD_CMD_SPECIFY = 0x03,
263 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
264 FD_CMD_WRITE = 0x05,
265 FD_CMD_READ = 0x06,
266 FD_CMD_RECALIBRATE = 0x07,
267 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
268 FD_CMD_WRITE_DELETED = 0x09,
269 FD_CMD_READ_ID = 0x0a,
270 FD_CMD_READ_DELETED = 0x0c,
271 FD_CMD_FORMAT_TRACK = 0x0d,
272 FD_CMD_DUMPREG = 0x0e,
273 FD_CMD_SEEK = 0x0f,
274 FD_CMD_VERSION = 0x10,
275 FD_CMD_SCAN_EQUAL = 0x11,
276 FD_CMD_PERPENDICULAR_MODE = 0x12,
277 FD_CMD_CONFIGURE = 0x13,
278 FD_CMD_LOCK = 0x14,
279 FD_CMD_VERIFY = 0x16,
280 FD_CMD_POWERDOWN_MODE = 0x17,
281 FD_CMD_PART_ID = 0x18,
282 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
283 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
284 FD_CMD_SAVE = 0x2e,
285 FD_CMD_OPTION = 0x33,
286 FD_CMD_RESTORE = 0x4e,
287 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
288 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
289 FD_CMD_FORMAT_AND_WRITE = 0xcd,
290 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
291 };
292
293 enum {
294 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
295 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
296 FD_CONFIG_POLL = 0x10, /* Poll enabled */
297 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
298 FD_CONFIG_EIS = 0x40, /* No implied seeks */
299 };
300
301 enum {
302 FD_SR0_EQPMT = 0x10,
303 FD_SR0_SEEK = 0x20,
304 FD_SR0_ABNTERM = 0x40,
305 FD_SR0_INVCMD = 0x80,
306 FD_SR0_RDYCHG = 0xc0,
307 };
308
309 enum {
310 FD_SR1_MA = 0x01, /* Missing address mark */
311 FD_SR1_NW = 0x02, /* Not writable */
312 FD_SR1_EC = 0x80, /* End of cylinder */
313 };
314
315 enum {
316 FD_SR2_SNS = 0x04, /* Scan not satisfied */
317 FD_SR2_SEH = 0x08, /* Scan equal hit */
318 };
319
320 enum {
321 FD_SRA_DIR = 0x01,
322 FD_SRA_nWP = 0x02,
323 FD_SRA_nINDX = 0x04,
324 FD_SRA_HDSEL = 0x08,
325 FD_SRA_nTRK0 = 0x10,
326 FD_SRA_STEP = 0x20,
327 FD_SRA_nDRV2 = 0x40,
328 FD_SRA_INTPEND = 0x80,
329 };
330
331 enum {
332 FD_SRB_MTR0 = 0x01,
333 FD_SRB_MTR1 = 0x02,
334 FD_SRB_WGATE = 0x04,
335 FD_SRB_RDATA = 0x08,
336 FD_SRB_WDATA = 0x10,
337 FD_SRB_DR0 = 0x20,
338 };
339
340 enum {
341 #if MAX_FD == 4
342 FD_DOR_SELMASK = 0x03,
343 #else
344 FD_DOR_SELMASK = 0x01,
345 #endif
346 FD_DOR_nRESET = 0x04,
347 FD_DOR_DMAEN = 0x08,
348 FD_DOR_MOTEN0 = 0x10,
349 FD_DOR_MOTEN1 = 0x20,
350 FD_DOR_MOTEN2 = 0x40,
351 FD_DOR_MOTEN3 = 0x80,
352 };
353
354 enum {
355 #if MAX_FD == 4
356 FD_TDR_BOOTSEL = 0x0c,
357 #else
358 FD_TDR_BOOTSEL = 0x04,
359 #endif
360 };
361
362 enum {
363 FD_DSR_DRATEMASK= 0x03,
364 FD_DSR_PWRDOWN = 0x40,
365 FD_DSR_SWRESET = 0x80,
366 };
367
368 enum {
369 FD_MSR_DRV0BUSY = 0x01,
370 FD_MSR_DRV1BUSY = 0x02,
371 FD_MSR_DRV2BUSY = 0x04,
372 FD_MSR_DRV3BUSY = 0x08,
373 FD_MSR_CMDBUSY = 0x10,
374 FD_MSR_NONDMA = 0x20,
375 FD_MSR_DIO = 0x40,
376 FD_MSR_RQM = 0x80,
377 };
378
379 enum {
380 FD_DIR_DSKCHG = 0x80,
381 };
382
383 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
384 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
385 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
386
387 struct FDCtrl {
388 MemoryRegion iomem;
389 qemu_irq irq;
390 /* Controller state */
391 QEMUTimer *result_timer;
392 int dma_chann;
393 /* Controller's identification */
394 uint8_t version;
395 /* HW */
396 uint8_t sra;
397 uint8_t srb;
398 uint8_t dor;
399 uint8_t dor_vmstate; /* only used as temp during vmstate */
400 uint8_t tdr;
401 uint8_t dsr;
402 uint8_t msr;
403 uint8_t cur_drv;
404 uint8_t status0;
405 uint8_t status1;
406 uint8_t status2;
407 /* Command FIFO */
408 uint8_t *fifo;
409 int32_t fifo_size;
410 uint32_t data_pos;
411 uint32_t data_len;
412 uint8_t data_state;
413 uint8_t data_dir;
414 uint8_t eot; /* last wanted sector */
415 /* States kept only to be returned back */
416 /* precompensation */
417 uint8_t precomp_trk;
418 uint8_t config;
419 uint8_t lock;
420 /* Power down config (also with status regB access mode */
421 uint8_t pwrd;
422 /* Floppy drives */
423 uint8_t num_floppies;
424 /* Sun4m quirks? */
425 int sun4m;
426 FDrive drives[MAX_FD];
427 int reset_sensei;
428 uint32_t check_media_rate;
429 /* Timers state */
430 uint8_t timer0;
431 uint8_t timer1;
432 };
433
434 typedef struct FDCtrlSysBus {
435 SysBusDevice busdev;
436 struct FDCtrl state;
437 } FDCtrlSysBus;
438
439 typedef struct FDCtrlISABus {
440 ISADevice busdev;
441 uint32_t iobase;
442 uint32_t irq;
443 uint32_t dma;
444 struct FDCtrl state;
445 int32_t bootindexA;
446 int32_t bootindexB;
447 } FDCtrlISABus;
448
449 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
450 {
451 FDCtrl *fdctrl = opaque;
452 uint32_t retval;
453
454 reg &= 7;
455 switch (reg) {
456 case FD_REG_SRA:
457 retval = fdctrl_read_statusA(fdctrl);
458 break;
459 case FD_REG_SRB:
460 retval = fdctrl_read_statusB(fdctrl);
461 break;
462 case FD_REG_DOR:
463 retval = fdctrl_read_dor(fdctrl);
464 break;
465 case FD_REG_TDR:
466 retval = fdctrl_read_tape(fdctrl);
467 break;
468 case FD_REG_MSR:
469 retval = fdctrl_read_main_status(fdctrl);
470 break;
471 case FD_REG_FIFO:
472 retval = fdctrl_read_data(fdctrl);
473 break;
474 case FD_REG_DIR:
475 retval = fdctrl_read_dir(fdctrl);
476 break;
477 default:
478 retval = (uint32_t)(-1);
479 break;
480 }
481 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
482
483 return retval;
484 }
485
486 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
487 {
488 FDCtrl *fdctrl = opaque;
489
490 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
491
492 reg &= 7;
493 switch (reg) {
494 case FD_REG_DOR:
495 fdctrl_write_dor(fdctrl, value);
496 break;
497 case FD_REG_TDR:
498 fdctrl_write_tape(fdctrl, value);
499 break;
500 case FD_REG_DSR:
501 fdctrl_write_rate(fdctrl, value);
502 break;
503 case FD_REG_FIFO:
504 fdctrl_write_data(fdctrl, value);
505 break;
506 case FD_REG_CCR:
507 fdctrl_write_ccr(fdctrl, value);
508 break;
509 default:
510 break;
511 }
512 }
513
514 static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
515 unsigned ize)
516 {
517 return fdctrl_read(opaque, (uint32_t)reg);
518 }
519
520 static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
521 uint64_t value, unsigned size)
522 {
523 fdctrl_write(opaque, (uint32_t)reg, value);
524 }
525
526 static const MemoryRegionOps fdctrl_mem_ops = {
527 .read = fdctrl_read_mem,
528 .write = fdctrl_write_mem,
529 .endianness = DEVICE_NATIVE_ENDIAN,
530 };
531
532 static const MemoryRegionOps fdctrl_mem_strict_ops = {
533 .read = fdctrl_read_mem,
534 .write = fdctrl_write_mem,
535 .endianness = DEVICE_NATIVE_ENDIAN,
536 .valid = {
537 .min_access_size = 1,
538 .max_access_size = 1,
539 },
540 };
541
542 static bool fdrive_media_changed_needed(void *opaque)
543 {
544 FDrive *drive = opaque;
545
546 return (drive->bs != NULL && drive->media_changed != 1);
547 }
548
549 static const VMStateDescription vmstate_fdrive_media_changed = {
550 .name = "fdrive/media_changed",
551 .version_id = 1,
552 .minimum_version_id = 1,
553 .minimum_version_id_old = 1,
554 .fields = (VMStateField[]) {
555 VMSTATE_UINT8(media_changed, FDrive),
556 VMSTATE_END_OF_LIST()
557 }
558 };
559
560 static bool fdrive_media_rate_needed(void *opaque)
561 {
562 FDrive *drive = opaque;
563
564 return drive->fdctrl->check_media_rate;
565 }
566
567 static const VMStateDescription vmstate_fdrive_media_rate = {
568 .name = "fdrive/media_rate",
569 .version_id = 1,
570 .minimum_version_id = 1,
571 .minimum_version_id_old = 1,
572 .fields = (VMStateField[]) {
573 VMSTATE_UINT8(media_rate, FDrive),
574 VMSTATE_END_OF_LIST()
575 }
576 };
577
578 static const VMStateDescription vmstate_fdrive = {
579 .name = "fdrive",
580 .version_id = 1,
581 .minimum_version_id = 1,
582 .minimum_version_id_old = 1,
583 .fields = (VMStateField[]) {
584 VMSTATE_UINT8(head, FDrive),
585 VMSTATE_UINT8(track, FDrive),
586 VMSTATE_UINT8(sect, FDrive),
587 VMSTATE_END_OF_LIST()
588 },
589 .subsections = (VMStateSubsection[]) {
590 {
591 .vmsd = &vmstate_fdrive_media_changed,
592 .needed = &fdrive_media_changed_needed,
593 } , {
594 .vmsd = &vmstate_fdrive_media_rate,
595 .needed = &fdrive_media_rate_needed,
596 } , {
597 /* empty */
598 }
599 }
600 };
601
602 static void fdc_pre_save(void *opaque)
603 {
604 FDCtrl *s = opaque;
605
606 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
607 }
608
609 static int fdc_post_load(void *opaque, int version_id)
610 {
611 FDCtrl *s = opaque;
612
613 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
614 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
615 return 0;
616 }
617
618 static const VMStateDescription vmstate_fdc = {
619 .name = "fdc",
620 .version_id = 2,
621 .minimum_version_id = 2,
622 .minimum_version_id_old = 2,
623 .pre_save = fdc_pre_save,
624 .post_load = fdc_post_load,
625 .fields = (VMStateField []) {
626 /* Controller State */
627 VMSTATE_UINT8(sra, FDCtrl),
628 VMSTATE_UINT8(srb, FDCtrl),
629 VMSTATE_UINT8(dor_vmstate, FDCtrl),
630 VMSTATE_UINT8(tdr, FDCtrl),
631 VMSTATE_UINT8(dsr, FDCtrl),
632 VMSTATE_UINT8(msr, FDCtrl),
633 VMSTATE_UINT8(status0, FDCtrl),
634 VMSTATE_UINT8(status1, FDCtrl),
635 VMSTATE_UINT8(status2, FDCtrl),
636 /* Command FIFO */
637 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
638 uint8_t),
639 VMSTATE_UINT32(data_pos, FDCtrl),
640 VMSTATE_UINT32(data_len, FDCtrl),
641 VMSTATE_UINT8(data_state, FDCtrl),
642 VMSTATE_UINT8(data_dir, FDCtrl),
643 VMSTATE_UINT8(eot, FDCtrl),
644 /* States kept only to be returned back */
645 VMSTATE_UINT8(timer0, FDCtrl),
646 VMSTATE_UINT8(timer1, FDCtrl),
647 VMSTATE_UINT8(precomp_trk, FDCtrl),
648 VMSTATE_UINT8(config, FDCtrl),
649 VMSTATE_UINT8(lock, FDCtrl),
650 VMSTATE_UINT8(pwrd, FDCtrl),
651 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
652 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
653 vmstate_fdrive, FDrive),
654 VMSTATE_END_OF_LIST()
655 }
656 };
657
658 static void fdctrl_external_reset_sysbus(DeviceState *d)
659 {
660 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
661 FDCtrl *s = &sys->state;
662
663 fdctrl_reset(s, 0);
664 }
665
666 static void fdctrl_external_reset_isa(DeviceState *d)
667 {
668 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
669 FDCtrl *s = &isa->state;
670
671 fdctrl_reset(s, 0);
672 }
673
674 static void fdctrl_handle_tc(void *opaque, int irq, int level)
675 {
676 //FDCtrl *s = opaque;
677
678 if (level) {
679 // XXX
680 FLOPPY_DPRINTF("TC pulsed\n");
681 }
682 }
683
684 /* Change IRQ state */
685 static void fdctrl_reset_irq(FDCtrl *fdctrl)
686 {
687 if (!(fdctrl->sra & FD_SRA_INTPEND))
688 return;
689 FLOPPY_DPRINTF("Reset interrupt\n");
690 qemu_set_irq(fdctrl->irq, 0);
691 fdctrl->sra &= ~FD_SRA_INTPEND;
692 }
693
694 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
695 {
696 /* Sparc mutation */
697 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
698 /* XXX: not sure */
699 fdctrl->msr &= ~FD_MSR_CMDBUSY;
700 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
701 fdctrl->status0 = status0;
702 return;
703 }
704 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
705 qemu_set_irq(fdctrl->irq, 1);
706 fdctrl->sra |= FD_SRA_INTPEND;
707 }
708 if (status0 & FD_SR0_SEEK) {
709 FDrive *cur_drv;
710 /* A seek clears the disk change line (if a disk is inserted) */
711 cur_drv = get_cur_drv(fdctrl);
712 if (cur_drv->max_track) {
713 cur_drv->media_changed = 0;
714 }
715 }
716
717 fdctrl->reset_sensei = 0;
718 fdctrl->status0 = status0;
719 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
720 }
721
722 /* Reset controller */
723 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
724 {
725 int i;
726
727 FLOPPY_DPRINTF("reset controller\n");
728 fdctrl_reset_irq(fdctrl);
729 /* Initialise controller */
730 fdctrl->sra = 0;
731 fdctrl->srb = 0xc0;
732 if (!fdctrl->drives[1].bs)
733 fdctrl->sra |= FD_SRA_nDRV2;
734 fdctrl->cur_drv = 0;
735 fdctrl->dor = FD_DOR_nRESET;
736 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
737 fdctrl->msr = FD_MSR_RQM;
738 /* FIFO state */
739 fdctrl->data_pos = 0;
740 fdctrl->data_len = 0;
741 fdctrl->data_state = 0;
742 fdctrl->data_dir = FD_DIR_WRITE;
743 for (i = 0; i < MAX_FD; i++)
744 fd_recalibrate(&fdctrl->drives[i]);
745 fdctrl_reset_fifo(fdctrl);
746 if (do_irq) {
747 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
748 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
749 }
750 }
751
752 static inline FDrive *drv0(FDCtrl *fdctrl)
753 {
754 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
755 }
756
757 static inline FDrive *drv1(FDCtrl *fdctrl)
758 {
759 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
760 return &fdctrl->drives[1];
761 else
762 return &fdctrl->drives[0];
763 }
764
765 #if MAX_FD == 4
766 static inline FDrive *drv2(FDCtrl *fdctrl)
767 {
768 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
769 return &fdctrl->drives[2];
770 else
771 return &fdctrl->drives[1];
772 }
773
774 static inline FDrive *drv3(FDCtrl *fdctrl)
775 {
776 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
777 return &fdctrl->drives[3];
778 else
779 return &fdctrl->drives[2];
780 }
781 #endif
782
783 static FDrive *get_cur_drv(FDCtrl *fdctrl)
784 {
785 switch (fdctrl->cur_drv) {
786 case 0: return drv0(fdctrl);
787 case 1: return drv1(fdctrl);
788 #if MAX_FD == 4
789 case 2: return drv2(fdctrl);
790 case 3: return drv3(fdctrl);
791 #endif
792 default: return NULL;
793 }
794 }
795
796 /* Status A register : 0x00 (read-only) */
797 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
798 {
799 uint32_t retval = fdctrl->sra;
800
801 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
802
803 return retval;
804 }
805
806 /* Status B register : 0x01 (read-only) */
807 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
808 {
809 uint32_t retval = fdctrl->srb;
810
811 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
812
813 return retval;
814 }
815
816 /* Digital output register : 0x02 */
817 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
818 {
819 uint32_t retval = fdctrl->dor;
820
821 /* Selected drive */
822 retval |= fdctrl->cur_drv;
823 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
824
825 return retval;
826 }
827
828 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
829 {
830 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
831
832 /* Motors */
833 if (value & FD_DOR_MOTEN0)
834 fdctrl->srb |= FD_SRB_MTR0;
835 else
836 fdctrl->srb &= ~FD_SRB_MTR0;
837 if (value & FD_DOR_MOTEN1)
838 fdctrl->srb |= FD_SRB_MTR1;
839 else
840 fdctrl->srb &= ~FD_SRB_MTR1;
841
842 /* Drive */
843 if (value & 1)
844 fdctrl->srb |= FD_SRB_DR0;
845 else
846 fdctrl->srb &= ~FD_SRB_DR0;
847
848 /* Reset */
849 if (!(value & FD_DOR_nRESET)) {
850 if (fdctrl->dor & FD_DOR_nRESET) {
851 FLOPPY_DPRINTF("controller enter RESET state\n");
852 }
853 } else {
854 if (!(fdctrl->dor & FD_DOR_nRESET)) {
855 FLOPPY_DPRINTF("controller out of RESET state\n");
856 fdctrl_reset(fdctrl, 1);
857 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
858 }
859 }
860 /* Selected drive */
861 fdctrl->cur_drv = value & FD_DOR_SELMASK;
862
863 fdctrl->dor = value;
864 }
865
866 /* Tape drive register : 0x03 */
867 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
868 {
869 uint32_t retval = fdctrl->tdr;
870
871 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
872
873 return retval;
874 }
875
876 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
877 {
878 /* Reset mode */
879 if (!(fdctrl->dor & FD_DOR_nRESET)) {
880 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
881 return;
882 }
883 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
884 /* Disk boot selection indicator */
885 fdctrl->tdr = value & FD_TDR_BOOTSEL;
886 /* Tape indicators: never allow */
887 }
888
889 /* Main status register : 0x04 (read) */
890 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
891 {
892 uint32_t retval = fdctrl->msr;
893
894 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
895 fdctrl->dor |= FD_DOR_nRESET;
896
897 /* Sparc mutation */
898 if (fdctrl->sun4m) {
899 retval |= FD_MSR_DIO;
900 fdctrl_reset_irq(fdctrl);
901 };
902
903 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
904
905 return retval;
906 }
907
908 /* Data select rate register : 0x04 (write) */
909 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
910 {
911 /* Reset mode */
912 if (!(fdctrl->dor & FD_DOR_nRESET)) {
913 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
914 return;
915 }
916 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
917 /* Reset: autoclear */
918 if (value & FD_DSR_SWRESET) {
919 fdctrl->dor &= ~FD_DOR_nRESET;
920 fdctrl_reset(fdctrl, 1);
921 fdctrl->dor |= FD_DOR_nRESET;
922 }
923 if (value & FD_DSR_PWRDOWN) {
924 fdctrl_reset(fdctrl, 1);
925 }
926 fdctrl->dsr = value;
927 }
928
929 /* Configuration control register: 0x07 (write) */
930 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
931 {
932 /* Reset mode */
933 if (!(fdctrl->dor & FD_DOR_nRESET)) {
934 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
935 return;
936 }
937 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
938
939 /* Only the rate selection bits used in AT mode, and we
940 * store those in the DSR.
941 */
942 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
943 (value & FD_DSR_DRATEMASK);
944 }
945
946 static int fdctrl_media_changed(FDrive *drv)
947 {
948 return drv->media_changed;
949 }
950
951 /* Digital input register : 0x07 (read-only) */
952 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
953 {
954 uint32_t retval = 0;
955
956 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
957 retval |= FD_DIR_DSKCHG;
958 }
959 if (retval != 0) {
960 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
961 }
962
963 return retval;
964 }
965
966 /* FIFO state control */
967 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
968 {
969 fdctrl->data_dir = FD_DIR_WRITE;
970 fdctrl->data_pos = 0;
971 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
972 }
973
974 /* Set FIFO status for the host to read */
975 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
976 {
977 fdctrl->data_dir = FD_DIR_READ;
978 fdctrl->data_len = fifo_len;
979 fdctrl->data_pos = 0;
980 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
981 if (do_irq)
982 fdctrl_raise_irq(fdctrl, 0x00);
983 }
984
985 /* Set an error: unimplemented/unknown command */
986 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
987 {
988 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
989 fdctrl->fifo[0] = FD_SR0_INVCMD;
990 fdctrl_set_fifo(fdctrl, 1, 0);
991 }
992
993 /* Seek to next sector */
994 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
995 {
996 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
997 cur_drv->head, cur_drv->track, cur_drv->sect,
998 fd_sector(cur_drv));
999 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1000 error in fact */
1001 if (cur_drv->sect >= cur_drv->last_sect ||
1002 cur_drv->sect == fdctrl->eot) {
1003 cur_drv->sect = 1;
1004 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1005 if (cur_drv->head == 0 &&
1006 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1007 cur_drv->head = 1;
1008 } else {
1009 cur_drv->head = 0;
1010 cur_drv->track++;
1011 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1012 return 0;
1013 }
1014 } else {
1015 cur_drv->track++;
1016 return 0;
1017 }
1018 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1019 cur_drv->head, cur_drv->track,
1020 cur_drv->sect, fd_sector(cur_drv));
1021 } else {
1022 cur_drv->sect++;
1023 }
1024 return 1;
1025 }
1026
1027 /* Callback for transfer end (stop or abort) */
1028 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1029 uint8_t status1, uint8_t status2)
1030 {
1031 FDrive *cur_drv;
1032
1033 cur_drv = get_cur_drv(fdctrl);
1034 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1035 status0, status1, status2,
1036 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1037 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1038 fdctrl->fifo[1] = status1;
1039 fdctrl->fifo[2] = status2;
1040 fdctrl->fifo[3] = cur_drv->track;
1041 fdctrl->fifo[4] = cur_drv->head;
1042 fdctrl->fifo[5] = cur_drv->sect;
1043 fdctrl->fifo[6] = FD_SECTOR_SC;
1044 fdctrl->data_dir = FD_DIR_READ;
1045 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1046 DMA_release_DREQ(fdctrl->dma_chann);
1047 }
1048 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1049 fdctrl->msr &= ~FD_MSR_NONDMA;
1050 fdctrl_set_fifo(fdctrl, 7, 1);
1051 }
1052
1053 /* Prepare a data transfer (either DMA or FIFO) */
1054 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1055 {
1056 FDrive *cur_drv;
1057 uint8_t kh, kt, ks;
1058 int did_seek = 0;
1059
1060 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1061 cur_drv = get_cur_drv(fdctrl);
1062 kt = fdctrl->fifo[2];
1063 kh = fdctrl->fifo[3];
1064 ks = fdctrl->fifo[4];
1065 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1066 GET_CUR_DRV(fdctrl), kh, kt, ks,
1067 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1068 NUM_SIDES(cur_drv)));
1069 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1070 case 2:
1071 /* sect too big */
1072 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1073 fdctrl->fifo[3] = kt;
1074 fdctrl->fifo[4] = kh;
1075 fdctrl->fifo[5] = ks;
1076 return;
1077 case 3:
1078 /* track too big */
1079 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1080 fdctrl->fifo[3] = kt;
1081 fdctrl->fifo[4] = kh;
1082 fdctrl->fifo[5] = ks;
1083 return;
1084 case 4:
1085 /* No seek enabled */
1086 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1087 fdctrl->fifo[3] = kt;
1088 fdctrl->fifo[4] = kh;
1089 fdctrl->fifo[5] = ks;
1090 return;
1091 case 1:
1092 did_seek = 1;
1093 break;
1094 default:
1095 break;
1096 }
1097
1098 /* Check the data rate. If the programmed data rate does not match
1099 * the currently inserted medium, the operation has to fail. */
1100 if (fdctrl->check_media_rate &&
1101 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1102 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1103 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1104 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1105 fdctrl->fifo[3] = kt;
1106 fdctrl->fifo[4] = kh;
1107 fdctrl->fifo[5] = ks;
1108 return;
1109 }
1110
1111 /* Set the FIFO state */
1112 fdctrl->data_dir = direction;
1113 fdctrl->data_pos = 0;
1114 fdctrl->msr |= FD_MSR_CMDBUSY;
1115 if (fdctrl->fifo[0] & 0x80)
1116 fdctrl->data_state |= FD_STATE_MULTI;
1117 else
1118 fdctrl->data_state &= ~FD_STATE_MULTI;
1119 if (did_seek)
1120 fdctrl->data_state |= FD_STATE_SEEK;
1121 else
1122 fdctrl->data_state &= ~FD_STATE_SEEK;
1123 if (fdctrl->fifo[5] == 00) {
1124 fdctrl->data_len = fdctrl->fifo[8];
1125 } else {
1126 int tmp;
1127 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1128 tmp = (fdctrl->fifo[6] - ks + 1);
1129 if (fdctrl->fifo[0] & 0x80)
1130 tmp += fdctrl->fifo[6];
1131 fdctrl->data_len *= tmp;
1132 }
1133 fdctrl->eot = fdctrl->fifo[6];
1134 if (fdctrl->dor & FD_DOR_DMAEN) {
1135 int dma_mode;
1136 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1137 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1138 dma_mode = (dma_mode >> 2) & 3;
1139 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1140 dma_mode, direction,
1141 (128 << fdctrl->fifo[5]) *
1142 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1143 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1144 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1145 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1146 (direction == FD_DIR_READ && dma_mode == 1)) {
1147 /* No access is allowed until DMA transfer has completed */
1148 fdctrl->msr &= ~FD_MSR_RQM;
1149 /* Now, we just have to wait for the DMA controller to
1150 * recall us...
1151 */
1152 DMA_hold_DREQ(fdctrl->dma_chann);
1153 DMA_schedule(fdctrl->dma_chann);
1154 return;
1155 } else {
1156 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1157 }
1158 }
1159 FLOPPY_DPRINTF("start non-DMA transfer\n");
1160 fdctrl->msr |= FD_MSR_NONDMA;
1161 if (direction != FD_DIR_WRITE)
1162 fdctrl->msr |= FD_MSR_DIO;
1163 /* IO based transfer: calculate len */
1164 fdctrl_raise_irq(fdctrl, 0x00);
1165
1166 return;
1167 }
1168
1169 /* Prepare a transfer of deleted data */
1170 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1171 {
1172 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1173
1174 /* We don't handle deleted data,
1175 * so we don't return *ANYTHING*
1176 */
1177 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1178 }
1179
1180 /* handlers for DMA transfers */
1181 static int fdctrl_transfer_handler (void *opaque, int nchan,
1182 int dma_pos, int dma_len)
1183 {
1184 FDCtrl *fdctrl;
1185 FDrive *cur_drv;
1186 int len, start_pos, rel_pos;
1187 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1188
1189 fdctrl = opaque;
1190 if (fdctrl->msr & FD_MSR_RQM) {
1191 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1192 return 0;
1193 }
1194 cur_drv = get_cur_drv(fdctrl);
1195 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1196 fdctrl->data_dir == FD_DIR_SCANH)
1197 status2 = FD_SR2_SNS;
1198 if (dma_len > fdctrl->data_len)
1199 dma_len = fdctrl->data_len;
1200 if (cur_drv->bs == NULL) {
1201 if (fdctrl->data_dir == FD_DIR_WRITE)
1202 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1203 else
1204 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1205 len = 0;
1206 goto transfer_error;
1207 }
1208 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1209 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1210 len = dma_len - fdctrl->data_pos;
1211 if (len + rel_pos > FD_SECTOR_LEN)
1212 len = FD_SECTOR_LEN - rel_pos;
1213 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1214 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1215 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1216 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1217 fd_sector(cur_drv) * FD_SECTOR_LEN);
1218 if (fdctrl->data_dir != FD_DIR_WRITE ||
1219 len < FD_SECTOR_LEN || rel_pos != 0) {
1220 /* READ & SCAN commands and realign to a sector for WRITE */
1221 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1222 fdctrl->fifo, 1) < 0) {
1223 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1224 fd_sector(cur_drv));
1225 /* Sure, image size is too small... */
1226 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1227 }
1228 }
1229 switch (fdctrl->data_dir) {
1230 case FD_DIR_READ:
1231 /* READ commands */
1232 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1233 fdctrl->data_pos, len);
1234 break;
1235 case FD_DIR_WRITE:
1236 /* WRITE commands */
1237 if (cur_drv->ro) {
1238 /* Handle readonly medium early, no need to do DMA, touch the
1239 * LED or attempt any writes. A real floppy doesn't attempt
1240 * to write to readonly media either. */
1241 fdctrl_stop_transfer(fdctrl,
1242 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1243 0x00);
1244 goto transfer_error;
1245 }
1246
1247 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1248 fdctrl->data_pos, len);
1249 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1250 fdctrl->fifo, 1) < 0) {
1251 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1252 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1253 goto transfer_error;
1254 }
1255 break;
1256 default:
1257 /* SCAN commands */
1258 {
1259 uint8_t tmpbuf[FD_SECTOR_LEN];
1260 int ret;
1261 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1262 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1263 if (ret == 0) {
1264 status2 = FD_SR2_SEH;
1265 goto end_transfer;
1266 }
1267 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1268 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1269 status2 = 0x00;
1270 goto end_transfer;
1271 }
1272 }
1273 break;
1274 }
1275 fdctrl->data_pos += len;
1276 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1277 if (rel_pos == 0) {
1278 /* Seek to next sector */
1279 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1280 break;
1281 }
1282 }
1283 end_transfer:
1284 len = fdctrl->data_pos - start_pos;
1285 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1286 fdctrl->data_pos, len, fdctrl->data_len);
1287 if (fdctrl->data_dir == FD_DIR_SCANE ||
1288 fdctrl->data_dir == FD_DIR_SCANL ||
1289 fdctrl->data_dir == FD_DIR_SCANH)
1290 status2 = FD_SR2_SEH;
1291 if (FD_DID_SEEK(fdctrl->data_state))
1292 status0 |= FD_SR0_SEEK;
1293 fdctrl->data_len -= len;
1294 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1295 transfer_error:
1296
1297 return len;
1298 }
1299
1300 /* Data register : 0x05 */
1301 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1302 {
1303 FDrive *cur_drv;
1304 uint32_t retval = 0;
1305 int pos;
1306
1307 cur_drv = get_cur_drv(fdctrl);
1308 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1309 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1310 FLOPPY_ERROR("controller not ready for reading\n");
1311 return 0;
1312 }
1313 pos = fdctrl->data_pos;
1314 if (fdctrl->msr & FD_MSR_NONDMA) {
1315 pos %= FD_SECTOR_LEN;
1316 if (pos == 0) {
1317 if (fdctrl->data_pos != 0)
1318 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1319 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1320 fd_sector(cur_drv));
1321 return 0;
1322 }
1323 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1324 FLOPPY_DPRINTF("error getting sector %d\n",
1325 fd_sector(cur_drv));
1326 /* Sure, image size is too small... */
1327 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1328 }
1329 }
1330 }
1331 retval = fdctrl->fifo[pos];
1332 if (++fdctrl->data_pos == fdctrl->data_len) {
1333 fdctrl->data_pos = 0;
1334 /* Switch from transfer mode to status mode
1335 * then from status mode to command mode
1336 */
1337 if (fdctrl->msr & FD_MSR_NONDMA) {
1338 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1339 } else {
1340 fdctrl_reset_fifo(fdctrl);
1341 fdctrl_reset_irq(fdctrl);
1342 }
1343 }
1344 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1345
1346 return retval;
1347 }
1348
1349 static void fdctrl_format_sector(FDCtrl *fdctrl)
1350 {
1351 FDrive *cur_drv;
1352 uint8_t kh, kt, ks;
1353
1354 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1355 cur_drv = get_cur_drv(fdctrl);
1356 kt = fdctrl->fifo[6];
1357 kh = fdctrl->fifo[7];
1358 ks = fdctrl->fifo[8];
1359 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1360 GET_CUR_DRV(fdctrl), kh, kt, ks,
1361 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1362 NUM_SIDES(cur_drv)));
1363 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1364 case 2:
1365 /* sect too big */
1366 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1367 fdctrl->fifo[3] = kt;
1368 fdctrl->fifo[4] = kh;
1369 fdctrl->fifo[5] = ks;
1370 return;
1371 case 3:
1372 /* track too big */
1373 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1374 fdctrl->fifo[3] = kt;
1375 fdctrl->fifo[4] = kh;
1376 fdctrl->fifo[5] = ks;
1377 return;
1378 case 4:
1379 /* No seek enabled */
1380 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1381 fdctrl->fifo[3] = kt;
1382 fdctrl->fifo[4] = kh;
1383 fdctrl->fifo[5] = ks;
1384 return;
1385 case 1:
1386 fdctrl->data_state |= FD_STATE_SEEK;
1387 break;
1388 default:
1389 break;
1390 }
1391 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1392 if (cur_drv->bs == NULL ||
1393 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1394 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1395 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1396 } else {
1397 if (cur_drv->sect == cur_drv->last_sect) {
1398 fdctrl->data_state &= ~FD_STATE_FORMAT;
1399 /* Last sector done */
1400 if (FD_DID_SEEK(fdctrl->data_state))
1401 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1402 else
1403 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1404 } else {
1405 /* More to do */
1406 fdctrl->data_pos = 0;
1407 fdctrl->data_len = 4;
1408 }
1409 }
1410 }
1411
1412 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1413 {
1414 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1415 fdctrl->fifo[0] = fdctrl->lock << 4;
1416 fdctrl_set_fifo(fdctrl, 1, 0);
1417 }
1418
1419 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1420 {
1421 FDrive *cur_drv = get_cur_drv(fdctrl);
1422
1423 /* Drives position */
1424 fdctrl->fifo[0] = drv0(fdctrl)->track;
1425 fdctrl->fifo[1] = drv1(fdctrl)->track;
1426 #if MAX_FD == 4
1427 fdctrl->fifo[2] = drv2(fdctrl)->track;
1428 fdctrl->fifo[3] = drv3(fdctrl)->track;
1429 #else
1430 fdctrl->fifo[2] = 0;
1431 fdctrl->fifo[3] = 0;
1432 #endif
1433 /* timers */
1434 fdctrl->fifo[4] = fdctrl->timer0;
1435 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1436 fdctrl->fifo[6] = cur_drv->last_sect;
1437 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1438 (cur_drv->perpendicular << 2);
1439 fdctrl->fifo[8] = fdctrl->config;
1440 fdctrl->fifo[9] = fdctrl->precomp_trk;
1441 fdctrl_set_fifo(fdctrl, 10, 0);
1442 }
1443
1444 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1445 {
1446 /* Controller's version */
1447 fdctrl->fifo[0] = fdctrl->version;
1448 fdctrl_set_fifo(fdctrl, 1, 0);
1449 }
1450
1451 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1452 {
1453 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1454 fdctrl_set_fifo(fdctrl, 1, 0);
1455 }
1456
1457 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1458 {
1459 FDrive *cur_drv = get_cur_drv(fdctrl);
1460
1461 /* Drives position */
1462 drv0(fdctrl)->track = fdctrl->fifo[3];
1463 drv1(fdctrl)->track = fdctrl->fifo[4];
1464 #if MAX_FD == 4
1465 drv2(fdctrl)->track = fdctrl->fifo[5];
1466 drv3(fdctrl)->track = fdctrl->fifo[6];
1467 #endif
1468 /* timers */
1469 fdctrl->timer0 = fdctrl->fifo[7];
1470 fdctrl->timer1 = fdctrl->fifo[8];
1471 cur_drv->last_sect = fdctrl->fifo[9];
1472 fdctrl->lock = fdctrl->fifo[10] >> 7;
1473 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1474 fdctrl->config = fdctrl->fifo[11];
1475 fdctrl->precomp_trk = fdctrl->fifo[12];
1476 fdctrl->pwrd = fdctrl->fifo[13];
1477 fdctrl_reset_fifo(fdctrl);
1478 }
1479
1480 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1481 {
1482 FDrive *cur_drv = get_cur_drv(fdctrl);
1483
1484 fdctrl->fifo[0] = 0;
1485 fdctrl->fifo[1] = 0;
1486 /* Drives position */
1487 fdctrl->fifo[2] = drv0(fdctrl)->track;
1488 fdctrl->fifo[3] = drv1(fdctrl)->track;
1489 #if MAX_FD == 4
1490 fdctrl->fifo[4] = drv2(fdctrl)->track;
1491 fdctrl->fifo[5] = drv3(fdctrl)->track;
1492 #else
1493 fdctrl->fifo[4] = 0;
1494 fdctrl->fifo[5] = 0;
1495 #endif
1496 /* timers */
1497 fdctrl->fifo[6] = fdctrl->timer0;
1498 fdctrl->fifo[7] = fdctrl->timer1;
1499 fdctrl->fifo[8] = cur_drv->last_sect;
1500 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1501 (cur_drv->perpendicular << 2);
1502 fdctrl->fifo[10] = fdctrl->config;
1503 fdctrl->fifo[11] = fdctrl->precomp_trk;
1504 fdctrl->fifo[12] = fdctrl->pwrd;
1505 fdctrl->fifo[13] = 0;
1506 fdctrl->fifo[14] = 0;
1507 fdctrl_set_fifo(fdctrl, 15, 0);
1508 }
1509
1510 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1511 {
1512 FDrive *cur_drv = get_cur_drv(fdctrl);
1513
1514 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1515 qemu_mod_timer(fdctrl->result_timer,
1516 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1517 }
1518
1519 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1520 {
1521 FDrive *cur_drv;
1522
1523 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1524 cur_drv = get_cur_drv(fdctrl);
1525 fdctrl->data_state |= FD_STATE_FORMAT;
1526 if (fdctrl->fifo[0] & 0x80)
1527 fdctrl->data_state |= FD_STATE_MULTI;
1528 else
1529 fdctrl->data_state &= ~FD_STATE_MULTI;
1530 fdctrl->data_state &= ~FD_STATE_SEEK;
1531 cur_drv->bps =
1532 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1533 #if 0
1534 cur_drv->last_sect =
1535 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1536 fdctrl->fifo[3] / 2;
1537 #else
1538 cur_drv->last_sect = fdctrl->fifo[3];
1539 #endif
1540 /* TODO: implement format using DMA expected by the Bochs BIOS
1541 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1542 * the sector with the specified fill byte
1543 */
1544 fdctrl->data_state &= ~FD_STATE_FORMAT;
1545 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1546 }
1547
1548 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1549 {
1550 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1551 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1552 if (fdctrl->fifo[2] & 1)
1553 fdctrl->dor &= ~FD_DOR_DMAEN;
1554 else
1555 fdctrl->dor |= FD_DOR_DMAEN;
1556 /* No result back */
1557 fdctrl_reset_fifo(fdctrl);
1558 }
1559
1560 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1561 {
1562 FDrive *cur_drv;
1563
1564 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1565 cur_drv = get_cur_drv(fdctrl);
1566 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1567 /* 1 Byte status back */
1568 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1569 (cur_drv->track == 0 ? 0x10 : 0x00) |
1570 (cur_drv->head << 2) |
1571 GET_CUR_DRV(fdctrl) |
1572 0x28;
1573 fdctrl_set_fifo(fdctrl, 1, 0);
1574 }
1575
1576 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1577 {
1578 FDrive *cur_drv;
1579
1580 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1581 cur_drv = get_cur_drv(fdctrl);
1582 fd_recalibrate(cur_drv);
1583 fdctrl_reset_fifo(fdctrl);
1584 /* Raise Interrupt */
1585 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1586 }
1587
1588 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1589 {
1590 FDrive *cur_drv = get_cur_drv(fdctrl);
1591
1592 if(fdctrl->reset_sensei > 0) {
1593 fdctrl->fifo[0] =
1594 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1595 fdctrl->reset_sensei--;
1596 } else {
1597 /* XXX: status0 handling is broken for read/write
1598 commands, so we do this hack. It should be suppressed
1599 ASAP */
1600 fdctrl->fifo[0] =
1601 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1602 }
1603
1604 fdctrl->fifo[1] = cur_drv->track;
1605 fdctrl_set_fifo(fdctrl, 2, 0);
1606 fdctrl_reset_irq(fdctrl);
1607 fdctrl->status0 = FD_SR0_RDYCHG;
1608 }
1609
1610 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1611 {
1612 FDrive *cur_drv;
1613
1614 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1615 cur_drv = get_cur_drv(fdctrl);
1616 fdctrl_reset_fifo(fdctrl);
1617 /* The seek command just sends step pulses to the drive and doesn't care if
1618 * there is a medium inserted of if it's banging the head against the drive.
1619 */
1620 if (fdctrl->fifo[2] > cur_drv->max_track) {
1621 cur_drv->track = cur_drv->max_track;
1622 } else {
1623 cur_drv->track = fdctrl->fifo[2];
1624 }
1625 /* Raise Interrupt */
1626 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1627 }
1628
1629 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1630 {
1631 FDrive *cur_drv = get_cur_drv(fdctrl);
1632
1633 if (fdctrl->fifo[1] & 0x80)
1634 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1635 /* No result back */
1636 fdctrl_reset_fifo(fdctrl);
1637 }
1638
1639 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1640 {
1641 fdctrl->config = fdctrl->fifo[2];
1642 fdctrl->precomp_trk = fdctrl->fifo[3];
1643 /* No result back */
1644 fdctrl_reset_fifo(fdctrl);
1645 }
1646
1647 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1648 {
1649 fdctrl->pwrd = fdctrl->fifo[1];
1650 fdctrl->fifo[0] = fdctrl->fifo[1];
1651 fdctrl_set_fifo(fdctrl, 1, 0);
1652 }
1653
1654 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1655 {
1656 /* No result back */
1657 fdctrl_reset_fifo(fdctrl);
1658 }
1659
1660 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1661 {
1662 FDrive *cur_drv = get_cur_drv(fdctrl);
1663
1664 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1665 /* Command parameters done */
1666 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1667 fdctrl->fifo[0] = fdctrl->fifo[1];
1668 fdctrl->fifo[2] = 0;
1669 fdctrl->fifo[3] = 0;
1670 fdctrl_set_fifo(fdctrl, 4, 0);
1671 } else {
1672 fdctrl_reset_fifo(fdctrl);
1673 }
1674 } else if (fdctrl->data_len > 7) {
1675 /* ERROR */
1676 fdctrl->fifo[0] = 0x80 |
1677 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1678 fdctrl_set_fifo(fdctrl, 1, 0);
1679 }
1680 }
1681
1682 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1683 {
1684 FDrive *cur_drv;
1685
1686 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1687 cur_drv = get_cur_drv(fdctrl);
1688 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1689 cur_drv->track = cur_drv->max_track - 1;
1690 } else {
1691 cur_drv->track += fdctrl->fifo[2];
1692 }
1693 fdctrl_reset_fifo(fdctrl);
1694 /* Raise Interrupt */
1695 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1696 }
1697
1698 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1699 {
1700 FDrive *cur_drv;
1701
1702 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1703 cur_drv = get_cur_drv(fdctrl);
1704 if (fdctrl->fifo[2] > cur_drv->track) {
1705 cur_drv->track = 0;
1706 } else {
1707 cur_drv->track -= fdctrl->fifo[2];
1708 }
1709 fdctrl_reset_fifo(fdctrl);
1710 /* Raise Interrupt */
1711 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1712 }
1713
1714 static const struct {
1715 uint8_t value;
1716 uint8_t mask;
1717 const char* name;
1718 int parameters;
1719 void (*handler)(FDCtrl *fdctrl, int direction);
1720 int direction;
1721 } handlers[] = {
1722 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1723 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1724 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1725 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1726 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1727 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1728 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1729 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1730 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1731 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1732 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1733 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1734 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1735 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1736 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1737 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1738 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1739 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1740 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1741 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1742 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1743 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1744 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1745 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1746 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1747 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1748 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1749 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1750 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1751 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1752 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1753 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1754 };
1755 /* Associate command to an index in the 'handlers' array */
1756 static uint8_t command_to_handler[256];
1757
1758 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1759 {
1760 FDrive *cur_drv;
1761 int pos;
1762
1763 /* Reset mode */
1764 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1765 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1766 return;
1767 }
1768 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1769 FLOPPY_ERROR("controller not ready for writing\n");
1770 return;
1771 }
1772 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1773 /* Is it write command time ? */
1774 if (fdctrl->msr & FD_MSR_NONDMA) {
1775 /* FIFO data write */
1776 pos = fdctrl->data_pos++;
1777 pos %= FD_SECTOR_LEN;
1778 fdctrl->fifo[pos] = value;
1779 if (pos == FD_SECTOR_LEN - 1 ||
1780 fdctrl->data_pos == fdctrl->data_len) {
1781 cur_drv = get_cur_drv(fdctrl);
1782 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1783 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1784 return;
1785 }
1786 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1787 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1788 fd_sector(cur_drv));
1789 return;
1790 }
1791 }
1792 /* Switch from transfer mode to status mode
1793 * then from status mode to command mode
1794 */
1795 if (fdctrl->data_pos == fdctrl->data_len)
1796 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1797 return;
1798 }
1799 if (fdctrl->data_pos == 0) {
1800 /* Command */
1801 pos = command_to_handler[value & 0xff];
1802 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1803 fdctrl->data_len = handlers[pos].parameters + 1;
1804 fdctrl->msr |= FD_MSR_CMDBUSY;
1805 }
1806
1807 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1808 fdctrl->fifo[fdctrl->data_pos++] = value;
1809 if (fdctrl->data_pos == fdctrl->data_len) {
1810 /* We now have all parameters
1811 * and will be able to treat the command
1812 */
1813 if (fdctrl->data_state & FD_STATE_FORMAT) {
1814 fdctrl_format_sector(fdctrl);
1815 return;
1816 }
1817
1818 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1819 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1820 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1821 }
1822 }
1823
1824 static void fdctrl_result_timer(void *opaque)
1825 {
1826 FDCtrl *fdctrl = opaque;
1827 FDrive *cur_drv = get_cur_drv(fdctrl);
1828
1829 /* Pretend we are spinning.
1830 * This is needed for Coherent, which uses READ ID to check for
1831 * sector interleaving.
1832 */
1833 if (cur_drv->last_sect != 0) {
1834 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1835 }
1836 /* READ_ID can't automatically succeed! */
1837 if (fdctrl->check_media_rate &&
1838 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1839 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
1840 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1841 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1842 } else {
1843 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1844 }
1845 }
1846
1847 static void fdctrl_change_cb(void *opaque, bool load)
1848 {
1849 FDrive *drive = opaque;
1850
1851 drive->media_changed = 1;
1852 fd_revalidate(drive);
1853 }
1854
1855 static const BlockDevOps fdctrl_block_ops = {
1856 .change_media_cb = fdctrl_change_cb,
1857 };
1858
1859 /* Init functions */
1860 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1861 {
1862 unsigned int i;
1863 FDrive *drive;
1864
1865 for (i = 0; i < MAX_FD; i++) {
1866 drive = &fdctrl->drives[i];
1867 drive->fdctrl = fdctrl;
1868
1869 if (drive->bs) {
1870 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1871 error_report("fdc doesn't support drive option werror");
1872 return -1;
1873 }
1874 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1875 error_report("fdc doesn't support drive option rerror");
1876 return -1;
1877 }
1878 }
1879
1880 fd_init(drive);
1881 fd_revalidate(drive);
1882 if (drive->bs) {
1883 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
1884 }
1885 }
1886 return 0;
1887 }
1888
1889 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1890 target_phys_addr_t mmio_base, DriveInfo **fds)
1891 {
1892 FDCtrl *fdctrl;
1893 DeviceState *dev;
1894 FDCtrlSysBus *sys;
1895
1896 dev = qdev_create(NULL, "sysbus-fdc");
1897 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1898 fdctrl = &sys->state;
1899 fdctrl->dma_chann = dma_chann; /* FIXME */
1900 if (fds[0]) {
1901 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1902 }
1903 if (fds[1]) {
1904 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1905 }
1906 qdev_init_nofail(dev);
1907 sysbus_connect_irq(&sys->busdev, 0, irq);
1908 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1909 }
1910
1911 void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1912 DriveInfo **fds, qemu_irq *fdc_tc)
1913 {
1914 DeviceState *dev;
1915 FDCtrlSysBus *sys;
1916
1917 dev = qdev_create(NULL, "SUNW,fdtwo");
1918 if (fds[0]) {
1919 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1920 }
1921 qdev_init_nofail(dev);
1922 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1923 sysbus_connect_irq(&sys->busdev, 0, irq);
1924 sysbus_mmio_map(&sys->busdev, 0, io_base);
1925 *fdc_tc = qdev_get_gpio_in(dev, 0);
1926 }
1927
1928 static int fdctrl_init_common(FDCtrl *fdctrl)
1929 {
1930 int i, j;
1931 static int command_tables_inited = 0;
1932
1933 /* Fill 'command_to_handler' lookup table */
1934 if (!command_tables_inited) {
1935 command_tables_inited = 1;
1936 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1937 for (j = 0; j < sizeof(command_to_handler); j++) {
1938 if ((j & handlers[i].mask) == handlers[i].value) {
1939 command_to_handler[j] = i;
1940 }
1941 }
1942 }
1943 }
1944
1945 FLOPPY_DPRINTF("init controller\n");
1946 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1947 fdctrl->fifo_size = 512;
1948 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
1949 fdctrl_result_timer, fdctrl);
1950
1951 fdctrl->version = 0x90; /* Intel 82078 controller */
1952 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1953 fdctrl->num_floppies = MAX_FD;
1954
1955 if (fdctrl->dma_chann != -1)
1956 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1957 return fdctrl_connect_drives(fdctrl);
1958 }
1959
1960 static const MemoryRegionPortio fdc_portio_list[] = {
1961 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
1962 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
1963 PORTIO_END_OF_LIST(),
1964 };
1965
1966 static int isabus_fdc_init1(ISADevice *dev)
1967 {
1968 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1969 FDCtrl *fdctrl = &isa->state;
1970 int ret;
1971
1972 isa_register_portio_list(dev, isa->iobase, fdc_portio_list, fdctrl, "fdc");
1973
1974 isa_init_irq(&isa->busdev, &fdctrl->irq, isa->irq);
1975 fdctrl->dma_chann = isa->dma;
1976
1977 qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 2);
1978 ret = fdctrl_init_common(fdctrl);
1979
1980 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
1981 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
1982
1983 return ret;
1984 }
1985
1986 static int sysbus_fdc_init1(SysBusDevice *dev)
1987 {
1988 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
1989 FDCtrl *fdctrl = &sys->state;
1990 int ret;
1991
1992 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
1993 sysbus_init_mmio(dev, &fdctrl->iomem);
1994 sysbus_init_irq(dev, &fdctrl->irq);
1995 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1996 fdctrl->dma_chann = -1;
1997
1998 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
1999 ret = fdctrl_init_common(fdctrl);
2000
2001 return ret;
2002 }
2003
2004 static int sun4m_fdc_init1(SysBusDevice *dev)
2005 {
2006 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2007
2008 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
2009 "fdctrl", 0x08);
2010 sysbus_init_mmio(dev, &fdctrl->iomem);
2011 sysbus_init_irq(dev, &fdctrl->irq);
2012 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2013
2014 fdctrl->sun4m = 1;
2015 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2016 return fdctrl_init_common(fdctrl);
2017 }
2018
2019 void fdc_get_bs(BlockDriverState *bs[], ISADevice *dev)
2020 {
2021 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
2022 FDCtrl *fdctrl = &isa->state;
2023 int i;
2024
2025 for (i = 0; i < MAX_FD; i++) {
2026 bs[i] = fdctrl->drives[i].bs;
2027 }
2028 }
2029
2030
2031 static const VMStateDescription vmstate_isa_fdc ={
2032 .name = "fdc",
2033 .version_id = 2,
2034 .minimum_version_id = 2,
2035 .fields = (VMStateField []) {
2036 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2037 VMSTATE_END_OF_LIST()
2038 }
2039 };
2040
2041 static Property isa_fdc_properties[] = {
2042 DEFINE_PROP_HEX32("iobase", FDCtrlISABus, iobase, 0x3f0),
2043 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2044 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2045 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2046 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2047 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2048 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
2049 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2050 0, true),
2051 DEFINE_PROP_END_OF_LIST(),
2052 };
2053
2054 static void isabus_fdc_class_init1(ObjectClass *klass, void *data)
2055 {
2056 DeviceClass *dc = DEVICE_CLASS(klass);
2057 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
2058 ic->init = isabus_fdc_init1;
2059 dc->fw_name = "fdc";
2060 dc->no_user = 1;
2061 dc->reset = fdctrl_external_reset_isa;
2062 dc->vmsd = &vmstate_isa_fdc;
2063 dc->props = isa_fdc_properties;
2064 }
2065
2066 static TypeInfo isa_fdc_info = {
2067 .name = "isa-fdc",
2068 .parent = TYPE_ISA_DEVICE,
2069 .instance_size = sizeof(FDCtrlISABus),
2070 .class_init = isabus_fdc_class_init1,
2071 };
2072
2073 static const VMStateDescription vmstate_sysbus_fdc ={
2074 .name = "fdc",
2075 .version_id = 2,
2076 .minimum_version_id = 2,
2077 .fields = (VMStateField []) {
2078 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2079 VMSTATE_END_OF_LIST()
2080 }
2081 };
2082
2083 static Property sysbus_fdc_properties[] = {
2084 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2085 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2086 DEFINE_PROP_END_OF_LIST(),
2087 };
2088
2089 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2090 {
2091 DeviceClass *dc = DEVICE_CLASS(klass);
2092 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2093
2094 k->init = sysbus_fdc_init1;
2095 dc->reset = fdctrl_external_reset_sysbus;
2096 dc->vmsd = &vmstate_sysbus_fdc;
2097 dc->props = sysbus_fdc_properties;
2098 }
2099
2100 static TypeInfo sysbus_fdc_info = {
2101 .name = "sysbus-fdc",
2102 .parent = TYPE_SYS_BUS_DEVICE,
2103 .instance_size = sizeof(FDCtrlSysBus),
2104 .class_init = sysbus_fdc_class_init,
2105 };
2106
2107 static Property sun4m_fdc_properties[] = {
2108 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2109 DEFINE_PROP_END_OF_LIST(),
2110 };
2111
2112 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2113 {
2114 DeviceClass *dc = DEVICE_CLASS(klass);
2115 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2116
2117 k->init = sun4m_fdc_init1;
2118 dc->reset = fdctrl_external_reset_sysbus;
2119 dc->vmsd = &vmstate_sysbus_fdc;
2120 dc->props = sun4m_fdc_properties;
2121 }
2122
2123 static TypeInfo sun4m_fdc_info = {
2124 .name = "SUNW,fdtwo",
2125 .parent = TYPE_SYS_BUS_DEVICE,
2126 .instance_size = sizeof(FDCtrlSysBus),
2127 .class_init = sun4m_fdc_class_init,
2128 };
2129
2130 static void fdc_register_types(void)
2131 {
2132 type_register_static(&isa_fdc_info);
2133 type_register_static(&sysbus_fdc_info);
2134 type_register_static(&sun4m_fdc_info);
2135 }
2136
2137 type_init(fdc_register_types)
Qemu copy for testing