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FDC fix 7/10 (Hervé Poussineau):
[qemu.git] / hw / fdc.c
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29 #include "hw.h"
30 #include "fdc.h"
31 #include "block.h"
32 #include "qemu-timer.h"
33 #include "isa.h"
34
35 /********************************************************/
36 /* debug Floppy devices */
37 //#define DEBUG_FLOPPY
38
39 #ifdef DEBUG_FLOPPY
40 #define FLOPPY_DPRINTF(fmt, args...) \
41 do { printf("FLOPPY: " fmt , ##args); } while (0)
42 #else
43 #define FLOPPY_DPRINTF(fmt, args...)
44 #endif
45
46 #define FLOPPY_ERROR(fmt, args...) \
47 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ##args); } while (0)
48
49 /********************************************************/
50 /* Floppy drive emulation */
51
52 /* Will always be a fixed parameter for us */
53 #define FD_SECTOR_LEN 512
54 #define FD_SECTOR_SC 2 /* Sector size code */
55
56 /* Floppy disk drive emulation */
57 typedef enum fdisk_type_t {
58 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
59 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
60 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
61 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
62 FDRIVE_DISK_NONE = 0x05, /* No disk */
63 } fdisk_type_t;
64
65 typedef enum fdrive_type_t {
66 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
67 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
68 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
69 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
70 } fdrive_type_t;
71
72 typedef enum fdisk_flags_t {
73 FDISK_DBL_SIDES = 0x01,
74 } fdisk_flags_t;
75
76 typedef struct fdrive_t {
77 BlockDriverState *bs;
78 /* Drive status */
79 fdrive_type_t drive;
80 uint8_t perpendicular; /* 2.88 MB access mode */
81 /* Position */
82 uint8_t head;
83 uint8_t track;
84 uint8_t sect;
85 /* Media */
86 fdisk_flags_t flags;
87 uint8_t last_sect; /* Nb sector per track */
88 uint8_t max_track; /* Nb of tracks */
89 uint16_t bps; /* Bytes per sector */
90 uint8_t ro; /* Is read-only */
91 } fdrive_t;
92
93 static void fd_init (fdrive_t *drv, BlockDriverState *bs)
94 {
95 /* Drive */
96 drv->bs = bs;
97 drv->drive = FDRIVE_DRV_NONE;
98 drv->perpendicular = 0;
99 /* Disk */
100 drv->last_sect = 0;
101 drv->max_track = 0;
102 }
103
104 static int _fd_sector (uint8_t head, uint8_t track,
105 uint8_t sect, uint8_t last_sect)
106 {
107 return (((track * 2) + head) * last_sect) + sect - 1;
108 }
109
110 /* Returns current position, in sectors, for given drive */
111 static int fd_sector (fdrive_t *drv)
112 {
113 return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
114 }
115
116 /* Seek to a new position:
117 * returns 0 if already on right track
118 * returns 1 if track changed
119 * returns 2 if track is invalid
120 * returns 3 if sector is invalid
121 * returns 4 if seek is disabled
122 */
123 static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
124 int enable_seek)
125 {
126 uint32_t sector;
127 int ret;
128
129 if (track > drv->max_track ||
130 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
131 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
132 head, track, sect, 1,
133 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
134 drv->max_track, drv->last_sect);
135 return 2;
136 }
137 if (sect > drv->last_sect) {
138 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
139 head, track, sect, 1,
140 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
141 drv->max_track, drv->last_sect);
142 return 3;
143 }
144 sector = _fd_sector(head, track, sect, drv->last_sect);
145 ret = 0;
146 if (sector != fd_sector(drv)) {
147 #if 0
148 if (!enable_seek) {
149 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
150 head, track, sect, 1, drv->max_track, drv->last_sect);
151 return 4;
152 }
153 #endif
154 drv->head = head;
155 if (drv->track != track)
156 ret = 1;
157 drv->track = track;
158 drv->sect = sect;
159 }
160
161 return ret;
162 }
163
164 /* Set drive back to track 0 */
165 static void fd_recalibrate (fdrive_t *drv)
166 {
167 FLOPPY_DPRINTF("recalibrate\n");
168 drv->head = 0;
169 drv->track = 0;
170 drv->sect = 1;
171 }
172
173 /* Recognize floppy formats */
174 typedef struct fd_format_t {
175 fdrive_type_t drive;
176 fdisk_type_t disk;
177 uint8_t last_sect;
178 uint8_t max_track;
179 uint8_t max_head;
180 const char *str;
181 } fd_format_t;
182
183 static const fd_format_t fd_formats[] = {
184 /* First entry is default format */
185 /* 1.44 MB 3"1/2 floppy disks */
186 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
187 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
188 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
189 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
190 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
191 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
192 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
193 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
194 /* 2.88 MB 3"1/2 floppy disks */
195 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
196 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
197 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
198 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
199 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
200 /* 720 kB 3"1/2 floppy disks */
201 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
202 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
203 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
204 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
205 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
206 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
207 /* 1.2 MB 5"1/4 floppy disks */
208 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
209 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
210 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
211 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
212 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
213 /* 720 kB 5"1/4 floppy disks */
214 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
215 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
216 /* 360 kB 5"1/4 floppy disks */
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
219 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
220 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
221 /* 320 kB 5"1/4 floppy disks */
222 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
224 /* 360 kB must match 5"1/4 better than 3"1/2... */
225 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
226 /* end */
227 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
228 };
229
230 /* Revalidate a disk drive after a disk change */
231 static void fd_revalidate (fdrive_t *drv)
232 {
233 const fd_format_t *parse;
234 uint64_t nb_sectors, size;
235 int i, first_match, match;
236 int nb_heads, max_track, last_sect, ro;
237
238 FLOPPY_DPRINTF("revalidate\n");
239 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
240 ro = bdrv_is_read_only(drv->bs);
241 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
242 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
243 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
244 nb_heads - 1, max_track, last_sect);
245 } else {
246 bdrv_get_geometry(drv->bs, &nb_sectors);
247 match = -1;
248 first_match = -1;
249 for (i = 0;; i++) {
250 parse = &fd_formats[i];
251 if (parse->drive == FDRIVE_DRV_NONE)
252 break;
253 if (drv->drive == parse->drive ||
254 drv->drive == FDRIVE_DRV_NONE) {
255 size = (parse->max_head + 1) * parse->max_track *
256 parse->last_sect;
257 if (nb_sectors == size) {
258 match = i;
259 break;
260 }
261 if (first_match == -1)
262 first_match = i;
263 }
264 }
265 if (match == -1) {
266 if (first_match == -1)
267 match = 1;
268 else
269 match = first_match;
270 parse = &fd_formats[match];
271 }
272 nb_heads = parse->max_head + 1;
273 max_track = parse->max_track;
274 last_sect = parse->last_sect;
275 drv->drive = parse->drive;
276 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
277 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
278 }
279 if (nb_heads == 1) {
280 drv->flags &= ~FDISK_DBL_SIDES;
281 } else {
282 drv->flags |= FDISK_DBL_SIDES;
283 }
284 drv->max_track = max_track;
285 drv->last_sect = last_sect;
286 drv->ro = ro;
287 } else {
288 FLOPPY_DPRINTF("No disk in drive\n");
289 drv->last_sect = 0;
290 drv->max_track = 0;
291 drv->flags &= ~FDISK_DBL_SIDES;
292 }
293 }
294
295 /********************************************************/
296 /* Intel 82078 floppy disk controller emulation */
297
298 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
299 static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
300 static int fdctrl_transfer_handler (void *opaque, int nchan,
301 int dma_pos, int dma_len);
302 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
303
304 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
305 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
306 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
307 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
308 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
309 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
310 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
311 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
312 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
313 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
314 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
315
316 enum {
317 FD_DIR_WRITE = 0,
318 FD_DIR_READ = 1,
319 FD_DIR_SCANE = 2,
320 FD_DIR_SCANL = 3,
321 FD_DIR_SCANH = 4,
322 };
323
324 enum {
325 FD_STATE_MULTI = 0x01, /* multi track flag */
326 FD_STATE_FORMAT = 0x02, /* format flag */
327 FD_STATE_SEEK = 0x04, /* seek flag */
328 };
329
330 enum {
331 FD_REG_SRA = 0x00,
332 FD_REG_SRB = 0x01,
333 FD_REG_DOR = 0x02,
334 FD_REG_TDR = 0x03,
335 FD_REG_MSR = 0x04,
336 FD_REG_DSR = 0x04,
337 FD_REG_FIFO = 0x05,
338 FD_REG_DIR = 0x07,
339 };
340
341 enum {
342 FD_CMD_READ_TRACK = 0x02,
343 FD_CMD_SPECIFY = 0x03,
344 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
345 FD_CMD_WRITE = 0x05,
346 FD_CMD_READ = 0x06,
347 FD_CMD_RECALIBRATE = 0x07,
348 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
349 FD_CMD_WRITE_DELETED = 0x09,
350 FD_CMD_READ_ID = 0x0a,
351 FD_CMD_READ_DELETED = 0x0c,
352 FD_CMD_FORMAT_TRACK = 0x0d,
353 FD_CMD_DUMPREG = 0x0e,
354 FD_CMD_SEEK = 0x0f,
355 FD_CMD_VERSION = 0x10,
356 FD_CMD_SCAN_EQUAL = 0x11,
357 FD_CMD_PERPENDICULAR_MODE = 0x12,
358 FD_CMD_CONFIGURE = 0x13,
359 FD_CMD_LOCK = 0x14,
360 FD_CMD_VERIFY = 0x16,
361 FD_CMD_POWERDOWN_MODE = 0x17,
362 FD_CMD_PART_ID = 0x18,
363 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
364 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
365 FD_CMD_SAVE = 0x2c,
366 FD_CMD_OPTION = 0x33,
367 FD_CMD_RESTORE = 0x4c,
368 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
369 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
370 FD_CMD_FORMAT_AND_WRITE = 0xcd,
371 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
372 };
373
374 enum {
375 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
376 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
377 FD_CONFIG_POLL = 0x10, /* Poll enabled */
378 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
379 FD_CONFIG_EIS = 0x40, /* No implied seeks */
380 };
381
382 enum {
383 FD_SR0_EQPMT = 0x10,
384 FD_SR0_SEEK = 0x20,
385 FD_SR0_ABNTERM = 0x40,
386 FD_SR0_INVCMD = 0x80,
387 FD_SR0_RDYCHG = 0xc0,
388 };
389
390 enum {
391 FD_SR1_EC = 0x80, /* End of cylinder */
392 };
393
394 enum {
395 FD_SR2_SNS = 0x04, /* Scan not satisfied */
396 FD_SR2_SEH = 0x08, /* Scan equal hit */
397 };
398
399 enum {
400 FD_SRA_DIR = 0x01,
401 FD_SRA_nWP = 0x02,
402 FD_SRA_nINDX = 0x04,
403 FD_SRA_HDSEL = 0x08,
404 FD_SRA_nTRK0 = 0x10,
405 FD_SRA_STEP = 0x20,
406 FD_SRA_nDRV2 = 0x40,
407 FD_SRA_INTPEND = 0x80,
408 };
409
410 enum {
411 FD_SRB_MTR0 = 0x01,
412 FD_SRB_MTR1 = 0x02,
413 FD_SRB_WGATE = 0x04,
414 FD_SRB_RDATA = 0x08,
415 FD_SRB_WDATA = 0x10,
416 FD_SRB_DR0 = 0x20,
417 };
418
419 enum {
420 FD_DOR_SELMASK = 0x01,
421 FD_DOR_nRESET = 0x04,
422 FD_DOR_DMAEN = 0x08,
423 FD_DOR_MOTEN0 = 0x10,
424 FD_DOR_MOTEN1 = 0x20,
425 FD_DOR_MOTEN2 = 0x40,
426 FD_DOR_MOTEN3 = 0x80,
427 };
428
429 enum {
430 FD_TDR_BOOTSEL = 0x0c,
431 };
432
433 enum {
434 FD_DSR_DRATEMASK= 0x03,
435 FD_DSR_PWRDOWN = 0x40,
436 FD_DSR_SWRESET = 0x80,
437 };
438
439 enum {
440 FD_MSR_DRV0BUSY = 0x01,
441 FD_MSR_DRV1BUSY = 0x02,
442 FD_MSR_DRV2BUSY = 0x04,
443 FD_MSR_DRV3BUSY = 0x08,
444 FD_MSR_CMDBUSY = 0x10,
445 FD_MSR_NONDMA = 0x20,
446 FD_MSR_DIO = 0x40,
447 FD_MSR_RQM = 0x80,
448 };
449
450 enum {
451 FD_DIR_DSKCHG = 0x80,
452 };
453
454 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
455 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
456 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
457
458 struct fdctrl_t {
459 /* Controller's identification */
460 uint8_t version;
461 /* HW */
462 qemu_irq irq;
463 int dma_chann;
464 target_phys_addr_t io_base;
465 /* Controller state */
466 QEMUTimer *result_timer;
467 uint8_t sra;
468 uint8_t srb;
469 uint8_t dor;
470 uint8_t dsr;
471 uint8_t msr;
472 uint8_t cur_drv;
473 uint8_t bootsel;
474 uint8_t status0;
475 uint8_t status1;
476 uint8_t status2;
477 /* Command FIFO */
478 uint8_t *fifo;
479 uint32_t data_pos;
480 uint32_t data_len;
481 uint8_t data_state;
482 uint8_t data_dir;
483 uint8_t eot; /* last wanted sector */
484 /* States kept only to be returned back */
485 /* Timers state */
486 uint8_t timer0;
487 uint8_t timer1;
488 /* precompensation */
489 uint8_t precomp_trk;
490 uint8_t config;
491 uint8_t lock;
492 /* Power down config (also with status regB access mode */
493 uint8_t pwrd;
494 /* Sun4m quirks? */
495 int sun4m;
496 /* Floppy drives */
497 fdrive_t drives[2];
498 };
499
500 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
501 {
502 fdctrl_t *fdctrl = opaque;
503 uint32_t retval;
504
505 switch (reg & 0x07) {
506 case FD_REG_SRA:
507 retval = fdctrl_read_statusA(fdctrl);
508 break;
509 case FD_REG_SRB:
510 retval = fdctrl_read_statusB(fdctrl);
511 break;
512 case FD_REG_DOR:
513 retval = fdctrl_read_dor(fdctrl);
514 break;
515 case FD_REG_TDR:
516 retval = fdctrl_read_tape(fdctrl);
517 break;
518 case FD_REG_MSR:
519 retval = fdctrl_read_main_status(fdctrl);
520 break;
521 case FD_REG_FIFO:
522 retval = fdctrl_read_data(fdctrl);
523 break;
524 case FD_REG_DIR:
525 retval = fdctrl_read_dir(fdctrl);
526 break;
527 default:
528 retval = (uint32_t)(-1);
529 break;
530 }
531 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
532
533 return retval;
534 }
535
536 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
537 {
538 fdctrl_t *fdctrl = opaque;
539
540 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
541
542 switch (reg & 0x07) {
543 case FD_REG_DOR:
544 fdctrl_write_dor(fdctrl, value);
545 break;
546 case FD_REG_TDR:
547 fdctrl_write_tape(fdctrl, value);
548 break;
549 case FD_REG_DSR:
550 fdctrl_write_rate(fdctrl, value);
551 break;
552 case FD_REG_FIFO:
553 fdctrl_write_data(fdctrl, value);
554 break;
555 default:
556 break;
557 }
558 }
559
560 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
561 {
562 return fdctrl_read(opaque, (uint32_t)reg);
563 }
564
565 static void fdctrl_write_mem (void *opaque,
566 target_phys_addr_t reg, uint32_t value)
567 {
568 fdctrl_write(opaque, (uint32_t)reg, value);
569 }
570
571 static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
572 fdctrl_read_mem,
573 fdctrl_read_mem,
574 fdctrl_read_mem,
575 };
576
577 static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
578 fdctrl_write_mem,
579 fdctrl_write_mem,
580 fdctrl_write_mem,
581 };
582
583 static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
584 fdctrl_read_mem,
585 NULL,
586 NULL,
587 };
588
589 static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
590 fdctrl_write_mem,
591 NULL,
592 NULL,
593 };
594
595 static void fd_save (QEMUFile *f, fdrive_t *fd)
596 {
597 qemu_put_8s(f, &fd->head);
598 qemu_put_8s(f, &fd->track);
599 qemu_put_8s(f, &fd->sect);
600 }
601
602 static void fdc_save (QEMUFile *f, void *opaque)
603 {
604 fdctrl_t *s = opaque;
605
606 /* Controller state */
607 qemu_put_8s(f, &s->sra);
608 qemu_put_8s(f, &s->srb);
609 qemu_put_8s(f, &s->dsr);
610 qemu_put_8s(f, &s->msr);
611 qemu_put_8s(f, &s->status0);
612 qemu_put_8s(f, &s->status1);
613 qemu_put_8s(f, &s->status2);
614 qemu_put_8s(f, &s->cur_drv);
615 qemu_put_8s(f, &s->bootsel);
616 /* Command FIFO */
617 qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
618 qemu_put_be32s(f, &s->data_pos);
619 qemu_put_be32s(f, &s->data_len);
620 qemu_put_8s(f, &s->data_state);
621 qemu_put_8s(f, &s->data_dir);
622 qemu_put_8s(f, &s->eot);
623 /* States kept only to be returned back */
624 qemu_put_8s(f, &s->timer0);
625 qemu_put_8s(f, &s->timer1);
626 qemu_put_8s(f, &s->precomp_trk);
627 qemu_put_8s(f, &s->config);
628 qemu_put_8s(f, &s->lock);
629 qemu_put_8s(f, &s->pwrd);
630 fd_save(f, &s->drives[0]);
631 fd_save(f, &s->drives[1]);
632 }
633
634 static int fd_load (QEMUFile *f, fdrive_t *fd)
635 {
636 qemu_get_8s(f, &fd->head);
637 qemu_get_8s(f, &fd->track);
638 qemu_get_8s(f, &fd->sect);
639
640 return 0;
641 }
642
643 static int fdc_load (QEMUFile *f, void *opaque, int version_id)
644 {
645 fdctrl_t *s = opaque;
646 int ret;
647
648 if (version_id != 2)
649 return -EINVAL;
650
651 /* Controller state */
652 qemu_get_8s(f, &s->sra);
653 qemu_get_8s(f, &s->srb);
654 qemu_get_8s(f, &s->dsr);
655 qemu_get_8s(f, &s->msr);
656 qemu_get_8s(f, &s->status0);
657 qemu_get_8s(f, &s->status1);
658 qemu_get_8s(f, &s->status2);
659 qemu_get_8s(f, &s->cur_drv);
660 qemu_get_8s(f, &s->bootsel);
661 /* Command FIFO */
662 qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
663 qemu_get_be32s(f, &s->data_pos);
664 qemu_get_be32s(f, &s->data_len);
665 qemu_get_8s(f, &s->data_state);
666 qemu_get_8s(f, &s->data_dir);
667 qemu_get_8s(f, &s->eot);
668 /* States kept only to be returned back */
669 qemu_get_8s(f, &s->timer0);
670 qemu_get_8s(f, &s->timer1);
671 qemu_get_8s(f, &s->precomp_trk);
672 qemu_get_8s(f, &s->config);
673 qemu_get_8s(f, &s->lock);
674 qemu_get_8s(f, &s->pwrd);
675
676 ret = fd_load(f, &s->drives[0]);
677 if (ret == 0)
678 ret = fd_load(f, &s->drives[1]);
679
680 return ret;
681 }
682
683 static void fdctrl_external_reset(void *opaque)
684 {
685 fdctrl_t *s = opaque;
686
687 fdctrl_reset(s, 0);
688 }
689
690 static void fdctrl_handle_tc(void *opaque, int irq, int level)
691 {
692 //fdctrl_t *s = opaque;
693
694 if (level) {
695 // XXX
696 FLOPPY_DPRINTF("TC pulsed\n");
697 }
698 }
699
700 /* XXX: may change if moved to bdrv */
701 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
702 {
703 return fdctrl->drives[drive_num].drive;
704 }
705
706 /* Change IRQ state */
707 static void fdctrl_reset_irq (fdctrl_t *fdctrl)
708 {
709 if (!(fdctrl->sra & FD_SRA_INTPEND))
710 return;
711 FLOPPY_DPRINTF("Reset interrupt\n");
712 qemu_set_irq(fdctrl->irq, 0);
713 fdctrl->sra &= ~FD_SRA_INTPEND;
714 }
715
716 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
717 {
718 /* Sparc mutation */
719 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
720 /* XXX: not sure */
721 fdctrl->msr &= ~FD_MSR_CMDBUSY;
722 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
723 fdctrl->status0 = status0;
724 return;
725 }
726 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
727 qemu_set_irq(fdctrl->irq, 1);
728 fdctrl->sra |= FD_SRA_INTPEND;
729 }
730 fdctrl->status0 = status0;
731 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
732 }
733
734 /* Reset controller */
735 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
736 {
737 int i;
738
739 FLOPPY_DPRINTF("reset controller\n");
740 fdctrl_reset_irq(fdctrl);
741 /* Initialise controller */
742 fdctrl->sra = 0;
743 fdctrl->srb = 0xc0;
744 if (!fdctrl->drives[1].bs)
745 fdctrl->sra |= FD_SRA_nDRV2;
746 fdctrl->cur_drv = 0;
747 fdctrl->dor = FD_DOR_nRESET;
748 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
749 fdctrl->msr = FD_MSR_RQM;
750 /* FIFO state */
751 fdctrl->data_pos = 0;
752 fdctrl->data_len = 0;
753 fdctrl->data_state = 0;
754 fdctrl->data_dir = FD_DIR_WRITE;
755 for (i = 0; i < MAX_FD; i++)
756 fd_recalibrate(&fdctrl->drives[i]);
757 fdctrl_reset_fifo(fdctrl);
758 if (do_irq) {
759 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
760 }
761 }
762
763 static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
764 {
765 return &fdctrl->drives[fdctrl->bootsel];
766 }
767
768 static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
769 {
770 return &fdctrl->drives[1 - fdctrl->bootsel];
771 }
772
773 static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
774 {
775 return fdctrl->cur_drv == 0 ? drv0(fdctrl) : drv1(fdctrl);
776 }
777
778 /* Status A register : 0x00 (read-only) */
779 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
780 {
781 uint32_t retval = fdctrl->sra;
782
783 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
784
785 return retval;
786 }
787
788 /* Status B register : 0x01 (read-only) */
789 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
790 {
791 uint32_t retval = fdctrl->srb;
792
793 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
794
795 return retval;
796 }
797
798 /* Digital output register : 0x02 */
799 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
800 {
801 uint32_t retval = fdctrl->dor;
802
803 /* Selected drive */
804 retval |= fdctrl->cur_drv;
805 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
806
807 return retval;
808 }
809
810 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
811 {
812 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
813
814 /* Motors */
815 if (value & FD_DOR_MOTEN0)
816 fdctrl->srb |= FD_SRB_MTR0;
817 else
818 fdctrl->srb &= ~FD_SRB_MTR0;
819 if (value & FD_DOR_MOTEN1)
820 fdctrl->srb |= FD_SRB_MTR1;
821 else
822 fdctrl->srb &= ~FD_SRB_MTR1;
823
824 /* Drive */
825 if (value & 1)
826 fdctrl->srb |= FD_SRB_DR0;
827 else
828 fdctrl->srb &= ~FD_SRB_DR0;
829
830 /* Reset */
831 if (!(value & FD_DOR_nRESET)) {
832 if (fdctrl->dor & FD_DOR_nRESET) {
833 FLOPPY_DPRINTF("controller enter RESET state\n");
834 }
835 } else {
836 if (!(fdctrl->dor & FD_DOR_nRESET)) {
837 FLOPPY_DPRINTF("controller out of RESET state\n");
838 fdctrl_reset(fdctrl, 1);
839 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
840 }
841 }
842 /* Selected drive */
843 fdctrl->cur_drv = value & FD_DOR_SELMASK;
844
845 fdctrl->dor = value;
846 }
847
848 /* Tape drive register : 0x03 */
849 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
850 {
851 uint32_t retval = 0;
852
853 /* Disk boot selection indicator */
854 retval |= fdctrl->bootsel << 2;
855 /* Tape indicators: never allowed */
856 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
857
858 return retval;
859 }
860
861 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
862 {
863 /* Reset mode */
864 if (!(fdctrl->dor & FD_DOR_nRESET)) {
865 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
866 return;
867 }
868 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
869 /* Disk boot selection indicator */
870 fdctrl->bootsel = (value & FD_TDR_BOOTSEL) >> 2;
871 /* Tape indicators: never allow */
872 }
873
874 /* Main status register : 0x04 (read) */
875 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
876 {
877 uint32_t retval = fdctrl->msr;
878
879 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
880 fdctrl->dor |= FD_DOR_nRESET;
881
882 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
883
884 return retval;
885 }
886
887 /* Data select rate register : 0x04 (write) */
888 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
889 {
890 /* Reset mode */
891 if (!(fdctrl->dor & FD_DOR_nRESET)) {
892 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
893 return;
894 }
895 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
896 /* Reset: autoclear */
897 if (value & FD_DSR_SWRESET) {
898 fdctrl->dor &= ~FD_DOR_nRESET;
899 fdctrl_reset(fdctrl, 1);
900 fdctrl->dor |= FD_DOR_nRESET;
901 }
902 if (value & FD_DSR_PWRDOWN) {
903 fdctrl_reset(fdctrl, 1);
904 }
905 fdctrl->dsr = value;
906 }
907
908 static int fdctrl_media_changed(fdrive_t *drv)
909 {
910 int ret;
911
912 if (!drv->bs)
913 return 0;
914 ret = bdrv_media_changed(drv->bs);
915 if (ret) {
916 fd_revalidate(drv);
917 }
918 return ret;
919 }
920
921 /* Digital input register : 0x07 (read-only) */
922 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
923 {
924 uint32_t retval = 0;
925
926 if (fdctrl_media_changed(drv0(fdctrl)) ||
927 fdctrl_media_changed(drv1(fdctrl)))
928 retval |= FD_DIR_DSKCHG;
929 if (retval != 0)
930 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
931
932 return retval;
933 }
934
935 /* FIFO state control */
936 static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
937 {
938 fdctrl->data_dir = FD_DIR_WRITE;
939 fdctrl->data_pos = 0;
940 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
941 }
942
943 /* Set FIFO status for the host to read */
944 static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
945 {
946 fdctrl->data_dir = FD_DIR_READ;
947 fdctrl->data_len = fifo_len;
948 fdctrl->data_pos = 0;
949 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
950 if (do_irq)
951 fdctrl_raise_irq(fdctrl, 0x00);
952 }
953
954 /* Set an error: unimplemented/unknown command */
955 static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
956 {
957 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
958 fdctrl->fifo[0] = FD_SR0_INVCMD;
959 fdctrl_set_fifo(fdctrl, 1, 0);
960 }
961
962 /* Seek to next sector */
963 static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
964 {
965 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
966 cur_drv->head, cur_drv->track, cur_drv->sect,
967 fd_sector(cur_drv));
968 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
969 error in fact */
970 if (cur_drv->sect >= cur_drv->last_sect ||
971 cur_drv->sect == fdctrl->eot) {
972 cur_drv->sect = 1;
973 if (FD_MULTI_TRACK(fdctrl->data_state)) {
974 if (cur_drv->head == 0 &&
975 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
976 cur_drv->head = 1;
977 } else {
978 cur_drv->head = 0;
979 cur_drv->track++;
980 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
981 return 0;
982 }
983 } else {
984 cur_drv->track++;
985 return 0;
986 }
987 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
988 cur_drv->head, cur_drv->track,
989 cur_drv->sect, fd_sector(cur_drv));
990 } else {
991 cur_drv->sect++;
992 }
993 return 1;
994 }
995
996 /* Callback for transfer end (stop or abort) */
997 static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
998 uint8_t status1, uint8_t status2)
999 {
1000 fdrive_t *cur_drv;
1001
1002 cur_drv = get_cur_drv(fdctrl);
1003 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1004 status0, status1, status2,
1005 status0 | (cur_drv->head << 2) | fdctrl->cur_drv);
1006 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | fdctrl->cur_drv;
1007 fdctrl->fifo[1] = status1;
1008 fdctrl->fifo[2] = status2;
1009 fdctrl->fifo[3] = cur_drv->track;
1010 fdctrl->fifo[4] = cur_drv->head;
1011 fdctrl->fifo[5] = cur_drv->sect;
1012 fdctrl->fifo[6] = FD_SECTOR_SC;
1013 fdctrl->data_dir = FD_DIR_READ;
1014 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1015 DMA_release_DREQ(fdctrl->dma_chann);
1016 }
1017 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1018 fdctrl->msr &= ~FD_MSR_NONDMA;
1019 fdctrl_set_fifo(fdctrl, 7, 1);
1020 }
1021
1022 /* Prepare a data transfer (either DMA or FIFO) */
1023 static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1024 {
1025 fdrive_t *cur_drv;
1026 uint8_t kh, kt, ks;
1027 int did_seek = 0;
1028
1029 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1030 cur_drv = get_cur_drv(fdctrl);
1031 kt = fdctrl->fifo[2];
1032 kh = fdctrl->fifo[3];
1033 ks = fdctrl->fifo[4];
1034 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1035 fdctrl->cur_drv, kh, kt, ks,
1036 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1037 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1038 case 2:
1039 /* sect too big */
1040 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1041 fdctrl->fifo[3] = kt;
1042 fdctrl->fifo[4] = kh;
1043 fdctrl->fifo[5] = ks;
1044 return;
1045 case 3:
1046 /* track too big */
1047 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1048 fdctrl->fifo[3] = kt;
1049 fdctrl->fifo[4] = kh;
1050 fdctrl->fifo[5] = ks;
1051 return;
1052 case 4:
1053 /* No seek enabled */
1054 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1055 fdctrl->fifo[3] = kt;
1056 fdctrl->fifo[4] = kh;
1057 fdctrl->fifo[5] = ks;
1058 return;
1059 case 1:
1060 did_seek = 1;
1061 break;
1062 default:
1063 break;
1064 }
1065
1066 /* Set the FIFO state */
1067 fdctrl->data_dir = direction;
1068 fdctrl->data_pos = 0;
1069 fdctrl->msr |= FD_MSR_CMDBUSY;
1070 if (fdctrl->fifo[0] & 0x80)
1071 fdctrl->data_state |= FD_STATE_MULTI;
1072 else
1073 fdctrl->data_state &= ~FD_STATE_MULTI;
1074 if (did_seek)
1075 fdctrl->data_state |= FD_STATE_SEEK;
1076 else
1077 fdctrl->data_state &= ~FD_STATE_SEEK;
1078 if (fdctrl->fifo[5] == 00) {
1079 fdctrl->data_len = fdctrl->fifo[8];
1080 } else {
1081 int tmp;
1082 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1083 tmp = (cur_drv->last_sect - ks + 1);
1084 if (fdctrl->fifo[0] & 0x80)
1085 tmp += cur_drv->last_sect;
1086 fdctrl->data_len *= tmp;
1087 }
1088 fdctrl->eot = fdctrl->fifo[6];
1089 if (fdctrl->dor & FD_DOR_DMAEN) {
1090 int dma_mode;
1091 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1092 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1093 dma_mode = (dma_mode >> 2) & 3;
1094 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1095 dma_mode, direction,
1096 (128 << fdctrl->fifo[5]) *
1097 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1098 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1099 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1100 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1101 (direction == FD_DIR_READ && dma_mode == 1)) {
1102 /* No access is allowed until DMA transfer has completed */
1103 fdctrl->msr &= ~FD_MSR_RQM;
1104 /* Now, we just have to wait for the DMA controller to
1105 * recall us...
1106 */
1107 DMA_hold_DREQ(fdctrl->dma_chann);
1108 DMA_schedule(fdctrl->dma_chann);
1109 return;
1110 } else {
1111 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1112 }
1113 }
1114 FLOPPY_DPRINTF("start non-DMA transfer\n");
1115 fdctrl->msr |= FD_MSR_NONDMA;
1116 if (direction != FD_DIR_WRITE)
1117 fdctrl->msr |= FD_MSR_DIO;
1118 /* IO based transfer: calculate len */
1119 fdctrl_raise_irq(fdctrl, 0x00);
1120
1121 return;
1122 }
1123
1124 /* Prepare a transfer of deleted data */
1125 static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1126 {
1127 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1128
1129 /* We don't handle deleted data,
1130 * so we don't return *ANYTHING*
1131 */
1132 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1133 }
1134
1135 /* handlers for DMA transfers */
1136 static int fdctrl_transfer_handler (void *opaque, int nchan,
1137 int dma_pos, int dma_len)
1138 {
1139 fdctrl_t *fdctrl;
1140 fdrive_t *cur_drv;
1141 int len, start_pos, rel_pos;
1142 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1143
1144 fdctrl = opaque;
1145 if (fdctrl->msr & FD_MSR_RQM) {
1146 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1147 return 0;
1148 }
1149 cur_drv = get_cur_drv(fdctrl);
1150 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1151 fdctrl->data_dir == FD_DIR_SCANH)
1152 status2 = FD_SR2_SNS;
1153 if (dma_len > fdctrl->data_len)
1154 dma_len = fdctrl->data_len;
1155 if (cur_drv->bs == NULL) {
1156 if (fdctrl->data_dir == FD_DIR_WRITE)
1157 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1158 else
1159 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1160 len = 0;
1161 goto transfer_error;
1162 }
1163 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1164 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1165 len = dma_len - fdctrl->data_pos;
1166 if (len + rel_pos > FD_SECTOR_LEN)
1167 len = FD_SECTOR_LEN - rel_pos;
1168 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1169 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1170 fdctrl->data_len, fdctrl->cur_drv, cur_drv->head,
1171 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1172 fd_sector(cur_drv) * FD_SECTOR_LEN);
1173 if (fdctrl->data_dir != FD_DIR_WRITE ||
1174 len < FD_SECTOR_LEN || rel_pos != 0) {
1175 /* READ & SCAN commands and realign to a sector for WRITE */
1176 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1177 fdctrl->fifo, 1) < 0) {
1178 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1179 fd_sector(cur_drv));
1180 /* Sure, image size is too small... */
1181 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1182 }
1183 }
1184 switch (fdctrl->data_dir) {
1185 case FD_DIR_READ:
1186 /* READ commands */
1187 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1188 fdctrl->data_pos, len);
1189 break;
1190 case FD_DIR_WRITE:
1191 /* WRITE commands */
1192 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1193 fdctrl->data_pos, len);
1194 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1195 fdctrl->fifo, 1) < 0) {
1196 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1197 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1198 goto transfer_error;
1199 }
1200 break;
1201 default:
1202 /* SCAN commands */
1203 {
1204 uint8_t tmpbuf[FD_SECTOR_LEN];
1205 int ret;
1206 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1207 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1208 if (ret == 0) {
1209 status2 = FD_SR2_SEH;
1210 goto end_transfer;
1211 }
1212 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1213 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1214 status2 = 0x00;
1215 goto end_transfer;
1216 }
1217 }
1218 break;
1219 }
1220 fdctrl->data_pos += len;
1221 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1222 if (rel_pos == 0) {
1223 /* Seek to next sector */
1224 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1225 break;
1226 }
1227 }
1228 end_transfer:
1229 len = fdctrl->data_pos - start_pos;
1230 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1231 fdctrl->data_pos, len, fdctrl->data_len);
1232 if (fdctrl->data_dir == FD_DIR_SCANE ||
1233 fdctrl->data_dir == FD_DIR_SCANL ||
1234 fdctrl->data_dir == FD_DIR_SCANH)
1235 status2 = FD_SR2_SEH;
1236 if (FD_DID_SEEK(fdctrl->data_state))
1237 status0 |= FD_SR0_SEEK;
1238 fdctrl->data_len -= len;
1239 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1240 transfer_error:
1241
1242 return len;
1243 }
1244
1245 /* Data register : 0x05 */
1246 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1247 {
1248 fdrive_t *cur_drv;
1249 uint32_t retval = 0;
1250 int pos;
1251
1252 cur_drv = get_cur_drv(fdctrl);
1253 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1254 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1255 FLOPPY_ERROR("controller not ready for reading\n");
1256 return 0;
1257 }
1258 pos = fdctrl->data_pos;
1259 if (fdctrl->msr & FD_MSR_NONDMA) {
1260 pos %= FD_SECTOR_LEN;
1261 if (pos == 0) {
1262 if (fdctrl->data_pos != 0)
1263 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1264 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1265 fd_sector(cur_drv));
1266 return 0;
1267 }
1268 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1269 FLOPPY_DPRINTF("error getting sector %d\n",
1270 fd_sector(cur_drv));
1271 /* Sure, image size is too small... */
1272 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1273 }
1274 }
1275 }
1276 retval = fdctrl->fifo[pos];
1277 if (++fdctrl->data_pos == fdctrl->data_len) {
1278 fdctrl->data_pos = 0;
1279 /* Switch from transfer mode to status mode
1280 * then from status mode to command mode
1281 */
1282 if (fdctrl->msr & FD_MSR_NONDMA) {
1283 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1284 } else {
1285 fdctrl_reset_fifo(fdctrl);
1286 fdctrl_reset_irq(fdctrl);
1287 }
1288 }
1289 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1290
1291 return retval;
1292 }
1293
1294 static void fdctrl_format_sector (fdctrl_t *fdctrl)
1295 {
1296 fdrive_t *cur_drv;
1297 uint8_t kh, kt, ks;
1298
1299 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1300 cur_drv = get_cur_drv(fdctrl);
1301 kt = fdctrl->fifo[6];
1302 kh = fdctrl->fifo[7];
1303 ks = fdctrl->fifo[8];
1304 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1305 fdctrl->cur_drv, kh, kt, ks,
1306 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1307 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1308 case 2:
1309 /* sect too big */
1310 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1311 fdctrl->fifo[3] = kt;
1312 fdctrl->fifo[4] = kh;
1313 fdctrl->fifo[5] = ks;
1314 return;
1315 case 3:
1316 /* track too big */
1317 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1318 fdctrl->fifo[3] = kt;
1319 fdctrl->fifo[4] = kh;
1320 fdctrl->fifo[5] = ks;
1321 return;
1322 case 4:
1323 /* No seek enabled */
1324 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1325 fdctrl->fifo[3] = kt;
1326 fdctrl->fifo[4] = kh;
1327 fdctrl->fifo[5] = ks;
1328 return;
1329 case 1:
1330 fdctrl->data_state |= FD_STATE_SEEK;
1331 break;
1332 default:
1333 break;
1334 }
1335 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1336 if (cur_drv->bs == NULL ||
1337 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1338 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1339 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1340 } else {
1341 if (cur_drv->sect == cur_drv->last_sect) {
1342 fdctrl->data_state &= ~FD_STATE_FORMAT;
1343 /* Last sector done */
1344 if (FD_DID_SEEK(fdctrl->data_state))
1345 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1346 else
1347 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1348 } else {
1349 /* More to do */
1350 fdctrl->data_pos = 0;
1351 fdctrl->data_len = 4;
1352 }
1353 }
1354 }
1355
1356 static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1357 {
1358 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1359 fdctrl->fifo[0] = fdctrl->lock << 4;
1360 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1361 }
1362
1363 static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1364 {
1365 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1366
1367 /* Drives position */
1368 fdctrl->fifo[0] = drv0(fdctrl)->track;
1369 fdctrl->fifo[1] = drv1(fdctrl)->track;
1370 fdctrl->fifo[2] = 0;
1371 fdctrl->fifo[3] = 0;
1372 /* timers */
1373 fdctrl->fifo[4] = fdctrl->timer0;
1374 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1375 fdctrl->fifo[6] = cur_drv->last_sect;
1376 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1377 (cur_drv->perpendicular << 2);
1378 fdctrl->fifo[8] = fdctrl->config;
1379 fdctrl->fifo[9] = fdctrl->precomp_trk;
1380 fdctrl_set_fifo(fdctrl, 10, 0);
1381 }
1382
1383 static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1384 {
1385 /* Controller's version */
1386 fdctrl->fifo[0] = fdctrl->version;
1387 fdctrl_set_fifo(fdctrl, 1, 1);
1388 }
1389
1390 static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1391 {
1392 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1393 fdctrl_set_fifo(fdctrl, 1, 0);
1394 }
1395
1396 static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1397 {
1398 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1399
1400 /* Drives position */
1401 drv0(fdctrl)->track = fdctrl->fifo[3];
1402 drv1(fdctrl)->track = fdctrl->fifo[4];
1403 /* timers */
1404 fdctrl->timer0 = fdctrl->fifo[7];
1405 fdctrl->timer1 = fdctrl->fifo[8];
1406 cur_drv->last_sect = fdctrl->fifo[9];
1407 fdctrl->lock = fdctrl->fifo[10] >> 7;
1408 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1409 fdctrl->config = fdctrl->fifo[11];
1410 fdctrl->precomp_trk = fdctrl->fifo[12];
1411 fdctrl->pwrd = fdctrl->fifo[13];
1412 fdctrl_reset_fifo(fdctrl);
1413 }
1414
1415 static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1416 {
1417 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1418
1419 fdctrl->fifo[0] = 0;
1420 fdctrl->fifo[1] = 0;
1421 /* Drives position */
1422 fdctrl->fifo[2] = drv0(fdctrl)->track;
1423 fdctrl->fifo[3] = drv1(fdctrl)->track;
1424 fdctrl->fifo[4] = 0;
1425 fdctrl->fifo[5] = 0;
1426 /* timers */
1427 fdctrl->fifo[6] = fdctrl->timer0;
1428 fdctrl->fifo[7] = fdctrl->timer1;
1429 fdctrl->fifo[8] = cur_drv->last_sect;
1430 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1431 (cur_drv->perpendicular << 2);
1432 fdctrl->fifo[10] = fdctrl->config;
1433 fdctrl->fifo[11] = fdctrl->precomp_trk;
1434 fdctrl->fifo[12] = fdctrl->pwrd;
1435 fdctrl->fifo[13] = 0;
1436 fdctrl->fifo[14] = 0;
1437 fdctrl_set_fifo(fdctrl, 15, 1);
1438 }
1439
1440 static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1441 {
1442 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1443
1444 /* XXX: should set main status register to busy */
1445 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1446 qemu_mod_timer(fdctrl->result_timer,
1447 qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
1448 }
1449
1450 static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1451 {
1452 fdrive_t *cur_drv;
1453
1454 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1455 cur_drv = get_cur_drv(fdctrl);
1456 fdctrl->data_state |= FD_STATE_FORMAT;
1457 if (fdctrl->fifo[0] & 0x80)
1458 fdctrl->data_state |= FD_STATE_MULTI;
1459 else
1460 fdctrl->data_state &= ~FD_STATE_MULTI;
1461 fdctrl->data_state &= ~FD_STATE_SEEK;
1462 cur_drv->bps =
1463 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1464 #if 0
1465 cur_drv->last_sect =
1466 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1467 fdctrl->fifo[3] / 2;
1468 #else
1469 cur_drv->last_sect = fdctrl->fifo[3];
1470 #endif
1471 /* TODO: implement format using DMA expected by the Bochs BIOS
1472 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1473 * the sector with the specified fill byte
1474 */
1475 fdctrl->data_state &= ~FD_STATE_FORMAT;
1476 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1477 }
1478
1479 static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1480 {
1481 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1482 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1483 if (fdctrl->fifo[2] & 1)
1484 fdctrl->dor &= ~FD_DOR_DMAEN;
1485 else
1486 fdctrl->dor |= FD_DOR_DMAEN;
1487 /* No result back */
1488 fdctrl_reset_fifo(fdctrl);
1489 }
1490
1491 static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1492 {
1493 fdrive_t *cur_drv;
1494
1495 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1496 cur_drv = get_cur_drv(fdctrl);
1497 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1498 /* 1 Byte status back */
1499 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1500 (cur_drv->track == 0 ? 0x10 : 0x00) |
1501 (cur_drv->head << 2) |
1502 fdctrl->cur_drv |
1503 0x28;
1504 fdctrl_set_fifo(fdctrl, 1, 0);
1505 }
1506
1507 static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1508 {
1509 fdrive_t *cur_drv;
1510
1511 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1512 cur_drv = get_cur_drv(fdctrl);
1513 fd_recalibrate(cur_drv);
1514 fdctrl_reset_fifo(fdctrl);
1515 /* Raise Interrupt */
1516 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1517 }
1518
1519 static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1520 {
1521 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1522
1523 #if 0
1524 fdctrl->fifo[0] =
1525 fdctrl->status0 | (cur_drv->head << 2) | fdctrl->cur_drv;
1526 #else
1527 /* XXX: status0 handling is broken for read/write
1528 commands, so we do this hack. It should be suppressed
1529 ASAP */
1530 fdctrl->fifo[0] =
1531 FD_SR0_SEEK | (cur_drv->head << 2) | fdctrl->cur_drv;
1532 #endif
1533 fdctrl->fifo[1] = cur_drv->track;
1534 fdctrl_set_fifo(fdctrl, 2, 0);
1535 fdctrl_reset_irq(fdctrl);
1536 fdctrl->status0 = FD_SR0_RDYCHG;
1537 }
1538
1539 static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1540 {
1541 fdrive_t *cur_drv;
1542
1543 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1544 cur_drv = get_cur_drv(fdctrl);
1545 fdctrl_reset_fifo(fdctrl);
1546 if (fdctrl->fifo[2] > cur_drv->max_track) {
1547 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1548 } else {
1549 cur_drv->track = fdctrl->fifo[2];
1550 /* Raise Interrupt */
1551 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1552 }
1553 }
1554
1555 static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1556 {
1557 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1558
1559 if (fdctrl->fifo[1] & 0x80)
1560 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1561 /* No result back */
1562 fdctrl_reset_fifo(fdctrl);
1563 }
1564
1565 static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1566 {
1567 fdctrl->config = fdctrl->fifo[2];
1568 fdctrl->precomp_trk = fdctrl->fifo[3];
1569 /* No result back */
1570 fdctrl_reset_fifo(fdctrl);
1571 }
1572
1573 static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1574 {
1575 fdctrl->pwrd = fdctrl->fifo[1];
1576 fdctrl->fifo[0] = fdctrl->fifo[1];
1577 fdctrl_set_fifo(fdctrl, 1, 1);
1578 }
1579
1580 static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1581 {
1582 /* No result back */
1583 fdctrl_reset_fifo(fdctrl);
1584 }
1585
1586 static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1587 {
1588 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1589
1590 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1591 /* Command parameters done */
1592 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1593 fdctrl->fifo[0] = fdctrl->fifo[1];
1594 fdctrl->fifo[2] = 0;
1595 fdctrl->fifo[3] = 0;
1596 fdctrl_set_fifo(fdctrl, 4, 1);
1597 } else {
1598 fdctrl_reset_fifo(fdctrl);
1599 }
1600 } else if (fdctrl->data_len > 7) {
1601 /* ERROR */
1602 fdctrl->fifo[0] = 0x80 |
1603 (cur_drv->head << 2) | fdctrl->cur_drv;
1604 fdctrl_set_fifo(fdctrl, 1, 1);
1605 }
1606 }
1607
1608 static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1609 {
1610 fdrive_t *cur_drv;
1611
1612 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1613 cur_drv = get_cur_drv(fdctrl);
1614 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1615 cur_drv->track = cur_drv->max_track - 1;
1616 } else {
1617 cur_drv->track += fdctrl->fifo[2];
1618 }
1619 fdctrl_reset_fifo(fdctrl);
1620 /* Raise Interrupt */
1621 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1622 }
1623
1624 static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1625 {
1626 fdrive_t *cur_drv;
1627
1628 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1629 cur_drv = get_cur_drv(fdctrl);
1630 if (fdctrl->fifo[2] > cur_drv->track) {
1631 cur_drv->track = 0;
1632 } else {
1633 cur_drv->track -= fdctrl->fifo[2];
1634 }
1635 fdctrl_reset_fifo(fdctrl);
1636 /* Raise Interrupt */
1637 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1638 }
1639
1640 static const struct {
1641 uint8_t value;
1642 uint8_t mask;
1643 const char* name;
1644 int parameters;
1645 void (*handler)(fdctrl_t *fdctrl, int direction);
1646 int direction;
1647 } handlers[] = {
1648 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1649 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1650 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1651 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1652 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1653 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1654 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1655 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1656 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1657 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1658 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1659 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1660 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1661 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1662 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1663 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1664 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1665 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1666 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1667 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1668 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1669 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1670 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1671 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1672 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1673 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1674 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1675 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1676 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1677 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1678 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1679 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1680 };
1681 /* Associate command to an index in the 'handlers' array */
1682 static uint8_t command_to_handler[256];
1683
1684 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1685 {
1686 fdrive_t *cur_drv;
1687 int pos;
1688
1689 /* Reset mode */
1690 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1691 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1692 return;
1693 }
1694 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1695 FLOPPY_ERROR("controller not ready for writing\n");
1696 return;
1697 }
1698 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1699 /* Is it write command time ? */
1700 if (fdctrl->msr & FD_MSR_NONDMA) {
1701 /* FIFO data write */
1702 fdctrl->fifo[fdctrl->data_pos++] = value;
1703 if (fdctrl->data_pos % FD_SECTOR_LEN == (FD_SECTOR_LEN - 1) ||
1704 fdctrl->data_pos == fdctrl->data_len) {
1705 cur_drv = get_cur_drv(fdctrl);
1706 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1707 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1708 return;
1709 }
1710 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1711 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1712 fd_sector(cur_drv));
1713 return;
1714 }
1715 }
1716 /* Switch from transfer mode to status mode
1717 * then from status mode to command mode
1718 */
1719 if (fdctrl->data_pos == fdctrl->data_len)
1720 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1721 return;
1722 }
1723 if (fdctrl->data_pos == 0) {
1724 /* Command */
1725 pos = command_to_handler[value & 0xff];
1726 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1727 fdctrl->data_len = handlers[pos].parameters + 1;
1728 }
1729
1730 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1731 fdctrl->fifo[fdctrl->data_pos++] = value;
1732 if (fdctrl->data_pos == fdctrl->data_len) {
1733 /* We now have all parameters
1734 * and will be able to treat the command
1735 */
1736 if (fdctrl->data_state & FD_STATE_FORMAT) {
1737 fdctrl_format_sector(fdctrl);
1738 return;
1739 }
1740
1741 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1742 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1743 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1744 }
1745 }
1746
1747 static void fdctrl_result_timer(void *opaque)
1748 {
1749 fdctrl_t *fdctrl = opaque;
1750 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1751
1752 /* Pretend we are spinning.
1753 * This is needed for Coherent, which uses READ ID to check for
1754 * sector interleaving.
1755 */
1756 if (cur_drv->last_sect != 0) {
1757 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1758 }
1759 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1760 }
1761
1762 /* Init functions */
1763 static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
1764 target_phys_addr_t io_base,
1765 BlockDriverState **fds)
1766 {
1767 fdctrl_t *fdctrl;
1768 int i, j;
1769
1770 /* Fill 'command_to_handler' lookup table */
1771 for (i = sizeof(handlers)/sizeof(handlers[0]) - 1; i >= 0; i--) {
1772 for (j = 0; j < sizeof(command_to_handler); j++) {
1773 if ((j & handlers[i].mask) == handlers[i].value)
1774 command_to_handler[j] = i;
1775 }
1776 }
1777
1778 FLOPPY_DPRINTF("init controller\n");
1779 fdctrl = qemu_mallocz(sizeof(fdctrl_t));
1780 if (!fdctrl)
1781 return NULL;
1782 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1783 if (fdctrl->fifo == NULL) {
1784 qemu_free(fdctrl);
1785 return NULL;
1786 }
1787 fdctrl->result_timer = qemu_new_timer(vm_clock,
1788 fdctrl_result_timer, fdctrl);
1789
1790 fdctrl->version = 0x90; /* Intel 82078 controller */
1791 fdctrl->irq = irq;
1792 fdctrl->dma_chann = dma_chann;
1793 fdctrl->io_base = io_base;
1794 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1795 if (fdctrl->dma_chann != -1) {
1796 DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1797 }
1798 for (i = 0; i < MAX_FD; i++) {
1799 fd_init(&fdctrl->drives[i], fds[i]);
1800 }
1801 fdctrl_external_reset(fdctrl);
1802 register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
1803 qemu_register_reset(fdctrl_external_reset, fdctrl);
1804 for (i = 0; i < MAX_FD; i++) {
1805 fd_revalidate(&fdctrl->drives[i]);
1806 }
1807
1808 return fdctrl;
1809 }
1810
1811 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1812 target_phys_addr_t io_base,
1813 BlockDriverState **fds)
1814 {
1815 fdctrl_t *fdctrl;
1816 int io_mem;
1817
1818 fdctrl = fdctrl_init_common(irq, dma_chann, io_base, fds);
1819
1820 fdctrl->sun4m = 0;
1821 if (mem_mapped) {
1822 io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write,
1823 fdctrl);
1824 cpu_register_physical_memory(io_base, 0x08, io_mem);
1825 } else {
1826 register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read,
1827 fdctrl);
1828 register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read,
1829 fdctrl);
1830 register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write,
1831 fdctrl);
1832 register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
1833 fdctrl);
1834 }
1835
1836 return fdctrl;
1837 }
1838
1839 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1840 BlockDriverState **fds, qemu_irq *fdc_tc)
1841 {
1842 fdctrl_t *fdctrl;
1843 int io_mem;
1844
1845 fdctrl = fdctrl_init_common(irq, -1, io_base, fds);
1846 fdctrl->sun4m = 1;
1847 io_mem = cpu_register_io_memory(0, fdctrl_mem_read_strict,
1848 fdctrl_mem_write_strict,
1849 fdctrl);
1850 cpu_register_physical_memory(io_base, 0x08, io_mem);
1851 *fdc_tc = *qemu_allocate_irqs(fdctrl_handle_tc, fdctrl, 1);
1852
1853 return fdctrl;
1854 }
Qemu copy for testing