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FDC fix 3/10 (Hervé Poussineau):
[qemu.git] / hw / fdc.c
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29 #include "hw.h"
30 #include "fdc.h"
31 #include "block.h"
32 #include "qemu-timer.h"
33 #include "isa.h"
34
35 /********************************************************/
36 /* debug Floppy devices */
37 //#define DEBUG_FLOPPY
38
39 #ifdef DEBUG_FLOPPY
40 #define FLOPPY_DPRINTF(fmt, args...) \
41 do { printf("FLOPPY: " fmt , ##args); } while (0)
42 #else
43 #define FLOPPY_DPRINTF(fmt, args...)
44 #endif
45
46 #define FLOPPY_ERROR(fmt, args...) \
47 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ##args); } while (0)
48
49 /********************************************************/
50 /* Floppy drive emulation */
51
52 /* Will always be a fixed parameter for us */
53 #define FD_SECTOR_LEN 512
54 #define FD_SECTOR_SC 2 /* Sector size code */
55
56 /* Floppy disk drive emulation */
57 typedef enum fdisk_type_t {
58 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
59 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
60 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
61 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
62 FDRIVE_DISK_NONE = 0x05, /* No disk */
63 } fdisk_type_t;
64
65 typedef enum fdrive_type_t {
66 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
67 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
68 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
69 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
70 } fdrive_type_t;
71
72 typedef enum fdrive_flags_t {
73 FDRIVE_MOTOR_ON = 0x01, /* motor on/off */
74 } fdrive_flags_t;
75
76 typedef enum fdisk_flags_t {
77 FDISK_DBL_SIDES = 0x01,
78 } fdisk_flags_t;
79
80 typedef struct fdrive_t {
81 BlockDriverState *bs;
82 /* Drive status */
83 fdrive_type_t drive;
84 fdrive_flags_t drflags;
85 uint8_t perpendicular; /* 2.88 MB access mode */
86 /* Position */
87 uint8_t head;
88 uint8_t track;
89 uint8_t sect;
90 /* Last operation status */
91 uint8_t dir; /* Direction */
92 uint8_t rw; /* Read/write */
93 /* Media */
94 fdisk_flags_t flags;
95 uint8_t last_sect; /* Nb sector per track */
96 uint8_t max_track; /* Nb of tracks */
97 uint16_t bps; /* Bytes per sector */
98 uint8_t ro; /* Is read-only */
99 } fdrive_t;
100
101 static void fd_init (fdrive_t *drv, BlockDriverState *bs)
102 {
103 /* Drive */
104 drv->bs = bs;
105 drv->drive = FDRIVE_DRV_NONE;
106 drv->drflags = 0;
107 drv->perpendicular = 0;
108 /* Disk */
109 drv->last_sect = 0;
110 drv->max_track = 0;
111 }
112
113 static int _fd_sector (uint8_t head, uint8_t track,
114 uint8_t sect, uint8_t last_sect)
115 {
116 return (((track * 2) + head) * last_sect) + sect - 1;
117 }
118
119 /* Returns current position, in sectors, for given drive */
120 static int fd_sector (fdrive_t *drv)
121 {
122 return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
123 }
124
125 static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
126 int enable_seek)
127 {
128 uint32_t sector;
129 int ret;
130
131 if (track > drv->max_track ||
132 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
133 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
134 head, track, sect, 1,
135 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
136 drv->max_track, drv->last_sect);
137 return 2;
138 }
139 if (sect > drv->last_sect) {
140 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
141 head, track, sect, 1,
142 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
143 drv->max_track, drv->last_sect);
144 return 3;
145 }
146 sector = _fd_sector(head, track, sect, drv->last_sect);
147 ret = 0;
148 if (sector != fd_sector(drv)) {
149 #if 0
150 if (!enable_seek) {
151 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
152 head, track, sect, 1, drv->max_track, drv->last_sect);
153 return 4;
154 }
155 #endif
156 drv->head = head;
157 if (drv->track != track)
158 ret = 1;
159 drv->track = track;
160 drv->sect = sect;
161 }
162
163 return ret;
164 }
165
166 /* Set drive back to track 0 */
167 static void fd_recalibrate (fdrive_t *drv)
168 {
169 FLOPPY_DPRINTF("recalibrate\n");
170 drv->head = 0;
171 drv->track = 0;
172 drv->sect = 1;
173 drv->dir = 1;
174 drv->rw = 0;
175 }
176
177 /* Recognize floppy formats */
178 typedef struct fd_format_t {
179 fdrive_type_t drive;
180 fdisk_type_t disk;
181 uint8_t last_sect;
182 uint8_t max_track;
183 uint8_t max_head;
184 const char *str;
185 } fd_format_t;
186
187 static const fd_format_t fd_formats[] = {
188 /* First entry is default format */
189 /* 1.44 MB 3"1/2 floppy disks */
190 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
191 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
192 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
193 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
197 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
198 /* 2.88 MB 3"1/2 floppy disks */
199 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
200 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
201 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
202 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
203 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
204 /* 720 kB 3"1/2 floppy disks */
205 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
206 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
207 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
208 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
210 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
211 /* 1.2 MB 5"1/4 floppy disks */
212 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
213 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
214 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
215 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
216 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
217 /* 720 kB 5"1/4 floppy disks */
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
219 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
220 /* 360 kB 5"1/4 floppy disks */
221 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
222 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
224 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
225 /* 320 kB 5"1/4 floppy disks */
226 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
227 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
228 /* 360 kB must match 5"1/4 better than 3"1/2... */
229 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
230 /* end */
231 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
232 };
233
234 /* Revalidate a disk drive after a disk change */
235 static void fd_revalidate (fdrive_t *drv)
236 {
237 const fd_format_t *parse;
238 uint64_t nb_sectors, size;
239 int i, first_match, match;
240 int nb_heads, max_track, last_sect, ro;
241
242 FLOPPY_DPRINTF("revalidate\n");
243 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
244 ro = bdrv_is_read_only(drv->bs);
245 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
246 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
247 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
248 nb_heads - 1, max_track, last_sect);
249 } else {
250 bdrv_get_geometry(drv->bs, &nb_sectors);
251 match = -1;
252 first_match = -1;
253 for (i = 0;; i++) {
254 parse = &fd_formats[i];
255 if (parse->drive == FDRIVE_DRV_NONE)
256 break;
257 if (drv->drive == parse->drive ||
258 drv->drive == FDRIVE_DRV_NONE) {
259 size = (parse->max_head + 1) * parse->max_track *
260 parse->last_sect;
261 if (nb_sectors == size) {
262 match = i;
263 break;
264 }
265 if (first_match == -1)
266 first_match = i;
267 }
268 }
269 if (match == -1) {
270 if (first_match == -1)
271 match = 1;
272 else
273 match = first_match;
274 parse = &fd_formats[match];
275 }
276 nb_heads = parse->max_head + 1;
277 max_track = parse->max_track;
278 last_sect = parse->last_sect;
279 drv->drive = parse->drive;
280 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
281 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
282 }
283 if (nb_heads == 1) {
284 drv->flags &= ~FDISK_DBL_SIDES;
285 } else {
286 drv->flags |= FDISK_DBL_SIDES;
287 }
288 drv->max_track = max_track;
289 drv->last_sect = last_sect;
290 drv->ro = ro;
291 } else {
292 FLOPPY_DPRINTF("No disk in drive\n");
293 drv->last_sect = 0;
294 drv->max_track = 0;
295 drv->flags &= ~FDISK_DBL_SIDES;
296 }
297 }
298
299 /* Motor control */
300 static void fd_start (fdrive_t *drv)
301 {
302 drv->drflags |= FDRIVE_MOTOR_ON;
303 }
304
305 static void fd_stop (fdrive_t *drv)
306 {
307 drv->drflags &= ~FDRIVE_MOTOR_ON;
308 }
309
310 /* Re-initialise a drives (motor off, repositioned) */
311 static void fd_reset (fdrive_t *drv)
312 {
313 fd_stop(drv);
314 fd_recalibrate(drv);
315 }
316
317 /********************************************************/
318 /* Intel 82078 floppy disk controller emulation */
319
320 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
321 static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
322 static int fdctrl_transfer_handler (void *opaque, int nchan,
323 int dma_pos, int dma_len);
324 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status);
325
326 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
327 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
328 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
329 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
330 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
331 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
332 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
333 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
334 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
335 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
336 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
337
338 enum {
339 FD_CTRL_ACTIVE = 0x01, /* XXX: suppress that */
340 FD_CTRL_RESET = 0x02,
341 FD_CTRL_SLEEP = 0x04, /* XXX: suppress that */
342 FD_CTRL_BUSY = 0x08, /* dma transfer in progress */
343 };
344
345 enum {
346 FD_DIR_WRITE = 0,
347 FD_DIR_READ = 1,
348 FD_DIR_SCANE = 2,
349 FD_DIR_SCANL = 3,
350 FD_DIR_SCANH = 4,
351 };
352
353 enum {
354 FD_STATE_CMD = 0x00,
355 FD_STATE_STATUS = 0x01,
356 FD_STATE_DATA = 0x02,
357 FD_STATE_STATE = 0x03,
358 FD_STATE_MULTI = 0x10,
359 FD_STATE_SEEK = 0x20,
360 FD_STATE_FORMAT = 0x40,
361 };
362
363 enum {
364 FD_REG_SRA = 0x00,
365 FD_REG_SRB = 0x01,
366 FD_REG_DOR = 0x02,
367 FD_REG_TDR = 0x03,
368 FD_REG_MSR = 0x04,
369 FD_REG_DSR = 0x04,
370 FD_REG_FIFO = 0x05,
371 FD_REG_DIR = 0x07,
372 };
373
374 enum {
375 FD_CMD_READ_TRACK = 0x02,
376 FD_CMD_SPECIFY = 0x03,
377 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
378 FD_CMD_WRITE = 0x05,
379 FD_CMD_READ = 0x06,
380 FD_CMD_RECALIBRATE = 0x07,
381 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
382 FD_CMD_WRITE_DELETED = 0x09,
383 FD_CMD_READ_ID = 0x0a,
384 FD_CMD_READ_DELETED = 0x0c,
385 FD_CMD_FORMAT_TRACK = 0x0d,
386 FD_CMD_DUMPREG = 0x0e,
387 FD_CMD_SEEK = 0x0f,
388 FD_CMD_VERSION = 0x10,
389 FD_CMD_SCAN_EQUAL = 0x11,
390 FD_CMD_PERPENDICULAR_MODE = 0x12,
391 FD_CMD_CONFIGURE = 0x13,
392 FD_CMD_LOCK = 0x14,
393 FD_CMD_VERIFY = 0x16,
394 FD_CMD_POWERDOWN_MODE = 0x17,
395 FD_CMD_PART_ID = 0x18,
396 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
397 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
398 FD_CMD_SAVE = 0x2c,
399 FD_CMD_OPTION = 0x33,
400 FD_CMD_RESTORE = 0x4c,
401 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
402 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
403 FD_CMD_FORMAT_AND_WRITE = 0xcd,
404 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
405 };
406
407 enum {
408 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
409 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
410 FD_CONFIG_POLL = 0x10, /* Poll enabled */
411 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
412 FD_CONFIG_EIS = 0x40, /* No implied seeks */
413 };
414
415 enum {
416 FD_SR0_EQPMT = 0x10,
417 FD_SR0_SEEK = 0x20,
418 FD_SR0_ABNTERM = 0x40,
419 FD_SR0_INVCMD = 0x80,
420 FD_SR0_RDYCHG = 0xc0,
421 };
422
423 enum {
424 FD_SRA_DIR = 0x01,
425 FD_SRA_nWP = 0x02,
426 FD_SRA_nINDX = 0x04,
427 FD_SRA_HDSEL = 0x08,
428 FD_SRA_nTRK0 = 0x10,
429 FD_SRA_STEP = 0x20,
430 FD_SRA_nDRV2 = 0x40,
431 FD_SRA_INTPEND = 0x80,
432 };
433
434 enum {
435 FD_SRB_MTR0 = 0x01,
436 FD_SRB_MTR1 = 0x02,
437 FD_SRB_WGATE = 0x04,
438 FD_SRB_RDATA = 0x08,
439 FD_SRB_WDATA = 0x10,
440 FD_SRB_DR0 = 0x20,
441 };
442
443 enum {
444 FD_DOR_SELMASK = 0x01,
445 FD_DOR_nRESET = 0x04,
446 FD_DOR_DMAEN = 0x08,
447 FD_DOR_MOTEN0 = 0x10,
448 FD_DOR_MOTEN1 = 0x20,
449 FD_DOR_MOTEN2 = 0x40,
450 FD_DOR_MOTEN3 = 0x80,
451 };
452
453 enum {
454 FD_TDR_BOOTSEL = 0x0c,
455 };
456
457 enum {
458 FD_DSR_DRATEMASK= 0x03,
459 FD_DSR_PWRDOWN = 0x40,
460 FD_DSR_SWRESET = 0x80,
461 };
462
463 enum {
464 FD_MSR_DRV0BUSY = 0x01,
465 FD_MSR_DRV1BUSY = 0x02,
466 FD_MSR_DRV2BUSY = 0x04,
467 FD_MSR_DRV3BUSY = 0x08,
468 FD_MSR_CMDBUSY = 0x10,
469 FD_MSR_NONDMA = 0x20,
470 FD_MSR_DIO = 0x40,
471 FD_MSR_RQM = 0x80,
472 };
473
474 enum {
475 FD_DIR_DSKCHG = 0x80,
476 };
477
478 #define FD_STATE(state) ((state) & FD_STATE_STATE)
479 #define FD_SET_STATE(state, new_state) \
480 do { (state) = ((state) & ~FD_STATE_STATE) | (new_state); } while (0)
481 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
482 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
483 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
484
485 struct fdctrl_t {
486 fdctrl_t *fdctrl;
487 /* Controller's identification */
488 uint8_t version;
489 /* HW */
490 qemu_irq irq;
491 int dma_chann;
492 target_phys_addr_t io_base;
493 /* Controller state */
494 QEMUTimer *result_timer;
495 uint8_t sra;
496 uint8_t srb;
497 uint8_t state;
498 uint8_t dma_en;
499 uint8_t cur_drv;
500 uint8_t bootsel;
501 /* Command FIFO */
502 uint8_t *fifo;
503 uint32_t data_pos;
504 uint32_t data_len;
505 uint8_t data_state;
506 uint8_t data_dir;
507 uint8_t int_status;
508 uint8_t eot; /* last wanted sector */
509 /* States kept only to be returned back */
510 /* Timers state */
511 uint8_t timer0;
512 uint8_t timer1;
513 /* precompensation */
514 uint8_t precomp_trk;
515 uint8_t config;
516 uint8_t lock;
517 /* Power down config (also with status regB access mode */
518 uint8_t pwrd;
519 /* Sun4m quirks? */
520 int sun4m;
521 /* Floppy drives */
522 fdrive_t drives[2];
523 };
524
525 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
526 {
527 fdctrl_t *fdctrl = opaque;
528 uint32_t retval;
529
530 switch (reg & 0x07) {
531 case FD_REG_SRA:
532 retval = fdctrl_read_statusA(fdctrl);
533 break;
534 case FD_REG_SRB:
535 retval = fdctrl_read_statusB(fdctrl);
536 break;
537 case FD_REG_DOR:
538 retval = fdctrl_read_dor(fdctrl);
539 break;
540 case FD_REG_TDR:
541 retval = fdctrl_read_tape(fdctrl);
542 break;
543 case FD_REG_MSR:
544 retval = fdctrl_read_main_status(fdctrl);
545 break;
546 case FD_REG_FIFO:
547 retval = fdctrl_read_data(fdctrl);
548 break;
549 case FD_REG_DIR:
550 retval = fdctrl_read_dir(fdctrl);
551 break;
552 default:
553 retval = (uint32_t)(-1);
554 break;
555 }
556 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
557
558 return retval;
559 }
560
561 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
562 {
563 fdctrl_t *fdctrl = opaque;
564
565 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
566
567 switch (reg & 0x07) {
568 case FD_REG_DOR:
569 fdctrl_write_dor(fdctrl, value);
570 break;
571 case FD_REG_TDR:
572 fdctrl_write_tape(fdctrl, value);
573 break;
574 case FD_REG_DSR:
575 fdctrl_write_rate(fdctrl, value);
576 break;
577 case FD_REG_FIFO:
578 fdctrl_write_data(fdctrl, value);
579 break;
580 default:
581 break;
582 }
583 }
584
585 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
586 {
587 return fdctrl_read(opaque, (uint32_t)reg);
588 }
589
590 static void fdctrl_write_mem (void *opaque,
591 target_phys_addr_t reg, uint32_t value)
592 {
593 fdctrl_write(opaque, (uint32_t)reg, value);
594 }
595
596 static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
597 fdctrl_read_mem,
598 fdctrl_read_mem,
599 fdctrl_read_mem,
600 };
601
602 static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
603 fdctrl_write_mem,
604 fdctrl_write_mem,
605 fdctrl_write_mem,
606 };
607
608 static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
609 fdctrl_read_mem,
610 NULL,
611 NULL,
612 };
613
614 static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
615 fdctrl_write_mem,
616 NULL,
617 NULL,
618 };
619
620 static void fd_save (QEMUFile *f, fdrive_t *fd)
621 {
622 uint8_t tmp;
623
624 tmp = fd->drflags;
625 qemu_put_8s(f, &tmp);
626 qemu_put_8s(f, &fd->head);
627 qemu_put_8s(f, &fd->track);
628 qemu_put_8s(f, &fd->sect);
629 qemu_put_8s(f, &fd->dir);
630 qemu_put_8s(f, &fd->rw);
631 }
632
633 static void fdc_save (QEMUFile *f, void *opaque)
634 {
635 fdctrl_t *s = opaque;
636
637 /* Controller state */
638 qemu_put_8s(f, &s->sra);
639 qemu_put_8s(f, &s->srb);
640 qemu_put_8s(f, &s->state);
641 qemu_put_8s(f, &s->dma_en);
642 qemu_put_8s(f, &s->cur_drv);
643 qemu_put_8s(f, &s->bootsel);
644 qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
645 qemu_put_be32s(f, &s->data_pos);
646 qemu_put_be32s(f, &s->data_len);
647 qemu_put_8s(f, &s->data_state);
648 qemu_put_8s(f, &s->data_dir);
649 qemu_put_8s(f, &s->int_status);
650 qemu_put_8s(f, &s->eot);
651 qemu_put_8s(f, &s->timer0);
652 qemu_put_8s(f, &s->timer1);
653 qemu_put_8s(f, &s->precomp_trk);
654 qemu_put_8s(f, &s->config);
655 qemu_put_8s(f, &s->lock);
656 qemu_put_8s(f, &s->pwrd);
657 fd_save(f, &s->drives[0]);
658 fd_save(f, &s->drives[1]);
659 }
660
661 static int fd_load (QEMUFile *f, fdrive_t *fd)
662 {
663 uint8_t tmp;
664
665 qemu_get_8s(f, &tmp);
666 fd->drflags = tmp;
667 qemu_get_8s(f, &fd->head);
668 qemu_get_8s(f, &fd->track);
669 qemu_get_8s(f, &fd->sect);
670 qemu_get_8s(f, &fd->dir);
671 qemu_get_8s(f, &fd->rw);
672
673 return 0;
674 }
675
676 static int fdc_load (QEMUFile *f, void *opaque, int version_id)
677 {
678 fdctrl_t *s = opaque;
679 int ret;
680
681 if (version_id != 1)
682 return -EINVAL;
683
684 /* Controller state */
685 qemu_get_8s(f, &s->sra);
686 qemu_get_8s(f, &s->srb);
687 qemu_get_8s(f, &s->state);
688 qemu_get_8s(f, &s->dma_en);
689 qemu_get_8s(f, &s->cur_drv);
690 qemu_get_8s(f, &s->bootsel);
691 qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
692 qemu_get_be32s(f, &s->data_pos);
693 qemu_get_be32s(f, &s->data_len);
694 qemu_get_8s(f, &s->data_state);
695 qemu_get_8s(f, &s->data_dir);
696 qemu_get_8s(f, &s->int_status);
697 qemu_get_8s(f, &s->eot);
698 qemu_get_8s(f, &s->timer0);
699 qemu_get_8s(f, &s->timer1);
700 qemu_get_8s(f, &s->precomp_trk);
701 qemu_get_8s(f, &s->config);
702 qemu_get_8s(f, &s->lock);
703 qemu_get_8s(f, &s->pwrd);
704
705 ret = fd_load(f, &s->drives[0]);
706 if (ret == 0)
707 ret = fd_load(f, &s->drives[1]);
708
709 return ret;
710 }
711
712 static void fdctrl_external_reset(void *opaque)
713 {
714 fdctrl_t *s = opaque;
715
716 fdctrl_reset(s, 0);
717 }
718
719 static void fdctrl_handle_tc(void *opaque, int irq, int level)
720 {
721 //fdctrl_t *s = opaque;
722
723 if (level) {
724 // XXX
725 FLOPPY_DPRINTF("TC pulsed\n");
726 }
727 }
728
729 /* XXX: may change if moved to bdrv */
730 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
731 {
732 return fdctrl->drives[drive_num].drive;
733 }
734
735 /* Change IRQ state */
736 static void fdctrl_reset_irq (fdctrl_t *fdctrl)
737 {
738 if (!(fdctrl->sra & FD_SRA_INTPEND))
739 return;
740 FLOPPY_DPRINTF("Reset interrupt\n");
741 qemu_set_irq(fdctrl->irq, 0);
742 fdctrl->sra &= ~FD_SRA_INTPEND;
743 }
744
745 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status)
746 {
747 // Sparc mutation
748 if (fdctrl->sun4m && !fdctrl->dma_en) {
749 fdctrl->state &= ~FD_CTRL_BUSY;
750 fdctrl->int_status = status;
751 return;
752 }
753 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
754 qemu_set_irq(fdctrl->irq, 1);
755 fdctrl->sra |= FD_SRA_INTPEND;
756 }
757 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", status);
758 fdctrl->int_status = status;
759 }
760
761 /* Reset controller */
762 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
763 {
764 int i;
765
766 FLOPPY_DPRINTF("reset controller\n");
767 fdctrl_reset_irq(fdctrl);
768 /* Initialise controller */
769 fdctrl->sra = 0;
770 fdctrl->srb = 0xc0;
771 if (!fdctrl->drives[1].bs)
772 fdctrl->sra |= FD_SRA_nDRV2;
773 fdctrl->cur_drv = 0;
774 /* FIFO state */
775 fdctrl->data_pos = 0;
776 fdctrl->data_len = 0;
777 fdctrl->data_state = FD_STATE_CMD;
778 fdctrl->data_dir = FD_DIR_WRITE;
779 for (i = 0; i < MAX_FD; i++)
780 fd_reset(&fdctrl->drives[i]);
781 fdctrl_reset_fifo(fdctrl);
782 if (do_irq)
783 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
784 }
785
786 static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
787 {
788 return &fdctrl->drives[fdctrl->bootsel];
789 }
790
791 static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
792 {
793 return &fdctrl->drives[1 - fdctrl->bootsel];
794 }
795
796 static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
797 {
798 return fdctrl->cur_drv == 0 ? drv0(fdctrl) : drv1(fdctrl);
799 }
800
801 /* Status A register : 0x00 (read-only) */
802 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
803 {
804 uint32_t retval = fdctrl->sra;
805
806 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
807
808 return retval;
809 }
810
811 /* Status B register : 0x01 (read-only) */
812 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
813 {
814 uint32_t retval = fdctrl->srb;
815
816 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
817
818 return retval;
819 }
820
821 /* Digital output register : 0x02 */
822 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
823 {
824 uint32_t retval = 0;
825
826 /* Drive motors state indicators */
827 if (drv0(fdctrl)->drflags & FDRIVE_MOTOR_ON)
828 retval |= FD_DOR_MOTEN0;
829 if (drv1(fdctrl)->drflags & FDRIVE_MOTOR_ON)
830 retval |= FD_DOR_MOTEN1;
831 /* DMA enable */
832 if (fdctrl->dma_en)
833 retval |= FD_DOR_DMAEN;
834 /* Reset indicator */
835 if (!(fdctrl->state & FD_CTRL_RESET))
836 retval |= FD_DOR_nRESET;
837 /* Selected drive */
838 retval |= fdctrl->cur_drv;
839 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
840
841 return retval;
842 }
843
844 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
845 {
846 /* Reset mode */
847 if (fdctrl->state & FD_CTRL_RESET) {
848 if (!(value & FD_DOR_nRESET)) {
849 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
850 return;
851 }
852 }
853 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
854
855 /* Motors */
856 if (value & FD_DOR_MOTEN0)
857 fdctrl->srb |= FD_SRB_MTR0;
858 else
859 fdctrl->srb &= ~FD_SRB_MTR0;
860 if (value & FD_DOR_MOTEN1)
861 fdctrl->srb |= FD_SRB_MTR1;
862 else
863 fdctrl->srb &= ~FD_SRB_MTR1;
864
865 /* Drive */
866 if (value & 1)
867 fdctrl->srb |= FD_SRB_DR0;
868 else
869 fdctrl->srb &= ~FD_SRB_DR0;
870
871 /* Drive motors state indicators */
872 if (value & FD_DOR_MOTEN1)
873 fd_start(drv1(fdctrl));
874 else
875 fd_stop(drv1(fdctrl));
876 if (value & FD_DOR_MOTEN0)
877 fd_start(drv0(fdctrl));
878 else
879 fd_stop(drv0(fdctrl));
880 /* DMA enable */
881 #if 0
882 if (fdctrl->dma_chann != -1)
883 fdctrl->dma_en = value & FD_DOR_DMAEN ? 1 : 0;
884 #endif
885 /* Reset */
886 if (!(value & FD_DOR_nRESET)) {
887 if (!(fdctrl->state & FD_CTRL_RESET)) {
888 FLOPPY_DPRINTF("controller enter RESET state\n");
889 fdctrl->state |= FD_CTRL_RESET;
890 }
891 } else {
892 if (fdctrl->state & FD_CTRL_RESET) {
893 FLOPPY_DPRINTF("controller out of RESET state\n");
894 fdctrl_reset(fdctrl, 1);
895 fdctrl->state &= ~(FD_CTRL_RESET | FD_CTRL_SLEEP);
896 }
897 }
898 /* Selected drive */
899 fdctrl->cur_drv = value & FD_DOR_SELMASK;
900 }
901
902 /* Tape drive register : 0x03 */
903 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
904 {
905 uint32_t retval = 0;
906
907 /* Disk boot selection indicator */
908 retval |= fdctrl->bootsel << 2;
909 /* Tape indicators: never allowed */
910 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
911
912 return retval;
913 }
914
915 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
916 {
917 /* Reset mode */
918 if (fdctrl->state & FD_CTRL_RESET) {
919 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
920 return;
921 }
922 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
923 /* Disk boot selection indicator */
924 fdctrl->bootsel = (value & FD_TDR_BOOTSEL) >> 2;
925 /* Tape indicators: never allow */
926 }
927
928 /* Main status register : 0x04 (read) */
929 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
930 {
931 uint32_t retval = 0;
932
933 fdctrl->state &= ~(FD_CTRL_SLEEP | FD_CTRL_RESET);
934 if (!(fdctrl->state & FD_CTRL_BUSY)) {
935 /* Data transfer allowed */
936 retval |= FD_MSR_RQM;
937 /* Data transfer direction indicator */
938 if (fdctrl->data_dir == FD_DIR_READ)
939 retval |= FD_MSR_DIO;
940 }
941 /* Should handle FD_MSR_NONDMA for SPECIFY command */
942 /* Command busy indicator */
943 if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA ||
944 FD_STATE(fdctrl->data_state) == FD_STATE_STATUS)
945 retval |= FD_MSR_CMDBUSY;
946 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
947
948 return retval;
949 }
950
951 /* Data select rate register : 0x04 (write) */
952 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
953 {
954 /* Reset mode */
955 if (fdctrl->state & FD_CTRL_RESET) {
956 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
957 return;
958 }
959 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
960 /* Reset: autoclear */
961 if (value & FD_DSR_SWRESET) {
962 fdctrl->state |= FD_CTRL_RESET;
963 fdctrl_reset(fdctrl, 1);
964 fdctrl->state &= ~FD_CTRL_RESET;
965 }
966 if (value & FD_DSR_PWRDOWN) {
967 fdctrl->state |= FD_CTRL_SLEEP;
968 fdctrl_reset(fdctrl, 1);
969 }
970 }
971
972 static int fdctrl_media_changed(fdrive_t *drv)
973 {
974 int ret;
975
976 if (!drv->bs)
977 return 0;
978 ret = bdrv_media_changed(drv->bs);
979 if (ret) {
980 fd_revalidate(drv);
981 }
982 return ret;
983 }
984
985 /* Digital input register : 0x07 (read-only) */
986 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
987 {
988 uint32_t retval = 0;
989
990 if (fdctrl_media_changed(drv0(fdctrl)) ||
991 fdctrl_media_changed(drv1(fdctrl)))
992 retval |= FD_DIR_DSKCHG;
993 if (retval != 0)
994 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
995
996 return retval;
997 }
998
999 /* FIFO state control */
1000 static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
1001 {
1002 fdctrl->data_dir = FD_DIR_WRITE;
1003 fdctrl->data_pos = 0;
1004 FD_SET_STATE(fdctrl->data_state, FD_STATE_CMD);
1005 }
1006
1007 /* Set FIFO status for the host to read */
1008 static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
1009 {
1010 fdctrl->data_dir = FD_DIR_READ;
1011 fdctrl->data_len = fifo_len;
1012 fdctrl->data_pos = 0;
1013 FD_SET_STATE(fdctrl->data_state, FD_STATE_STATUS);
1014 if (do_irq)
1015 fdctrl_raise_irq(fdctrl, 0x00);
1016 }
1017
1018 /* Set an error: unimplemented/unknown command */
1019 static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1020 {
1021 #if 0
1022 fdrive_t *cur_drv;
1023
1024 cur_drv = get_cur_drv(fdctrl);
1025 fdctrl->fifo[0] = FD_SR0_ABNTERM | FD_SR0_SEEK | (cur_drv->head << 2) | fdctrl->cur_drv;
1026 fdctrl->fifo[1] = 0x00;
1027 fdctrl->fifo[2] = 0x00;
1028 fdctrl_set_fifo(fdctrl, 3, 1);
1029 #else
1030 // fdctrl_reset_fifo(fdctrl);
1031 fdctrl->fifo[0] = FD_SR0_INVCMD;
1032 fdctrl_set_fifo(fdctrl, 1, 0);
1033 #endif
1034 }
1035
1036 /* Seek to next sector */
1037 static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1038 {
1039 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1040 cur_drv->head, cur_drv->track, cur_drv->sect,
1041 fd_sector(cur_drv));
1042 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1043 error in fact */
1044 if (cur_drv->sect >= cur_drv->last_sect ||
1045 cur_drv->sect == fdctrl->eot) {
1046 cur_drv->sect = 1;
1047 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1048 if (cur_drv->head == 0 &&
1049 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1050 cur_drv->head = 1;
1051 } else {
1052 cur_drv->head = 0;
1053 cur_drv->track++;
1054 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1055 return 0;
1056 }
1057 } else {
1058 cur_drv->track++;
1059 return 0;
1060 }
1061 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1062 cur_drv->head, cur_drv->track,
1063 cur_drv->sect, fd_sector(cur_drv));
1064 } else {
1065 cur_drv->sect++;
1066 }
1067 return 1;
1068 }
1069
1070 /* Callback for transfer end (stop or abort) */
1071 static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1072 uint8_t status1, uint8_t status2)
1073 {
1074 fdrive_t *cur_drv;
1075
1076 cur_drv = get_cur_drv(fdctrl);
1077 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1078 status0, status1, status2,
1079 status0 | (cur_drv->head << 2) | fdctrl->cur_drv);
1080 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | fdctrl->cur_drv;
1081 fdctrl->fifo[1] = status1;
1082 fdctrl->fifo[2] = status2;
1083 fdctrl->fifo[3] = cur_drv->track;
1084 fdctrl->fifo[4] = cur_drv->head;
1085 fdctrl->fifo[5] = cur_drv->sect;
1086 fdctrl->fifo[6] = FD_SECTOR_SC;
1087 fdctrl->data_dir = FD_DIR_READ;
1088 if (fdctrl->state & FD_CTRL_BUSY) {
1089 DMA_release_DREQ(fdctrl->dma_chann);
1090 fdctrl->state &= ~FD_CTRL_BUSY;
1091 }
1092 fdctrl_set_fifo(fdctrl, 7, 1);
1093 }
1094
1095 /* Prepare a data transfer (either DMA or FIFO) */
1096 static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1097 {
1098 fdrive_t *cur_drv;
1099 uint8_t kh, kt, ks;
1100 int did_seek;
1101
1102 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1103 cur_drv = get_cur_drv(fdctrl);
1104 kt = fdctrl->fifo[2];
1105 kh = fdctrl->fifo[3];
1106 ks = fdctrl->fifo[4];
1107 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1108 fdctrl->cur_drv, kh, kt, ks,
1109 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1110 did_seek = 0;
1111 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & 0x40)) {
1112 case 2:
1113 /* sect too big */
1114 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1115 fdctrl->fifo[3] = kt;
1116 fdctrl->fifo[4] = kh;
1117 fdctrl->fifo[5] = ks;
1118 return;
1119 case 3:
1120 /* track too big */
1121 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x80, 0x00);
1122 fdctrl->fifo[3] = kt;
1123 fdctrl->fifo[4] = kh;
1124 fdctrl->fifo[5] = ks;
1125 return;
1126 case 4:
1127 /* No seek enabled */
1128 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1129 fdctrl->fifo[3] = kt;
1130 fdctrl->fifo[4] = kh;
1131 fdctrl->fifo[5] = ks;
1132 return;
1133 case 1:
1134 did_seek = 1;
1135 break;
1136 default:
1137 break;
1138 }
1139 /* Set the FIFO state */
1140 fdctrl->data_dir = direction;
1141 fdctrl->data_pos = 0;
1142 FD_SET_STATE(fdctrl->data_state, FD_STATE_DATA); /* FIFO ready for data */
1143 if (fdctrl->fifo[0] & 0x80)
1144 fdctrl->data_state |= FD_STATE_MULTI;
1145 else
1146 fdctrl->data_state &= ~FD_STATE_MULTI;
1147 if (did_seek)
1148 fdctrl->data_state |= FD_STATE_SEEK;
1149 else
1150 fdctrl->data_state &= ~FD_STATE_SEEK;
1151 if (fdctrl->fifo[5] == 00) {
1152 fdctrl->data_len = fdctrl->fifo[8];
1153 } else {
1154 int tmp;
1155 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1156 tmp = (cur_drv->last_sect - ks + 1);
1157 if (fdctrl->fifo[0] & 0x80)
1158 tmp += cur_drv->last_sect;
1159 fdctrl->data_len *= tmp;
1160 }
1161 fdctrl->eot = fdctrl->fifo[6];
1162 if (fdctrl->dma_en) {
1163 int dma_mode;
1164 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1165 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1166 dma_mode = (dma_mode >> 2) & 3;
1167 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1168 dma_mode, direction,
1169 (128 << fdctrl->fifo[5]) *
1170 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1171 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1172 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1173 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1174 (direction == FD_DIR_READ && dma_mode == 1)) {
1175 /* No access is allowed until DMA transfer has completed */
1176 fdctrl->state |= FD_CTRL_BUSY;
1177 /* Now, we just have to wait for the DMA controller to
1178 * recall us...
1179 */
1180 DMA_hold_DREQ(fdctrl->dma_chann);
1181 DMA_schedule(fdctrl->dma_chann);
1182 return;
1183 } else {
1184 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1185 }
1186 }
1187 FLOPPY_DPRINTF("start non-DMA transfer\n");
1188 /* IO based transfer: calculate len */
1189 fdctrl_raise_irq(fdctrl, 0x00);
1190
1191 return;
1192 }
1193
1194 /* Prepare a transfer of deleted data */
1195 static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1196 {
1197 /* We don't handle deleted data,
1198 * so we don't return *ANYTHING*
1199 */
1200 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1201 }
1202
1203 /* handlers for DMA transfers */
1204 static int fdctrl_transfer_handler (void *opaque, int nchan,
1205 int dma_pos, int dma_len)
1206 {
1207 fdctrl_t *fdctrl;
1208 fdrive_t *cur_drv;
1209 int len, start_pos, rel_pos;
1210 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1211
1212 fdctrl = opaque;
1213 if (!(fdctrl->state & FD_CTRL_BUSY)) {
1214 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1215 return 0;
1216 }
1217 cur_drv = get_cur_drv(fdctrl);
1218 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1219 fdctrl->data_dir == FD_DIR_SCANH)
1220 status2 = 0x04;
1221 if (dma_len > fdctrl->data_len)
1222 dma_len = fdctrl->data_len;
1223 if (cur_drv->bs == NULL) {
1224 if (fdctrl->data_dir == FD_DIR_WRITE)
1225 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1226 else
1227 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1228 len = 0;
1229 goto transfer_error;
1230 }
1231 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1232 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1233 len = dma_len - fdctrl->data_pos;
1234 if (len + rel_pos > FD_SECTOR_LEN)
1235 len = FD_SECTOR_LEN - rel_pos;
1236 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1237 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1238 fdctrl->data_len, fdctrl->cur_drv, cur_drv->head,
1239 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1240 fd_sector(cur_drv) * FD_SECTOR_LEN);
1241 if (fdctrl->data_dir != FD_DIR_WRITE ||
1242 len < FD_SECTOR_LEN || rel_pos != 0) {
1243 /* READ & SCAN commands and realign to a sector for WRITE */
1244 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1245 fdctrl->fifo, 1) < 0) {
1246 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1247 fd_sector(cur_drv));
1248 /* Sure, image size is too small... */
1249 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1250 }
1251 }
1252 switch (fdctrl->data_dir) {
1253 case FD_DIR_READ:
1254 /* READ commands */
1255 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1256 fdctrl->data_pos, len);
1257 break;
1258 case FD_DIR_WRITE:
1259 /* WRITE commands */
1260 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1261 fdctrl->data_pos, len);
1262 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1263 fdctrl->fifo, 1) < 0) {
1264 FLOPPY_ERROR("writting sector %d\n", fd_sector(cur_drv));
1265 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1266 goto transfer_error;
1267 }
1268 break;
1269 default:
1270 /* SCAN commands */
1271 {
1272 uint8_t tmpbuf[FD_SECTOR_LEN];
1273 int ret;
1274 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1275 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1276 if (ret == 0) {
1277 status2 = 0x08;
1278 goto end_transfer;
1279 }
1280 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1281 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1282 status2 = 0x00;
1283 goto end_transfer;
1284 }
1285 }
1286 break;
1287 }
1288 fdctrl->data_pos += len;
1289 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1290 if (rel_pos == 0) {
1291 /* Seek to next sector */
1292 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1293 break;
1294 }
1295 }
1296 end_transfer:
1297 len = fdctrl->data_pos - start_pos;
1298 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1299 fdctrl->data_pos, len, fdctrl->data_len);
1300 if (fdctrl->data_dir == FD_DIR_SCANE ||
1301 fdctrl->data_dir == FD_DIR_SCANL ||
1302 fdctrl->data_dir == FD_DIR_SCANH)
1303 status2 = 0x08;
1304 if (FD_DID_SEEK(fdctrl->data_state))
1305 status0 |= FD_SR0_SEEK;
1306 fdctrl->data_len -= len;
1307 // if (fdctrl->data_len == 0)
1308 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1309 transfer_error:
1310
1311 return len;
1312 }
1313
1314 /* Data register : 0x05 */
1315 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1316 {
1317 fdrive_t *cur_drv;
1318 uint32_t retval = 0;
1319 int pos;
1320
1321 cur_drv = get_cur_drv(fdctrl);
1322 fdctrl->state &= ~FD_CTRL_SLEEP;
1323 if (FD_STATE(fdctrl->data_state) == FD_STATE_CMD) {
1324 FLOPPY_ERROR("can't read data in CMD state\n");
1325 return 0;
1326 }
1327 pos = fdctrl->data_pos;
1328 if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
1329 pos %= FD_SECTOR_LEN;
1330 if (pos == 0) {
1331 if (fdctrl->data_pos != 0)
1332 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1333 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1334 fd_sector(cur_drv));
1335 return 0;
1336 }
1337 bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1);
1338 }
1339 }
1340 retval = fdctrl->fifo[pos];
1341 if (++fdctrl->data_pos == fdctrl->data_len) {
1342 fdctrl->data_pos = 0;
1343 /* Switch from transfer mode to status mode
1344 * then from status mode to command mode
1345 */
1346 if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
1347 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1348 } else {
1349 fdctrl_reset_fifo(fdctrl);
1350 fdctrl_reset_irq(fdctrl);
1351 }
1352 }
1353 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1354
1355 return retval;
1356 }
1357
1358 static void fdctrl_format_sector (fdctrl_t *fdctrl)
1359 {
1360 fdrive_t *cur_drv;
1361 uint8_t kh, kt, ks;
1362 int did_seek;
1363
1364 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1365 cur_drv = get_cur_drv(fdctrl);
1366 kt = fdctrl->fifo[6];
1367 kh = fdctrl->fifo[7];
1368 ks = fdctrl->fifo[8];
1369 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1370 fdctrl->cur_drv, kh, kt, ks,
1371 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1372 did_seek = 0;
1373 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1374 case 2:
1375 /* sect too big */
1376 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1377 fdctrl->fifo[3] = kt;
1378 fdctrl->fifo[4] = kh;
1379 fdctrl->fifo[5] = ks;
1380 return;
1381 case 3:
1382 /* track too big */
1383 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x80, 0x00);
1384 fdctrl->fifo[3] = kt;
1385 fdctrl->fifo[4] = kh;
1386 fdctrl->fifo[5] = ks;
1387 return;
1388 case 4:
1389 /* No seek enabled */
1390 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1391 fdctrl->fifo[3] = kt;
1392 fdctrl->fifo[4] = kh;
1393 fdctrl->fifo[5] = ks;
1394 return;
1395 case 1:
1396 did_seek = 1;
1397 fdctrl->data_state |= FD_STATE_SEEK;
1398 break;
1399 default:
1400 break;
1401 }
1402 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1403 if (cur_drv->bs == NULL ||
1404 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1405 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1406 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1407 } else {
1408 if (cur_drv->sect == cur_drv->last_sect) {
1409 fdctrl->data_state &= ~FD_STATE_FORMAT;
1410 /* Last sector done */
1411 if (FD_DID_SEEK(fdctrl->data_state))
1412 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1413 else
1414 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1415 } else {
1416 /* More to do */
1417 fdctrl->data_pos = 0;
1418 fdctrl->data_len = 4;
1419 }
1420 }
1421 }
1422
1423 static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1424 {
1425 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1426 fdctrl->fifo[0] = fdctrl->lock << 4;
1427 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1428 }
1429
1430 static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1431 {
1432 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1433
1434 /* Drives position */
1435 fdctrl->fifo[0] = drv0(fdctrl)->track;
1436 fdctrl->fifo[1] = drv1(fdctrl)->track;
1437 fdctrl->fifo[2] = 0;
1438 fdctrl->fifo[3] = 0;
1439 /* timers */
1440 fdctrl->fifo[4] = fdctrl->timer0;
1441 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | fdctrl->dma_en;
1442 fdctrl->fifo[6] = cur_drv->last_sect;
1443 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1444 (cur_drv->perpendicular << 2);
1445 fdctrl->fifo[8] = fdctrl->config;
1446 fdctrl->fifo[9] = fdctrl->precomp_trk;
1447 fdctrl_set_fifo(fdctrl, 10, 0);
1448 }
1449
1450 static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1451 {
1452 /* Controller's version */
1453 fdctrl->fifo[0] = fdctrl->version;
1454 fdctrl_set_fifo(fdctrl, 1, 1);
1455 }
1456
1457 static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1458 {
1459 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1460 fdctrl_set_fifo(fdctrl, 1, 0);
1461 }
1462
1463 static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1464 {
1465 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1466
1467 /* Drives position */
1468 drv0(fdctrl)->track = fdctrl->fifo[3];
1469 drv1(fdctrl)->track = fdctrl->fifo[4];
1470 /* timers */
1471 fdctrl->timer0 = fdctrl->fifo[7];
1472 fdctrl->timer1 = fdctrl->fifo[8];
1473 cur_drv->last_sect = fdctrl->fifo[9];
1474 fdctrl->lock = fdctrl->fifo[10] >> 7;
1475 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1476 fdctrl->config = fdctrl->fifo[11];
1477 fdctrl->precomp_trk = fdctrl->fifo[12];
1478 fdctrl->pwrd = fdctrl->fifo[13];
1479 fdctrl_reset_fifo(fdctrl);
1480 }
1481
1482 static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1483 {
1484 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1485
1486 fdctrl->fifo[0] = 0;
1487 fdctrl->fifo[1] = 0;
1488 /* Drives position */
1489 fdctrl->fifo[2] = drv0(fdctrl)->track;
1490 fdctrl->fifo[3] = drv1(fdctrl)->track;
1491 fdctrl->fifo[4] = 0;
1492 fdctrl->fifo[5] = 0;
1493 /* timers */
1494 fdctrl->fifo[6] = fdctrl->timer0;
1495 fdctrl->fifo[7] = fdctrl->timer1;
1496 fdctrl->fifo[8] = cur_drv->last_sect;
1497 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1498 (cur_drv->perpendicular << 2);
1499 fdctrl->fifo[10] = fdctrl->config;
1500 fdctrl->fifo[11] = fdctrl->precomp_trk;
1501 fdctrl->fifo[12] = fdctrl->pwrd;
1502 fdctrl->fifo[13] = 0;
1503 fdctrl->fifo[14] = 0;
1504 fdctrl_set_fifo(fdctrl, 15, 1);
1505 }
1506
1507 static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1508 {
1509 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1510
1511 /* XXX: should set main status register to busy */
1512 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1513 qemu_mod_timer(fdctrl->result_timer,
1514 qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
1515 }
1516
1517 static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1518 {
1519 fdrive_t *cur_drv;
1520
1521 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1522 cur_drv = get_cur_drv(fdctrl);
1523 fdctrl->data_state |= FD_STATE_FORMAT;
1524 if (fdctrl->fifo[0] & 0x80)
1525 fdctrl->data_state |= FD_STATE_MULTI;
1526 else
1527 fdctrl->data_state &= ~FD_STATE_MULTI;
1528 fdctrl->data_state &= ~FD_STATE_SEEK;
1529 cur_drv->bps =
1530 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1531 #if 0
1532 cur_drv->last_sect =
1533 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1534 fdctrl->fifo[3] / 2;
1535 #else
1536 cur_drv->last_sect = fdctrl->fifo[3];
1537 #endif
1538 /* TODO: implement format using DMA expected by the Bochs BIOS
1539 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1540 * the sector with the specified fill byte
1541 */
1542 fdctrl->data_state &= ~FD_STATE_FORMAT;
1543 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1544 }
1545
1546 static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1547 {
1548 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1549 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1550 fdctrl->dma_en = 1 - (fdctrl->fifo[2] & 1) ;
1551 /* No result back */
1552 fdctrl_reset_fifo(fdctrl);
1553 }
1554
1555 static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1556 {
1557 fdrive_t *cur_drv;
1558
1559 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1560 cur_drv = get_cur_drv(fdctrl);
1561 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1562 /* 1 Byte status back */
1563 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1564 (cur_drv->track == 0 ? 0x10 : 0x00) |
1565 (cur_drv->head << 2) |
1566 fdctrl->cur_drv |
1567 0x28;
1568 fdctrl_set_fifo(fdctrl, 1, 0);
1569 }
1570
1571 static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1572 {
1573 fdrive_t *cur_drv;
1574
1575 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1576 cur_drv = get_cur_drv(fdctrl);
1577 fd_recalibrate(cur_drv);
1578 fdctrl_reset_fifo(fdctrl);
1579 /* Raise Interrupt */
1580 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1581 }
1582
1583 static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1584 {
1585 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1586
1587 #if 0
1588 fdctrl->fifo[0] =
1589 fdctrl->int_status | (cur_drv->head << 2) | fdctrl->cur_drv;
1590 #else
1591 /* XXX: int_status handling is broken for read/write
1592 commands, so we do this hack. It should be suppressed
1593 ASAP */
1594 fdctrl->fifo[0] =
1595 0x20 | (cur_drv->head << 2) | fdctrl->cur_drv;
1596 #endif
1597 fdctrl->fifo[1] = cur_drv->track;
1598 fdctrl_set_fifo(fdctrl, 2, 0);
1599 fdctrl_reset_irq(fdctrl);
1600 fdctrl->int_status = FD_SR0_RDYCHG;
1601 }
1602
1603 static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1604 {
1605 fdrive_t *cur_drv;
1606
1607 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1608 cur_drv = get_cur_drv(fdctrl);
1609 fd_start(cur_drv);
1610 if (fdctrl->fifo[2] <= cur_drv->track)
1611 cur_drv->dir = 1;
1612 else
1613 cur_drv->dir = 0;
1614 fdctrl_reset_fifo(fdctrl);
1615 if (fdctrl->fifo[2] > cur_drv->max_track) {
1616 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1617 } else {
1618 cur_drv->track = fdctrl->fifo[2];
1619 /* Raise Interrupt */
1620 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1621 }
1622 }
1623
1624 static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1625 {
1626 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1627
1628 if (fdctrl->fifo[1] & 0x80)
1629 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1630 /* No result back */
1631 fdctrl_reset_fifo(fdctrl);
1632 }
1633
1634 static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1635 {
1636 fdctrl->config = fdctrl->fifo[2];
1637 fdctrl->precomp_trk = fdctrl->fifo[3];
1638 /* No result back */
1639 fdctrl_reset_fifo(fdctrl);
1640 }
1641
1642 static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1643 {
1644 fdctrl->pwrd = fdctrl->fifo[1];
1645 fdctrl->fifo[0] = fdctrl->fifo[1];
1646 fdctrl_set_fifo(fdctrl, 1, 1);
1647 }
1648
1649 static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1650 {
1651 /* No result back */
1652 fdctrl_reset_fifo(fdctrl);
1653 }
1654
1655 static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1656 {
1657 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1658
1659 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1660 /* Command parameters done */
1661 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1662 fdctrl->fifo[0] = fdctrl->fifo[1];
1663 fdctrl->fifo[2] = 0;
1664 fdctrl->fifo[3] = 0;
1665 fdctrl_set_fifo(fdctrl, 4, 1);
1666 } else {
1667 fdctrl_reset_fifo(fdctrl);
1668 }
1669 } else if (fdctrl->data_len > 7) {
1670 /* ERROR */
1671 fdctrl->fifo[0] = 0x80 |
1672 (cur_drv->head << 2) | fdctrl->cur_drv;
1673 fdctrl_set_fifo(fdctrl, 1, 1);
1674 }
1675 }
1676
1677 static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1678 {
1679 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1680
1681 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1682 cur_drv = get_cur_drv(fdctrl);
1683 fd_start(cur_drv);
1684 cur_drv->dir = 0;
1685 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1686 cur_drv->track = cur_drv->max_track - 1;
1687 } else {
1688 cur_drv->track += fdctrl->fifo[2];
1689 }
1690 fdctrl_reset_fifo(fdctrl);
1691 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1692 }
1693
1694 static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1695 {
1696 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1697
1698 fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
1699 cur_drv = get_cur_drv(fdctrl);
1700 fd_start(cur_drv);
1701 cur_drv->dir = 1;
1702 if (fdctrl->fifo[2] > cur_drv->track) {
1703 cur_drv->track = 0;
1704 } else {
1705 cur_drv->track -= fdctrl->fifo[2];
1706 }
1707 fdctrl_reset_fifo(fdctrl);
1708 /* Raise Interrupt */
1709 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1710 }
1711
1712 static const struct {
1713 uint8_t value;
1714 uint8_t mask;
1715 const char* name;
1716 int parameters;
1717 void (*handler)(fdctrl_t *fdctrl, int direction);
1718 int direction;
1719 } handlers[] = {
1720 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1721 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1722 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1723 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1724 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1725 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1726 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1727 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1728 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1729 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1730 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1731 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1732 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1733 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1734 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1735 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1736 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1737 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1738 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1739 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1740 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1741 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1742 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1743 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1744 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1745 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1746 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1747 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1748 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1749 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1750 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1751 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1752 };
1753 /* Associate command to an index in the 'handlers' array */
1754 static uint8_t command_to_handler[256];
1755
1756 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1757 {
1758 fdrive_t *cur_drv;
1759 int pos;
1760
1761 cur_drv = get_cur_drv(fdctrl);
1762 /* Reset mode */
1763 if (fdctrl->state & FD_CTRL_RESET) {
1764 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1765 return;
1766 }
1767 fdctrl->state &= ~FD_CTRL_SLEEP;
1768 if (FD_STATE(fdctrl->data_state) == FD_STATE_STATUS) {
1769 FLOPPY_ERROR("can't write data in status mode\n");
1770 return;
1771 }
1772 /* Is it write command time ? */
1773 if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
1774 /* FIFO data write */
1775 fdctrl->fifo[fdctrl->data_pos++] = value;
1776 if (fdctrl->data_pos % FD_SECTOR_LEN == (FD_SECTOR_LEN - 1) ||
1777 fdctrl->data_pos == fdctrl->data_len) {
1778 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1);
1779 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1780 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1781 fd_sector(cur_drv));
1782 return;
1783 }
1784 }
1785 /* Switch from transfer mode to status mode
1786 * then from status mode to command mode
1787 */
1788 if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA)
1789 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1790 return;
1791 }
1792 if (fdctrl->data_pos == 0) {
1793 /* Command */
1794 pos = command_to_handler[value & 0xff];
1795 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1796 fdctrl->data_len = handlers[pos].parameters + 1;
1797 }
1798
1799 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1800 fdctrl->fifo[fdctrl->data_pos] = value;
1801 if (++fdctrl->data_pos == fdctrl->data_len) {
1802 /* We now have all parameters
1803 * and will be able to treat the command
1804 */
1805 if (fdctrl->data_state & FD_STATE_FORMAT) {
1806 fdctrl_format_sector(fdctrl);
1807 return;
1808 }
1809
1810 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1811 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1812 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1813 }
1814 }
1815
1816 static void fdctrl_result_timer(void *opaque)
1817 {
1818 fdctrl_t *fdctrl = opaque;
1819 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1820
1821 /* Pretend we are spinning.
1822 * This is needed for Coherent, which uses READ ID to check for
1823 * sector interleaving.
1824 */
1825 if (cur_drv->last_sect != 0) {
1826 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1827 }
1828 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1829 }
1830
1831 /* Init functions */
1832 static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
1833 target_phys_addr_t io_base,
1834 BlockDriverState **fds)
1835 {
1836 fdctrl_t *fdctrl;
1837 int i, j;
1838
1839 /* Fill 'command_to_handler' lookup table */
1840 for (i = sizeof(handlers)/sizeof(handlers[0]) - 1; i >= 0; i--) {
1841 for (j = 0; j < sizeof(command_to_handler); j++) {
1842 if ((j & handlers[i].mask) == handlers[i].value)
1843 command_to_handler[j] = i;
1844 }
1845 }
1846
1847 FLOPPY_DPRINTF("init controller\n");
1848 fdctrl = qemu_mallocz(sizeof(fdctrl_t));
1849 if (!fdctrl)
1850 return NULL;
1851 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1852 if (fdctrl->fifo == NULL) {
1853 qemu_free(fdctrl);
1854 return NULL;
1855 }
1856 fdctrl->result_timer = qemu_new_timer(vm_clock,
1857 fdctrl_result_timer, fdctrl);
1858
1859 fdctrl->version = 0x90; /* Intel 82078 controller */
1860 fdctrl->irq = irq;
1861 fdctrl->dma_chann = dma_chann;
1862 fdctrl->io_base = io_base;
1863 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1864 if (fdctrl->dma_chann != -1) {
1865 fdctrl->dma_en = 1;
1866 DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1867 } else {
1868 fdctrl->dma_en = 0;
1869 }
1870 for (i = 0; i < MAX_FD; i++) {
1871 fd_init(&fdctrl->drives[i], fds[i]);
1872 }
1873 fdctrl_reset(fdctrl, 0);
1874 fdctrl->state = FD_CTRL_ACTIVE;
1875 register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl);
1876 qemu_register_reset(fdctrl_external_reset, fdctrl);
1877 for (i = 0; i < MAX_FD; i++) {
1878 fd_revalidate(&fdctrl->drives[i]);
1879 }
1880
1881 return fdctrl;
1882 }
1883
1884 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1885 target_phys_addr_t io_base,
1886 BlockDriverState **fds)
1887 {
1888 fdctrl_t *fdctrl;
1889 int io_mem;
1890
1891 fdctrl = fdctrl_init_common(irq, dma_chann, io_base, fds);
1892
1893 fdctrl->sun4m = 0;
1894 if (mem_mapped) {
1895 io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write,
1896 fdctrl);
1897 cpu_register_physical_memory(io_base, 0x08, io_mem);
1898 } else {
1899 register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read,
1900 fdctrl);
1901 register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read,
1902 fdctrl);
1903 register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write,
1904 fdctrl);
1905 register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
1906 fdctrl);
1907 }
1908
1909 return fdctrl;
1910 }
1911
1912 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1913 BlockDriverState **fds, qemu_irq *fdc_tc)
1914 {
1915 fdctrl_t *fdctrl;
1916 int io_mem;
1917
1918 fdctrl = fdctrl_init_common(irq, 0, io_base, fds);
1919 fdctrl->sun4m = 1;
1920 io_mem = cpu_register_io_memory(0, fdctrl_mem_read_strict,
1921 fdctrl_mem_write_strict,
1922 fdctrl);
1923 cpu_register_physical_memory(io_base, 0x08, io_mem);
1924 *fdc_tc = *qemu_allocate_irqs(fdctrl_handle_tc, fdctrl, 1);
1925
1926 return fdctrl;
1927 }
Qemu copy for testing