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Merge branch 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
[qemu.git] / hw / fdc.c
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37 #include "blockdev.h"
38 #include "sysemu.h"
39 #include "qemu-log.h"
40
41 /********************************************************/
42 /* debug Floppy devices */
43 //#define DEBUG_FLOPPY
44
45 #ifdef DEBUG_FLOPPY
46 #define FLOPPY_DPRINTF(fmt, ...) \
47 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
48 #else
49 #define FLOPPY_DPRINTF(fmt, ...)
50 #endif
51
52 /********************************************************/
53 /* Floppy drive emulation */
54
55 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
56 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
57
58 /* Will always be a fixed parameter for us */
59 #define FD_SECTOR_LEN 512
60 #define FD_SECTOR_SC 2 /* Sector size code */
61 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
62
63 typedef struct FDCtrl FDCtrl;
64
65 /* Floppy disk drive emulation */
66 typedef enum FDiskFlags {
67 FDISK_DBL_SIDES = 0x01,
68 } FDiskFlags;
69
70 typedef struct FDrive {
71 FDCtrl *fdctrl;
72 BlockDriverState *bs;
73 /* Drive status */
74 FDriveType drive;
75 uint8_t perpendicular; /* 2.88 MB access mode */
76 /* Position */
77 uint8_t head;
78 uint8_t track;
79 uint8_t sect;
80 /* Media */
81 FDiskFlags flags;
82 uint8_t last_sect; /* Nb sector per track */
83 uint8_t max_track; /* Nb of tracks */
84 uint16_t bps; /* Bytes per sector */
85 uint8_t ro; /* Is read-only */
86 uint8_t media_changed; /* Is media changed */
87 uint8_t media_rate; /* Data rate of medium */
88 } FDrive;
89
90 static void fd_init(FDrive *drv)
91 {
92 /* Drive */
93 drv->drive = FDRIVE_DRV_NONE;
94 drv->perpendicular = 0;
95 /* Disk */
96 drv->last_sect = 0;
97 drv->max_track = 0;
98 }
99
100 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
101
102 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
103 uint8_t last_sect, uint8_t num_sides)
104 {
105 return (((track * num_sides) + head) * last_sect) + sect - 1;
106 }
107
108 /* Returns current position, in sectors, for given drive */
109 static int fd_sector(FDrive *drv)
110 {
111 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
112 NUM_SIDES(drv));
113 }
114
115 /* Seek to a new position:
116 * returns 0 if already on right track
117 * returns 1 if track changed
118 * returns 2 if track is invalid
119 * returns 3 if sector is invalid
120 * returns 4 if seek is disabled
121 */
122 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
123 int enable_seek)
124 {
125 uint32_t sector;
126 int ret;
127
128 if (track > drv->max_track ||
129 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
130 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
131 head, track, sect, 1,
132 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
133 drv->max_track, drv->last_sect);
134 return 2;
135 }
136 if (sect > drv->last_sect) {
137 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
138 head, track, sect, 1,
139 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
140 drv->max_track, drv->last_sect);
141 return 3;
142 }
143 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
144 ret = 0;
145 if (sector != fd_sector(drv)) {
146 #if 0
147 if (!enable_seek) {
148 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
149 " (max=%d %02x %02x)\n",
150 head, track, sect, 1, drv->max_track,
151 drv->last_sect);
152 return 4;
153 }
154 #endif
155 drv->head = head;
156 if (drv->track != track)
157 ret = 1;
158 drv->track = track;
159 drv->sect = sect;
160 }
161
162 if (drv->bs == NULL || !bdrv_is_inserted(drv->bs)) {
163 ret = 2;
164 }
165
166 return ret;
167 }
168
169 /* Set drive back to track 0 */
170 static void fd_recalibrate(FDrive *drv)
171 {
172 FLOPPY_DPRINTF("recalibrate\n");
173 drv->head = 0;
174 drv->track = 0;
175 drv->sect = 1;
176 }
177
178 /* Revalidate a disk drive after a disk change */
179 static void fd_revalidate(FDrive *drv)
180 {
181 int nb_heads, max_track, last_sect, ro;
182 FDriveType drive;
183 FDriveRate rate;
184
185 FLOPPY_DPRINTF("revalidate\n");
186 if (drv->bs != NULL) {
187 ro = bdrv_is_read_only(drv->bs);
188 bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,
189 &last_sect, drv->drive, &drive, &rate);
190 if (!bdrv_is_inserted(drv->bs)) {
191 FLOPPY_DPRINTF("No disk in drive\n");
192 } else if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
193 FLOPPY_DPRINTF("User defined disk (%d %d %d)\n",
194 nb_heads - 1, max_track, last_sect);
195 } else {
196 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
197 max_track, last_sect, ro ? "ro" : "rw");
198 }
199 if (nb_heads == 1) {
200 drv->flags &= ~FDISK_DBL_SIDES;
201 } else {
202 drv->flags |= FDISK_DBL_SIDES;
203 }
204 drv->max_track = max_track;
205 drv->last_sect = last_sect;
206 drv->ro = ro;
207 drv->drive = drive;
208 drv->media_rate = rate;
209 } else {
210 FLOPPY_DPRINTF("No drive connected\n");
211 drv->last_sect = 0;
212 drv->max_track = 0;
213 drv->flags &= ~FDISK_DBL_SIDES;
214 }
215 }
216
217 /********************************************************/
218 /* Intel 82078 floppy disk controller emulation */
219
220 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
221 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
222 static int fdctrl_transfer_handler (void *opaque, int nchan,
223 int dma_pos, int dma_len);
224 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
225 static FDrive *get_cur_drv(FDCtrl *fdctrl);
226
227 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
228 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
229 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
230 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
231 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
232 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
233 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
234 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
235 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
236 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
237 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
238 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
239
240 enum {
241 FD_DIR_WRITE = 0,
242 FD_DIR_READ = 1,
243 FD_DIR_SCANE = 2,
244 FD_DIR_SCANL = 3,
245 FD_DIR_SCANH = 4,
246 };
247
248 enum {
249 FD_STATE_MULTI = 0x01, /* multi track flag */
250 FD_STATE_FORMAT = 0x02, /* format flag */
251 FD_STATE_SEEK = 0x04, /* seek flag */
252 };
253
254 enum {
255 FD_REG_SRA = 0x00,
256 FD_REG_SRB = 0x01,
257 FD_REG_DOR = 0x02,
258 FD_REG_TDR = 0x03,
259 FD_REG_MSR = 0x04,
260 FD_REG_DSR = 0x04,
261 FD_REG_FIFO = 0x05,
262 FD_REG_DIR = 0x07,
263 FD_REG_CCR = 0x07,
264 };
265
266 enum {
267 FD_CMD_READ_TRACK = 0x02,
268 FD_CMD_SPECIFY = 0x03,
269 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
270 FD_CMD_WRITE = 0x05,
271 FD_CMD_READ = 0x06,
272 FD_CMD_RECALIBRATE = 0x07,
273 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
274 FD_CMD_WRITE_DELETED = 0x09,
275 FD_CMD_READ_ID = 0x0a,
276 FD_CMD_READ_DELETED = 0x0c,
277 FD_CMD_FORMAT_TRACK = 0x0d,
278 FD_CMD_DUMPREG = 0x0e,
279 FD_CMD_SEEK = 0x0f,
280 FD_CMD_VERSION = 0x10,
281 FD_CMD_SCAN_EQUAL = 0x11,
282 FD_CMD_PERPENDICULAR_MODE = 0x12,
283 FD_CMD_CONFIGURE = 0x13,
284 FD_CMD_LOCK = 0x14,
285 FD_CMD_VERIFY = 0x16,
286 FD_CMD_POWERDOWN_MODE = 0x17,
287 FD_CMD_PART_ID = 0x18,
288 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
289 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
290 FD_CMD_SAVE = 0x2e,
291 FD_CMD_OPTION = 0x33,
292 FD_CMD_RESTORE = 0x4e,
293 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
294 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
295 FD_CMD_FORMAT_AND_WRITE = 0xcd,
296 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
297 };
298
299 enum {
300 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
301 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
302 FD_CONFIG_POLL = 0x10, /* Poll enabled */
303 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
304 FD_CONFIG_EIS = 0x40, /* No implied seeks */
305 };
306
307 enum {
308 FD_SR0_EQPMT = 0x10,
309 FD_SR0_SEEK = 0x20,
310 FD_SR0_ABNTERM = 0x40,
311 FD_SR0_INVCMD = 0x80,
312 FD_SR0_RDYCHG = 0xc0,
313 };
314
315 enum {
316 FD_SR1_MA = 0x01, /* Missing address mark */
317 FD_SR1_NW = 0x02, /* Not writable */
318 FD_SR1_EC = 0x80, /* End of cylinder */
319 };
320
321 enum {
322 FD_SR2_SNS = 0x04, /* Scan not satisfied */
323 FD_SR2_SEH = 0x08, /* Scan equal hit */
324 };
325
326 enum {
327 FD_SRA_DIR = 0x01,
328 FD_SRA_nWP = 0x02,
329 FD_SRA_nINDX = 0x04,
330 FD_SRA_HDSEL = 0x08,
331 FD_SRA_nTRK0 = 0x10,
332 FD_SRA_STEP = 0x20,
333 FD_SRA_nDRV2 = 0x40,
334 FD_SRA_INTPEND = 0x80,
335 };
336
337 enum {
338 FD_SRB_MTR0 = 0x01,
339 FD_SRB_MTR1 = 0x02,
340 FD_SRB_WGATE = 0x04,
341 FD_SRB_RDATA = 0x08,
342 FD_SRB_WDATA = 0x10,
343 FD_SRB_DR0 = 0x20,
344 };
345
346 enum {
347 #if MAX_FD == 4
348 FD_DOR_SELMASK = 0x03,
349 #else
350 FD_DOR_SELMASK = 0x01,
351 #endif
352 FD_DOR_nRESET = 0x04,
353 FD_DOR_DMAEN = 0x08,
354 FD_DOR_MOTEN0 = 0x10,
355 FD_DOR_MOTEN1 = 0x20,
356 FD_DOR_MOTEN2 = 0x40,
357 FD_DOR_MOTEN3 = 0x80,
358 };
359
360 enum {
361 #if MAX_FD == 4
362 FD_TDR_BOOTSEL = 0x0c,
363 #else
364 FD_TDR_BOOTSEL = 0x04,
365 #endif
366 };
367
368 enum {
369 FD_DSR_DRATEMASK= 0x03,
370 FD_DSR_PWRDOWN = 0x40,
371 FD_DSR_SWRESET = 0x80,
372 };
373
374 enum {
375 FD_MSR_DRV0BUSY = 0x01,
376 FD_MSR_DRV1BUSY = 0x02,
377 FD_MSR_DRV2BUSY = 0x04,
378 FD_MSR_DRV3BUSY = 0x08,
379 FD_MSR_CMDBUSY = 0x10,
380 FD_MSR_NONDMA = 0x20,
381 FD_MSR_DIO = 0x40,
382 FD_MSR_RQM = 0x80,
383 };
384
385 enum {
386 FD_DIR_DSKCHG = 0x80,
387 };
388
389 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
390 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
391 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
392
393 struct FDCtrl {
394 MemoryRegion iomem;
395 qemu_irq irq;
396 /* Controller state */
397 QEMUTimer *result_timer;
398 int dma_chann;
399 /* Controller's identification */
400 uint8_t version;
401 /* HW */
402 uint8_t sra;
403 uint8_t srb;
404 uint8_t dor;
405 uint8_t dor_vmstate; /* only used as temp during vmstate */
406 uint8_t tdr;
407 uint8_t dsr;
408 uint8_t msr;
409 uint8_t cur_drv;
410 uint8_t status0;
411 uint8_t status1;
412 uint8_t status2;
413 /* Command FIFO */
414 uint8_t *fifo;
415 int32_t fifo_size;
416 uint32_t data_pos;
417 uint32_t data_len;
418 uint8_t data_state;
419 uint8_t data_dir;
420 uint8_t eot; /* last wanted sector */
421 /* States kept only to be returned back */
422 /* precompensation */
423 uint8_t precomp_trk;
424 uint8_t config;
425 uint8_t lock;
426 /* Power down config (also with status regB access mode */
427 uint8_t pwrd;
428 /* Floppy drives */
429 uint8_t num_floppies;
430 /* Sun4m quirks? */
431 int sun4m;
432 FDrive drives[MAX_FD];
433 int reset_sensei;
434 uint32_t check_media_rate;
435 /* Timers state */
436 uint8_t timer0;
437 uint8_t timer1;
438 };
439
440 typedef struct FDCtrlSysBus {
441 SysBusDevice busdev;
442 struct FDCtrl state;
443 } FDCtrlSysBus;
444
445 typedef struct FDCtrlISABus {
446 ISADevice busdev;
447 uint32_t iobase;
448 uint32_t irq;
449 uint32_t dma;
450 struct FDCtrl state;
451 int32_t bootindexA;
452 int32_t bootindexB;
453 } FDCtrlISABus;
454
455 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
456 {
457 FDCtrl *fdctrl = opaque;
458 uint32_t retval;
459
460 reg &= 7;
461 switch (reg) {
462 case FD_REG_SRA:
463 retval = fdctrl_read_statusA(fdctrl);
464 break;
465 case FD_REG_SRB:
466 retval = fdctrl_read_statusB(fdctrl);
467 break;
468 case FD_REG_DOR:
469 retval = fdctrl_read_dor(fdctrl);
470 break;
471 case FD_REG_TDR:
472 retval = fdctrl_read_tape(fdctrl);
473 break;
474 case FD_REG_MSR:
475 retval = fdctrl_read_main_status(fdctrl);
476 break;
477 case FD_REG_FIFO:
478 retval = fdctrl_read_data(fdctrl);
479 break;
480 case FD_REG_DIR:
481 retval = fdctrl_read_dir(fdctrl);
482 break;
483 default:
484 retval = (uint32_t)(-1);
485 break;
486 }
487 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
488
489 return retval;
490 }
491
492 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
493 {
494 FDCtrl *fdctrl = opaque;
495
496 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
497
498 reg &= 7;
499 switch (reg) {
500 case FD_REG_DOR:
501 fdctrl_write_dor(fdctrl, value);
502 break;
503 case FD_REG_TDR:
504 fdctrl_write_tape(fdctrl, value);
505 break;
506 case FD_REG_DSR:
507 fdctrl_write_rate(fdctrl, value);
508 break;
509 case FD_REG_FIFO:
510 fdctrl_write_data(fdctrl, value);
511 break;
512 case FD_REG_CCR:
513 fdctrl_write_ccr(fdctrl, value);
514 break;
515 default:
516 break;
517 }
518 }
519
520 static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
521 unsigned ize)
522 {
523 return fdctrl_read(opaque, (uint32_t)reg);
524 }
525
526 static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
527 uint64_t value, unsigned size)
528 {
529 fdctrl_write(opaque, (uint32_t)reg, value);
530 }
531
532 static const MemoryRegionOps fdctrl_mem_ops = {
533 .read = fdctrl_read_mem,
534 .write = fdctrl_write_mem,
535 .endianness = DEVICE_NATIVE_ENDIAN,
536 };
537
538 static const MemoryRegionOps fdctrl_mem_strict_ops = {
539 .read = fdctrl_read_mem,
540 .write = fdctrl_write_mem,
541 .endianness = DEVICE_NATIVE_ENDIAN,
542 .valid = {
543 .min_access_size = 1,
544 .max_access_size = 1,
545 },
546 };
547
548 static bool fdrive_media_changed_needed(void *opaque)
549 {
550 FDrive *drive = opaque;
551
552 return (drive->bs != NULL && drive->media_changed != 1);
553 }
554
555 static const VMStateDescription vmstate_fdrive_media_changed = {
556 .name = "fdrive/media_changed",
557 .version_id = 1,
558 .minimum_version_id = 1,
559 .minimum_version_id_old = 1,
560 .fields = (VMStateField[]) {
561 VMSTATE_UINT8(media_changed, FDrive),
562 VMSTATE_END_OF_LIST()
563 }
564 };
565
566 static bool fdrive_media_rate_needed(void *opaque)
567 {
568 FDrive *drive = opaque;
569
570 return drive->fdctrl->check_media_rate;
571 }
572
573 static const VMStateDescription vmstate_fdrive_media_rate = {
574 .name = "fdrive/media_rate",
575 .version_id = 1,
576 .minimum_version_id = 1,
577 .minimum_version_id_old = 1,
578 .fields = (VMStateField[]) {
579 VMSTATE_UINT8(media_rate, FDrive),
580 VMSTATE_END_OF_LIST()
581 }
582 };
583
584 static const VMStateDescription vmstate_fdrive = {
585 .name = "fdrive",
586 .version_id = 1,
587 .minimum_version_id = 1,
588 .minimum_version_id_old = 1,
589 .fields = (VMStateField[]) {
590 VMSTATE_UINT8(head, FDrive),
591 VMSTATE_UINT8(track, FDrive),
592 VMSTATE_UINT8(sect, FDrive),
593 VMSTATE_END_OF_LIST()
594 },
595 .subsections = (VMStateSubsection[]) {
596 {
597 .vmsd = &vmstate_fdrive_media_changed,
598 .needed = &fdrive_media_changed_needed,
599 } , {
600 .vmsd = &vmstate_fdrive_media_rate,
601 .needed = &fdrive_media_rate_needed,
602 } , {
603 /* empty */
604 }
605 }
606 };
607
608 static void fdc_pre_save(void *opaque)
609 {
610 FDCtrl *s = opaque;
611
612 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
613 }
614
615 static int fdc_post_load(void *opaque, int version_id)
616 {
617 FDCtrl *s = opaque;
618
619 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
620 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
621 return 0;
622 }
623
624 static const VMStateDescription vmstate_fdc = {
625 .name = "fdc",
626 .version_id = 2,
627 .minimum_version_id = 2,
628 .minimum_version_id_old = 2,
629 .pre_save = fdc_pre_save,
630 .post_load = fdc_post_load,
631 .fields = (VMStateField []) {
632 /* Controller State */
633 VMSTATE_UINT8(sra, FDCtrl),
634 VMSTATE_UINT8(srb, FDCtrl),
635 VMSTATE_UINT8(dor_vmstate, FDCtrl),
636 VMSTATE_UINT8(tdr, FDCtrl),
637 VMSTATE_UINT8(dsr, FDCtrl),
638 VMSTATE_UINT8(msr, FDCtrl),
639 VMSTATE_UINT8(status0, FDCtrl),
640 VMSTATE_UINT8(status1, FDCtrl),
641 VMSTATE_UINT8(status2, FDCtrl),
642 /* Command FIFO */
643 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
644 uint8_t),
645 VMSTATE_UINT32(data_pos, FDCtrl),
646 VMSTATE_UINT32(data_len, FDCtrl),
647 VMSTATE_UINT8(data_state, FDCtrl),
648 VMSTATE_UINT8(data_dir, FDCtrl),
649 VMSTATE_UINT8(eot, FDCtrl),
650 /* States kept only to be returned back */
651 VMSTATE_UINT8(timer0, FDCtrl),
652 VMSTATE_UINT8(timer1, FDCtrl),
653 VMSTATE_UINT8(precomp_trk, FDCtrl),
654 VMSTATE_UINT8(config, FDCtrl),
655 VMSTATE_UINT8(lock, FDCtrl),
656 VMSTATE_UINT8(pwrd, FDCtrl),
657 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
658 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
659 vmstate_fdrive, FDrive),
660 VMSTATE_END_OF_LIST()
661 }
662 };
663
664 static void fdctrl_external_reset_sysbus(DeviceState *d)
665 {
666 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
667 FDCtrl *s = &sys->state;
668
669 fdctrl_reset(s, 0);
670 }
671
672 static void fdctrl_external_reset_isa(DeviceState *d)
673 {
674 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
675 FDCtrl *s = &isa->state;
676
677 fdctrl_reset(s, 0);
678 }
679
680 static void fdctrl_handle_tc(void *opaque, int irq, int level)
681 {
682 //FDCtrl *s = opaque;
683
684 if (level) {
685 // XXX
686 FLOPPY_DPRINTF("TC pulsed\n");
687 }
688 }
689
690 /* Change IRQ state */
691 static void fdctrl_reset_irq(FDCtrl *fdctrl)
692 {
693 if (!(fdctrl->sra & FD_SRA_INTPEND))
694 return;
695 FLOPPY_DPRINTF("Reset interrupt\n");
696 qemu_set_irq(fdctrl->irq, 0);
697 fdctrl->sra &= ~FD_SRA_INTPEND;
698 }
699
700 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
701 {
702 /* Sparc mutation */
703 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
704 /* XXX: not sure */
705 fdctrl->msr &= ~FD_MSR_CMDBUSY;
706 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
707 fdctrl->status0 = status0;
708 return;
709 }
710 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
711 qemu_set_irq(fdctrl->irq, 1);
712 fdctrl->sra |= FD_SRA_INTPEND;
713 }
714 if (status0 & FD_SR0_SEEK) {
715 FDrive *cur_drv;
716 /* A seek clears the disk change line (if a disk is inserted) */
717 cur_drv = get_cur_drv(fdctrl);
718 if (cur_drv->bs != NULL && bdrv_is_inserted(cur_drv->bs)) {
719 cur_drv->media_changed = 0;
720 }
721 }
722
723 fdctrl->reset_sensei = 0;
724 fdctrl->status0 = status0;
725 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
726 }
727
728 /* Reset controller */
729 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
730 {
731 int i;
732
733 FLOPPY_DPRINTF("reset controller\n");
734 fdctrl_reset_irq(fdctrl);
735 /* Initialise controller */
736 fdctrl->sra = 0;
737 fdctrl->srb = 0xc0;
738 if (!fdctrl->drives[1].bs)
739 fdctrl->sra |= FD_SRA_nDRV2;
740 fdctrl->cur_drv = 0;
741 fdctrl->dor = FD_DOR_nRESET;
742 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
743 fdctrl->msr = FD_MSR_RQM;
744 /* FIFO state */
745 fdctrl->data_pos = 0;
746 fdctrl->data_len = 0;
747 fdctrl->data_state = 0;
748 fdctrl->data_dir = FD_DIR_WRITE;
749 for (i = 0; i < MAX_FD; i++)
750 fd_recalibrate(&fdctrl->drives[i]);
751 fdctrl_reset_fifo(fdctrl);
752 if (do_irq) {
753 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
754 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
755 }
756 }
757
758 static inline FDrive *drv0(FDCtrl *fdctrl)
759 {
760 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
761 }
762
763 static inline FDrive *drv1(FDCtrl *fdctrl)
764 {
765 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
766 return &fdctrl->drives[1];
767 else
768 return &fdctrl->drives[0];
769 }
770
771 #if MAX_FD == 4
772 static inline FDrive *drv2(FDCtrl *fdctrl)
773 {
774 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
775 return &fdctrl->drives[2];
776 else
777 return &fdctrl->drives[1];
778 }
779
780 static inline FDrive *drv3(FDCtrl *fdctrl)
781 {
782 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
783 return &fdctrl->drives[3];
784 else
785 return &fdctrl->drives[2];
786 }
787 #endif
788
789 static FDrive *get_cur_drv(FDCtrl *fdctrl)
790 {
791 switch (fdctrl->cur_drv) {
792 case 0: return drv0(fdctrl);
793 case 1: return drv1(fdctrl);
794 #if MAX_FD == 4
795 case 2: return drv2(fdctrl);
796 case 3: return drv3(fdctrl);
797 #endif
798 default: return NULL;
799 }
800 }
801
802 /* Status A register : 0x00 (read-only) */
803 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
804 {
805 uint32_t retval = fdctrl->sra;
806
807 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
808
809 return retval;
810 }
811
812 /* Status B register : 0x01 (read-only) */
813 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
814 {
815 uint32_t retval = fdctrl->srb;
816
817 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
818
819 return retval;
820 }
821
822 /* Digital output register : 0x02 */
823 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
824 {
825 uint32_t retval = fdctrl->dor;
826
827 /* Selected drive */
828 retval |= fdctrl->cur_drv;
829 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
830
831 return retval;
832 }
833
834 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
835 {
836 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
837
838 /* Motors */
839 if (value & FD_DOR_MOTEN0)
840 fdctrl->srb |= FD_SRB_MTR0;
841 else
842 fdctrl->srb &= ~FD_SRB_MTR0;
843 if (value & FD_DOR_MOTEN1)
844 fdctrl->srb |= FD_SRB_MTR1;
845 else
846 fdctrl->srb &= ~FD_SRB_MTR1;
847
848 /* Drive */
849 if (value & 1)
850 fdctrl->srb |= FD_SRB_DR0;
851 else
852 fdctrl->srb &= ~FD_SRB_DR0;
853
854 /* Reset */
855 if (!(value & FD_DOR_nRESET)) {
856 if (fdctrl->dor & FD_DOR_nRESET) {
857 FLOPPY_DPRINTF("controller enter RESET state\n");
858 }
859 } else {
860 if (!(fdctrl->dor & FD_DOR_nRESET)) {
861 FLOPPY_DPRINTF("controller out of RESET state\n");
862 fdctrl_reset(fdctrl, 1);
863 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
864 }
865 }
866 /* Selected drive */
867 fdctrl->cur_drv = value & FD_DOR_SELMASK;
868
869 fdctrl->dor = value;
870 }
871
872 /* Tape drive register : 0x03 */
873 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
874 {
875 uint32_t retval = fdctrl->tdr;
876
877 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
878
879 return retval;
880 }
881
882 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
883 {
884 /* Reset mode */
885 if (!(fdctrl->dor & FD_DOR_nRESET)) {
886 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
887 return;
888 }
889 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
890 /* Disk boot selection indicator */
891 fdctrl->tdr = value & FD_TDR_BOOTSEL;
892 /* Tape indicators: never allow */
893 }
894
895 /* Main status register : 0x04 (read) */
896 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
897 {
898 uint32_t retval = fdctrl->msr;
899
900 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
901 fdctrl->dor |= FD_DOR_nRESET;
902
903 /* Sparc mutation */
904 if (fdctrl->sun4m) {
905 retval |= FD_MSR_DIO;
906 fdctrl_reset_irq(fdctrl);
907 };
908
909 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
910
911 return retval;
912 }
913
914 /* Data select rate register : 0x04 (write) */
915 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
916 {
917 /* Reset mode */
918 if (!(fdctrl->dor & FD_DOR_nRESET)) {
919 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
920 return;
921 }
922 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
923 /* Reset: autoclear */
924 if (value & FD_DSR_SWRESET) {
925 fdctrl->dor &= ~FD_DOR_nRESET;
926 fdctrl_reset(fdctrl, 1);
927 fdctrl->dor |= FD_DOR_nRESET;
928 }
929 if (value & FD_DSR_PWRDOWN) {
930 fdctrl_reset(fdctrl, 1);
931 }
932 fdctrl->dsr = value;
933 }
934
935 /* Configuration control register: 0x07 (write) */
936 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
937 {
938 /* Reset mode */
939 if (!(fdctrl->dor & FD_DOR_nRESET)) {
940 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
941 return;
942 }
943 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
944
945 /* Only the rate selection bits used in AT mode, and we
946 * store those in the DSR.
947 */
948 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
949 (value & FD_DSR_DRATEMASK);
950 }
951
952 static int fdctrl_media_changed(FDrive *drv)
953 {
954 return drv->media_changed;
955 }
956
957 /* Digital input register : 0x07 (read-only) */
958 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
959 {
960 uint32_t retval = 0;
961
962 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
963 retval |= FD_DIR_DSKCHG;
964 }
965 if (retval != 0) {
966 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
967 }
968
969 return retval;
970 }
971
972 /* FIFO state control */
973 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
974 {
975 fdctrl->data_dir = FD_DIR_WRITE;
976 fdctrl->data_pos = 0;
977 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
978 }
979
980 /* Set FIFO status for the host to read */
981 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
982 {
983 fdctrl->data_dir = FD_DIR_READ;
984 fdctrl->data_len = fifo_len;
985 fdctrl->data_pos = 0;
986 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
987 if (do_irq)
988 fdctrl_raise_irq(fdctrl, 0x00);
989 }
990
991 /* Set an error: unimplemented/unknown command */
992 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
993 {
994 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
995 fdctrl->fifo[0]);
996 fdctrl->fifo[0] = FD_SR0_INVCMD;
997 fdctrl_set_fifo(fdctrl, 1, 0);
998 }
999
1000 /* Seek to next sector */
1001 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1002 {
1003 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1004 cur_drv->head, cur_drv->track, cur_drv->sect,
1005 fd_sector(cur_drv));
1006 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1007 error in fact */
1008 if (cur_drv->sect >= cur_drv->last_sect ||
1009 cur_drv->sect == fdctrl->eot) {
1010 cur_drv->sect = 1;
1011 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1012 if (cur_drv->head == 0 &&
1013 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1014 cur_drv->head = 1;
1015 } else {
1016 cur_drv->head = 0;
1017 cur_drv->track++;
1018 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1019 return 0;
1020 }
1021 } else {
1022 cur_drv->track++;
1023 return 0;
1024 }
1025 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1026 cur_drv->head, cur_drv->track,
1027 cur_drv->sect, fd_sector(cur_drv));
1028 } else {
1029 cur_drv->sect++;
1030 }
1031 return 1;
1032 }
1033
1034 /* Callback for transfer end (stop or abort) */
1035 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1036 uint8_t status1, uint8_t status2)
1037 {
1038 FDrive *cur_drv;
1039
1040 cur_drv = get_cur_drv(fdctrl);
1041 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1042 status0, status1, status2,
1043 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1044 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1045 fdctrl->fifo[1] = status1;
1046 fdctrl->fifo[2] = status2;
1047 fdctrl->fifo[3] = cur_drv->track;
1048 fdctrl->fifo[4] = cur_drv->head;
1049 fdctrl->fifo[5] = cur_drv->sect;
1050 fdctrl->fifo[6] = FD_SECTOR_SC;
1051 fdctrl->data_dir = FD_DIR_READ;
1052 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1053 DMA_release_DREQ(fdctrl->dma_chann);
1054 }
1055 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1056 fdctrl->msr &= ~FD_MSR_NONDMA;
1057 fdctrl_set_fifo(fdctrl, 7, 1);
1058 }
1059
1060 /* Prepare a data transfer (either DMA or FIFO) */
1061 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1062 {
1063 FDrive *cur_drv;
1064 uint8_t kh, kt, ks;
1065 int did_seek = 0;
1066
1067 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1068 cur_drv = get_cur_drv(fdctrl);
1069 kt = fdctrl->fifo[2];
1070 kh = fdctrl->fifo[3];
1071 ks = fdctrl->fifo[4];
1072 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1073 GET_CUR_DRV(fdctrl), kh, kt, ks,
1074 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1075 NUM_SIDES(cur_drv)));
1076 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1077 case 2:
1078 /* sect too big */
1079 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1080 fdctrl->fifo[3] = kt;
1081 fdctrl->fifo[4] = kh;
1082 fdctrl->fifo[5] = ks;
1083 return;
1084 case 3:
1085 /* track too big */
1086 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1087 fdctrl->fifo[3] = kt;
1088 fdctrl->fifo[4] = kh;
1089 fdctrl->fifo[5] = ks;
1090 return;
1091 case 4:
1092 /* No seek enabled */
1093 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1094 fdctrl->fifo[3] = kt;
1095 fdctrl->fifo[4] = kh;
1096 fdctrl->fifo[5] = ks;
1097 return;
1098 case 1:
1099 did_seek = 1;
1100 break;
1101 default:
1102 break;
1103 }
1104
1105 /* Check the data rate. If the programmed data rate does not match
1106 * the currently inserted medium, the operation has to fail. */
1107 if (fdctrl->check_media_rate &&
1108 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1109 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1110 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1111 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1112 fdctrl->fifo[3] = kt;
1113 fdctrl->fifo[4] = kh;
1114 fdctrl->fifo[5] = ks;
1115 return;
1116 }
1117
1118 /* Set the FIFO state */
1119 fdctrl->data_dir = direction;
1120 fdctrl->data_pos = 0;
1121 fdctrl->msr |= FD_MSR_CMDBUSY;
1122 if (fdctrl->fifo[0] & 0x80)
1123 fdctrl->data_state |= FD_STATE_MULTI;
1124 else
1125 fdctrl->data_state &= ~FD_STATE_MULTI;
1126 if (did_seek)
1127 fdctrl->data_state |= FD_STATE_SEEK;
1128 else
1129 fdctrl->data_state &= ~FD_STATE_SEEK;
1130 if (fdctrl->fifo[5] == 00) {
1131 fdctrl->data_len = fdctrl->fifo[8];
1132 } else {
1133 int tmp;
1134 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1135 tmp = (fdctrl->fifo[6] - ks + 1);
1136 if (fdctrl->fifo[0] & 0x80)
1137 tmp += fdctrl->fifo[6];
1138 fdctrl->data_len *= tmp;
1139 }
1140 fdctrl->eot = fdctrl->fifo[6];
1141 if (fdctrl->dor & FD_DOR_DMAEN) {
1142 int dma_mode;
1143 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1144 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1145 dma_mode = (dma_mode >> 2) & 3;
1146 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1147 dma_mode, direction,
1148 (128 << fdctrl->fifo[5]) *
1149 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1150 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1151 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1152 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1153 (direction == FD_DIR_READ && dma_mode == 1)) {
1154 /* No access is allowed until DMA transfer has completed */
1155 fdctrl->msr &= ~FD_MSR_RQM;
1156 /* Now, we just have to wait for the DMA controller to
1157 * recall us...
1158 */
1159 DMA_hold_DREQ(fdctrl->dma_chann);
1160 DMA_schedule(fdctrl->dma_chann);
1161 return;
1162 } else {
1163 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1164 direction);
1165 }
1166 }
1167 FLOPPY_DPRINTF("start non-DMA transfer\n");
1168 fdctrl->msr |= FD_MSR_NONDMA;
1169 if (direction != FD_DIR_WRITE)
1170 fdctrl->msr |= FD_MSR_DIO;
1171 /* IO based transfer: calculate len */
1172 fdctrl_raise_irq(fdctrl, 0x00);
1173
1174 return;
1175 }
1176
1177 /* Prepare a transfer of deleted data */
1178 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1179 {
1180 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1181
1182 /* We don't handle deleted data,
1183 * so we don't return *ANYTHING*
1184 */
1185 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1186 }
1187
1188 /* handlers for DMA transfers */
1189 static int fdctrl_transfer_handler (void *opaque, int nchan,
1190 int dma_pos, int dma_len)
1191 {
1192 FDCtrl *fdctrl;
1193 FDrive *cur_drv;
1194 int len, start_pos, rel_pos;
1195 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1196
1197 fdctrl = opaque;
1198 if (fdctrl->msr & FD_MSR_RQM) {
1199 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1200 return 0;
1201 }
1202 cur_drv = get_cur_drv(fdctrl);
1203 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1204 fdctrl->data_dir == FD_DIR_SCANH)
1205 status2 = FD_SR2_SNS;
1206 if (dma_len > fdctrl->data_len)
1207 dma_len = fdctrl->data_len;
1208 if (cur_drv->bs == NULL) {
1209 if (fdctrl->data_dir == FD_DIR_WRITE)
1210 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1211 else
1212 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1213 len = 0;
1214 goto transfer_error;
1215 }
1216 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1217 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1218 len = dma_len - fdctrl->data_pos;
1219 if (len + rel_pos > FD_SECTOR_LEN)
1220 len = FD_SECTOR_LEN - rel_pos;
1221 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1222 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1223 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1224 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1225 fd_sector(cur_drv) * FD_SECTOR_LEN);
1226 if (fdctrl->data_dir != FD_DIR_WRITE ||
1227 len < FD_SECTOR_LEN || rel_pos != 0) {
1228 /* READ & SCAN commands and realign to a sector for WRITE */
1229 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1230 fdctrl->fifo, 1) < 0) {
1231 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1232 fd_sector(cur_drv));
1233 /* Sure, image size is too small... */
1234 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1235 }
1236 }
1237 switch (fdctrl->data_dir) {
1238 case FD_DIR_READ:
1239 /* READ commands */
1240 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1241 fdctrl->data_pos, len);
1242 break;
1243 case FD_DIR_WRITE:
1244 /* WRITE commands */
1245 if (cur_drv->ro) {
1246 /* Handle readonly medium early, no need to do DMA, touch the
1247 * LED or attempt any writes. A real floppy doesn't attempt
1248 * to write to readonly media either. */
1249 fdctrl_stop_transfer(fdctrl,
1250 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1251 0x00);
1252 goto transfer_error;
1253 }
1254
1255 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1256 fdctrl->data_pos, len);
1257 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1258 fdctrl->fifo, 1) < 0) {
1259 FLOPPY_DPRINTF("error writing sector %d\n",
1260 fd_sector(cur_drv));
1261 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1262 goto transfer_error;
1263 }
1264 break;
1265 default:
1266 /* SCAN commands */
1267 {
1268 uint8_t tmpbuf[FD_SECTOR_LEN];
1269 int ret;
1270 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1271 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1272 if (ret == 0) {
1273 status2 = FD_SR2_SEH;
1274 goto end_transfer;
1275 }
1276 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1277 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1278 status2 = 0x00;
1279 goto end_transfer;
1280 }
1281 }
1282 break;
1283 }
1284 fdctrl->data_pos += len;
1285 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1286 if (rel_pos == 0) {
1287 /* Seek to next sector */
1288 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1289 break;
1290 }
1291 }
1292 end_transfer:
1293 len = fdctrl->data_pos - start_pos;
1294 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1295 fdctrl->data_pos, len, fdctrl->data_len);
1296 if (fdctrl->data_dir == FD_DIR_SCANE ||
1297 fdctrl->data_dir == FD_DIR_SCANL ||
1298 fdctrl->data_dir == FD_DIR_SCANH)
1299 status2 = FD_SR2_SEH;
1300 if (FD_DID_SEEK(fdctrl->data_state))
1301 status0 |= FD_SR0_SEEK;
1302 fdctrl->data_len -= len;
1303 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1304 transfer_error:
1305
1306 return len;
1307 }
1308
1309 /* Data register : 0x05 */
1310 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1311 {
1312 FDrive *cur_drv;
1313 uint32_t retval = 0;
1314 int pos;
1315
1316 cur_drv = get_cur_drv(fdctrl);
1317 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1318 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1319 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1320 return 0;
1321 }
1322 pos = fdctrl->data_pos;
1323 if (fdctrl->msr & FD_MSR_NONDMA) {
1324 pos %= FD_SECTOR_LEN;
1325 if (pos == 0) {
1326 if (fdctrl->data_pos != 0)
1327 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1328 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1329 fd_sector(cur_drv));
1330 return 0;
1331 }
1332 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1333 FLOPPY_DPRINTF("error getting sector %d\n",
1334 fd_sector(cur_drv));
1335 /* Sure, image size is too small... */
1336 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1337 }
1338 }
1339 }
1340 retval = fdctrl->fifo[pos];
1341 if (++fdctrl->data_pos == fdctrl->data_len) {
1342 fdctrl->data_pos = 0;
1343 /* Switch from transfer mode to status mode
1344 * then from status mode to command mode
1345 */
1346 if (fdctrl->msr & FD_MSR_NONDMA) {
1347 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1348 } else {
1349 fdctrl_reset_fifo(fdctrl);
1350 fdctrl_reset_irq(fdctrl);
1351 }
1352 }
1353 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1354
1355 return retval;
1356 }
1357
1358 static void fdctrl_format_sector(FDCtrl *fdctrl)
1359 {
1360 FDrive *cur_drv;
1361 uint8_t kh, kt, ks;
1362
1363 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1364 cur_drv = get_cur_drv(fdctrl);
1365 kt = fdctrl->fifo[6];
1366 kh = fdctrl->fifo[7];
1367 ks = fdctrl->fifo[8];
1368 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1369 GET_CUR_DRV(fdctrl), kh, kt, ks,
1370 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1371 NUM_SIDES(cur_drv)));
1372 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1373 case 2:
1374 /* sect too big */
1375 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1376 fdctrl->fifo[3] = kt;
1377 fdctrl->fifo[4] = kh;
1378 fdctrl->fifo[5] = ks;
1379 return;
1380 case 3:
1381 /* track too big */
1382 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1383 fdctrl->fifo[3] = kt;
1384 fdctrl->fifo[4] = kh;
1385 fdctrl->fifo[5] = ks;
1386 return;
1387 case 4:
1388 /* No seek enabled */
1389 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1390 fdctrl->fifo[3] = kt;
1391 fdctrl->fifo[4] = kh;
1392 fdctrl->fifo[5] = ks;
1393 return;
1394 case 1:
1395 fdctrl->data_state |= FD_STATE_SEEK;
1396 break;
1397 default:
1398 break;
1399 }
1400 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1401 if (cur_drv->bs == NULL ||
1402 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1403 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
1404 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1405 } else {
1406 if (cur_drv->sect == cur_drv->last_sect) {
1407 fdctrl->data_state &= ~FD_STATE_FORMAT;
1408 /* Last sector done */
1409 if (FD_DID_SEEK(fdctrl->data_state))
1410 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1411 else
1412 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1413 } else {
1414 /* More to do */
1415 fdctrl->data_pos = 0;
1416 fdctrl->data_len = 4;
1417 }
1418 }
1419 }
1420
1421 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1422 {
1423 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1424 fdctrl->fifo[0] = fdctrl->lock << 4;
1425 fdctrl_set_fifo(fdctrl, 1, 0);
1426 }
1427
1428 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1429 {
1430 FDrive *cur_drv = get_cur_drv(fdctrl);
1431
1432 /* Drives position */
1433 fdctrl->fifo[0] = drv0(fdctrl)->track;
1434 fdctrl->fifo[1] = drv1(fdctrl)->track;
1435 #if MAX_FD == 4
1436 fdctrl->fifo[2] = drv2(fdctrl)->track;
1437 fdctrl->fifo[3] = drv3(fdctrl)->track;
1438 #else
1439 fdctrl->fifo[2] = 0;
1440 fdctrl->fifo[3] = 0;
1441 #endif
1442 /* timers */
1443 fdctrl->fifo[4] = fdctrl->timer0;
1444 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1445 fdctrl->fifo[6] = cur_drv->last_sect;
1446 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1447 (cur_drv->perpendicular << 2);
1448 fdctrl->fifo[8] = fdctrl->config;
1449 fdctrl->fifo[9] = fdctrl->precomp_trk;
1450 fdctrl_set_fifo(fdctrl, 10, 0);
1451 }
1452
1453 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1454 {
1455 /* Controller's version */
1456 fdctrl->fifo[0] = fdctrl->version;
1457 fdctrl_set_fifo(fdctrl, 1, 0);
1458 }
1459
1460 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1461 {
1462 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1463 fdctrl_set_fifo(fdctrl, 1, 0);
1464 }
1465
1466 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1467 {
1468 FDrive *cur_drv = get_cur_drv(fdctrl);
1469
1470 /* Drives position */
1471 drv0(fdctrl)->track = fdctrl->fifo[3];
1472 drv1(fdctrl)->track = fdctrl->fifo[4];
1473 #if MAX_FD == 4
1474 drv2(fdctrl)->track = fdctrl->fifo[5];
1475 drv3(fdctrl)->track = fdctrl->fifo[6];
1476 #endif
1477 /* timers */
1478 fdctrl->timer0 = fdctrl->fifo[7];
1479 fdctrl->timer1 = fdctrl->fifo[8];
1480 cur_drv->last_sect = fdctrl->fifo[9];
1481 fdctrl->lock = fdctrl->fifo[10] >> 7;
1482 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1483 fdctrl->config = fdctrl->fifo[11];
1484 fdctrl->precomp_trk = fdctrl->fifo[12];
1485 fdctrl->pwrd = fdctrl->fifo[13];
1486 fdctrl_reset_fifo(fdctrl);
1487 }
1488
1489 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1490 {
1491 FDrive *cur_drv = get_cur_drv(fdctrl);
1492
1493 fdctrl->fifo[0] = 0;
1494 fdctrl->fifo[1] = 0;
1495 /* Drives position */
1496 fdctrl->fifo[2] = drv0(fdctrl)->track;
1497 fdctrl->fifo[3] = drv1(fdctrl)->track;
1498 #if MAX_FD == 4
1499 fdctrl->fifo[4] = drv2(fdctrl)->track;
1500 fdctrl->fifo[5] = drv3(fdctrl)->track;
1501 #else
1502 fdctrl->fifo[4] = 0;
1503 fdctrl->fifo[5] = 0;
1504 #endif
1505 /* timers */
1506 fdctrl->fifo[6] = fdctrl->timer0;
1507 fdctrl->fifo[7] = fdctrl->timer1;
1508 fdctrl->fifo[8] = cur_drv->last_sect;
1509 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1510 (cur_drv->perpendicular << 2);
1511 fdctrl->fifo[10] = fdctrl->config;
1512 fdctrl->fifo[11] = fdctrl->precomp_trk;
1513 fdctrl->fifo[12] = fdctrl->pwrd;
1514 fdctrl->fifo[13] = 0;
1515 fdctrl->fifo[14] = 0;
1516 fdctrl_set_fifo(fdctrl, 15, 0);
1517 }
1518
1519 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1520 {
1521 FDrive *cur_drv = get_cur_drv(fdctrl);
1522
1523 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1524 qemu_mod_timer(fdctrl->result_timer,
1525 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1526 }
1527
1528 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1529 {
1530 FDrive *cur_drv;
1531
1532 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1533 cur_drv = get_cur_drv(fdctrl);
1534 fdctrl->data_state |= FD_STATE_FORMAT;
1535 if (fdctrl->fifo[0] & 0x80)
1536 fdctrl->data_state |= FD_STATE_MULTI;
1537 else
1538 fdctrl->data_state &= ~FD_STATE_MULTI;
1539 fdctrl->data_state &= ~FD_STATE_SEEK;
1540 cur_drv->bps =
1541 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1542 #if 0
1543 cur_drv->last_sect =
1544 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1545 fdctrl->fifo[3] / 2;
1546 #else
1547 cur_drv->last_sect = fdctrl->fifo[3];
1548 #endif
1549 /* TODO: implement format using DMA expected by the Bochs BIOS
1550 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1551 * the sector with the specified fill byte
1552 */
1553 fdctrl->data_state &= ~FD_STATE_FORMAT;
1554 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1555 }
1556
1557 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1558 {
1559 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1560 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1561 if (fdctrl->fifo[2] & 1)
1562 fdctrl->dor &= ~FD_DOR_DMAEN;
1563 else
1564 fdctrl->dor |= FD_DOR_DMAEN;
1565 /* No result back */
1566 fdctrl_reset_fifo(fdctrl);
1567 }
1568
1569 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1570 {
1571 FDrive *cur_drv;
1572
1573 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1574 cur_drv = get_cur_drv(fdctrl);
1575 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1576 /* 1 Byte status back */
1577 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1578 (cur_drv->track == 0 ? 0x10 : 0x00) |
1579 (cur_drv->head << 2) |
1580 GET_CUR_DRV(fdctrl) |
1581 0x28;
1582 fdctrl_set_fifo(fdctrl, 1, 0);
1583 }
1584
1585 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1586 {
1587 FDrive *cur_drv;
1588
1589 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1590 cur_drv = get_cur_drv(fdctrl);
1591 fd_recalibrate(cur_drv);
1592 fdctrl_reset_fifo(fdctrl);
1593 /* Raise Interrupt */
1594 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1595 }
1596
1597 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1598 {
1599 FDrive *cur_drv = get_cur_drv(fdctrl);
1600
1601 if(fdctrl->reset_sensei > 0) {
1602 fdctrl->fifo[0] =
1603 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1604 fdctrl->reset_sensei--;
1605 } else {
1606 /* XXX: status0 handling is broken for read/write
1607 commands, so we do this hack. It should be suppressed
1608 ASAP */
1609 fdctrl->fifo[0] =
1610 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1611 }
1612
1613 fdctrl->fifo[1] = cur_drv->track;
1614 fdctrl_set_fifo(fdctrl, 2, 0);
1615 fdctrl_reset_irq(fdctrl);
1616 fdctrl->status0 = FD_SR0_RDYCHG;
1617 }
1618
1619 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1620 {
1621 FDrive *cur_drv;
1622
1623 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1624 cur_drv = get_cur_drv(fdctrl);
1625 fdctrl_reset_fifo(fdctrl);
1626 /* The seek command just sends step pulses to the drive and doesn't care if
1627 * there is a medium inserted of if it's banging the head against the drive.
1628 */
1629 if (fdctrl->fifo[2] > cur_drv->max_track) {
1630 cur_drv->track = cur_drv->max_track;
1631 } else {
1632 cur_drv->track = fdctrl->fifo[2];
1633 }
1634 /* Raise Interrupt */
1635 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1636 }
1637
1638 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1639 {
1640 FDrive *cur_drv = get_cur_drv(fdctrl);
1641
1642 if (fdctrl->fifo[1] & 0x80)
1643 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1644 /* No result back */
1645 fdctrl_reset_fifo(fdctrl);
1646 }
1647
1648 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1649 {
1650 fdctrl->config = fdctrl->fifo[2];
1651 fdctrl->precomp_trk = fdctrl->fifo[3];
1652 /* No result back */
1653 fdctrl_reset_fifo(fdctrl);
1654 }
1655
1656 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1657 {
1658 fdctrl->pwrd = fdctrl->fifo[1];
1659 fdctrl->fifo[0] = fdctrl->fifo[1];
1660 fdctrl_set_fifo(fdctrl, 1, 0);
1661 }
1662
1663 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1664 {
1665 /* No result back */
1666 fdctrl_reset_fifo(fdctrl);
1667 }
1668
1669 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1670 {
1671 FDrive *cur_drv = get_cur_drv(fdctrl);
1672
1673 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1674 /* Command parameters done */
1675 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1676 fdctrl->fifo[0] = fdctrl->fifo[1];
1677 fdctrl->fifo[2] = 0;
1678 fdctrl->fifo[3] = 0;
1679 fdctrl_set_fifo(fdctrl, 4, 0);
1680 } else {
1681 fdctrl_reset_fifo(fdctrl);
1682 }
1683 } else if (fdctrl->data_len > 7) {
1684 /* ERROR */
1685 fdctrl->fifo[0] = 0x80 |
1686 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1687 fdctrl_set_fifo(fdctrl, 1, 0);
1688 }
1689 }
1690
1691 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1692 {
1693 FDrive *cur_drv;
1694
1695 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1696 cur_drv = get_cur_drv(fdctrl);
1697 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1698 cur_drv->track = cur_drv->max_track - 1;
1699 } else {
1700 cur_drv->track += fdctrl->fifo[2];
1701 }
1702 fdctrl_reset_fifo(fdctrl);
1703 /* Raise Interrupt */
1704 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1705 }
1706
1707 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1708 {
1709 FDrive *cur_drv;
1710
1711 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1712 cur_drv = get_cur_drv(fdctrl);
1713 if (fdctrl->fifo[2] > cur_drv->track) {
1714 cur_drv->track = 0;
1715 } else {
1716 cur_drv->track -= fdctrl->fifo[2];
1717 }
1718 fdctrl_reset_fifo(fdctrl);
1719 /* Raise Interrupt */
1720 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1721 }
1722
1723 static const struct {
1724 uint8_t value;
1725 uint8_t mask;
1726 const char* name;
1727 int parameters;
1728 void (*handler)(FDCtrl *fdctrl, int direction);
1729 int direction;
1730 } handlers[] = {
1731 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1732 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1733 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1734 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1735 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1736 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1737 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1738 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1739 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1740 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1741 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1742 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1743 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1744 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1745 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1746 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1747 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1748 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1749 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1750 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1751 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1752 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1753 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1754 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1755 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1756 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1757 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1758 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1759 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1760 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1761 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1762 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1763 };
1764 /* Associate command to an index in the 'handlers' array */
1765 static uint8_t command_to_handler[256];
1766
1767 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1768 {
1769 FDrive *cur_drv;
1770 int pos;
1771
1772 /* Reset mode */
1773 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1774 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1775 return;
1776 }
1777 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1778 FLOPPY_DPRINTF("error: controller not ready for writing\n");
1779 return;
1780 }
1781 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1782 /* Is it write command time ? */
1783 if (fdctrl->msr & FD_MSR_NONDMA) {
1784 /* FIFO data write */
1785 pos = fdctrl->data_pos++;
1786 pos %= FD_SECTOR_LEN;
1787 fdctrl->fifo[pos] = value;
1788 if (pos == FD_SECTOR_LEN - 1 ||
1789 fdctrl->data_pos == fdctrl->data_len) {
1790 cur_drv = get_cur_drv(fdctrl);
1791 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1792 FLOPPY_DPRINTF("error writing sector %d\n",
1793 fd_sector(cur_drv));
1794 return;
1795 }
1796 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1797 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1798 fd_sector(cur_drv));
1799 return;
1800 }
1801 }
1802 /* Switch from transfer mode to status mode
1803 * then from status mode to command mode
1804 */
1805 if (fdctrl->data_pos == fdctrl->data_len)
1806 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1807 return;
1808 }
1809 if (fdctrl->data_pos == 0) {
1810 /* Command */
1811 pos = command_to_handler[value & 0xff];
1812 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1813 fdctrl->data_len = handlers[pos].parameters + 1;
1814 fdctrl->msr |= FD_MSR_CMDBUSY;
1815 }
1816
1817 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1818 fdctrl->fifo[fdctrl->data_pos++] = value;
1819 if (fdctrl->data_pos == fdctrl->data_len) {
1820 /* We now have all parameters
1821 * and will be able to treat the command
1822 */
1823 if (fdctrl->data_state & FD_STATE_FORMAT) {
1824 fdctrl_format_sector(fdctrl);
1825 return;
1826 }
1827
1828 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1829 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1830 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1831 }
1832 }
1833
1834 static void fdctrl_result_timer(void *opaque)
1835 {
1836 FDCtrl *fdctrl = opaque;
1837 FDrive *cur_drv = get_cur_drv(fdctrl);
1838
1839 /* Pretend we are spinning.
1840 * This is needed for Coherent, which uses READ ID to check for
1841 * sector interleaving.
1842 */
1843 if (cur_drv->last_sect != 0) {
1844 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1845 }
1846 /* READ_ID can't automatically succeed! */
1847 if (fdctrl->check_media_rate &&
1848 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1849 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
1850 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1851 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1852 } else {
1853 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1854 }
1855 }
1856
1857 static void fdctrl_change_cb(void *opaque, bool load)
1858 {
1859 FDrive *drive = opaque;
1860
1861 drive->media_changed = 1;
1862 fd_revalidate(drive);
1863 }
1864
1865 static const BlockDevOps fdctrl_block_ops = {
1866 .change_media_cb = fdctrl_change_cb,
1867 };
1868
1869 /* Init functions */
1870 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1871 {
1872 unsigned int i;
1873 FDrive *drive;
1874
1875 for (i = 0; i < MAX_FD; i++) {
1876 drive = &fdctrl->drives[i];
1877 drive->fdctrl = fdctrl;
1878
1879 if (drive->bs) {
1880 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1881 error_report("fdc doesn't support drive option werror");
1882 return -1;
1883 }
1884 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1885 error_report("fdc doesn't support drive option rerror");
1886 return -1;
1887 }
1888 }
1889
1890 fd_init(drive);
1891 fdctrl_change_cb(drive, 0);
1892 if (drive->bs) {
1893 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
1894 }
1895 }
1896 return 0;
1897 }
1898
1899 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
1900 {
1901 ISADevice *dev;
1902
1903 dev = isa_try_create(bus, "isa-fdc");
1904 if (!dev) {
1905 return NULL;
1906 }
1907
1908 if (fds[0]) {
1909 qdev_prop_set_drive_nofail(&dev->qdev, "driveA", fds[0]->bdrv);
1910 }
1911 if (fds[1]) {
1912 qdev_prop_set_drive_nofail(&dev->qdev, "driveB", fds[1]->bdrv);
1913 }
1914 qdev_init_nofail(&dev->qdev);
1915
1916 return dev;
1917 }
1918
1919 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1920 target_phys_addr_t mmio_base, DriveInfo **fds)
1921 {
1922 FDCtrl *fdctrl;
1923 DeviceState *dev;
1924 FDCtrlSysBus *sys;
1925
1926 dev = qdev_create(NULL, "sysbus-fdc");
1927 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1928 fdctrl = &sys->state;
1929 fdctrl->dma_chann = dma_chann; /* FIXME */
1930 if (fds[0]) {
1931 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1932 }
1933 if (fds[1]) {
1934 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1935 }
1936 qdev_init_nofail(dev);
1937 sysbus_connect_irq(&sys->busdev, 0, irq);
1938 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1939 }
1940
1941 void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1942 DriveInfo **fds, qemu_irq *fdc_tc)
1943 {
1944 DeviceState *dev;
1945 FDCtrlSysBus *sys;
1946
1947 dev = qdev_create(NULL, "SUNW,fdtwo");
1948 if (fds[0]) {
1949 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1950 }
1951 qdev_init_nofail(dev);
1952 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1953 sysbus_connect_irq(&sys->busdev, 0, irq);
1954 sysbus_mmio_map(&sys->busdev, 0, io_base);
1955 *fdc_tc = qdev_get_gpio_in(dev, 0);
1956 }
1957
1958 static int fdctrl_init_common(FDCtrl *fdctrl)
1959 {
1960 int i, j;
1961 static int command_tables_inited = 0;
1962
1963 /* Fill 'command_to_handler' lookup table */
1964 if (!command_tables_inited) {
1965 command_tables_inited = 1;
1966 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1967 for (j = 0; j < sizeof(command_to_handler); j++) {
1968 if ((j & handlers[i].mask) == handlers[i].value) {
1969 command_to_handler[j] = i;
1970 }
1971 }
1972 }
1973 }
1974
1975 FLOPPY_DPRINTF("init controller\n");
1976 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1977 fdctrl->fifo_size = 512;
1978 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
1979 fdctrl_result_timer, fdctrl);
1980
1981 fdctrl->version = 0x90; /* Intel 82078 controller */
1982 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1983 fdctrl->num_floppies = MAX_FD;
1984
1985 if (fdctrl->dma_chann != -1)
1986 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1987 return fdctrl_connect_drives(fdctrl);
1988 }
1989
1990 static const MemoryRegionPortio fdc_portio_list[] = {
1991 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
1992 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
1993 PORTIO_END_OF_LIST(),
1994 };
1995
1996 static int isabus_fdc_init1(ISADevice *dev)
1997 {
1998 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1999 FDCtrl *fdctrl = &isa->state;
2000 int ret;
2001
2002 isa_register_portio_list(dev, isa->iobase, fdc_portio_list, fdctrl, "fdc");
2003
2004 isa_init_irq(&isa->busdev, &fdctrl->irq, isa->irq);
2005 fdctrl->dma_chann = isa->dma;
2006
2007 qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 2);
2008 ret = fdctrl_init_common(fdctrl);
2009
2010 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
2011 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
2012
2013 return ret;
2014 }
2015
2016 static int sysbus_fdc_init1(SysBusDevice *dev)
2017 {
2018 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
2019 FDCtrl *fdctrl = &sys->state;
2020 int ret;
2021
2022 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
2023 sysbus_init_mmio(dev, &fdctrl->iomem);
2024 sysbus_init_irq(dev, &fdctrl->irq);
2025 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2026 fdctrl->dma_chann = -1;
2027
2028 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2029 ret = fdctrl_init_common(fdctrl);
2030
2031 return ret;
2032 }
2033
2034 static int sun4m_fdc_init1(SysBusDevice *dev)
2035 {
2036 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2037
2038 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
2039 "fdctrl", 0x08);
2040 sysbus_init_mmio(dev, &fdctrl->iomem);
2041 sysbus_init_irq(dev, &fdctrl->irq);
2042 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2043
2044 fdctrl->sun4m = 1;
2045 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2046 return fdctrl_init_common(fdctrl);
2047 }
2048
2049 void fdc_get_bs(BlockDriverState *bs[], ISADevice *dev)
2050 {
2051 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
2052 FDCtrl *fdctrl = &isa->state;
2053 int i;
2054
2055 for (i = 0; i < MAX_FD; i++) {
2056 bs[i] = fdctrl->drives[i].bs;
2057 }
2058 }
2059
2060
2061 static const VMStateDescription vmstate_isa_fdc ={
2062 .name = "fdc",
2063 .version_id = 2,
2064 .minimum_version_id = 2,
2065 .fields = (VMStateField []) {
2066 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2067 VMSTATE_END_OF_LIST()
2068 }
2069 };
2070
2071 static Property isa_fdc_properties[] = {
2072 DEFINE_PROP_HEX32("iobase", FDCtrlISABus, iobase, 0x3f0),
2073 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2074 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2075 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2076 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2077 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2078 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
2079 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2080 0, true),
2081 DEFINE_PROP_END_OF_LIST(),
2082 };
2083
2084 static void isabus_fdc_class_init1(ObjectClass *klass, void *data)
2085 {
2086 DeviceClass *dc = DEVICE_CLASS(klass);
2087 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
2088 ic->init = isabus_fdc_init1;
2089 dc->fw_name = "fdc";
2090 dc->no_user = 1;
2091 dc->reset = fdctrl_external_reset_isa;
2092 dc->vmsd = &vmstate_isa_fdc;
2093 dc->props = isa_fdc_properties;
2094 }
2095
2096 static TypeInfo isa_fdc_info = {
2097 .name = "isa-fdc",
2098 .parent = TYPE_ISA_DEVICE,
2099 .instance_size = sizeof(FDCtrlISABus),
2100 .class_init = isabus_fdc_class_init1,
2101 };
2102
2103 static const VMStateDescription vmstate_sysbus_fdc ={
2104 .name = "fdc",
2105 .version_id = 2,
2106 .minimum_version_id = 2,
2107 .fields = (VMStateField []) {
2108 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2109 VMSTATE_END_OF_LIST()
2110 }
2111 };
2112
2113 static Property sysbus_fdc_properties[] = {
2114 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2115 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2116 DEFINE_PROP_END_OF_LIST(),
2117 };
2118
2119 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2120 {
2121 DeviceClass *dc = DEVICE_CLASS(klass);
2122 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2123
2124 k->init = sysbus_fdc_init1;
2125 dc->reset = fdctrl_external_reset_sysbus;
2126 dc->vmsd = &vmstate_sysbus_fdc;
2127 dc->props = sysbus_fdc_properties;
2128 }
2129
2130 static TypeInfo sysbus_fdc_info = {
2131 .name = "sysbus-fdc",
2132 .parent = TYPE_SYS_BUS_DEVICE,
2133 .instance_size = sizeof(FDCtrlSysBus),
2134 .class_init = sysbus_fdc_class_init,
2135 };
2136
2137 static Property sun4m_fdc_properties[] = {
2138 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2139 DEFINE_PROP_END_OF_LIST(),
2140 };
2141
2142 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2143 {
2144 DeviceClass *dc = DEVICE_CLASS(klass);
2145 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2146
2147 k->init = sun4m_fdc_init1;
2148 dc->reset = fdctrl_external_reset_sysbus;
2149 dc->vmsd = &vmstate_sysbus_fdc;
2150 dc->props = sun4m_fdc_properties;
2151 }
2152
2153 static TypeInfo sun4m_fdc_info = {
2154 .name = "SUNW,fdtwo",
2155 .parent = TYPE_SYS_BUS_DEVICE,
2156 .instance_size = sizeof(FDCtrlSysBus),
2157 .class_init = sun4m_fdc_class_init,
2158 };
2159
2160 static void fdc_register_types(void)
2161 {
2162 type_register_static(&isa_fdc_info);
2163 type_register_static(&sysbus_fdc_info);
2164 type_register_static(&sun4m_fdc_info);
2165 }
2166
2167 type_init(fdc_register_types)
Qemu copy for testing