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Merge branch 'prep-up' of git://repo.or.cz/qemu/afaerber
[qemu.git] / hw / fdc.c
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37 #include "blockdev.h"
38 #include "sysemu.h"
39
40 /********************************************************/
41 /* debug Floppy devices */
42 //#define DEBUG_FLOPPY
43
44 #ifdef DEBUG_FLOPPY
45 #define FLOPPY_DPRINTF(fmt, ...) \
46 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
47 #else
48 #define FLOPPY_DPRINTF(fmt, ...)
49 #endif
50
51 #define FLOPPY_ERROR(fmt, ...) \
52 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
53
54 /********************************************************/
55 /* Floppy drive emulation */
56
57 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
58 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
59
60 /* Will always be a fixed parameter for us */
61 #define FD_SECTOR_LEN 512
62 #define FD_SECTOR_SC 2 /* Sector size code */
63 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
64
65 typedef struct FDCtrl FDCtrl;
66
67 /* Floppy disk drive emulation */
68 typedef enum FDiskFlags {
69 FDISK_DBL_SIDES = 0x01,
70 } FDiskFlags;
71
72 typedef struct FDrive {
73 FDCtrl *fdctrl;
74 BlockDriverState *bs;
75 /* Drive status */
76 FDriveType drive;
77 uint8_t perpendicular; /* 2.88 MB access mode */
78 /* Position */
79 uint8_t head;
80 uint8_t track;
81 uint8_t sect;
82 /* Media */
83 FDiskFlags flags;
84 uint8_t last_sect; /* Nb sector per track */
85 uint8_t max_track; /* Nb of tracks */
86 uint16_t bps; /* Bytes per sector */
87 uint8_t ro; /* Is read-only */
88 uint8_t media_changed; /* Is media changed */
89 uint8_t media_rate; /* Data rate of medium */
90 } FDrive;
91
92 static void fd_init(FDrive *drv)
93 {
94 /* Drive */
95 drv->drive = FDRIVE_DRV_NONE;
96 drv->perpendicular = 0;
97 /* Disk */
98 drv->last_sect = 0;
99 drv->max_track = 0;
100 }
101
102 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
103
104 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
105 uint8_t last_sect, uint8_t num_sides)
106 {
107 return (((track * num_sides) + head) * last_sect) + sect - 1;
108 }
109
110 /* Returns current position, in sectors, for given drive */
111 static int fd_sector(FDrive *drv)
112 {
113 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
114 NUM_SIDES(drv));
115 }
116
117 /* Seek to a new position:
118 * returns 0 if already on right track
119 * returns 1 if track changed
120 * returns 2 if track is invalid
121 * returns 3 if sector is invalid
122 * returns 4 if seek is disabled
123 */
124 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
125 int enable_seek)
126 {
127 uint32_t sector;
128 int ret;
129
130 if (track > drv->max_track ||
131 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
132 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
133 head, track, sect, 1,
134 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
135 drv->max_track, drv->last_sect);
136 return 2;
137 }
138 if (sect > drv->last_sect) {
139 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
140 head, track, sect, 1,
141 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
142 drv->max_track, drv->last_sect);
143 return 3;
144 }
145 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
146 ret = 0;
147 if (sector != fd_sector(drv)) {
148 #if 0
149 if (!enable_seek) {
150 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
151 head, track, sect, 1, drv->max_track, drv->last_sect);
152 return 4;
153 }
154 #endif
155 drv->head = head;
156 if (drv->track != track)
157 ret = 1;
158 drv->track = track;
159 drv->sect = sect;
160 }
161
162 return ret;
163 }
164
165 /* Set drive back to track 0 */
166 static void fd_recalibrate(FDrive *drv)
167 {
168 FLOPPY_DPRINTF("recalibrate\n");
169 drv->head = 0;
170 drv->track = 0;
171 drv->sect = 1;
172 }
173
174 /* Revalidate a disk drive after a disk change */
175 static void fd_revalidate(FDrive *drv)
176 {
177 int nb_heads, max_track, last_sect, ro;
178 FDriveType drive;
179 FDriveRate rate;
180
181 FLOPPY_DPRINTF("revalidate\n");
182 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
183 ro = bdrv_is_read_only(drv->bs);
184 bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,
185 &last_sect, drv->drive, &drive, &rate);
186 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
187 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
188 nb_heads - 1, max_track, last_sect);
189 } else {
190 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
191 max_track, last_sect, ro ? "ro" : "rw");
192 }
193 if (nb_heads == 1) {
194 drv->flags &= ~FDISK_DBL_SIDES;
195 } else {
196 drv->flags |= FDISK_DBL_SIDES;
197 }
198 drv->max_track = max_track;
199 drv->last_sect = last_sect;
200 drv->ro = ro;
201 drv->drive = drive;
202 drv->media_rate = rate;
203 } else {
204 FLOPPY_DPRINTF("No disk in drive\n");
205 drv->last_sect = 0;
206 drv->max_track = 0;
207 drv->flags &= ~FDISK_DBL_SIDES;
208 }
209 }
210
211 /********************************************************/
212 /* Intel 82078 floppy disk controller emulation */
213
214 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
215 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
216 static int fdctrl_transfer_handler (void *opaque, int nchan,
217 int dma_pos, int dma_len);
218 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
219 static FDrive *get_cur_drv(FDCtrl *fdctrl);
220
221 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
222 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
223 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
224 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
225 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
226 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
227 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
228 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
229 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
230 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
231 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
232 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
233
234 enum {
235 FD_DIR_WRITE = 0,
236 FD_DIR_READ = 1,
237 FD_DIR_SCANE = 2,
238 FD_DIR_SCANL = 3,
239 FD_DIR_SCANH = 4,
240 };
241
242 enum {
243 FD_STATE_MULTI = 0x01, /* multi track flag */
244 FD_STATE_FORMAT = 0x02, /* format flag */
245 FD_STATE_SEEK = 0x04, /* seek flag */
246 };
247
248 enum {
249 FD_REG_SRA = 0x00,
250 FD_REG_SRB = 0x01,
251 FD_REG_DOR = 0x02,
252 FD_REG_TDR = 0x03,
253 FD_REG_MSR = 0x04,
254 FD_REG_DSR = 0x04,
255 FD_REG_FIFO = 0x05,
256 FD_REG_DIR = 0x07,
257 FD_REG_CCR = 0x07,
258 };
259
260 enum {
261 FD_CMD_READ_TRACK = 0x02,
262 FD_CMD_SPECIFY = 0x03,
263 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
264 FD_CMD_WRITE = 0x05,
265 FD_CMD_READ = 0x06,
266 FD_CMD_RECALIBRATE = 0x07,
267 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
268 FD_CMD_WRITE_DELETED = 0x09,
269 FD_CMD_READ_ID = 0x0a,
270 FD_CMD_READ_DELETED = 0x0c,
271 FD_CMD_FORMAT_TRACK = 0x0d,
272 FD_CMD_DUMPREG = 0x0e,
273 FD_CMD_SEEK = 0x0f,
274 FD_CMD_VERSION = 0x10,
275 FD_CMD_SCAN_EQUAL = 0x11,
276 FD_CMD_PERPENDICULAR_MODE = 0x12,
277 FD_CMD_CONFIGURE = 0x13,
278 FD_CMD_LOCK = 0x14,
279 FD_CMD_VERIFY = 0x16,
280 FD_CMD_POWERDOWN_MODE = 0x17,
281 FD_CMD_PART_ID = 0x18,
282 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
283 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
284 FD_CMD_SAVE = 0x2e,
285 FD_CMD_OPTION = 0x33,
286 FD_CMD_RESTORE = 0x4e,
287 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
288 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
289 FD_CMD_FORMAT_AND_WRITE = 0xcd,
290 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
291 };
292
293 enum {
294 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
295 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
296 FD_CONFIG_POLL = 0x10, /* Poll enabled */
297 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
298 FD_CONFIG_EIS = 0x40, /* No implied seeks */
299 };
300
301 enum {
302 FD_SR0_EQPMT = 0x10,
303 FD_SR0_SEEK = 0x20,
304 FD_SR0_ABNTERM = 0x40,
305 FD_SR0_INVCMD = 0x80,
306 FD_SR0_RDYCHG = 0xc0,
307 };
308
309 enum {
310 FD_SR1_MA = 0x01, /* Missing address mark */
311 FD_SR1_NW = 0x02, /* Not writable */
312 FD_SR1_EC = 0x80, /* End of cylinder */
313 };
314
315 enum {
316 FD_SR2_SNS = 0x04, /* Scan not satisfied */
317 FD_SR2_SEH = 0x08, /* Scan equal hit */
318 };
319
320 enum {
321 FD_SRA_DIR = 0x01,
322 FD_SRA_nWP = 0x02,
323 FD_SRA_nINDX = 0x04,
324 FD_SRA_HDSEL = 0x08,
325 FD_SRA_nTRK0 = 0x10,
326 FD_SRA_STEP = 0x20,
327 FD_SRA_nDRV2 = 0x40,
328 FD_SRA_INTPEND = 0x80,
329 };
330
331 enum {
332 FD_SRB_MTR0 = 0x01,
333 FD_SRB_MTR1 = 0x02,
334 FD_SRB_WGATE = 0x04,
335 FD_SRB_RDATA = 0x08,
336 FD_SRB_WDATA = 0x10,
337 FD_SRB_DR0 = 0x20,
338 };
339
340 enum {
341 #if MAX_FD == 4
342 FD_DOR_SELMASK = 0x03,
343 #else
344 FD_DOR_SELMASK = 0x01,
345 #endif
346 FD_DOR_nRESET = 0x04,
347 FD_DOR_DMAEN = 0x08,
348 FD_DOR_MOTEN0 = 0x10,
349 FD_DOR_MOTEN1 = 0x20,
350 FD_DOR_MOTEN2 = 0x40,
351 FD_DOR_MOTEN3 = 0x80,
352 };
353
354 enum {
355 #if MAX_FD == 4
356 FD_TDR_BOOTSEL = 0x0c,
357 #else
358 FD_TDR_BOOTSEL = 0x04,
359 #endif
360 };
361
362 enum {
363 FD_DSR_DRATEMASK= 0x03,
364 FD_DSR_PWRDOWN = 0x40,
365 FD_DSR_SWRESET = 0x80,
366 };
367
368 enum {
369 FD_MSR_DRV0BUSY = 0x01,
370 FD_MSR_DRV1BUSY = 0x02,
371 FD_MSR_DRV2BUSY = 0x04,
372 FD_MSR_DRV3BUSY = 0x08,
373 FD_MSR_CMDBUSY = 0x10,
374 FD_MSR_NONDMA = 0x20,
375 FD_MSR_DIO = 0x40,
376 FD_MSR_RQM = 0x80,
377 };
378
379 enum {
380 FD_DIR_DSKCHG = 0x80,
381 };
382
383 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
384 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
385 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
386
387 struct FDCtrl {
388 MemoryRegion iomem;
389 qemu_irq irq;
390 /* Controller state */
391 QEMUTimer *result_timer;
392 int dma_chann;
393 /* Controller's identification */
394 uint8_t version;
395 /* HW */
396 uint8_t sra;
397 uint8_t srb;
398 uint8_t dor;
399 uint8_t dor_vmstate; /* only used as temp during vmstate */
400 uint8_t tdr;
401 uint8_t dsr;
402 uint8_t msr;
403 uint8_t cur_drv;
404 uint8_t status0;
405 uint8_t status1;
406 uint8_t status2;
407 /* Command FIFO */
408 uint8_t *fifo;
409 int32_t fifo_size;
410 uint32_t data_pos;
411 uint32_t data_len;
412 uint8_t data_state;
413 uint8_t data_dir;
414 uint8_t eot; /* last wanted sector */
415 /* States kept only to be returned back */
416 /* precompensation */
417 uint8_t precomp_trk;
418 uint8_t config;
419 uint8_t lock;
420 /* Power down config (also with status regB access mode */
421 uint8_t pwrd;
422 /* Floppy drives */
423 uint8_t num_floppies;
424 /* Sun4m quirks? */
425 int sun4m;
426 FDrive drives[MAX_FD];
427 int reset_sensei;
428 uint32_t check_media_rate;
429 /* Timers state */
430 uint8_t timer0;
431 uint8_t timer1;
432 };
433
434 typedef struct FDCtrlSysBus {
435 SysBusDevice busdev;
436 struct FDCtrl state;
437 } FDCtrlSysBus;
438
439 typedef struct FDCtrlISABus {
440 ISADevice busdev;
441 uint32_t iobase;
442 uint32_t irq;
443 uint32_t dma;
444 struct FDCtrl state;
445 int32_t bootindexA;
446 int32_t bootindexB;
447 } FDCtrlISABus;
448
449 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
450 {
451 FDCtrl *fdctrl = opaque;
452 uint32_t retval;
453
454 reg &= 7;
455 switch (reg) {
456 case FD_REG_SRA:
457 retval = fdctrl_read_statusA(fdctrl);
458 break;
459 case FD_REG_SRB:
460 retval = fdctrl_read_statusB(fdctrl);
461 break;
462 case FD_REG_DOR:
463 retval = fdctrl_read_dor(fdctrl);
464 break;
465 case FD_REG_TDR:
466 retval = fdctrl_read_tape(fdctrl);
467 break;
468 case FD_REG_MSR:
469 retval = fdctrl_read_main_status(fdctrl);
470 break;
471 case FD_REG_FIFO:
472 retval = fdctrl_read_data(fdctrl);
473 break;
474 case FD_REG_DIR:
475 retval = fdctrl_read_dir(fdctrl);
476 break;
477 default:
478 retval = (uint32_t)(-1);
479 break;
480 }
481 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
482
483 return retval;
484 }
485
486 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
487 {
488 FDCtrl *fdctrl = opaque;
489
490 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
491
492 reg &= 7;
493 switch (reg) {
494 case FD_REG_DOR:
495 fdctrl_write_dor(fdctrl, value);
496 break;
497 case FD_REG_TDR:
498 fdctrl_write_tape(fdctrl, value);
499 break;
500 case FD_REG_DSR:
501 fdctrl_write_rate(fdctrl, value);
502 break;
503 case FD_REG_FIFO:
504 fdctrl_write_data(fdctrl, value);
505 break;
506 case FD_REG_CCR:
507 fdctrl_write_ccr(fdctrl, value);
508 break;
509 default:
510 break;
511 }
512 }
513
514 static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
515 unsigned ize)
516 {
517 return fdctrl_read(opaque, (uint32_t)reg);
518 }
519
520 static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
521 uint64_t value, unsigned size)
522 {
523 fdctrl_write(opaque, (uint32_t)reg, value);
524 }
525
526 static const MemoryRegionOps fdctrl_mem_ops = {
527 .read = fdctrl_read_mem,
528 .write = fdctrl_write_mem,
529 .endianness = DEVICE_NATIVE_ENDIAN,
530 };
531
532 static const MemoryRegionOps fdctrl_mem_strict_ops = {
533 .read = fdctrl_read_mem,
534 .write = fdctrl_write_mem,
535 .endianness = DEVICE_NATIVE_ENDIAN,
536 .valid = {
537 .min_access_size = 1,
538 .max_access_size = 1,
539 },
540 };
541
542 static bool fdrive_media_changed_needed(void *opaque)
543 {
544 FDrive *drive = opaque;
545
546 return (drive->bs != NULL && drive->media_changed != 1);
547 }
548
549 static const VMStateDescription vmstate_fdrive_media_changed = {
550 .name = "fdrive/media_changed",
551 .version_id = 1,
552 .minimum_version_id = 1,
553 .minimum_version_id_old = 1,
554 .fields = (VMStateField[]) {
555 VMSTATE_UINT8(media_changed, FDrive),
556 VMSTATE_END_OF_LIST()
557 }
558 };
559
560 static bool fdrive_media_rate_needed(void *opaque)
561 {
562 FDrive *drive = opaque;
563
564 return drive->fdctrl->check_media_rate;
565 }
566
567 static const VMStateDescription vmstate_fdrive_media_rate = {
568 .name = "fdrive/media_rate",
569 .version_id = 1,
570 .minimum_version_id = 1,
571 .minimum_version_id_old = 1,
572 .fields = (VMStateField[]) {
573 VMSTATE_UINT8(media_rate, FDrive),
574 VMSTATE_END_OF_LIST()
575 }
576 };
577
578 static const VMStateDescription vmstate_fdrive = {
579 .name = "fdrive",
580 .version_id = 1,
581 .minimum_version_id = 1,
582 .minimum_version_id_old = 1,
583 .fields = (VMStateField[]) {
584 VMSTATE_UINT8(head, FDrive),
585 VMSTATE_UINT8(track, FDrive),
586 VMSTATE_UINT8(sect, FDrive),
587 VMSTATE_END_OF_LIST()
588 },
589 .subsections = (VMStateSubsection[]) {
590 {
591 .vmsd = &vmstate_fdrive_media_changed,
592 .needed = &fdrive_media_changed_needed,
593 } , {
594 .vmsd = &vmstate_fdrive_media_rate,
595 .needed = &fdrive_media_rate_needed,
596 } , {
597 /* empty */
598 }
599 }
600 };
601
602 static void fdc_pre_save(void *opaque)
603 {
604 FDCtrl *s = opaque;
605
606 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
607 }
608
609 static int fdc_post_load(void *opaque, int version_id)
610 {
611 FDCtrl *s = opaque;
612
613 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
614 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
615 return 0;
616 }
617
618 static const VMStateDescription vmstate_fdc = {
619 .name = "fdc",
620 .version_id = 2,
621 .minimum_version_id = 2,
622 .minimum_version_id_old = 2,
623 .pre_save = fdc_pre_save,
624 .post_load = fdc_post_load,
625 .fields = (VMStateField []) {
626 /* Controller State */
627 VMSTATE_UINT8(sra, FDCtrl),
628 VMSTATE_UINT8(srb, FDCtrl),
629 VMSTATE_UINT8(dor_vmstate, FDCtrl),
630 VMSTATE_UINT8(tdr, FDCtrl),
631 VMSTATE_UINT8(dsr, FDCtrl),
632 VMSTATE_UINT8(msr, FDCtrl),
633 VMSTATE_UINT8(status0, FDCtrl),
634 VMSTATE_UINT8(status1, FDCtrl),
635 VMSTATE_UINT8(status2, FDCtrl),
636 /* Command FIFO */
637 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
638 uint8_t),
639 VMSTATE_UINT32(data_pos, FDCtrl),
640 VMSTATE_UINT32(data_len, FDCtrl),
641 VMSTATE_UINT8(data_state, FDCtrl),
642 VMSTATE_UINT8(data_dir, FDCtrl),
643 VMSTATE_UINT8(eot, FDCtrl),
644 /* States kept only to be returned back */
645 VMSTATE_UINT8(timer0, FDCtrl),
646 VMSTATE_UINT8(timer1, FDCtrl),
647 VMSTATE_UINT8(precomp_trk, FDCtrl),
648 VMSTATE_UINT8(config, FDCtrl),
649 VMSTATE_UINT8(lock, FDCtrl),
650 VMSTATE_UINT8(pwrd, FDCtrl),
651 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
652 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
653 vmstate_fdrive, FDrive),
654 VMSTATE_END_OF_LIST()
655 }
656 };
657
658 static void fdctrl_external_reset_sysbus(DeviceState *d)
659 {
660 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
661 FDCtrl *s = &sys->state;
662
663 fdctrl_reset(s, 0);
664 }
665
666 static void fdctrl_external_reset_isa(DeviceState *d)
667 {
668 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
669 FDCtrl *s = &isa->state;
670
671 fdctrl_reset(s, 0);
672 }
673
674 static void fdctrl_handle_tc(void *opaque, int irq, int level)
675 {
676 //FDCtrl *s = opaque;
677
678 if (level) {
679 // XXX
680 FLOPPY_DPRINTF("TC pulsed\n");
681 }
682 }
683
684 /* Change IRQ state */
685 static void fdctrl_reset_irq(FDCtrl *fdctrl)
686 {
687 if (!(fdctrl->sra & FD_SRA_INTPEND))
688 return;
689 FLOPPY_DPRINTF("Reset interrupt\n");
690 qemu_set_irq(fdctrl->irq, 0);
691 fdctrl->sra &= ~FD_SRA_INTPEND;
692 }
693
694 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
695 {
696 /* Sparc mutation */
697 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
698 /* XXX: not sure */
699 fdctrl->msr &= ~FD_MSR_CMDBUSY;
700 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
701 fdctrl->status0 = status0;
702 return;
703 }
704 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
705 qemu_set_irq(fdctrl->irq, 1);
706 fdctrl->sra |= FD_SRA_INTPEND;
707 }
708 fdctrl->reset_sensei = 0;
709 fdctrl->status0 = status0;
710 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
711 }
712
713 /* Reset controller */
714 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
715 {
716 int i;
717
718 FLOPPY_DPRINTF("reset controller\n");
719 fdctrl_reset_irq(fdctrl);
720 /* Initialise controller */
721 fdctrl->sra = 0;
722 fdctrl->srb = 0xc0;
723 if (!fdctrl->drives[1].bs)
724 fdctrl->sra |= FD_SRA_nDRV2;
725 fdctrl->cur_drv = 0;
726 fdctrl->dor = FD_DOR_nRESET;
727 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
728 fdctrl->msr = FD_MSR_RQM;
729 /* FIFO state */
730 fdctrl->data_pos = 0;
731 fdctrl->data_len = 0;
732 fdctrl->data_state = 0;
733 fdctrl->data_dir = FD_DIR_WRITE;
734 for (i = 0; i < MAX_FD; i++)
735 fd_recalibrate(&fdctrl->drives[i]);
736 fdctrl_reset_fifo(fdctrl);
737 if (do_irq) {
738 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
739 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
740 }
741 }
742
743 static inline FDrive *drv0(FDCtrl *fdctrl)
744 {
745 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
746 }
747
748 static inline FDrive *drv1(FDCtrl *fdctrl)
749 {
750 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
751 return &fdctrl->drives[1];
752 else
753 return &fdctrl->drives[0];
754 }
755
756 #if MAX_FD == 4
757 static inline FDrive *drv2(FDCtrl *fdctrl)
758 {
759 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
760 return &fdctrl->drives[2];
761 else
762 return &fdctrl->drives[1];
763 }
764
765 static inline FDrive *drv3(FDCtrl *fdctrl)
766 {
767 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
768 return &fdctrl->drives[3];
769 else
770 return &fdctrl->drives[2];
771 }
772 #endif
773
774 static FDrive *get_cur_drv(FDCtrl *fdctrl)
775 {
776 switch (fdctrl->cur_drv) {
777 case 0: return drv0(fdctrl);
778 case 1: return drv1(fdctrl);
779 #if MAX_FD == 4
780 case 2: return drv2(fdctrl);
781 case 3: return drv3(fdctrl);
782 #endif
783 default: return NULL;
784 }
785 }
786
787 /* Status A register : 0x00 (read-only) */
788 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
789 {
790 uint32_t retval = fdctrl->sra;
791
792 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
793
794 return retval;
795 }
796
797 /* Status B register : 0x01 (read-only) */
798 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
799 {
800 uint32_t retval = fdctrl->srb;
801
802 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
803
804 return retval;
805 }
806
807 /* Digital output register : 0x02 */
808 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
809 {
810 uint32_t retval = fdctrl->dor;
811
812 /* Selected drive */
813 retval |= fdctrl->cur_drv;
814 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
815
816 return retval;
817 }
818
819 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
820 {
821 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
822
823 /* Motors */
824 if (value & FD_DOR_MOTEN0)
825 fdctrl->srb |= FD_SRB_MTR0;
826 else
827 fdctrl->srb &= ~FD_SRB_MTR0;
828 if (value & FD_DOR_MOTEN1)
829 fdctrl->srb |= FD_SRB_MTR1;
830 else
831 fdctrl->srb &= ~FD_SRB_MTR1;
832
833 /* Drive */
834 if (value & 1)
835 fdctrl->srb |= FD_SRB_DR0;
836 else
837 fdctrl->srb &= ~FD_SRB_DR0;
838
839 /* Reset */
840 if (!(value & FD_DOR_nRESET)) {
841 if (fdctrl->dor & FD_DOR_nRESET) {
842 FLOPPY_DPRINTF("controller enter RESET state\n");
843 }
844 } else {
845 if (!(fdctrl->dor & FD_DOR_nRESET)) {
846 FLOPPY_DPRINTF("controller out of RESET state\n");
847 fdctrl_reset(fdctrl, 1);
848 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
849 }
850 }
851 /* Selected drive */
852 fdctrl->cur_drv = value & FD_DOR_SELMASK;
853
854 fdctrl->dor = value;
855 }
856
857 /* Tape drive register : 0x03 */
858 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
859 {
860 uint32_t retval = fdctrl->tdr;
861
862 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
863
864 return retval;
865 }
866
867 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
868 {
869 /* Reset mode */
870 if (!(fdctrl->dor & FD_DOR_nRESET)) {
871 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
872 return;
873 }
874 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
875 /* Disk boot selection indicator */
876 fdctrl->tdr = value & FD_TDR_BOOTSEL;
877 /* Tape indicators: never allow */
878 }
879
880 /* Main status register : 0x04 (read) */
881 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
882 {
883 uint32_t retval = fdctrl->msr;
884
885 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
886 fdctrl->dor |= FD_DOR_nRESET;
887
888 /* Sparc mutation */
889 if (fdctrl->sun4m) {
890 retval |= FD_MSR_DIO;
891 fdctrl_reset_irq(fdctrl);
892 };
893
894 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
895
896 return retval;
897 }
898
899 /* Data select rate register : 0x04 (write) */
900 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
901 {
902 /* Reset mode */
903 if (!(fdctrl->dor & FD_DOR_nRESET)) {
904 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
905 return;
906 }
907 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
908 /* Reset: autoclear */
909 if (value & FD_DSR_SWRESET) {
910 fdctrl->dor &= ~FD_DOR_nRESET;
911 fdctrl_reset(fdctrl, 1);
912 fdctrl->dor |= FD_DOR_nRESET;
913 }
914 if (value & FD_DSR_PWRDOWN) {
915 fdctrl_reset(fdctrl, 1);
916 }
917 fdctrl->dsr = value;
918 }
919
920 /* Configuration control register: 0x07 (write) */
921 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
922 {
923 /* Reset mode */
924 if (!(fdctrl->dor & FD_DOR_nRESET)) {
925 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
926 return;
927 }
928 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
929
930 /* Only the rate selection bits used in AT mode, and we
931 * store those in the DSR.
932 */
933 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
934 (value & FD_DSR_DRATEMASK);
935 }
936
937 static int fdctrl_media_changed(FDrive *drv)
938 {
939 int ret;
940
941 if (!drv->bs)
942 return 0;
943 if (drv->media_changed) {
944 drv->media_changed = 0;
945 ret = 1;
946 } else {
947 ret = bdrv_media_changed(drv->bs);
948 if (ret < 0) {
949 ret = 0; /* we don't know, assume no */
950 }
951 }
952 if (ret) {
953 fd_revalidate(drv);
954 }
955 return ret;
956 }
957
958 /* Digital input register : 0x07 (read-only) */
959 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
960 {
961 uint32_t retval = 0;
962
963 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
964 retval |= FD_DIR_DSKCHG;
965 }
966 if (retval != 0) {
967 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
968 }
969
970 return retval;
971 }
972
973 /* FIFO state control */
974 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
975 {
976 fdctrl->data_dir = FD_DIR_WRITE;
977 fdctrl->data_pos = 0;
978 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
979 }
980
981 /* Set FIFO status for the host to read */
982 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
983 {
984 fdctrl->data_dir = FD_DIR_READ;
985 fdctrl->data_len = fifo_len;
986 fdctrl->data_pos = 0;
987 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
988 if (do_irq)
989 fdctrl_raise_irq(fdctrl, 0x00);
990 }
991
992 /* Set an error: unimplemented/unknown command */
993 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
994 {
995 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
996 fdctrl->fifo[0] = FD_SR0_INVCMD;
997 fdctrl_set_fifo(fdctrl, 1, 0);
998 }
999
1000 /* Seek to next sector */
1001 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1002 {
1003 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1004 cur_drv->head, cur_drv->track, cur_drv->sect,
1005 fd_sector(cur_drv));
1006 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1007 error in fact */
1008 if (cur_drv->sect >= cur_drv->last_sect ||
1009 cur_drv->sect == fdctrl->eot) {
1010 cur_drv->sect = 1;
1011 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1012 if (cur_drv->head == 0 &&
1013 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1014 cur_drv->head = 1;
1015 } else {
1016 cur_drv->head = 0;
1017 cur_drv->track++;
1018 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1019 return 0;
1020 }
1021 } else {
1022 cur_drv->track++;
1023 return 0;
1024 }
1025 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1026 cur_drv->head, cur_drv->track,
1027 cur_drv->sect, fd_sector(cur_drv));
1028 } else {
1029 cur_drv->sect++;
1030 }
1031 return 1;
1032 }
1033
1034 /* Callback for transfer end (stop or abort) */
1035 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1036 uint8_t status1, uint8_t status2)
1037 {
1038 FDrive *cur_drv;
1039
1040 cur_drv = get_cur_drv(fdctrl);
1041 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1042 status0, status1, status2,
1043 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1044 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1045 fdctrl->fifo[1] = status1;
1046 fdctrl->fifo[2] = status2;
1047 fdctrl->fifo[3] = cur_drv->track;
1048 fdctrl->fifo[4] = cur_drv->head;
1049 fdctrl->fifo[5] = cur_drv->sect;
1050 fdctrl->fifo[6] = FD_SECTOR_SC;
1051 fdctrl->data_dir = FD_DIR_READ;
1052 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1053 DMA_release_DREQ(fdctrl->dma_chann);
1054 }
1055 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1056 fdctrl->msr &= ~FD_MSR_NONDMA;
1057 fdctrl_set_fifo(fdctrl, 7, 1);
1058 }
1059
1060 /* Prepare a data transfer (either DMA or FIFO) */
1061 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1062 {
1063 FDrive *cur_drv;
1064 uint8_t kh, kt, ks;
1065 int did_seek = 0;
1066
1067 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1068 cur_drv = get_cur_drv(fdctrl);
1069 kt = fdctrl->fifo[2];
1070 kh = fdctrl->fifo[3];
1071 ks = fdctrl->fifo[4];
1072 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1073 GET_CUR_DRV(fdctrl), kh, kt, ks,
1074 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1075 NUM_SIDES(cur_drv)));
1076 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1077 case 2:
1078 /* sect too big */
1079 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1080 fdctrl->fifo[3] = kt;
1081 fdctrl->fifo[4] = kh;
1082 fdctrl->fifo[5] = ks;
1083 return;
1084 case 3:
1085 /* track too big */
1086 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1087 fdctrl->fifo[3] = kt;
1088 fdctrl->fifo[4] = kh;
1089 fdctrl->fifo[5] = ks;
1090 return;
1091 case 4:
1092 /* No seek enabled */
1093 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1094 fdctrl->fifo[3] = kt;
1095 fdctrl->fifo[4] = kh;
1096 fdctrl->fifo[5] = ks;
1097 return;
1098 case 1:
1099 did_seek = 1;
1100 break;
1101 default:
1102 break;
1103 }
1104
1105 /* Check the data rate. If the programmed data rate does not match
1106 * the currently inserted medium, the operation has to fail. */
1107 if (fdctrl->check_media_rate &&
1108 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1109 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1110 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1111 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1112 fdctrl->fifo[3] = kt;
1113 fdctrl->fifo[4] = kh;
1114 fdctrl->fifo[5] = ks;
1115 return;
1116 }
1117
1118 /* Set the FIFO state */
1119 fdctrl->data_dir = direction;
1120 fdctrl->data_pos = 0;
1121 fdctrl->msr |= FD_MSR_CMDBUSY;
1122 if (fdctrl->fifo[0] & 0x80)
1123 fdctrl->data_state |= FD_STATE_MULTI;
1124 else
1125 fdctrl->data_state &= ~FD_STATE_MULTI;
1126 if (did_seek)
1127 fdctrl->data_state |= FD_STATE_SEEK;
1128 else
1129 fdctrl->data_state &= ~FD_STATE_SEEK;
1130 if (fdctrl->fifo[5] == 00) {
1131 fdctrl->data_len = fdctrl->fifo[8];
1132 } else {
1133 int tmp;
1134 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1135 tmp = (fdctrl->fifo[6] - ks + 1);
1136 if (fdctrl->fifo[0] & 0x80)
1137 tmp += fdctrl->fifo[6];
1138 fdctrl->data_len *= tmp;
1139 }
1140 fdctrl->eot = fdctrl->fifo[6];
1141 if (fdctrl->dor & FD_DOR_DMAEN) {
1142 int dma_mode;
1143 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1144 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1145 dma_mode = (dma_mode >> 2) & 3;
1146 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1147 dma_mode, direction,
1148 (128 << fdctrl->fifo[5]) *
1149 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1150 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1151 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1152 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1153 (direction == FD_DIR_READ && dma_mode == 1)) {
1154 /* No access is allowed until DMA transfer has completed */
1155 fdctrl->msr &= ~FD_MSR_RQM;
1156 /* Now, we just have to wait for the DMA controller to
1157 * recall us...
1158 */
1159 DMA_hold_DREQ(fdctrl->dma_chann);
1160 DMA_schedule(fdctrl->dma_chann);
1161 return;
1162 } else {
1163 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1164 }
1165 }
1166 FLOPPY_DPRINTF("start non-DMA transfer\n");
1167 fdctrl->msr |= FD_MSR_NONDMA;
1168 if (direction != FD_DIR_WRITE)
1169 fdctrl->msr |= FD_MSR_DIO;
1170 /* IO based transfer: calculate len */
1171 fdctrl_raise_irq(fdctrl, 0x00);
1172
1173 return;
1174 }
1175
1176 /* Prepare a transfer of deleted data */
1177 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1178 {
1179 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1180
1181 /* We don't handle deleted data,
1182 * so we don't return *ANYTHING*
1183 */
1184 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1185 }
1186
1187 /* handlers for DMA transfers */
1188 static int fdctrl_transfer_handler (void *opaque, int nchan,
1189 int dma_pos, int dma_len)
1190 {
1191 FDCtrl *fdctrl;
1192 FDrive *cur_drv;
1193 int len, start_pos, rel_pos;
1194 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1195
1196 fdctrl = opaque;
1197 if (fdctrl->msr & FD_MSR_RQM) {
1198 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1199 return 0;
1200 }
1201 cur_drv = get_cur_drv(fdctrl);
1202 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1203 fdctrl->data_dir == FD_DIR_SCANH)
1204 status2 = FD_SR2_SNS;
1205 if (dma_len > fdctrl->data_len)
1206 dma_len = fdctrl->data_len;
1207 if (cur_drv->bs == NULL) {
1208 if (fdctrl->data_dir == FD_DIR_WRITE)
1209 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1210 else
1211 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1212 len = 0;
1213 goto transfer_error;
1214 }
1215 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1216 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1217 len = dma_len - fdctrl->data_pos;
1218 if (len + rel_pos > FD_SECTOR_LEN)
1219 len = FD_SECTOR_LEN - rel_pos;
1220 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1221 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1222 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1223 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1224 fd_sector(cur_drv) * FD_SECTOR_LEN);
1225 if (fdctrl->data_dir != FD_DIR_WRITE ||
1226 len < FD_SECTOR_LEN || rel_pos != 0) {
1227 /* READ & SCAN commands and realign to a sector for WRITE */
1228 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1229 fdctrl->fifo, 1) < 0) {
1230 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1231 fd_sector(cur_drv));
1232 /* Sure, image size is too small... */
1233 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1234 }
1235 }
1236 switch (fdctrl->data_dir) {
1237 case FD_DIR_READ:
1238 /* READ commands */
1239 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1240 fdctrl->data_pos, len);
1241 break;
1242 case FD_DIR_WRITE:
1243 /* WRITE commands */
1244 if (cur_drv->ro) {
1245 /* Handle readonly medium early, no need to do DMA, touch the
1246 * LED or attempt any writes. A real floppy doesn't attempt
1247 * to write to readonly media either. */
1248 fdctrl_stop_transfer(fdctrl,
1249 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1250 0x00);
1251 goto transfer_error;
1252 }
1253
1254 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1255 fdctrl->data_pos, len);
1256 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1257 fdctrl->fifo, 1) < 0) {
1258 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1259 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1260 goto transfer_error;
1261 }
1262 break;
1263 default:
1264 /* SCAN commands */
1265 {
1266 uint8_t tmpbuf[FD_SECTOR_LEN];
1267 int ret;
1268 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1269 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1270 if (ret == 0) {
1271 status2 = FD_SR2_SEH;
1272 goto end_transfer;
1273 }
1274 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1275 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1276 status2 = 0x00;
1277 goto end_transfer;
1278 }
1279 }
1280 break;
1281 }
1282 fdctrl->data_pos += len;
1283 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1284 if (rel_pos == 0) {
1285 /* Seek to next sector */
1286 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1287 break;
1288 }
1289 }
1290 end_transfer:
1291 len = fdctrl->data_pos - start_pos;
1292 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1293 fdctrl->data_pos, len, fdctrl->data_len);
1294 if (fdctrl->data_dir == FD_DIR_SCANE ||
1295 fdctrl->data_dir == FD_DIR_SCANL ||
1296 fdctrl->data_dir == FD_DIR_SCANH)
1297 status2 = FD_SR2_SEH;
1298 if (FD_DID_SEEK(fdctrl->data_state))
1299 status0 |= FD_SR0_SEEK;
1300 fdctrl->data_len -= len;
1301 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1302 transfer_error:
1303
1304 return len;
1305 }
1306
1307 /* Data register : 0x05 */
1308 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1309 {
1310 FDrive *cur_drv;
1311 uint32_t retval = 0;
1312 int pos;
1313
1314 cur_drv = get_cur_drv(fdctrl);
1315 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1316 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1317 FLOPPY_ERROR("controller not ready for reading\n");
1318 return 0;
1319 }
1320 pos = fdctrl->data_pos;
1321 if (fdctrl->msr & FD_MSR_NONDMA) {
1322 pos %= FD_SECTOR_LEN;
1323 if (pos == 0) {
1324 if (fdctrl->data_pos != 0)
1325 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1326 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1327 fd_sector(cur_drv));
1328 return 0;
1329 }
1330 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1331 FLOPPY_DPRINTF("error getting sector %d\n",
1332 fd_sector(cur_drv));
1333 /* Sure, image size is too small... */
1334 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1335 }
1336 }
1337 }
1338 retval = fdctrl->fifo[pos];
1339 if (++fdctrl->data_pos == fdctrl->data_len) {
1340 fdctrl->data_pos = 0;
1341 /* Switch from transfer mode to status mode
1342 * then from status mode to command mode
1343 */
1344 if (fdctrl->msr & FD_MSR_NONDMA) {
1345 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1346 } else {
1347 fdctrl_reset_fifo(fdctrl);
1348 fdctrl_reset_irq(fdctrl);
1349 }
1350 }
1351 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1352
1353 return retval;
1354 }
1355
1356 static void fdctrl_format_sector(FDCtrl *fdctrl)
1357 {
1358 FDrive *cur_drv;
1359 uint8_t kh, kt, ks;
1360
1361 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1362 cur_drv = get_cur_drv(fdctrl);
1363 kt = fdctrl->fifo[6];
1364 kh = fdctrl->fifo[7];
1365 ks = fdctrl->fifo[8];
1366 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1367 GET_CUR_DRV(fdctrl), kh, kt, ks,
1368 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1369 NUM_SIDES(cur_drv)));
1370 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1371 case 2:
1372 /* sect too big */
1373 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1374 fdctrl->fifo[3] = kt;
1375 fdctrl->fifo[4] = kh;
1376 fdctrl->fifo[5] = ks;
1377 return;
1378 case 3:
1379 /* track too big */
1380 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1381 fdctrl->fifo[3] = kt;
1382 fdctrl->fifo[4] = kh;
1383 fdctrl->fifo[5] = ks;
1384 return;
1385 case 4:
1386 /* No seek enabled */
1387 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1388 fdctrl->fifo[3] = kt;
1389 fdctrl->fifo[4] = kh;
1390 fdctrl->fifo[5] = ks;
1391 return;
1392 case 1:
1393 fdctrl->data_state |= FD_STATE_SEEK;
1394 break;
1395 default:
1396 break;
1397 }
1398 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1399 if (cur_drv->bs == NULL ||
1400 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1401 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1402 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1403 } else {
1404 if (cur_drv->sect == cur_drv->last_sect) {
1405 fdctrl->data_state &= ~FD_STATE_FORMAT;
1406 /* Last sector done */
1407 if (FD_DID_SEEK(fdctrl->data_state))
1408 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1409 else
1410 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1411 } else {
1412 /* More to do */
1413 fdctrl->data_pos = 0;
1414 fdctrl->data_len = 4;
1415 }
1416 }
1417 }
1418
1419 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1420 {
1421 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1422 fdctrl->fifo[0] = fdctrl->lock << 4;
1423 fdctrl_set_fifo(fdctrl, 1, 0);
1424 }
1425
1426 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1427 {
1428 FDrive *cur_drv = get_cur_drv(fdctrl);
1429
1430 /* Drives position */
1431 fdctrl->fifo[0] = drv0(fdctrl)->track;
1432 fdctrl->fifo[1] = drv1(fdctrl)->track;
1433 #if MAX_FD == 4
1434 fdctrl->fifo[2] = drv2(fdctrl)->track;
1435 fdctrl->fifo[3] = drv3(fdctrl)->track;
1436 #else
1437 fdctrl->fifo[2] = 0;
1438 fdctrl->fifo[3] = 0;
1439 #endif
1440 /* timers */
1441 fdctrl->fifo[4] = fdctrl->timer0;
1442 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1443 fdctrl->fifo[6] = cur_drv->last_sect;
1444 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1445 (cur_drv->perpendicular << 2);
1446 fdctrl->fifo[8] = fdctrl->config;
1447 fdctrl->fifo[9] = fdctrl->precomp_trk;
1448 fdctrl_set_fifo(fdctrl, 10, 0);
1449 }
1450
1451 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1452 {
1453 /* Controller's version */
1454 fdctrl->fifo[0] = fdctrl->version;
1455 fdctrl_set_fifo(fdctrl, 1, 0);
1456 }
1457
1458 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1459 {
1460 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1461 fdctrl_set_fifo(fdctrl, 1, 0);
1462 }
1463
1464 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1465 {
1466 FDrive *cur_drv = get_cur_drv(fdctrl);
1467
1468 /* Drives position */
1469 drv0(fdctrl)->track = fdctrl->fifo[3];
1470 drv1(fdctrl)->track = fdctrl->fifo[4];
1471 #if MAX_FD == 4
1472 drv2(fdctrl)->track = fdctrl->fifo[5];
1473 drv3(fdctrl)->track = fdctrl->fifo[6];
1474 #endif
1475 /* timers */
1476 fdctrl->timer0 = fdctrl->fifo[7];
1477 fdctrl->timer1 = fdctrl->fifo[8];
1478 cur_drv->last_sect = fdctrl->fifo[9];
1479 fdctrl->lock = fdctrl->fifo[10] >> 7;
1480 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1481 fdctrl->config = fdctrl->fifo[11];
1482 fdctrl->precomp_trk = fdctrl->fifo[12];
1483 fdctrl->pwrd = fdctrl->fifo[13];
1484 fdctrl_reset_fifo(fdctrl);
1485 }
1486
1487 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1488 {
1489 FDrive *cur_drv = get_cur_drv(fdctrl);
1490
1491 fdctrl->fifo[0] = 0;
1492 fdctrl->fifo[1] = 0;
1493 /* Drives position */
1494 fdctrl->fifo[2] = drv0(fdctrl)->track;
1495 fdctrl->fifo[3] = drv1(fdctrl)->track;
1496 #if MAX_FD == 4
1497 fdctrl->fifo[4] = drv2(fdctrl)->track;
1498 fdctrl->fifo[5] = drv3(fdctrl)->track;
1499 #else
1500 fdctrl->fifo[4] = 0;
1501 fdctrl->fifo[5] = 0;
1502 #endif
1503 /* timers */
1504 fdctrl->fifo[6] = fdctrl->timer0;
1505 fdctrl->fifo[7] = fdctrl->timer1;
1506 fdctrl->fifo[8] = cur_drv->last_sect;
1507 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1508 (cur_drv->perpendicular << 2);
1509 fdctrl->fifo[10] = fdctrl->config;
1510 fdctrl->fifo[11] = fdctrl->precomp_trk;
1511 fdctrl->fifo[12] = fdctrl->pwrd;
1512 fdctrl->fifo[13] = 0;
1513 fdctrl->fifo[14] = 0;
1514 fdctrl_set_fifo(fdctrl, 15, 0);
1515 }
1516
1517 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1518 {
1519 FDrive *cur_drv = get_cur_drv(fdctrl);
1520
1521 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1522 qemu_mod_timer(fdctrl->result_timer,
1523 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1524 }
1525
1526 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1527 {
1528 FDrive *cur_drv;
1529
1530 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1531 cur_drv = get_cur_drv(fdctrl);
1532 fdctrl->data_state |= FD_STATE_FORMAT;
1533 if (fdctrl->fifo[0] & 0x80)
1534 fdctrl->data_state |= FD_STATE_MULTI;
1535 else
1536 fdctrl->data_state &= ~FD_STATE_MULTI;
1537 fdctrl->data_state &= ~FD_STATE_SEEK;
1538 cur_drv->bps =
1539 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1540 #if 0
1541 cur_drv->last_sect =
1542 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1543 fdctrl->fifo[3] / 2;
1544 #else
1545 cur_drv->last_sect = fdctrl->fifo[3];
1546 #endif
1547 /* TODO: implement format using DMA expected by the Bochs BIOS
1548 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1549 * the sector with the specified fill byte
1550 */
1551 fdctrl->data_state &= ~FD_STATE_FORMAT;
1552 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1553 }
1554
1555 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1556 {
1557 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1558 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1559 if (fdctrl->fifo[2] & 1)
1560 fdctrl->dor &= ~FD_DOR_DMAEN;
1561 else
1562 fdctrl->dor |= FD_DOR_DMAEN;
1563 /* No result back */
1564 fdctrl_reset_fifo(fdctrl);
1565 }
1566
1567 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1568 {
1569 FDrive *cur_drv;
1570
1571 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1572 cur_drv = get_cur_drv(fdctrl);
1573 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1574 /* 1 Byte status back */
1575 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1576 (cur_drv->track == 0 ? 0x10 : 0x00) |
1577 (cur_drv->head << 2) |
1578 GET_CUR_DRV(fdctrl) |
1579 0x28;
1580 fdctrl_set_fifo(fdctrl, 1, 0);
1581 }
1582
1583 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1584 {
1585 FDrive *cur_drv;
1586
1587 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1588 cur_drv = get_cur_drv(fdctrl);
1589 fd_recalibrate(cur_drv);
1590 fdctrl_reset_fifo(fdctrl);
1591 /* Raise Interrupt */
1592 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1593 }
1594
1595 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1596 {
1597 FDrive *cur_drv = get_cur_drv(fdctrl);
1598
1599 if(fdctrl->reset_sensei > 0) {
1600 fdctrl->fifo[0] =
1601 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1602 fdctrl->reset_sensei--;
1603 } else {
1604 /* XXX: status0 handling is broken for read/write
1605 commands, so we do this hack. It should be suppressed
1606 ASAP */
1607 fdctrl->fifo[0] =
1608 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1609 }
1610
1611 fdctrl->fifo[1] = cur_drv->track;
1612 fdctrl_set_fifo(fdctrl, 2, 0);
1613 fdctrl_reset_irq(fdctrl);
1614 fdctrl->status0 = FD_SR0_RDYCHG;
1615 }
1616
1617 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1618 {
1619 FDrive *cur_drv;
1620
1621 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1622 cur_drv = get_cur_drv(fdctrl);
1623 fdctrl_reset_fifo(fdctrl);
1624 /* The seek command just sends step pulses to the drive and doesn't care if
1625 * there is a medium inserted of if it's banging the head against the drive.
1626 */
1627 if (fdctrl->fifo[2] > cur_drv->max_track) {
1628 cur_drv->track = cur_drv->max_track;
1629 } else {
1630 cur_drv->track = fdctrl->fifo[2];
1631 }
1632 /* Raise Interrupt */
1633 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1634 }
1635
1636 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1637 {
1638 FDrive *cur_drv = get_cur_drv(fdctrl);
1639
1640 if (fdctrl->fifo[1] & 0x80)
1641 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1642 /* No result back */
1643 fdctrl_reset_fifo(fdctrl);
1644 }
1645
1646 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1647 {
1648 fdctrl->config = fdctrl->fifo[2];
1649 fdctrl->precomp_trk = fdctrl->fifo[3];
1650 /* No result back */
1651 fdctrl_reset_fifo(fdctrl);
1652 }
1653
1654 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1655 {
1656 fdctrl->pwrd = fdctrl->fifo[1];
1657 fdctrl->fifo[0] = fdctrl->fifo[1];
1658 fdctrl_set_fifo(fdctrl, 1, 0);
1659 }
1660
1661 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1662 {
1663 /* No result back */
1664 fdctrl_reset_fifo(fdctrl);
1665 }
1666
1667 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1668 {
1669 FDrive *cur_drv = get_cur_drv(fdctrl);
1670
1671 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1672 /* Command parameters done */
1673 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1674 fdctrl->fifo[0] = fdctrl->fifo[1];
1675 fdctrl->fifo[2] = 0;
1676 fdctrl->fifo[3] = 0;
1677 fdctrl_set_fifo(fdctrl, 4, 0);
1678 } else {
1679 fdctrl_reset_fifo(fdctrl);
1680 }
1681 } else if (fdctrl->data_len > 7) {
1682 /* ERROR */
1683 fdctrl->fifo[0] = 0x80 |
1684 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1685 fdctrl_set_fifo(fdctrl, 1, 0);
1686 }
1687 }
1688
1689 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1690 {
1691 FDrive *cur_drv;
1692
1693 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1694 cur_drv = get_cur_drv(fdctrl);
1695 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1696 cur_drv->track = cur_drv->max_track - 1;
1697 } else {
1698 cur_drv->track += fdctrl->fifo[2];
1699 }
1700 fdctrl_reset_fifo(fdctrl);
1701 /* Raise Interrupt */
1702 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1703 }
1704
1705 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1706 {
1707 FDrive *cur_drv;
1708
1709 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1710 cur_drv = get_cur_drv(fdctrl);
1711 if (fdctrl->fifo[2] > cur_drv->track) {
1712 cur_drv->track = 0;
1713 } else {
1714 cur_drv->track -= fdctrl->fifo[2];
1715 }
1716 fdctrl_reset_fifo(fdctrl);
1717 /* Raise Interrupt */
1718 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1719 }
1720
1721 static const struct {
1722 uint8_t value;
1723 uint8_t mask;
1724 const char* name;
1725 int parameters;
1726 void (*handler)(FDCtrl *fdctrl, int direction);
1727 int direction;
1728 } handlers[] = {
1729 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1730 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1731 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1732 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1733 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1734 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1735 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1736 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1737 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1738 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1739 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1740 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1741 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1742 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1743 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1744 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1745 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1746 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1747 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1748 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1749 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1750 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1751 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1752 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1753 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1754 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1755 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1756 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1757 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1758 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1759 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1760 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1761 };
1762 /* Associate command to an index in the 'handlers' array */
1763 static uint8_t command_to_handler[256];
1764
1765 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1766 {
1767 FDrive *cur_drv;
1768 int pos;
1769
1770 /* Reset mode */
1771 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1772 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1773 return;
1774 }
1775 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1776 FLOPPY_ERROR("controller not ready for writing\n");
1777 return;
1778 }
1779 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1780 /* Is it write command time ? */
1781 if (fdctrl->msr & FD_MSR_NONDMA) {
1782 /* FIFO data write */
1783 pos = fdctrl->data_pos++;
1784 pos %= FD_SECTOR_LEN;
1785 fdctrl->fifo[pos] = value;
1786 if (pos == FD_SECTOR_LEN - 1 ||
1787 fdctrl->data_pos == fdctrl->data_len) {
1788 cur_drv = get_cur_drv(fdctrl);
1789 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1790 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1791 return;
1792 }
1793 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1794 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1795 fd_sector(cur_drv));
1796 return;
1797 }
1798 }
1799 /* Switch from transfer mode to status mode
1800 * then from status mode to command mode
1801 */
1802 if (fdctrl->data_pos == fdctrl->data_len)
1803 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1804 return;
1805 }
1806 if (fdctrl->data_pos == 0) {
1807 /* Command */
1808 pos = command_to_handler[value & 0xff];
1809 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1810 fdctrl->data_len = handlers[pos].parameters + 1;
1811 fdctrl->msr |= FD_MSR_CMDBUSY;
1812 }
1813
1814 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1815 fdctrl->fifo[fdctrl->data_pos++] = value;
1816 if (fdctrl->data_pos == fdctrl->data_len) {
1817 /* We now have all parameters
1818 * and will be able to treat the command
1819 */
1820 if (fdctrl->data_state & FD_STATE_FORMAT) {
1821 fdctrl_format_sector(fdctrl);
1822 return;
1823 }
1824
1825 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1826 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1827 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1828 }
1829 }
1830
1831 static void fdctrl_result_timer(void *opaque)
1832 {
1833 FDCtrl *fdctrl = opaque;
1834 FDrive *cur_drv = get_cur_drv(fdctrl);
1835
1836 /* Pretend we are spinning.
1837 * This is needed for Coherent, which uses READ ID to check for
1838 * sector interleaving.
1839 */
1840 if (cur_drv->last_sect != 0) {
1841 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1842 }
1843 /* READ_ID can't automatically succeed! */
1844 if (fdctrl->check_media_rate &&
1845 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1846 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
1847 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1848 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1849 } else {
1850 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1851 }
1852 }
1853
1854 static void fdctrl_change_cb(void *opaque, bool load)
1855 {
1856 FDrive *drive = opaque;
1857
1858 drive->media_changed = 1;
1859 }
1860
1861 static const BlockDevOps fdctrl_block_ops = {
1862 .change_media_cb = fdctrl_change_cb,
1863 };
1864
1865 /* Init functions */
1866 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1867 {
1868 unsigned int i;
1869 FDrive *drive;
1870
1871 for (i = 0; i < MAX_FD; i++) {
1872 drive = &fdctrl->drives[i];
1873 drive->fdctrl = fdctrl;
1874
1875 if (drive->bs) {
1876 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1877 error_report("fdc doesn't support drive option werror");
1878 return -1;
1879 }
1880 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1881 error_report("fdc doesn't support drive option rerror");
1882 return -1;
1883 }
1884 }
1885
1886 fd_init(drive);
1887 fd_revalidate(drive);
1888 if (drive->bs) {
1889 drive->media_changed = 1;
1890 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
1891 }
1892 }
1893 return 0;
1894 }
1895
1896 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1897 target_phys_addr_t mmio_base, DriveInfo **fds)
1898 {
1899 FDCtrl *fdctrl;
1900 DeviceState *dev;
1901 FDCtrlSysBus *sys;
1902
1903 dev = qdev_create(NULL, "sysbus-fdc");
1904 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1905 fdctrl = &sys->state;
1906 fdctrl->dma_chann = dma_chann; /* FIXME */
1907 if (fds[0]) {
1908 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1909 }
1910 if (fds[1]) {
1911 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1912 }
1913 qdev_init_nofail(dev);
1914 sysbus_connect_irq(&sys->busdev, 0, irq);
1915 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1916 }
1917
1918 void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1919 DriveInfo **fds, qemu_irq *fdc_tc)
1920 {
1921 DeviceState *dev;
1922 FDCtrlSysBus *sys;
1923
1924 dev = qdev_create(NULL, "SUNW,fdtwo");
1925 if (fds[0]) {
1926 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1927 }
1928 qdev_init_nofail(dev);
1929 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1930 sysbus_connect_irq(&sys->busdev, 0, irq);
1931 sysbus_mmio_map(&sys->busdev, 0, io_base);
1932 *fdc_tc = qdev_get_gpio_in(dev, 0);
1933 }
1934
1935 static int fdctrl_init_common(FDCtrl *fdctrl)
1936 {
1937 int i, j;
1938 static int command_tables_inited = 0;
1939
1940 /* Fill 'command_to_handler' lookup table */
1941 if (!command_tables_inited) {
1942 command_tables_inited = 1;
1943 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1944 for (j = 0; j < sizeof(command_to_handler); j++) {
1945 if ((j & handlers[i].mask) == handlers[i].value) {
1946 command_to_handler[j] = i;
1947 }
1948 }
1949 }
1950 }
1951
1952 FLOPPY_DPRINTF("init controller\n");
1953 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1954 fdctrl->fifo_size = 512;
1955 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
1956 fdctrl_result_timer, fdctrl);
1957
1958 fdctrl->version = 0x90; /* Intel 82078 controller */
1959 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1960 fdctrl->num_floppies = MAX_FD;
1961
1962 if (fdctrl->dma_chann != -1)
1963 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1964 return fdctrl_connect_drives(fdctrl);
1965 }
1966
1967 static const MemoryRegionPortio fdc_portio_list[] = {
1968 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
1969 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
1970 PORTIO_END_OF_LIST(),
1971 };
1972
1973 static int isabus_fdc_init1(ISADevice *dev)
1974 {
1975 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1976 FDCtrl *fdctrl = &isa->state;
1977 int ret;
1978
1979 isa_register_portio_list(dev, isa->iobase, fdc_portio_list, fdctrl, "fdc");
1980
1981 isa_init_irq(&isa->busdev, &fdctrl->irq, isa->irq);
1982 fdctrl->dma_chann = isa->dma;
1983
1984 qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 2);
1985 ret = fdctrl_init_common(fdctrl);
1986
1987 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
1988 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
1989
1990 return ret;
1991 }
1992
1993 static int sysbus_fdc_init1(SysBusDevice *dev)
1994 {
1995 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
1996 FDCtrl *fdctrl = &sys->state;
1997 int ret;
1998
1999 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
2000 sysbus_init_mmio(dev, &fdctrl->iomem);
2001 sysbus_init_irq(dev, &fdctrl->irq);
2002 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2003 fdctrl->dma_chann = -1;
2004
2005 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2006 ret = fdctrl_init_common(fdctrl);
2007
2008 return ret;
2009 }
2010
2011 static int sun4m_fdc_init1(SysBusDevice *dev)
2012 {
2013 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2014
2015 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
2016 "fdctrl", 0x08);
2017 sysbus_init_mmio(dev, &fdctrl->iomem);
2018 sysbus_init_irq(dev, &fdctrl->irq);
2019 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2020
2021 fdctrl->sun4m = 1;
2022 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2023 return fdctrl_init_common(fdctrl);
2024 }
2025
2026 void fdc_get_bs(BlockDriverState *bs[], ISADevice *dev)
2027 {
2028 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
2029 FDCtrl *fdctrl = &isa->state;
2030 int i;
2031
2032 for (i = 0; i < MAX_FD; i++) {
2033 bs[i] = fdctrl->drives[i].bs;
2034 }
2035 }
2036
2037
2038 static const VMStateDescription vmstate_isa_fdc ={
2039 .name = "fdc",
2040 .version_id = 2,
2041 .minimum_version_id = 2,
2042 .fields = (VMStateField []) {
2043 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2044 VMSTATE_END_OF_LIST()
2045 }
2046 };
2047
2048 static Property isa_fdc_properties[] = {
2049 DEFINE_PROP_HEX32("iobase", FDCtrlISABus, iobase, 0x3f0),
2050 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2051 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2052 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2053 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2054 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2055 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
2056 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2057 0, true),
2058 DEFINE_PROP_END_OF_LIST(),
2059 };
2060
2061 static void isabus_fdc_class_init1(ObjectClass *klass, void *data)
2062 {
2063 DeviceClass *dc = DEVICE_CLASS(klass);
2064 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
2065 ic->init = isabus_fdc_init1;
2066 dc->fw_name = "fdc";
2067 dc->no_user = 1;
2068 dc->reset = fdctrl_external_reset_isa;
2069 dc->vmsd = &vmstate_isa_fdc;
2070 dc->props = isa_fdc_properties;
2071 }
2072
2073 static TypeInfo isa_fdc_info = {
2074 .name = "isa-fdc",
2075 .parent = TYPE_ISA_DEVICE,
2076 .instance_size = sizeof(FDCtrlISABus),
2077 .class_init = isabus_fdc_class_init1,
2078 };
2079
2080 static const VMStateDescription vmstate_sysbus_fdc ={
2081 .name = "fdc",
2082 .version_id = 2,
2083 .minimum_version_id = 2,
2084 .fields = (VMStateField []) {
2085 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2086 VMSTATE_END_OF_LIST()
2087 }
2088 };
2089
2090 static Property sysbus_fdc_properties[] = {
2091 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2092 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2093 DEFINE_PROP_END_OF_LIST(),
2094 };
2095
2096 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2097 {
2098 DeviceClass *dc = DEVICE_CLASS(klass);
2099 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2100
2101 k->init = sysbus_fdc_init1;
2102 dc->reset = fdctrl_external_reset_sysbus;
2103 dc->vmsd = &vmstate_sysbus_fdc;
2104 dc->props = sysbus_fdc_properties;
2105 }
2106
2107 static TypeInfo sysbus_fdc_info = {
2108 .name = "sysbus-fdc",
2109 .parent = TYPE_SYS_BUS_DEVICE,
2110 .instance_size = sizeof(FDCtrlSysBus),
2111 .class_init = sysbus_fdc_class_init,
2112 };
2113
2114 static Property sun4m_fdc_properties[] = {
2115 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2116 DEFINE_PROP_END_OF_LIST(),
2117 };
2118
2119 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2120 {
2121 DeviceClass *dc = DEVICE_CLASS(klass);
2122 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2123
2124 k->init = sun4m_fdc_init1;
2125 dc->reset = fdctrl_external_reset_sysbus;
2126 dc->vmsd = &vmstate_sysbus_fdc;
2127 dc->props = sun4m_fdc_properties;
2128 }
2129
2130 static TypeInfo sun4m_fdc_info = {
2131 .name = "SUNW,fdtwo",
2132 .parent = TYPE_SYS_BUS_DEVICE,
2133 .instance_size = sizeof(FDCtrlSysBus),
2134 .class_init = sun4m_fdc_class_init,
2135 };
2136
2137 static void fdc_register_types(void)
2138 {
2139 type_register_static(&isa_fdc_info);
2140 type_register_static(&sysbus_fdc_info);
2141 type_register_static(&sun4m_fdc_info);
2142 }
2143
2144 type_init(fdc_register_types)
Qemu copy for testing