]> git.proxmox.com Git - qemu.git/blob - hw/fdc.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
qdev: Decouple qdev_prop_drive from DriveInfo
[qemu.git] / hw / fdc.c
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-timer.h"
33 #include "isa.h"
34 #include "sysbus.h"
35 #include "qdev-addr.h"
36
37 /********************************************************/
38 /* debug Floppy devices */
39 //#define DEBUG_FLOPPY
40
41 #ifdef DEBUG_FLOPPY
42 #define FLOPPY_DPRINTF(fmt, ...) \
43 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
44 #else
45 #define FLOPPY_DPRINTF(fmt, ...)
46 #endif
47
48 #define FLOPPY_ERROR(fmt, ...) \
49 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
50
51 /********************************************************/
52 /* Floppy drive emulation */
53
54 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
55 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
56
57 /* Will always be a fixed parameter for us */
58 #define FD_SECTOR_LEN 512
59 #define FD_SECTOR_SC 2 /* Sector size code */
60 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
61
62 /* Floppy disk drive emulation */
63 typedef enum FDiskType {
64 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
65 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
66 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
67 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
68 FDRIVE_DISK_NONE = 0x05, /* No disk */
69 } FDiskType;
70
71 typedef enum FDriveType {
72 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
73 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
74 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
75 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
76 } FDriveType;
77
78 typedef enum FDiskFlags {
79 FDISK_DBL_SIDES = 0x01,
80 } FDiskFlags;
81
82 typedef struct FDrive {
83 BlockDriverState *bs;
84 /* Drive status */
85 FDriveType drive;
86 uint8_t perpendicular; /* 2.88 MB access mode */
87 /* Position */
88 uint8_t head;
89 uint8_t track;
90 uint8_t sect;
91 /* Media */
92 FDiskFlags flags;
93 uint8_t last_sect; /* Nb sector per track */
94 uint8_t max_track; /* Nb of tracks */
95 uint16_t bps; /* Bytes per sector */
96 uint8_t ro; /* Is read-only */
97 } FDrive;
98
99 static void fd_init(FDrive *drv)
100 {
101 /* Drive */
102 drv->drive = FDRIVE_DRV_NONE;
103 drv->perpendicular = 0;
104 /* Disk */
105 drv->last_sect = 0;
106 drv->max_track = 0;
107 }
108
109 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
110 uint8_t last_sect)
111 {
112 return (((track * 2) + head) * last_sect) + sect - 1;
113 }
114
115 /* Returns current position, in sectors, for given drive */
116 static int fd_sector(FDrive *drv)
117 {
118 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
119 }
120
121 /* Seek to a new position:
122 * returns 0 if already on right track
123 * returns 1 if track changed
124 * returns 2 if track is invalid
125 * returns 3 if sector is invalid
126 * returns 4 if seek is disabled
127 */
128 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
129 int enable_seek)
130 {
131 uint32_t sector;
132 int ret;
133
134 if (track > drv->max_track ||
135 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
136 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
137 head, track, sect, 1,
138 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
139 drv->max_track, drv->last_sect);
140 return 2;
141 }
142 if (sect > drv->last_sect) {
143 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
144 head, track, sect, 1,
145 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
146 drv->max_track, drv->last_sect);
147 return 3;
148 }
149 sector = fd_sector_calc(head, track, sect, drv->last_sect);
150 ret = 0;
151 if (sector != fd_sector(drv)) {
152 #if 0
153 if (!enable_seek) {
154 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
155 head, track, sect, 1, drv->max_track, drv->last_sect);
156 return 4;
157 }
158 #endif
159 drv->head = head;
160 if (drv->track != track)
161 ret = 1;
162 drv->track = track;
163 drv->sect = sect;
164 }
165
166 return ret;
167 }
168
169 /* Set drive back to track 0 */
170 static void fd_recalibrate(FDrive *drv)
171 {
172 FLOPPY_DPRINTF("recalibrate\n");
173 drv->head = 0;
174 drv->track = 0;
175 drv->sect = 1;
176 }
177
178 /* Recognize floppy formats */
179 typedef struct FDFormat {
180 FDriveType drive;
181 FDiskType disk;
182 uint8_t last_sect;
183 uint8_t max_track;
184 uint8_t max_head;
185 const char *str;
186 } FDFormat;
187
188 static const FDFormat fd_formats[] = {
189 /* First entry is default format */
190 /* 1.44 MB 3"1/2 floppy disks */
191 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
192 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
193 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
197 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
198 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
199 /* 2.88 MB 3"1/2 floppy disks */
200 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
201 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
202 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
203 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
204 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
205 /* 720 kB 3"1/2 floppy disks */
206 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
207 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
208 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
210 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
211 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
212 /* 1.2 MB 5"1/4 floppy disks */
213 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
214 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
215 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
216 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
218 /* 720 kB 5"1/4 floppy disks */
219 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
220 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
221 /* 360 kB 5"1/4 floppy disks */
222 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
224 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
225 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
226 /* 320 kB 5"1/4 floppy disks */
227 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
228 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
229 /* 360 kB must match 5"1/4 better than 3"1/2... */
230 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
231 /* end */
232 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
233 };
234
235 /* Revalidate a disk drive after a disk change */
236 static void fd_revalidate(FDrive *drv)
237 {
238 const FDFormat *parse;
239 uint64_t nb_sectors, size;
240 int i, first_match, match;
241 int nb_heads, max_track, last_sect, ro;
242
243 FLOPPY_DPRINTF("revalidate\n");
244 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
245 ro = bdrv_is_read_only(drv->bs);
246 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
247 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
248 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
249 nb_heads - 1, max_track, last_sect);
250 } else {
251 bdrv_get_geometry(drv->bs, &nb_sectors);
252 match = -1;
253 first_match = -1;
254 for (i = 0;; i++) {
255 parse = &fd_formats[i];
256 if (parse->drive == FDRIVE_DRV_NONE)
257 break;
258 if (drv->drive == parse->drive ||
259 drv->drive == FDRIVE_DRV_NONE) {
260 size = (parse->max_head + 1) * parse->max_track *
261 parse->last_sect;
262 if (nb_sectors == size) {
263 match = i;
264 break;
265 }
266 if (first_match == -1)
267 first_match = i;
268 }
269 }
270 if (match == -1) {
271 if (first_match == -1)
272 match = 1;
273 else
274 match = first_match;
275 parse = &fd_formats[match];
276 }
277 nb_heads = parse->max_head + 1;
278 max_track = parse->max_track;
279 last_sect = parse->last_sect;
280 drv->drive = parse->drive;
281 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
282 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
283 }
284 if (nb_heads == 1) {
285 drv->flags &= ~FDISK_DBL_SIDES;
286 } else {
287 drv->flags |= FDISK_DBL_SIDES;
288 }
289 drv->max_track = max_track;
290 drv->last_sect = last_sect;
291 drv->ro = ro;
292 } else {
293 FLOPPY_DPRINTF("No disk in drive\n");
294 drv->last_sect = 0;
295 drv->max_track = 0;
296 drv->flags &= ~FDISK_DBL_SIDES;
297 }
298 }
299
300 /********************************************************/
301 /* Intel 82078 floppy disk controller emulation */
302
303 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
304 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
305 static int fdctrl_transfer_handler (void *opaque, int nchan,
306 int dma_pos, int dma_len);
307 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
308
309 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
310 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
311 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
312 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
313 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
314 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
315 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
316 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
317 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
318 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
319 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
320
321 enum {
322 FD_DIR_WRITE = 0,
323 FD_DIR_READ = 1,
324 FD_DIR_SCANE = 2,
325 FD_DIR_SCANL = 3,
326 FD_DIR_SCANH = 4,
327 };
328
329 enum {
330 FD_STATE_MULTI = 0x01, /* multi track flag */
331 FD_STATE_FORMAT = 0x02, /* format flag */
332 FD_STATE_SEEK = 0x04, /* seek flag */
333 };
334
335 enum {
336 FD_REG_SRA = 0x00,
337 FD_REG_SRB = 0x01,
338 FD_REG_DOR = 0x02,
339 FD_REG_TDR = 0x03,
340 FD_REG_MSR = 0x04,
341 FD_REG_DSR = 0x04,
342 FD_REG_FIFO = 0x05,
343 FD_REG_DIR = 0x07,
344 };
345
346 enum {
347 FD_CMD_READ_TRACK = 0x02,
348 FD_CMD_SPECIFY = 0x03,
349 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
350 FD_CMD_WRITE = 0x05,
351 FD_CMD_READ = 0x06,
352 FD_CMD_RECALIBRATE = 0x07,
353 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
354 FD_CMD_WRITE_DELETED = 0x09,
355 FD_CMD_READ_ID = 0x0a,
356 FD_CMD_READ_DELETED = 0x0c,
357 FD_CMD_FORMAT_TRACK = 0x0d,
358 FD_CMD_DUMPREG = 0x0e,
359 FD_CMD_SEEK = 0x0f,
360 FD_CMD_VERSION = 0x10,
361 FD_CMD_SCAN_EQUAL = 0x11,
362 FD_CMD_PERPENDICULAR_MODE = 0x12,
363 FD_CMD_CONFIGURE = 0x13,
364 FD_CMD_LOCK = 0x14,
365 FD_CMD_VERIFY = 0x16,
366 FD_CMD_POWERDOWN_MODE = 0x17,
367 FD_CMD_PART_ID = 0x18,
368 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
369 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
370 FD_CMD_SAVE = 0x2e,
371 FD_CMD_OPTION = 0x33,
372 FD_CMD_RESTORE = 0x4e,
373 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
374 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
375 FD_CMD_FORMAT_AND_WRITE = 0xcd,
376 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
377 };
378
379 enum {
380 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
381 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
382 FD_CONFIG_POLL = 0x10, /* Poll enabled */
383 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
384 FD_CONFIG_EIS = 0x40, /* No implied seeks */
385 };
386
387 enum {
388 FD_SR0_EQPMT = 0x10,
389 FD_SR0_SEEK = 0x20,
390 FD_SR0_ABNTERM = 0x40,
391 FD_SR0_INVCMD = 0x80,
392 FD_SR0_RDYCHG = 0xc0,
393 };
394
395 enum {
396 FD_SR1_EC = 0x80, /* End of cylinder */
397 };
398
399 enum {
400 FD_SR2_SNS = 0x04, /* Scan not satisfied */
401 FD_SR2_SEH = 0x08, /* Scan equal hit */
402 };
403
404 enum {
405 FD_SRA_DIR = 0x01,
406 FD_SRA_nWP = 0x02,
407 FD_SRA_nINDX = 0x04,
408 FD_SRA_HDSEL = 0x08,
409 FD_SRA_nTRK0 = 0x10,
410 FD_SRA_STEP = 0x20,
411 FD_SRA_nDRV2 = 0x40,
412 FD_SRA_INTPEND = 0x80,
413 };
414
415 enum {
416 FD_SRB_MTR0 = 0x01,
417 FD_SRB_MTR1 = 0x02,
418 FD_SRB_WGATE = 0x04,
419 FD_SRB_RDATA = 0x08,
420 FD_SRB_WDATA = 0x10,
421 FD_SRB_DR0 = 0x20,
422 };
423
424 enum {
425 #if MAX_FD == 4
426 FD_DOR_SELMASK = 0x03,
427 #else
428 FD_DOR_SELMASK = 0x01,
429 #endif
430 FD_DOR_nRESET = 0x04,
431 FD_DOR_DMAEN = 0x08,
432 FD_DOR_MOTEN0 = 0x10,
433 FD_DOR_MOTEN1 = 0x20,
434 FD_DOR_MOTEN2 = 0x40,
435 FD_DOR_MOTEN3 = 0x80,
436 };
437
438 enum {
439 #if MAX_FD == 4
440 FD_TDR_BOOTSEL = 0x0c,
441 #else
442 FD_TDR_BOOTSEL = 0x04,
443 #endif
444 };
445
446 enum {
447 FD_DSR_DRATEMASK= 0x03,
448 FD_DSR_PWRDOWN = 0x40,
449 FD_DSR_SWRESET = 0x80,
450 };
451
452 enum {
453 FD_MSR_DRV0BUSY = 0x01,
454 FD_MSR_DRV1BUSY = 0x02,
455 FD_MSR_DRV2BUSY = 0x04,
456 FD_MSR_DRV3BUSY = 0x08,
457 FD_MSR_CMDBUSY = 0x10,
458 FD_MSR_NONDMA = 0x20,
459 FD_MSR_DIO = 0x40,
460 FD_MSR_RQM = 0x80,
461 };
462
463 enum {
464 FD_DIR_DSKCHG = 0x80,
465 };
466
467 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
468 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
469 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
470
471 struct FDCtrl {
472 /* Controller's identification */
473 uint8_t version;
474 /* HW */
475 qemu_irq irq;
476 int dma_chann;
477 /* Controller state */
478 QEMUTimer *result_timer;
479 uint8_t sra;
480 uint8_t srb;
481 uint8_t dor;
482 uint8_t dor_vmstate; /* only used as temp during vmstate */
483 uint8_t tdr;
484 uint8_t dsr;
485 uint8_t msr;
486 uint8_t cur_drv;
487 uint8_t status0;
488 uint8_t status1;
489 uint8_t status2;
490 /* Command FIFO */
491 uint8_t *fifo;
492 int32_t fifo_size;
493 uint32_t data_pos;
494 uint32_t data_len;
495 uint8_t data_state;
496 uint8_t data_dir;
497 uint8_t eot; /* last wanted sector */
498 /* States kept only to be returned back */
499 /* Timers state */
500 uint8_t timer0;
501 uint8_t timer1;
502 /* precompensation */
503 uint8_t precomp_trk;
504 uint8_t config;
505 uint8_t lock;
506 /* Power down config (also with status regB access mode */
507 uint8_t pwrd;
508 /* Sun4m quirks? */
509 int sun4m;
510 /* Floppy drives */
511 uint8_t num_floppies;
512 FDrive drives[MAX_FD];
513 int reset_sensei;
514 };
515
516 typedef struct FDCtrlSysBus {
517 SysBusDevice busdev;
518 struct FDCtrl state;
519 } FDCtrlSysBus;
520
521 typedef struct FDCtrlISABus {
522 ISADevice busdev;
523 struct FDCtrl state;
524 } FDCtrlISABus;
525
526 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
527 {
528 FDCtrl *fdctrl = opaque;
529 uint32_t retval;
530
531 switch (reg) {
532 case FD_REG_SRA:
533 retval = fdctrl_read_statusA(fdctrl);
534 break;
535 case FD_REG_SRB:
536 retval = fdctrl_read_statusB(fdctrl);
537 break;
538 case FD_REG_DOR:
539 retval = fdctrl_read_dor(fdctrl);
540 break;
541 case FD_REG_TDR:
542 retval = fdctrl_read_tape(fdctrl);
543 break;
544 case FD_REG_MSR:
545 retval = fdctrl_read_main_status(fdctrl);
546 break;
547 case FD_REG_FIFO:
548 retval = fdctrl_read_data(fdctrl);
549 break;
550 case FD_REG_DIR:
551 retval = fdctrl_read_dir(fdctrl);
552 break;
553 default:
554 retval = (uint32_t)(-1);
555 break;
556 }
557 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
558
559 return retval;
560 }
561
562 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
563 {
564 FDCtrl *fdctrl = opaque;
565
566 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
567
568 switch (reg) {
569 case FD_REG_DOR:
570 fdctrl_write_dor(fdctrl, value);
571 break;
572 case FD_REG_TDR:
573 fdctrl_write_tape(fdctrl, value);
574 break;
575 case FD_REG_DSR:
576 fdctrl_write_rate(fdctrl, value);
577 break;
578 case FD_REG_FIFO:
579 fdctrl_write_data(fdctrl, value);
580 break;
581 default:
582 break;
583 }
584 }
585
586 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
587 {
588 return fdctrl_read(opaque, reg & 7);
589 }
590
591 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
592 {
593 fdctrl_write(opaque, reg & 7, value);
594 }
595
596 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
597 {
598 return fdctrl_read(opaque, (uint32_t)reg);
599 }
600
601 static void fdctrl_write_mem (void *opaque,
602 target_phys_addr_t reg, uint32_t value)
603 {
604 fdctrl_write(opaque, (uint32_t)reg, value);
605 }
606
607 static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
608 fdctrl_read_mem,
609 fdctrl_read_mem,
610 fdctrl_read_mem,
611 };
612
613 static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
614 fdctrl_write_mem,
615 fdctrl_write_mem,
616 fdctrl_write_mem,
617 };
618
619 static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
620 fdctrl_read_mem,
621 NULL,
622 NULL,
623 };
624
625 static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
626 fdctrl_write_mem,
627 NULL,
628 NULL,
629 };
630
631 static const VMStateDescription vmstate_fdrive = {
632 .name = "fdrive",
633 .version_id = 1,
634 .minimum_version_id = 1,
635 .minimum_version_id_old = 1,
636 .fields = (VMStateField []) {
637 VMSTATE_UINT8(head, FDrive),
638 VMSTATE_UINT8(track, FDrive),
639 VMSTATE_UINT8(sect, FDrive),
640 VMSTATE_END_OF_LIST()
641 }
642 };
643
644 static void fdc_pre_save(void *opaque)
645 {
646 FDCtrl *s = opaque;
647
648 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
649 }
650
651 static int fdc_post_load(void *opaque, int version_id)
652 {
653 FDCtrl *s = opaque;
654
655 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
656 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
657 return 0;
658 }
659
660 static const VMStateDescription vmstate_fdc = {
661 .name = "fdc",
662 .version_id = 2,
663 .minimum_version_id = 2,
664 .minimum_version_id_old = 2,
665 .pre_save = fdc_pre_save,
666 .post_load = fdc_post_load,
667 .fields = (VMStateField []) {
668 /* Controller State */
669 VMSTATE_UINT8(sra, FDCtrl),
670 VMSTATE_UINT8(srb, FDCtrl),
671 VMSTATE_UINT8(dor_vmstate, FDCtrl),
672 VMSTATE_UINT8(tdr, FDCtrl),
673 VMSTATE_UINT8(dsr, FDCtrl),
674 VMSTATE_UINT8(msr, FDCtrl),
675 VMSTATE_UINT8(status0, FDCtrl),
676 VMSTATE_UINT8(status1, FDCtrl),
677 VMSTATE_UINT8(status2, FDCtrl),
678 /* Command FIFO */
679 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
680 uint8_t),
681 VMSTATE_UINT32(data_pos, FDCtrl),
682 VMSTATE_UINT32(data_len, FDCtrl),
683 VMSTATE_UINT8(data_state, FDCtrl),
684 VMSTATE_UINT8(data_dir, FDCtrl),
685 VMSTATE_UINT8(eot, FDCtrl),
686 /* States kept only to be returned back */
687 VMSTATE_UINT8(timer0, FDCtrl),
688 VMSTATE_UINT8(timer1, FDCtrl),
689 VMSTATE_UINT8(precomp_trk, FDCtrl),
690 VMSTATE_UINT8(config, FDCtrl),
691 VMSTATE_UINT8(lock, FDCtrl),
692 VMSTATE_UINT8(pwrd, FDCtrl),
693 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
694 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
695 vmstate_fdrive, FDrive),
696 VMSTATE_END_OF_LIST()
697 }
698 };
699
700 static void fdctrl_external_reset_sysbus(DeviceState *d)
701 {
702 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
703 FDCtrl *s = &sys->state;
704
705 fdctrl_reset(s, 0);
706 }
707
708 static void fdctrl_external_reset_isa(DeviceState *d)
709 {
710 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
711 FDCtrl *s = &isa->state;
712
713 fdctrl_reset(s, 0);
714 }
715
716 static void fdctrl_handle_tc(void *opaque, int irq, int level)
717 {
718 //FDCtrl *s = opaque;
719
720 if (level) {
721 // XXX
722 FLOPPY_DPRINTF("TC pulsed\n");
723 }
724 }
725
726 /* XXX: may change if moved to bdrv */
727 int fdctrl_get_drive_type(FDCtrl *fdctrl, int drive_num)
728 {
729 return fdctrl->drives[drive_num].drive;
730 }
731
732 /* Change IRQ state */
733 static void fdctrl_reset_irq(FDCtrl *fdctrl)
734 {
735 if (!(fdctrl->sra & FD_SRA_INTPEND))
736 return;
737 FLOPPY_DPRINTF("Reset interrupt\n");
738 qemu_set_irq(fdctrl->irq, 0);
739 fdctrl->sra &= ~FD_SRA_INTPEND;
740 }
741
742 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
743 {
744 /* Sparc mutation */
745 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
746 /* XXX: not sure */
747 fdctrl->msr &= ~FD_MSR_CMDBUSY;
748 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
749 fdctrl->status0 = status0;
750 return;
751 }
752 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
753 qemu_set_irq(fdctrl->irq, 1);
754 fdctrl->sra |= FD_SRA_INTPEND;
755 }
756 fdctrl->reset_sensei = 0;
757 fdctrl->status0 = status0;
758 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
759 }
760
761 /* Reset controller */
762 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
763 {
764 int i;
765
766 FLOPPY_DPRINTF("reset controller\n");
767 fdctrl_reset_irq(fdctrl);
768 /* Initialise controller */
769 fdctrl->sra = 0;
770 fdctrl->srb = 0xc0;
771 if (!fdctrl->drives[1].bs)
772 fdctrl->sra |= FD_SRA_nDRV2;
773 fdctrl->cur_drv = 0;
774 fdctrl->dor = FD_DOR_nRESET;
775 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
776 fdctrl->msr = FD_MSR_RQM;
777 /* FIFO state */
778 fdctrl->data_pos = 0;
779 fdctrl->data_len = 0;
780 fdctrl->data_state = 0;
781 fdctrl->data_dir = FD_DIR_WRITE;
782 for (i = 0; i < MAX_FD; i++)
783 fd_recalibrate(&fdctrl->drives[i]);
784 fdctrl_reset_fifo(fdctrl);
785 if (do_irq) {
786 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
787 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
788 }
789 }
790
791 static inline FDrive *drv0(FDCtrl *fdctrl)
792 {
793 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
794 }
795
796 static inline FDrive *drv1(FDCtrl *fdctrl)
797 {
798 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
799 return &fdctrl->drives[1];
800 else
801 return &fdctrl->drives[0];
802 }
803
804 #if MAX_FD == 4
805 static inline FDrive *drv2(FDCtrl *fdctrl)
806 {
807 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
808 return &fdctrl->drives[2];
809 else
810 return &fdctrl->drives[1];
811 }
812
813 static inline FDrive *drv3(FDCtrl *fdctrl)
814 {
815 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
816 return &fdctrl->drives[3];
817 else
818 return &fdctrl->drives[2];
819 }
820 #endif
821
822 static FDrive *get_cur_drv(FDCtrl *fdctrl)
823 {
824 switch (fdctrl->cur_drv) {
825 case 0: return drv0(fdctrl);
826 case 1: return drv1(fdctrl);
827 #if MAX_FD == 4
828 case 2: return drv2(fdctrl);
829 case 3: return drv3(fdctrl);
830 #endif
831 default: return NULL;
832 }
833 }
834
835 /* Status A register : 0x00 (read-only) */
836 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
837 {
838 uint32_t retval = fdctrl->sra;
839
840 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
841
842 return retval;
843 }
844
845 /* Status B register : 0x01 (read-only) */
846 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
847 {
848 uint32_t retval = fdctrl->srb;
849
850 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
851
852 return retval;
853 }
854
855 /* Digital output register : 0x02 */
856 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
857 {
858 uint32_t retval = fdctrl->dor;
859
860 /* Selected drive */
861 retval |= fdctrl->cur_drv;
862 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
863
864 return retval;
865 }
866
867 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
868 {
869 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
870
871 /* Motors */
872 if (value & FD_DOR_MOTEN0)
873 fdctrl->srb |= FD_SRB_MTR0;
874 else
875 fdctrl->srb &= ~FD_SRB_MTR0;
876 if (value & FD_DOR_MOTEN1)
877 fdctrl->srb |= FD_SRB_MTR1;
878 else
879 fdctrl->srb &= ~FD_SRB_MTR1;
880
881 /* Drive */
882 if (value & 1)
883 fdctrl->srb |= FD_SRB_DR0;
884 else
885 fdctrl->srb &= ~FD_SRB_DR0;
886
887 /* Reset */
888 if (!(value & FD_DOR_nRESET)) {
889 if (fdctrl->dor & FD_DOR_nRESET) {
890 FLOPPY_DPRINTF("controller enter RESET state\n");
891 }
892 } else {
893 if (!(fdctrl->dor & FD_DOR_nRESET)) {
894 FLOPPY_DPRINTF("controller out of RESET state\n");
895 fdctrl_reset(fdctrl, 1);
896 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
897 }
898 }
899 /* Selected drive */
900 fdctrl->cur_drv = value & FD_DOR_SELMASK;
901
902 fdctrl->dor = value;
903 }
904
905 /* Tape drive register : 0x03 */
906 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
907 {
908 uint32_t retval = fdctrl->tdr;
909
910 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
911
912 return retval;
913 }
914
915 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
916 {
917 /* Reset mode */
918 if (!(fdctrl->dor & FD_DOR_nRESET)) {
919 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
920 return;
921 }
922 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
923 /* Disk boot selection indicator */
924 fdctrl->tdr = value & FD_TDR_BOOTSEL;
925 /* Tape indicators: never allow */
926 }
927
928 /* Main status register : 0x04 (read) */
929 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
930 {
931 uint32_t retval = fdctrl->msr;
932
933 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
934 fdctrl->dor |= FD_DOR_nRESET;
935
936 /* Sparc mutation */
937 if (fdctrl->sun4m) {
938 retval |= FD_MSR_DIO;
939 fdctrl_reset_irq(fdctrl);
940 };
941
942 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
943
944 return retval;
945 }
946
947 /* Data select rate register : 0x04 (write) */
948 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
949 {
950 /* Reset mode */
951 if (!(fdctrl->dor & FD_DOR_nRESET)) {
952 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
953 return;
954 }
955 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
956 /* Reset: autoclear */
957 if (value & FD_DSR_SWRESET) {
958 fdctrl->dor &= ~FD_DOR_nRESET;
959 fdctrl_reset(fdctrl, 1);
960 fdctrl->dor |= FD_DOR_nRESET;
961 }
962 if (value & FD_DSR_PWRDOWN) {
963 fdctrl_reset(fdctrl, 1);
964 }
965 fdctrl->dsr = value;
966 }
967
968 static int fdctrl_media_changed(FDrive *drv)
969 {
970 int ret;
971
972 if (!drv->bs)
973 return 0;
974 ret = bdrv_media_changed(drv->bs);
975 if (ret) {
976 fd_revalidate(drv);
977 }
978 return ret;
979 }
980
981 /* Digital input register : 0x07 (read-only) */
982 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
983 {
984 uint32_t retval = 0;
985
986 if (fdctrl_media_changed(drv0(fdctrl))
987 || fdctrl_media_changed(drv1(fdctrl))
988 #if MAX_FD == 4
989 || fdctrl_media_changed(drv2(fdctrl))
990 || fdctrl_media_changed(drv3(fdctrl))
991 #endif
992 )
993 retval |= FD_DIR_DSKCHG;
994 if (retval != 0) {
995 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
996 }
997
998 return retval;
999 }
1000
1001 /* FIFO state control */
1002 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
1003 {
1004 fdctrl->data_dir = FD_DIR_WRITE;
1005 fdctrl->data_pos = 0;
1006 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1007 }
1008
1009 /* Set FIFO status for the host to read */
1010 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
1011 {
1012 fdctrl->data_dir = FD_DIR_READ;
1013 fdctrl->data_len = fifo_len;
1014 fdctrl->data_pos = 0;
1015 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1016 if (do_irq)
1017 fdctrl_raise_irq(fdctrl, 0x00);
1018 }
1019
1020 /* Set an error: unimplemented/unknown command */
1021 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1022 {
1023 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1024 fdctrl->fifo[0] = FD_SR0_INVCMD;
1025 fdctrl_set_fifo(fdctrl, 1, 0);
1026 }
1027
1028 /* Seek to next sector */
1029 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1030 {
1031 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1032 cur_drv->head, cur_drv->track, cur_drv->sect,
1033 fd_sector(cur_drv));
1034 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1035 error in fact */
1036 if (cur_drv->sect >= cur_drv->last_sect ||
1037 cur_drv->sect == fdctrl->eot) {
1038 cur_drv->sect = 1;
1039 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1040 if (cur_drv->head == 0 &&
1041 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1042 cur_drv->head = 1;
1043 } else {
1044 cur_drv->head = 0;
1045 cur_drv->track++;
1046 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1047 return 0;
1048 }
1049 } else {
1050 cur_drv->track++;
1051 return 0;
1052 }
1053 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1054 cur_drv->head, cur_drv->track,
1055 cur_drv->sect, fd_sector(cur_drv));
1056 } else {
1057 cur_drv->sect++;
1058 }
1059 return 1;
1060 }
1061
1062 /* Callback for transfer end (stop or abort) */
1063 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1064 uint8_t status1, uint8_t status2)
1065 {
1066 FDrive *cur_drv;
1067
1068 cur_drv = get_cur_drv(fdctrl);
1069 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1070 status0, status1, status2,
1071 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1072 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1073 fdctrl->fifo[1] = status1;
1074 fdctrl->fifo[2] = status2;
1075 fdctrl->fifo[3] = cur_drv->track;
1076 fdctrl->fifo[4] = cur_drv->head;
1077 fdctrl->fifo[5] = cur_drv->sect;
1078 fdctrl->fifo[6] = FD_SECTOR_SC;
1079 fdctrl->data_dir = FD_DIR_READ;
1080 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1081 DMA_release_DREQ(fdctrl->dma_chann);
1082 }
1083 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1084 fdctrl->msr &= ~FD_MSR_NONDMA;
1085 fdctrl_set_fifo(fdctrl, 7, 1);
1086 }
1087
1088 /* Prepare a data transfer (either DMA or FIFO) */
1089 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1090 {
1091 FDrive *cur_drv;
1092 uint8_t kh, kt, ks;
1093 int did_seek = 0;
1094
1095 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1096 cur_drv = get_cur_drv(fdctrl);
1097 kt = fdctrl->fifo[2];
1098 kh = fdctrl->fifo[3];
1099 ks = fdctrl->fifo[4];
1100 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1101 GET_CUR_DRV(fdctrl), kh, kt, ks,
1102 fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1103 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1104 case 2:
1105 /* sect too big */
1106 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1107 fdctrl->fifo[3] = kt;
1108 fdctrl->fifo[4] = kh;
1109 fdctrl->fifo[5] = ks;
1110 return;
1111 case 3:
1112 /* track too big */
1113 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1114 fdctrl->fifo[3] = kt;
1115 fdctrl->fifo[4] = kh;
1116 fdctrl->fifo[5] = ks;
1117 return;
1118 case 4:
1119 /* No seek enabled */
1120 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1121 fdctrl->fifo[3] = kt;
1122 fdctrl->fifo[4] = kh;
1123 fdctrl->fifo[5] = ks;
1124 return;
1125 case 1:
1126 did_seek = 1;
1127 break;
1128 default:
1129 break;
1130 }
1131
1132 /* Set the FIFO state */
1133 fdctrl->data_dir = direction;
1134 fdctrl->data_pos = 0;
1135 fdctrl->msr |= FD_MSR_CMDBUSY;
1136 if (fdctrl->fifo[0] & 0x80)
1137 fdctrl->data_state |= FD_STATE_MULTI;
1138 else
1139 fdctrl->data_state &= ~FD_STATE_MULTI;
1140 if (did_seek)
1141 fdctrl->data_state |= FD_STATE_SEEK;
1142 else
1143 fdctrl->data_state &= ~FD_STATE_SEEK;
1144 if (fdctrl->fifo[5] == 00) {
1145 fdctrl->data_len = fdctrl->fifo[8];
1146 } else {
1147 int tmp;
1148 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1149 tmp = (fdctrl->fifo[6] - ks + 1);
1150 if (fdctrl->fifo[0] & 0x80)
1151 tmp += fdctrl->fifo[6];
1152 fdctrl->data_len *= tmp;
1153 }
1154 fdctrl->eot = fdctrl->fifo[6];
1155 if (fdctrl->dor & FD_DOR_DMAEN) {
1156 int dma_mode;
1157 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1158 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1159 dma_mode = (dma_mode >> 2) & 3;
1160 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1161 dma_mode, direction,
1162 (128 << fdctrl->fifo[5]) *
1163 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1164 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1165 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1166 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1167 (direction == FD_DIR_READ && dma_mode == 1)) {
1168 /* No access is allowed until DMA transfer has completed */
1169 fdctrl->msr &= ~FD_MSR_RQM;
1170 /* Now, we just have to wait for the DMA controller to
1171 * recall us...
1172 */
1173 DMA_hold_DREQ(fdctrl->dma_chann);
1174 DMA_schedule(fdctrl->dma_chann);
1175 return;
1176 } else {
1177 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1178 }
1179 }
1180 FLOPPY_DPRINTF("start non-DMA transfer\n");
1181 fdctrl->msr |= FD_MSR_NONDMA;
1182 if (direction != FD_DIR_WRITE)
1183 fdctrl->msr |= FD_MSR_DIO;
1184 /* IO based transfer: calculate len */
1185 fdctrl_raise_irq(fdctrl, 0x00);
1186
1187 return;
1188 }
1189
1190 /* Prepare a transfer of deleted data */
1191 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1192 {
1193 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1194
1195 /* We don't handle deleted data,
1196 * so we don't return *ANYTHING*
1197 */
1198 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1199 }
1200
1201 /* handlers for DMA transfers */
1202 static int fdctrl_transfer_handler (void *opaque, int nchan,
1203 int dma_pos, int dma_len)
1204 {
1205 FDCtrl *fdctrl;
1206 FDrive *cur_drv;
1207 int len, start_pos, rel_pos;
1208 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1209
1210 fdctrl = opaque;
1211 if (fdctrl->msr & FD_MSR_RQM) {
1212 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1213 return 0;
1214 }
1215 cur_drv = get_cur_drv(fdctrl);
1216 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1217 fdctrl->data_dir == FD_DIR_SCANH)
1218 status2 = FD_SR2_SNS;
1219 if (dma_len > fdctrl->data_len)
1220 dma_len = fdctrl->data_len;
1221 if (cur_drv->bs == NULL) {
1222 if (fdctrl->data_dir == FD_DIR_WRITE)
1223 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1224 else
1225 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1226 len = 0;
1227 goto transfer_error;
1228 }
1229 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1230 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1231 len = dma_len - fdctrl->data_pos;
1232 if (len + rel_pos > FD_SECTOR_LEN)
1233 len = FD_SECTOR_LEN - rel_pos;
1234 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1235 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1236 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1237 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1238 fd_sector(cur_drv) * FD_SECTOR_LEN);
1239 if (fdctrl->data_dir != FD_DIR_WRITE ||
1240 len < FD_SECTOR_LEN || rel_pos != 0) {
1241 /* READ & SCAN commands and realign to a sector for WRITE */
1242 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1243 fdctrl->fifo, 1) < 0) {
1244 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1245 fd_sector(cur_drv));
1246 /* Sure, image size is too small... */
1247 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1248 }
1249 }
1250 switch (fdctrl->data_dir) {
1251 case FD_DIR_READ:
1252 /* READ commands */
1253 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1254 fdctrl->data_pos, len);
1255 break;
1256 case FD_DIR_WRITE:
1257 /* WRITE commands */
1258 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1259 fdctrl->data_pos, len);
1260 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1261 fdctrl->fifo, 1) < 0) {
1262 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1263 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1264 goto transfer_error;
1265 }
1266 break;
1267 default:
1268 /* SCAN commands */
1269 {
1270 uint8_t tmpbuf[FD_SECTOR_LEN];
1271 int ret;
1272 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1273 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1274 if (ret == 0) {
1275 status2 = FD_SR2_SEH;
1276 goto end_transfer;
1277 }
1278 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1279 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1280 status2 = 0x00;
1281 goto end_transfer;
1282 }
1283 }
1284 break;
1285 }
1286 fdctrl->data_pos += len;
1287 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1288 if (rel_pos == 0) {
1289 /* Seek to next sector */
1290 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1291 break;
1292 }
1293 }
1294 end_transfer:
1295 len = fdctrl->data_pos - start_pos;
1296 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1297 fdctrl->data_pos, len, fdctrl->data_len);
1298 if (fdctrl->data_dir == FD_DIR_SCANE ||
1299 fdctrl->data_dir == FD_DIR_SCANL ||
1300 fdctrl->data_dir == FD_DIR_SCANH)
1301 status2 = FD_SR2_SEH;
1302 if (FD_DID_SEEK(fdctrl->data_state))
1303 status0 |= FD_SR0_SEEK;
1304 fdctrl->data_len -= len;
1305 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1306 transfer_error:
1307
1308 return len;
1309 }
1310
1311 /* Data register : 0x05 */
1312 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1313 {
1314 FDrive *cur_drv;
1315 uint32_t retval = 0;
1316 int pos;
1317
1318 cur_drv = get_cur_drv(fdctrl);
1319 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1320 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1321 FLOPPY_ERROR("controller not ready for reading\n");
1322 return 0;
1323 }
1324 pos = fdctrl->data_pos;
1325 if (fdctrl->msr & FD_MSR_NONDMA) {
1326 pos %= FD_SECTOR_LEN;
1327 if (pos == 0) {
1328 if (fdctrl->data_pos != 0)
1329 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1330 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1331 fd_sector(cur_drv));
1332 return 0;
1333 }
1334 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1335 FLOPPY_DPRINTF("error getting sector %d\n",
1336 fd_sector(cur_drv));
1337 /* Sure, image size is too small... */
1338 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1339 }
1340 }
1341 }
1342 retval = fdctrl->fifo[pos];
1343 if (++fdctrl->data_pos == fdctrl->data_len) {
1344 fdctrl->data_pos = 0;
1345 /* Switch from transfer mode to status mode
1346 * then from status mode to command mode
1347 */
1348 if (fdctrl->msr & FD_MSR_NONDMA) {
1349 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1350 } else {
1351 fdctrl_reset_fifo(fdctrl);
1352 fdctrl_reset_irq(fdctrl);
1353 }
1354 }
1355 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1356
1357 return retval;
1358 }
1359
1360 static void fdctrl_format_sector(FDCtrl *fdctrl)
1361 {
1362 FDrive *cur_drv;
1363 uint8_t kh, kt, ks;
1364
1365 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1366 cur_drv = get_cur_drv(fdctrl);
1367 kt = fdctrl->fifo[6];
1368 kh = fdctrl->fifo[7];
1369 ks = fdctrl->fifo[8];
1370 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1371 GET_CUR_DRV(fdctrl), kh, kt, ks,
1372 fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1373 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1374 case 2:
1375 /* sect too big */
1376 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1377 fdctrl->fifo[3] = kt;
1378 fdctrl->fifo[4] = kh;
1379 fdctrl->fifo[5] = ks;
1380 return;
1381 case 3:
1382 /* track too big */
1383 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1384 fdctrl->fifo[3] = kt;
1385 fdctrl->fifo[4] = kh;
1386 fdctrl->fifo[5] = ks;
1387 return;
1388 case 4:
1389 /* No seek enabled */
1390 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1391 fdctrl->fifo[3] = kt;
1392 fdctrl->fifo[4] = kh;
1393 fdctrl->fifo[5] = ks;
1394 return;
1395 case 1:
1396 fdctrl->data_state |= FD_STATE_SEEK;
1397 break;
1398 default:
1399 break;
1400 }
1401 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1402 if (cur_drv->bs == NULL ||
1403 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1404 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1405 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1406 } else {
1407 if (cur_drv->sect == cur_drv->last_sect) {
1408 fdctrl->data_state &= ~FD_STATE_FORMAT;
1409 /* Last sector done */
1410 if (FD_DID_SEEK(fdctrl->data_state))
1411 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1412 else
1413 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1414 } else {
1415 /* More to do */
1416 fdctrl->data_pos = 0;
1417 fdctrl->data_len = 4;
1418 }
1419 }
1420 }
1421
1422 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1423 {
1424 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1425 fdctrl->fifo[0] = fdctrl->lock << 4;
1426 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1427 }
1428
1429 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1430 {
1431 FDrive *cur_drv = get_cur_drv(fdctrl);
1432
1433 /* Drives position */
1434 fdctrl->fifo[0] = drv0(fdctrl)->track;
1435 fdctrl->fifo[1] = drv1(fdctrl)->track;
1436 #if MAX_FD == 4
1437 fdctrl->fifo[2] = drv2(fdctrl)->track;
1438 fdctrl->fifo[3] = drv3(fdctrl)->track;
1439 #else
1440 fdctrl->fifo[2] = 0;
1441 fdctrl->fifo[3] = 0;
1442 #endif
1443 /* timers */
1444 fdctrl->fifo[4] = fdctrl->timer0;
1445 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1446 fdctrl->fifo[6] = cur_drv->last_sect;
1447 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1448 (cur_drv->perpendicular << 2);
1449 fdctrl->fifo[8] = fdctrl->config;
1450 fdctrl->fifo[9] = fdctrl->precomp_trk;
1451 fdctrl_set_fifo(fdctrl, 10, 0);
1452 }
1453
1454 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1455 {
1456 /* Controller's version */
1457 fdctrl->fifo[0] = fdctrl->version;
1458 fdctrl_set_fifo(fdctrl, 1, 1);
1459 }
1460
1461 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1462 {
1463 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1464 fdctrl_set_fifo(fdctrl, 1, 0);
1465 }
1466
1467 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1468 {
1469 FDrive *cur_drv = get_cur_drv(fdctrl);
1470
1471 /* Drives position */
1472 drv0(fdctrl)->track = fdctrl->fifo[3];
1473 drv1(fdctrl)->track = fdctrl->fifo[4];
1474 #if MAX_FD == 4
1475 drv2(fdctrl)->track = fdctrl->fifo[5];
1476 drv3(fdctrl)->track = fdctrl->fifo[6];
1477 #endif
1478 /* timers */
1479 fdctrl->timer0 = fdctrl->fifo[7];
1480 fdctrl->timer1 = fdctrl->fifo[8];
1481 cur_drv->last_sect = fdctrl->fifo[9];
1482 fdctrl->lock = fdctrl->fifo[10] >> 7;
1483 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1484 fdctrl->config = fdctrl->fifo[11];
1485 fdctrl->precomp_trk = fdctrl->fifo[12];
1486 fdctrl->pwrd = fdctrl->fifo[13];
1487 fdctrl_reset_fifo(fdctrl);
1488 }
1489
1490 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1491 {
1492 FDrive *cur_drv = get_cur_drv(fdctrl);
1493
1494 fdctrl->fifo[0] = 0;
1495 fdctrl->fifo[1] = 0;
1496 /* Drives position */
1497 fdctrl->fifo[2] = drv0(fdctrl)->track;
1498 fdctrl->fifo[3] = drv1(fdctrl)->track;
1499 #if MAX_FD == 4
1500 fdctrl->fifo[4] = drv2(fdctrl)->track;
1501 fdctrl->fifo[5] = drv3(fdctrl)->track;
1502 #else
1503 fdctrl->fifo[4] = 0;
1504 fdctrl->fifo[5] = 0;
1505 #endif
1506 /* timers */
1507 fdctrl->fifo[6] = fdctrl->timer0;
1508 fdctrl->fifo[7] = fdctrl->timer1;
1509 fdctrl->fifo[8] = cur_drv->last_sect;
1510 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1511 (cur_drv->perpendicular << 2);
1512 fdctrl->fifo[10] = fdctrl->config;
1513 fdctrl->fifo[11] = fdctrl->precomp_trk;
1514 fdctrl->fifo[12] = fdctrl->pwrd;
1515 fdctrl->fifo[13] = 0;
1516 fdctrl->fifo[14] = 0;
1517 fdctrl_set_fifo(fdctrl, 15, 1);
1518 }
1519
1520 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1521 {
1522 FDrive *cur_drv = get_cur_drv(fdctrl);
1523
1524 /* XXX: should set main status register to busy */
1525 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1526 qemu_mod_timer(fdctrl->result_timer,
1527 qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
1528 }
1529
1530 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1531 {
1532 FDrive *cur_drv;
1533
1534 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1535 cur_drv = get_cur_drv(fdctrl);
1536 fdctrl->data_state |= FD_STATE_FORMAT;
1537 if (fdctrl->fifo[0] & 0x80)
1538 fdctrl->data_state |= FD_STATE_MULTI;
1539 else
1540 fdctrl->data_state &= ~FD_STATE_MULTI;
1541 fdctrl->data_state &= ~FD_STATE_SEEK;
1542 cur_drv->bps =
1543 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1544 #if 0
1545 cur_drv->last_sect =
1546 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1547 fdctrl->fifo[3] / 2;
1548 #else
1549 cur_drv->last_sect = fdctrl->fifo[3];
1550 #endif
1551 /* TODO: implement format using DMA expected by the Bochs BIOS
1552 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1553 * the sector with the specified fill byte
1554 */
1555 fdctrl->data_state &= ~FD_STATE_FORMAT;
1556 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1557 }
1558
1559 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1560 {
1561 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1562 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1563 if (fdctrl->fifo[2] & 1)
1564 fdctrl->dor &= ~FD_DOR_DMAEN;
1565 else
1566 fdctrl->dor |= FD_DOR_DMAEN;
1567 /* No result back */
1568 fdctrl_reset_fifo(fdctrl);
1569 }
1570
1571 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1572 {
1573 FDrive *cur_drv;
1574
1575 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1576 cur_drv = get_cur_drv(fdctrl);
1577 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1578 /* 1 Byte status back */
1579 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1580 (cur_drv->track == 0 ? 0x10 : 0x00) |
1581 (cur_drv->head << 2) |
1582 GET_CUR_DRV(fdctrl) |
1583 0x28;
1584 fdctrl_set_fifo(fdctrl, 1, 0);
1585 }
1586
1587 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1588 {
1589 FDrive *cur_drv;
1590
1591 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1592 cur_drv = get_cur_drv(fdctrl);
1593 fd_recalibrate(cur_drv);
1594 fdctrl_reset_fifo(fdctrl);
1595 /* Raise Interrupt */
1596 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1597 }
1598
1599 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1600 {
1601 FDrive *cur_drv = get_cur_drv(fdctrl);
1602
1603 if(fdctrl->reset_sensei > 0) {
1604 fdctrl->fifo[0] =
1605 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1606 fdctrl->reset_sensei--;
1607 } else {
1608 /* XXX: status0 handling is broken for read/write
1609 commands, so we do this hack. It should be suppressed
1610 ASAP */
1611 fdctrl->fifo[0] =
1612 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1613 }
1614
1615 fdctrl->fifo[1] = cur_drv->track;
1616 fdctrl_set_fifo(fdctrl, 2, 0);
1617 fdctrl_reset_irq(fdctrl);
1618 fdctrl->status0 = FD_SR0_RDYCHG;
1619 }
1620
1621 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1622 {
1623 FDrive *cur_drv;
1624
1625 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1626 cur_drv = get_cur_drv(fdctrl);
1627 fdctrl_reset_fifo(fdctrl);
1628 if (fdctrl->fifo[2] > cur_drv->max_track) {
1629 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1630 } else {
1631 cur_drv->track = fdctrl->fifo[2];
1632 /* Raise Interrupt */
1633 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1634 }
1635 }
1636
1637 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1638 {
1639 FDrive *cur_drv = get_cur_drv(fdctrl);
1640
1641 if (fdctrl->fifo[1] & 0x80)
1642 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1643 /* No result back */
1644 fdctrl_reset_fifo(fdctrl);
1645 }
1646
1647 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1648 {
1649 fdctrl->config = fdctrl->fifo[2];
1650 fdctrl->precomp_trk = fdctrl->fifo[3];
1651 /* No result back */
1652 fdctrl_reset_fifo(fdctrl);
1653 }
1654
1655 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1656 {
1657 fdctrl->pwrd = fdctrl->fifo[1];
1658 fdctrl->fifo[0] = fdctrl->fifo[1];
1659 fdctrl_set_fifo(fdctrl, 1, 1);
1660 }
1661
1662 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1663 {
1664 /* No result back */
1665 fdctrl_reset_fifo(fdctrl);
1666 }
1667
1668 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1669 {
1670 FDrive *cur_drv = get_cur_drv(fdctrl);
1671
1672 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1673 /* Command parameters done */
1674 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1675 fdctrl->fifo[0] = fdctrl->fifo[1];
1676 fdctrl->fifo[2] = 0;
1677 fdctrl->fifo[3] = 0;
1678 fdctrl_set_fifo(fdctrl, 4, 1);
1679 } else {
1680 fdctrl_reset_fifo(fdctrl);
1681 }
1682 } else if (fdctrl->data_len > 7) {
1683 /* ERROR */
1684 fdctrl->fifo[0] = 0x80 |
1685 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1686 fdctrl_set_fifo(fdctrl, 1, 1);
1687 }
1688 }
1689
1690 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1691 {
1692 FDrive *cur_drv;
1693
1694 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1695 cur_drv = get_cur_drv(fdctrl);
1696 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1697 cur_drv->track = cur_drv->max_track - 1;
1698 } else {
1699 cur_drv->track += fdctrl->fifo[2];
1700 }
1701 fdctrl_reset_fifo(fdctrl);
1702 /* Raise Interrupt */
1703 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1704 }
1705
1706 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1707 {
1708 FDrive *cur_drv;
1709
1710 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1711 cur_drv = get_cur_drv(fdctrl);
1712 if (fdctrl->fifo[2] > cur_drv->track) {
1713 cur_drv->track = 0;
1714 } else {
1715 cur_drv->track -= fdctrl->fifo[2];
1716 }
1717 fdctrl_reset_fifo(fdctrl);
1718 /* Raise Interrupt */
1719 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1720 }
1721
1722 static const struct {
1723 uint8_t value;
1724 uint8_t mask;
1725 const char* name;
1726 int parameters;
1727 void (*handler)(FDCtrl *fdctrl, int direction);
1728 int direction;
1729 } handlers[] = {
1730 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1731 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1732 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1733 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1734 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1735 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1736 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1737 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1738 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1739 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1740 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1741 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1742 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1743 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1744 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1745 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1746 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1747 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1748 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1749 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1750 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1751 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1752 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1753 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1754 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1755 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1756 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1757 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1758 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1759 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1760 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1761 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1762 };
1763 /* Associate command to an index in the 'handlers' array */
1764 static uint8_t command_to_handler[256];
1765
1766 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1767 {
1768 FDrive *cur_drv;
1769 int pos;
1770
1771 /* Reset mode */
1772 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1773 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1774 return;
1775 }
1776 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1777 FLOPPY_ERROR("controller not ready for writing\n");
1778 return;
1779 }
1780 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1781 /* Is it write command time ? */
1782 if (fdctrl->msr & FD_MSR_NONDMA) {
1783 /* FIFO data write */
1784 pos = fdctrl->data_pos++;
1785 pos %= FD_SECTOR_LEN;
1786 fdctrl->fifo[pos] = value;
1787 if (pos == FD_SECTOR_LEN - 1 ||
1788 fdctrl->data_pos == fdctrl->data_len) {
1789 cur_drv = get_cur_drv(fdctrl);
1790 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1791 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1792 return;
1793 }
1794 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1795 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1796 fd_sector(cur_drv));
1797 return;
1798 }
1799 }
1800 /* Switch from transfer mode to status mode
1801 * then from status mode to command mode
1802 */
1803 if (fdctrl->data_pos == fdctrl->data_len)
1804 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1805 return;
1806 }
1807 if (fdctrl->data_pos == 0) {
1808 /* Command */
1809 pos = command_to_handler[value & 0xff];
1810 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1811 fdctrl->data_len = handlers[pos].parameters + 1;
1812 }
1813
1814 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1815 fdctrl->fifo[fdctrl->data_pos++] = value;
1816 if (fdctrl->data_pos == fdctrl->data_len) {
1817 /* We now have all parameters
1818 * and will be able to treat the command
1819 */
1820 if (fdctrl->data_state & FD_STATE_FORMAT) {
1821 fdctrl_format_sector(fdctrl);
1822 return;
1823 }
1824
1825 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1826 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1827 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1828 }
1829 }
1830
1831 static void fdctrl_result_timer(void *opaque)
1832 {
1833 FDCtrl *fdctrl = opaque;
1834 FDrive *cur_drv = get_cur_drv(fdctrl);
1835
1836 /* Pretend we are spinning.
1837 * This is needed for Coherent, which uses READ ID to check for
1838 * sector interleaving.
1839 */
1840 if (cur_drv->last_sect != 0) {
1841 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1842 }
1843 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1844 }
1845
1846 /* Init functions */
1847 static void fdctrl_connect_drives(FDCtrl *fdctrl)
1848 {
1849 unsigned int i;
1850
1851 for (i = 0; i < MAX_FD; i++) {
1852 fd_init(&fdctrl->drives[i]);
1853 fd_revalidate(&fdctrl->drives[i]);
1854 }
1855 }
1856
1857 FDCtrl *fdctrl_init_isa(DriveInfo **fds)
1858 {
1859 ISADevice *dev;
1860
1861 dev = isa_create("isa-fdc");
1862 if (fds[0]) {
1863 qdev_prop_set_drive(&dev->qdev, "driveA", fds[0]->bdrv);
1864 }
1865 if (fds[1]) {
1866 qdev_prop_set_drive(&dev->qdev, "driveB", fds[1]->bdrv);
1867 }
1868 if (qdev_init(&dev->qdev) < 0)
1869 return NULL;
1870 return &(DO_UPCAST(FDCtrlISABus, busdev, dev)->state);
1871 }
1872
1873 FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1874 target_phys_addr_t mmio_base, DriveInfo **fds)
1875 {
1876 FDCtrl *fdctrl;
1877 DeviceState *dev;
1878 FDCtrlSysBus *sys;
1879
1880 dev = qdev_create(NULL, "sysbus-fdc");
1881 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1882 fdctrl = &sys->state;
1883 fdctrl->dma_chann = dma_chann; /* FIXME */
1884 if (fds[0]) {
1885 qdev_prop_set_drive(dev, "driveA", fds[0]->bdrv);
1886 }
1887 if (fds[1]) {
1888 qdev_prop_set_drive(dev, "driveB", fds[1]->bdrv);
1889 }
1890 qdev_init_nofail(dev);
1891 sysbus_connect_irq(&sys->busdev, 0, irq);
1892 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1893
1894 return fdctrl;
1895 }
1896
1897 FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1898 DriveInfo **fds, qemu_irq *fdc_tc)
1899 {
1900 DeviceState *dev;
1901 FDCtrlSysBus *sys;
1902 FDCtrl *fdctrl;
1903
1904 dev = qdev_create(NULL, "SUNW,fdtwo");
1905 if (fds[0]) {
1906 qdev_prop_set_drive(dev, "drive", fds[0]->bdrv);
1907 }
1908 qdev_init_nofail(dev);
1909 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1910 fdctrl = &sys->state;
1911 sysbus_connect_irq(&sys->busdev, 0, irq);
1912 sysbus_mmio_map(&sys->busdev, 0, io_base);
1913 *fdc_tc = qdev_get_gpio_in(dev, 0);
1914
1915 return fdctrl;
1916 }
1917
1918 static int fdctrl_init_common(FDCtrl *fdctrl)
1919 {
1920 int i, j;
1921 static int command_tables_inited = 0;
1922
1923 /* Fill 'command_to_handler' lookup table */
1924 if (!command_tables_inited) {
1925 command_tables_inited = 1;
1926 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1927 for (j = 0; j < sizeof(command_to_handler); j++) {
1928 if ((j & handlers[i].mask) == handlers[i].value) {
1929 command_to_handler[j] = i;
1930 }
1931 }
1932 }
1933 }
1934
1935 FLOPPY_DPRINTF("init controller\n");
1936 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1937 fdctrl->fifo_size = 512;
1938 fdctrl->result_timer = qemu_new_timer(vm_clock,
1939 fdctrl_result_timer, fdctrl);
1940
1941 fdctrl->version = 0x90; /* Intel 82078 controller */
1942 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1943 fdctrl->num_floppies = MAX_FD;
1944
1945 if (fdctrl->dma_chann != -1)
1946 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1947 fdctrl_connect_drives(fdctrl);
1948
1949 return 0;
1950 }
1951
1952 static int isabus_fdc_init1(ISADevice *dev)
1953 {
1954 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1955 FDCtrl *fdctrl = &isa->state;
1956 int iobase = 0x3f0;
1957 int isairq = 6;
1958 int dma_chann = 2;
1959 int ret;
1960
1961 register_ioport_read(iobase + 0x01, 5, 1,
1962 &fdctrl_read_port, fdctrl);
1963 register_ioport_read(iobase + 0x07, 1, 1,
1964 &fdctrl_read_port, fdctrl);
1965 register_ioport_write(iobase + 0x01, 5, 1,
1966 &fdctrl_write_port, fdctrl);
1967 register_ioport_write(iobase + 0x07, 1, 1,
1968 &fdctrl_write_port, fdctrl);
1969 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1970 fdctrl->dma_chann = dma_chann;
1971
1972 qdev_set_legacy_instance_id(&dev->qdev, iobase, 2);
1973 ret = fdctrl_init_common(fdctrl);
1974
1975 return ret;
1976 }
1977
1978 static int sysbus_fdc_init1(SysBusDevice *dev)
1979 {
1980 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
1981 FDCtrl *fdctrl = &sys->state;
1982 int io;
1983 int ret;
1984
1985 io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
1986 sysbus_init_mmio(dev, 0x08, io);
1987 sysbus_init_irq(dev, &fdctrl->irq);
1988 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1989 fdctrl->dma_chann = -1;
1990
1991 qdev_set_legacy_instance_id(&dev->qdev, io, 2);
1992 ret = fdctrl_init_common(fdctrl);
1993
1994 return ret;
1995 }
1996
1997 static int sun4m_fdc_init1(SysBusDevice *dev)
1998 {
1999 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2000 int io;
2001
2002 io = cpu_register_io_memory(fdctrl_mem_read_strict,
2003 fdctrl_mem_write_strict, fdctrl);
2004 sysbus_init_mmio(dev, 0x08, io);
2005 sysbus_init_irq(dev, &fdctrl->irq);
2006 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2007
2008 fdctrl->sun4m = 1;
2009 qdev_set_legacy_instance_id(&dev->qdev, io, 2);
2010 return fdctrl_init_common(fdctrl);
2011 }
2012
2013 static const VMStateDescription vmstate_isa_fdc ={
2014 .name = "fdc",
2015 .version_id = 2,
2016 .minimum_version_id = 2,
2017 .fields = (VMStateField []) {
2018 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2019 VMSTATE_END_OF_LIST()
2020 }
2021 };
2022
2023 static ISADeviceInfo isa_fdc_info = {
2024 .init = isabus_fdc_init1,
2025 .qdev.name = "isa-fdc",
2026 .qdev.size = sizeof(FDCtrlISABus),
2027 .qdev.no_user = 1,
2028 .qdev.vmsd = &vmstate_isa_fdc,
2029 .qdev.reset = fdctrl_external_reset_isa,
2030 .qdev.props = (Property[]) {
2031 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2032 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2033 DEFINE_PROP_END_OF_LIST(),
2034 },
2035 };
2036
2037 static const VMStateDescription vmstate_sysbus_fdc ={
2038 .name = "fdc",
2039 .version_id = 2,
2040 .minimum_version_id = 2,
2041 .fields = (VMStateField []) {
2042 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2043 VMSTATE_END_OF_LIST()
2044 }
2045 };
2046
2047 static SysBusDeviceInfo sysbus_fdc_info = {
2048 .init = sysbus_fdc_init1,
2049 .qdev.name = "sysbus-fdc",
2050 .qdev.size = sizeof(FDCtrlSysBus),
2051 .qdev.vmsd = &vmstate_sysbus_fdc,
2052 .qdev.reset = fdctrl_external_reset_sysbus,
2053 .qdev.props = (Property[]) {
2054 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2055 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2056 DEFINE_PROP_END_OF_LIST(),
2057 },
2058 };
2059
2060 static SysBusDeviceInfo sun4m_fdc_info = {
2061 .init = sun4m_fdc_init1,
2062 .qdev.name = "SUNW,fdtwo",
2063 .qdev.size = sizeof(FDCtrlSysBus),
2064 .qdev.vmsd = &vmstate_sysbus_fdc,
2065 .qdev.reset = fdctrl_external_reset_sysbus,
2066 .qdev.props = (Property[]) {
2067 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2068 DEFINE_PROP_END_OF_LIST(),
2069 },
2070 };
2071
2072 static void fdc_register_devices(void)
2073 {
2074 isa_qdev_register(&isa_fdc_info);
2075 sysbus_register_withprop(&sysbus_fdc_info);
2076 sysbus_register_withprop(&sun4m_fdc_info);
2077 }
2078
2079 device_init(fdc_register_devices)
Qemu copy for testing