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block: add a transfer rate for floppy types
[qemu.git] / hw / fdc.c
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37 #include "blockdev.h"
38 #include "sysemu.h"
39
40 /********************************************************/
41 /* debug Floppy devices */
42 //#define DEBUG_FLOPPY
43
44 #ifdef DEBUG_FLOPPY
45 #define FLOPPY_DPRINTF(fmt, ...) \
46 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
47 #else
48 #define FLOPPY_DPRINTF(fmt, ...)
49 #endif
50
51 #define FLOPPY_ERROR(fmt, ...) \
52 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
53
54 /********************************************************/
55 /* Floppy drive emulation */
56
57 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
58 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
59
60 /* Will always be a fixed parameter for us */
61 #define FD_SECTOR_LEN 512
62 #define FD_SECTOR_SC 2 /* Sector size code */
63 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
64
65 /* Floppy disk drive emulation */
66 typedef enum FDiskFlags {
67 FDISK_DBL_SIDES = 0x01,
68 } FDiskFlags;
69
70 typedef struct FDrive {
71 BlockDriverState *bs;
72 /* Drive status */
73 FDriveType drive;
74 uint8_t perpendicular; /* 2.88 MB access mode */
75 /* Position */
76 uint8_t head;
77 uint8_t track;
78 uint8_t sect;
79 /* Media */
80 FDiskFlags flags;
81 uint8_t last_sect; /* Nb sector per track */
82 uint8_t max_track; /* Nb of tracks */
83 uint16_t bps; /* Bytes per sector */
84 uint8_t ro; /* Is read-only */
85 uint8_t media_changed; /* Is media changed */
86 } FDrive;
87
88 static void fd_init(FDrive *drv)
89 {
90 /* Drive */
91 drv->drive = FDRIVE_DRV_NONE;
92 drv->perpendicular = 0;
93 /* Disk */
94 drv->last_sect = 0;
95 drv->max_track = 0;
96 }
97
98 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
99
100 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
101 uint8_t last_sect, uint8_t num_sides)
102 {
103 return (((track * num_sides) + head) * last_sect) + sect - 1;
104 }
105
106 /* Returns current position, in sectors, for given drive */
107 static int fd_sector(FDrive *drv)
108 {
109 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
110 NUM_SIDES(drv));
111 }
112
113 /* Seek to a new position:
114 * returns 0 if already on right track
115 * returns 1 if track changed
116 * returns 2 if track is invalid
117 * returns 3 if sector is invalid
118 * returns 4 if seek is disabled
119 */
120 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
121 int enable_seek)
122 {
123 uint32_t sector;
124 int ret;
125
126 if (track > drv->max_track ||
127 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
128 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
129 head, track, sect, 1,
130 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
131 drv->max_track, drv->last_sect);
132 return 2;
133 }
134 if (sect > drv->last_sect) {
135 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
136 head, track, sect, 1,
137 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
138 drv->max_track, drv->last_sect);
139 return 3;
140 }
141 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
142 ret = 0;
143 if (sector != fd_sector(drv)) {
144 #if 0
145 if (!enable_seek) {
146 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
147 head, track, sect, 1, drv->max_track, drv->last_sect);
148 return 4;
149 }
150 #endif
151 drv->head = head;
152 if (drv->track != track)
153 ret = 1;
154 drv->track = track;
155 drv->sect = sect;
156 }
157
158 return ret;
159 }
160
161 /* Set drive back to track 0 */
162 static void fd_recalibrate(FDrive *drv)
163 {
164 FLOPPY_DPRINTF("recalibrate\n");
165 drv->head = 0;
166 drv->track = 0;
167 drv->sect = 1;
168 }
169
170 /* Revalidate a disk drive after a disk change */
171 static void fd_revalidate(FDrive *drv)
172 {
173 int nb_heads, max_track, last_sect, ro;
174 FDriveType drive;
175 FDriveRate rate;
176
177 FLOPPY_DPRINTF("revalidate\n");
178 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
179 ro = bdrv_is_read_only(drv->bs);
180 bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,
181 &last_sect, drv->drive, &drive, &rate);
182 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
183 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
184 nb_heads - 1, max_track, last_sect);
185 } else {
186 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
187 max_track, last_sect, ro ? "ro" : "rw");
188 }
189 if (nb_heads == 1) {
190 drv->flags &= ~FDISK_DBL_SIDES;
191 } else {
192 drv->flags |= FDISK_DBL_SIDES;
193 }
194 drv->max_track = max_track;
195 drv->last_sect = last_sect;
196 drv->ro = ro;
197 drv->drive = drive;
198 } else {
199 FLOPPY_DPRINTF("No disk in drive\n");
200 drv->last_sect = 0;
201 drv->max_track = 0;
202 drv->flags &= ~FDISK_DBL_SIDES;
203 }
204 }
205
206 /********************************************************/
207 /* Intel 82078 floppy disk controller emulation */
208
209 typedef struct FDCtrl FDCtrl;
210
211 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
212 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
213 static int fdctrl_transfer_handler (void *opaque, int nchan,
214 int dma_pos, int dma_len);
215 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
216
217 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
218 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
219 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
220 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
221 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
222 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
223 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
224 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
225 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
226 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
227 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
228 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
229
230 enum {
231 FD_DIR_WRITE = 0,
232 FD_DIR_READ = 1,
233 FD_DIR_SCANE = 2,
234 FD_DIR_SCANL = 3,
235 FD_DIR_SCANH = 4,
236 };
237
238 enum {
239 FD_STATE_MULTI = 0x01, /* multi track flag */
240 FD_STATE_FORMAT = 0x02, /* format flag */
241 FD_STATE_SEEK = 0x04, /* seek flag */
242 };
243
244 enum {
245 FD_REG_SRA = 0x00,
246 FD_REG_SRB = 0x01,
247 FD_REG_DOR = 0x02,
248 FD_REG_TDR = 0x03,
249 FD_REG_MSR = 0x04,
250 FD_REG_DSR = 0x04,
251 FD_REG_FIFO = 0x05,
252 FD_REG_DIR = 0x07,
253 FD_REG_CCR = 0x07,
254 };
255
256 enum {
257 FD_CMD_READ_TRACK = 0x02,
258 FD_CMD_SPECIFY = 0x03,
259 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
260 FD_CMD_WRITE = 0x05,
261 FD_CMD_READ = 0x06,
262 FD_CMD_RECALIBRATE = 0x07,
263 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
264 FD_CMD_WRITE_DELETED = 0x09,
265 FD_CMD_READ_ID = 0x0a,
266 FD_CMD_READ_DELETED = 0x0c,
267 FD_CMD_FORMAT_TRACK = 0x0d,
268 FD_CMD_DUMPREG = 0x0e,
269 FD_CMD_SEEK = 0x0f,
270 FD_CMD_VERSION = 0x10,
271 FD_CMD_SCAN_EQUAL = 0x11,
272 FD_CMD_PERPENDICULAR_MODE = 0x12,
273 FD_CMD_CONFIGURE = 0x13,
274 FD_CMD_LOCK = 0x14,
275 FD_CMD_VERIFY = 0x16,
276 FD_CMD_POWERDOWN_MODE = 0x17,
277 FD_CMD_PART_ID = 0x18,
278 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
279 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
280 FD_CMD_SAVE = 0x2e,
281 FD_CMD_OPTION = 0x33,
282 FD_CMD_RESTORE = 0x4e,
283 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
284 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
285 FD_CMD_FORMAT_AND_WRITE = 0xcd,
286 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
287 };
288
289 enum {
290 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
291 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
292 FD_CONFIG_POLL = 0x10, /* Poll enabled */
293 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
294 FD_CONFIG_EIS = 0x40, /* No implied seeks */
295 };
296
297 enum {
298 FD_SR0_EQPMT = 0x10,
299 FD_SR0_SEEK = 0x20,
300 FD_SR0_ABNTERM = 0x40,
301 FD_SR0_INVCMD = 0x80,
302 FD_SR0_RDYCHG = 0xc0,
303 };
304
305 enum {
306 FD_SR1_NW = 0x02, /* Not writable */
307 FD_SR1_EC = 0x80, /* End of cylinder */
308 };
309
310 enum {
311 FD_SR2_SNS = 0x04, /* Scan not satisfied */
312 FD_SR2_SEH = 0x08, /* Scan equal hit */
313 };
314
315 enum {
316 FD_SRA_DIR = 0x01,
317 FD_SRA_nWP = 0x02,
318 FD_SRA_nINDX = 0x04,
319 FD_SRA_HDSEL = 0x08,
320 FD_SRA_nTRK0 = 0x10,
321 FD_SRA_STEP = 0x20,
322 FD_SRA_nDRV2 = 0x40,
323 FD_SRA_INTPEND = 0x80,
324 };
325
326 enum {
327 FD_SRB_MTR0 = 0x01,
328 FD_SRB_MTR1 = 0x02,
329 FD_SRB_WGATE = 0x04,
330 FD_SRB_RDATA = 0x08,
331 FD_SRB_WDATA = 0x10,
332 FD_SRB_DR0 = 0x20,
333 };
334
335 enum {
336 #if MAX_FD == 4
337 FD_DOR_SELMASK = 0x03,
338 #else
339 FD_DOR_SELMASK = 0x01,
340 #endif
341 FD_DOR_nRESET = 0x04,
342 FD_DOR_DMAEN = 0x08,
343 FD_DOR_MOTEN0 = 0x10,
344 FD_DOR_MOTEN1 = 0x20,
345 FD_DOR_MOTEN2 = 0x40,
346 FD_DOR_MOTEN3 = 0x80,
347 };
348
349 enum {
350 #if MAX_FD == 4
351 FD_TDR_BOOTSEL = 0x0c,
352 #else
353 FD_TDR_BOOTSEL = 0x04,
354 #endif
355 };
356
357 enum {
358 FD_DSR_DRATEMASK= 0x03,
359 FD_DSR_PWRDOWN = 0x40,
360 FD_DSR_SWRESET = 0x80,
361 };
362
363 enum {
364 FD_MSR_DRV0BUSY = 0x01,
365 FD_MSR_DRV1BUSY = 0x02,
366 FD_MSR_DRV2BUSY = 0x04,
367 FD_MSR_DRV3BUSY = 0x08,
368 FD_MSR_CMDBUSY = 0x10,
369 FD_MSR_NONDMA = 0x20,
370 FD_MSR_DIO = 0x40,
371 FD_MSR_RQM = 0x80,
372 };
373
374 enum {
375 FD_DIR_DSKCHG = 0x80,
376 };
377
378 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
379 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
380 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
381
382 struct FDCtrl {
383 MemoryRegion iomem;
384 qemu_irq irq;
385 /* Controller state */
386 QEMUTimer *result_timer;
387 int dma_chann;
388 /* Controller's identification */
389 uint8_t version;
390 /* HW */
391 uint8_t sra;
392 uint8_t srb;
393 uint8_t dor;
394 uint8_t dor_vmstate; /* only used as temp during vmstate */
395 uint8_t tdr;
396 uint8_t dsr;
397 uint8_t msr;
398 uint8_t cur_drv;
399 uint8_t status0;
400 uint8_t status1;
401 uint8_t status2;
402 /* Command FIFO */
403 uint8_t *fifo;
404 int32_t fifo_size;
405 uint32_t data_pos;
406 uint32_t data_len;
407 uint8_t data_state;
408 uint8_t data_dir;
409 uint8_t eot; /* last wanted sector */
410 /* States kept only to be returned back */
411 /* precompensation */
412 uint8_t precomp_trk;
413 uint8_t config;
414 uint8_t lock;
415 /* Power down config (also with status regB access mode */
416 uint8_t pwrd;
417 /* Floppy drives */
418 uint8_t num_floppies;
419 /* Sun4m quirks? */
420 int sun4m;
421 FDrive drives[MAX_FD];
422 int reset_sensei;
423 /* Timers state */
424 uint8_t timer0;
425 uint8_t timer1;
426 };
427
428 typedef struct FDCtrlSysBus {
429 SysBusDevice busdev;
430 struct FDCtrl state;
431 } FDCtrlSysBus;
432
433 typedef struct FDCtrlISABus {
434 ISADevice busdev;
435 struct FDCtrl state;
436 int32_t bootindexA;
437 int32_t bootindexB;
438 } FDCtrlISABus;
439
440 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
441 {
442 FDCtrl *fdctrl = opaque;
443 uint32_t retval;
444
445 reg &= 7;
446 switch (reg) {
447 case FD_REG_SRA:
448 retval = fdctrl_read_statusA(fdctrl);
449 break;
450 case FD_REG_SRB:
451 retval = fdctrl_read_statusB(fdctrl);
452 break;
453 case FD_REG_DOR:
454 retval = fdctrl_read_dor(fdctrl);
455 break;
456 case FD_REG_TDR:
457 retval = fdctrl_read_tape(fdctrl);
458 break;
459 case FD_REG_MSR:
460 retval = fdctrl_read_main_status(fdctrl);
461 break;
462 case FD_REG_FIFO:
463 retval = fdctrl_read_data(fdctrl);
464 break;
465 case FD_REG_DIR:
466 retval = fdctrl_read_dir(fdctrl);
467 break;
468 default:
469 retval = (uint32_t)(-1);
470 break;
471 }
472 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
473
474 return retval;
475 }
476
477 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
478 {
479 FDCtrl *fdctrl = opaque;
480
481 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
482
483 reg &= 7;
484 switch (reg) {
485 case FD_REG_DOR:
486 fdctrl_write_dor(fdctrl, value);
487 break;
488 case FD_REG_TDR:
489 fdctrl_write_tape(fdctrl, value);
490 break;
491 case FD_REG_DSR:
492 fdctrl_write_rate(fdctrl, value);
493 break;
494 case FD_REG_FIFO:
495 fdctrl_write_data(fdctrl, value);
496 break;
497 case FD_REG_CCR:
498 fdctrl_write_ccr(fdctrl, value);
499 break;
500 default:
501 break;
502 }
503 }
504
505 static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
506 unsigned ize)
507 {
508 return fdctrl_read(opaque, (uint32_t)reg);
509 }
510
511 static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
512 uint64_t value, unsigned size)
513 {
514 fdctrl_write(opaque, (uint32_t)reg, value);
515 }
516
517 static const MemoryRegionOps fdctrl_mem_ops = {
518 .read = fdctrl_read_mem,
519 .write = fdctrl_write_mem,
520 .endianness = DEVICE_NATIVE_ENDIAN,
521 };
522
523 static const MemoryRegionOps fdctrl_mem_strict_ops = {
524 .read = fdctrl_read_mem,
525 .write = fdctrl_write_mem,
526 .endianness = DEVICE_NATIVE_ENDIAN,
527 .valid = {
528 .min_access_size = 1,
529 .max_access_size = 1,
530 },
531 };
532
533 static bool fdrive_media_changed_needed(void *opaque)
534 {
535 FDrive *drive = opaque;
536
537 return (drive->bs != NULL && drive->media_changed != 1);
538 }
539
540 static const VMStateDescription vmstate_fdrive_media_changed = {
541 .name = "fdrive/media_changed",
542 .version_id = 1,
543 .minimum_version_id = 1,
544 .minimum_version_id_old = 1,
545 .fields = (VMStateField[]) {
546 VMSTATE_UINT8(media_changed, FDrive),
547 VMSTATE_END_OF_LIST()
548 }
549 };
550
551 static const VMStateDescription vmstate_fdrive = {
552 .name = "fdrive",
553 .version_id = 1,
554 .minimum_version_id = 1,
555 .minimum_version_id_old = 1,
556 .fields = (VMStateField[]) {
557 VMSTATE_UINT8(head, FDrive),
558 VMSTATE_UINT8(track, FDrive),
559 VMSTATE_UINT8(sect, FDrive),
560 VMSTATE_END_OF_LIST()
561 },
562 .subsections = (VMStateSubsection[]) {
563 {
564 .vmsd = &vmstate_fdrive_media_changed,
565 .needed = &fdrive_media_changed_needed,
566 } , {
567 /* empty */
568 }
569 }
570 };
571
572 static void fdc_pre_save(void *opaque)
573 {
574 FDCtrl *s = opaque;
575
576 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
577 }
578
579 static int fdc_post_load(void *opaque, int version_id)
580 {
581 FDCtrl *s = opaque;
582
583 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
584 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
585 return 0;
586 }
587
588 static const VMStateDescription vmstate_fdc = {
589 .name = "fdc",
590 .version_id = 2,
591 .minimum_version_id = 2,
592 .minimum_version_id_old = 2,
593 .pre_save = fdc_pre_save,
594 .post_load = fdc_post_load,
595 .fields = (VMStateField []) {
596 /* Controller State */
597 VMSTATE_UINT8(sra, FDCtrl),
598 VMSTATE_UINT8(srb, FDCtrl),
599 VMSTATE_UINT8(dor_vmstate, FDCtrl),
600 VMSTATE_UINT8(tdr, FDCtrl),
601 VMSTATE_UINT8(dsr, FDCtrl),
602 VMSTATE_UINT8(msr, FDCtrl),
603 VMSTATE_UINT8(status0, FDCtrl),
604 VMSTATE_UINT8(status1, FDCtrl),
605 VMSTATE_UINT8(status2, FDCtrl),
606 /* Command FIFO */
607 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
608 uint8_t),
609 VMSTATE_UINT32(data_pos, FDCtrl),
610 VMSTATE_UINT32(data_len, FDCtrl),
611 VMSTATE_UINT8(data_state, FDCtrl),
612 VMSTATE_UINT8(data_dir, FDCtrl),
613 VMSTATE_UINT8(eot, FDCtrl),
614 /* States kept only to be returned back */
615 VMSTATE_UINT8(timer0, FDCtrl),
616 VMSTATE_UINT8(timer1, FDCtrl),
617 VMSTATE_UINT8(precomp_trk, FDCtrl),
618 VMSTATE_UINT8(config, FDCtrl),
619 VMSTATE_UINT8(lock, FDCtrl),
620 VMSTATE_UINT8(pwrd, FDCtrl),
621 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
622 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
623 vmstate_fdrive, FDrive),
624 VMSTATE_END_OF_LIST()
625 }
626 };
627
628 static void fdctrl_external_reset_sysbus(DeviceState *d)
629 {
630 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
631 FDCtrl *s = &sys->state;
632
633 fdctrl_reset(s, 0);
634 }
635
636 static void fdctrl_external_reset_isa(DeviceState *d)
637 {
638 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
639 FDCtrl *s = &isa->state;
640
641 fdctrl_reset(s, 0);
642 }
643
644 static void fdctrl_handle_tc(void *opaque, int irq, int level)
645 {
646 //FDCtrl *s = opaque;
647
648 if (level) {
649 // XXX
650 FLOPPY_DPRINTF("TC pulsed\n");
651 }
652 }
653
654 /* Change IRQ state */
655 static void fdctrl_reset_irq(FDCtrl *fdctrl)
656 {
657 if (!(fdctrl->sra & FD_SRA_INTPEND))
658 return;
659 FLOPPY_DPRINTF("Reset interrupt\n");
660 qemu_set_irq(fdctrl->irq, 0);
661 fdctrl->sra &= ~FD_SRA_INTPEND;
662 }
663
664 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
665 {
666 /* Sparc mutation */
667 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
668 /* XXX: not sure */
669 fdctrl->msr &= ~FD_MSR_CMDBUSY;
670 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
671 fdctrl->status0 = status0;
672 return;
673 }
674 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
675 qemu_set_irq(fdctrl->irq, 1);
676 fdctrl->sra |= FD_SRA_INTPEND;
677 }
678 fdctrl->reset_sensei = 0;
679 fdctrl->status0 = status0;
680 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
681 }
682
683 /* Reset controller */
684 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
685 {
686 int i;
687
688 FLOPPY_DPRINTF("reset controller\n");
689 fdctrl_reset_irq(fdctrl);
690 /* Initialise controller */
691 fdctrl->sra = 0;
692 fdctrl->srb = 0xc0;
693 if (!fdctrl->drives[1].bs)
694 fdctrl->sra |= FD_SRA_nDRV2;
695 fdctrl->cur_drv = 0;
696 fdctrl->dor = FD_DOR_nRESET;
697 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
698 fdctrl->msr = FD_MSR_RQM;
699 /* FIFO state */
700 fdctrl->data_pos = 0;
701 fdctrl->data_len = 0;
702 fdctrl->data_state = 0;
703 fdctrl->data_dir = FD_DIR_WRITE;
704 for (i = 0; i < MAX_FD; i++)
705 fd_recalibrate(&fdctrl->drives[i]);
706 fdctrl_reset_fifo(fdctrl);
707 if (do_irq) {
708 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
709 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
710 }
711 }
712
713 static inline FDrive *drv0(FDCtrl *fdctrl)
714 {
715 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
716 }
717
718 static inline FDrive *drv1(FDCtrl *fdctrl)
719 {
720 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
721 return &fdctrl->drives[1];
722 else
723 return &fdctrl->drives[0];
724 }
725
726 #if MAX_FD == 4
727 static inline FDrive *drv2(FDCtrl *fdctrl)
728 {
729 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
730 return &fdctrl->drives[2];
731 else
732 return &fdctrl->drives[1];
733 }
734
735 static inline FDrive *drv3(FDCtrl *fdctrl)
736 {
737 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
738 return &fdctrl->drives[3];
739 else
740 return &fdctrl->drives[2];
741 }
742 #endif
743
744 static FDrive *get_cur_drv(FDCtrl *fdctrl)
745 {
746 switch (fdctrl->cur_drv) {
747 case 0: return drv0(fdctrl);
748 case 1: return drv1(fdctrl);
749 #if MAX_FD == 4
750 case 2: return drv2(fdctrl);
751 case 3: return drv3(fdctrl);
752 #endif
753 default: return NULL;
754 }
755 }
756
757 /* Status A register : 0x00 (read-only) */
758 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
759 {
760 uint32_t retval = fdctrl->sra;
761
762 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
763
764 return retval;
765 }
766
767 /* Status B register : 0x01 (read-only) */
768 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
769 {
770 uint32_t retval = fdctrl->srb;
771
772 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
773
774 return retval;
775 }
776
777 /* Digital output register : 0x02 */
778 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
779 {
780 uint32_t retval = fdctrl->dor;
781
782 /* Selected drive */
783 retval |= fdctrl->cur_drv;
784 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
785
786 return retval;
787 }
788
789 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
790 {
791 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
792
793 /* Motors */
794 if (value & FD_DOR_MOTEN0)
795 fdctrl->srb |= FD_SRB_MTR0;
796 else
797 fdctrl->srb &= ~FD_SRB_MTR0;
798 if (value & FD_DOR_MOTEN1)
799 fdctrl->srb |= FD_SRB_MTR1;
800 else
801 fdctrl->srb &= ~FD_SRB_MTR1;
802
803 /* Drive */
804 if (value & 1)
805 fdctrl->srb |= FD_SRB_DR0;
806 else
807 fdctrl->srb &= ~FD_SRB_DR0;
808
809 /* Reset */
810 if (!(value & FD_DOR_nRESET)) {
811 if (fdctrl->dor & FD_DOR_nRESET) {
812 FLOPPY_DPRINTF("controller enter RESET state\n");
813 }
814 } else {
815 if (!(fdctrl->dor & FD_DOR_nRESET)) {
816 FLOPPY_DPRINTF("controller out of RESET state\n");
817 fdctrl_reset(fdctrl, 1);
818 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
819 }
820 }
821 /* Selected drive */
822 fdctrl->cur_drv = value & FD_DOR_SELMASK;
823
824 fdctrl->dor = value;
825 }
826
827 /* Tape drive register : 0x03 */
828 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
829 {
830 uint32_t retval = fdctrl->tdr;
831
832 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
833
834 return retval;
835 }
836
837 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
838 {
839 /* Reset mode */
840 if (!(fdctrl->dor & FD_DOR_nRESET)) {
841 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
842 return;
843 }
844 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
845 /* Disk boot selection indicator */
846 fdctrl->tdr = value & FD_TDR_BOOTSEL;
847 /* Tape indicators: never allow */
848 }
849
850 /* Main status register : 0x04 (read) */
851 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
852 {
853 uint32_t retval = fdctrl->msr;
854
855 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
856 fdctrl->dor |= FD_DOR_nRESET;
857
858 /* Sparc mutation */
859 if (fdctrl->sun4m) {
860 retval |= FD_MSR_DIO;
861 fdctrl_reset_irq(fdctrl);
862 };
863
864 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
865
866 return retval;
867 }
868
869 /* Data select rate register : 0x04 (write) */
870 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
871 {
872 /* Reset mode */
873 if (!(fdctrl->dor & FD_DOR_nRESET)) {
874 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
875 return;
876 }
877 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
878 /* Reset: autoclear */
879 if (value & FD_DSR_SWRESET) {
880 fdctrl->dor &= ~FD_DOR_nRESET;
881 fdctrl_reset(fdctrl, 1);
882 fdctrl->dor |= FD_DOR_nRESET;
883 }
884 if (value & FD_DSR_PWRDOWN) {
885 fdctrl_reset(fdctrl, 1);
886 }
887 fdctrl->dsr = value;
888 }
889
890 /* Configuration control register: 0x07 (write) */
891 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
892 {
893 /* Reset mode */
894 if (!(fdctrl->dor & FD_DOR_nRESET)) {
895 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
896 return;
897 }
898 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
899
900 /* Only the rate selection bits used in AT mode, and we
901 * store those in the DSR.
902 */
903 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
904 (value & FD_DSR_DRATEMASK);
905 }
906
907 static int fdctrl_media_changed(FDrive *drv)
908 {
909 int ret;
910
911 if (!drv->bs)
912 return 0;
913 if (drv->media_changed) {
914 drv->media_changed = 0;
915 ret = 1;
916 } else {
917 ret = bdrv_media_changed(drv->bs);
918 if (ret < 0) {
919 ret = 0; /* we don't know, assume no */
920 }
921 }
922 if (ret) {
923 fd_revalidate(drv);
924 }
925 return ret;
926 }
927
928 /* Digital input register : 0x07 (read-only) */
929 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
930 {
931 uint32_t retval = 0;
932
933 if (fdctrl_media_changed(drv0(fdctrl))
934 || fdctrl_media_changed(drv1(fdctrl))
935 #if MAX_FD == 4
936 || fdctrl_media_changed(drv2(fdctrl))
937 || fdctrl_media_changed(drv3(fdctrl))
938 #endif
939 )
940 retval |= FD_DIR_DSKCHG;
941 if (retval != 0) {
942 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
943 }
944
945 return retval;
946 }
947
948 /* FIFO state control */
949 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
950 {
951 fdctrl->data_dir = FD_DIR_WRITE;
952 fdctrl->data_pos = 0;
953 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
954 }
955
956 /* Set FIFO status for the host to read */
957 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
958 {
959 fdctrl->data_dir = FD_DIR_READ;
960 fdctrl->data_len = fifo_len;
961 fdctrl->data_pos = 0;
962 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
963 if (do_irq)
964 fdctrl_raise_irq(fdctrl, 0x00);
965 }
966
967 /* Set an error: unimplemented/unknown command */
968 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
969 {
970 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
971 fdctrl->fifo[0] = FD_SR0_INVCMD;
972 fdctrl_set_fifo(fdctrl, 1, 0);
973 }
974
975 /* Seek to next sector */
976 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
977 {
978 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
979 cur_drv->head, cur_drv->track, cur_drv->sect,
980 fd_sector(cur_drv));
981 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
982 error in fact */
983 if (cur_drv->sect >= cur_drv->last_sect ||
984 cur_drv->sect == fdctrl->eot) {
985 cur_drv->sect = 1;
986 if (FD_MULTI_TRACK(fdctrl->data_state)) {
987 if (cur_drv->head == 0 &&
988 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
989 cur_drv->head = 1;
990 } else {
991 cur_drv->head = 0;
992 cur_drv->track++;
993 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
994 return 0;
995 }
996 } else {
997 cur_drv->track++;
998 return 0;
999 }
1000 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1001 cur_drv->head, cur_drv->track,
1002 cur_drv->sect, fd_sector(cur_drv));
1003 } else {
1004 cur_drv->sect++;
1005 }
1006 return 1;
1007 }
1008
1009 /* Callback for transfer end (stop or abort) */
1010 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1011 uint8_t status1, uint8_t status2)
1012 {
1013 FDrive *cur_drv;
1014
1015 cur_drv = get_cur_drv(fdctrl);
1016 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1017 status0, status1, status2,
1018 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1019 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1020 fdctrl->fifo[1] = status1;
1021 fdctrl->fifo[2] = status2;
1022 fdctrl->fifo[3] = cur_drv->track;
1023 fdctrl->fifo[4] = cur_drv->head;
1024 fdctrl->fifo[5] = cur_drv->sect;
1025 fdctrl->fifo[6] = FD_SECTOR_SC;
1026 fdctrl->data_dir = FD_DIR_READ;
1027 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1028 DMA_release_DREQ(fdctrl->dma_chann);
1029 }
1030 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1031 fdctrl->msr &= ~FD_MSR_NONDMA;
1032 fdctrl_set_fifo(fdctrl, 7, 1);
1033 }
1034
1035 /* Prepare a data transfer (either DMA or FIFO) */
1036 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1037 {
1038 FDrive *cur_drv;
1039 uint8_t kh, kt, ks;
1040 int did_seek = 0;
1041
1042 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1043 cur_drv = get_cur_drv(fdctrl);
1044 kt = fdctrl->fifo[2];
1045 kh = fdctrl->fifo[3];
1046 ks = fdctrl->fifo[4];
1047 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1048 GET_CUR_DRV(fdctrl), kh, kt, ks,
1049 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1050 NUM_SIDES(cur_drv)));
1051 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1052 case 2:
1053 /* sect too big */
1054 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1055 fdctrl->fifo[3] = kt;
1056 fdctrl->fifo[4] = kh;
1057 fdctrl->fifo[5] = ks;
1058 return;
1059 case 3:
1060 /* track too big */
1061 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1062 fdctrl->fifo[3] = kt;
1063 fdctrl->fifo[4] = kh;
1064 fdctrl->fifo[5] = ks;
1065 return;
1066 case 4:
1067 /* No seek enabled */
1068 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1069 fdctrl->fifo[3] = kt;
1070 fdctrl->fifo[4] = kh;
1071 fdctrl->fifo[5] = ks;
1072 return;
1073 case 1:
1074 did_seek = 1;
1075 break;
1076 default:
1077 break;
1078 }
1079
1080 /* Set the FIFO state */
1081 fdctrl->data_dir = direction;
1082 fdctrl->data_pos = 0;
1083 fdctrl->msr |= FD_MSR_CMDBUSY;
1084 if (fdctrl->fifo[0] & 0x80)
1085 fdctrl->data_state |= FD_STATE_MULTI;
1086 else
1087 fdctrl->data_state &= ~FD_STATE_MULTI;
1088 if (did_seek)
1089 fdctrl->data_state |= FD_STATE_SEEK;
1090 else
1091 fdctrl->data_state &= ~FD_STATE_SEEK;
1092 if (fdctrl->fifo[5] == 00) {
1093 fdctrl->data_len = fdctrl->fifo[8];
1094 } else {
1095 int tmp;
1096 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1097 tmp = (fdctrl->fifo[6] - ks + 1);
1098 if (fdctrl->fifo[0] & 0x80)
1099 tmp += fdctrl->fifo[6];
1100 fdctrl->data_len *= tmp;
1101 }
1102 fdctrl->eot = fdctrl->fifo[6];
1103 if (fdctrl->dor & FD_DOR_DMAEN) {
1104 int dma_mode;
1105 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1106 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1107 dma_mode = (dma_mode >> 2) & 3;
1108 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1109 dma_mode, direction,
1110 (128 << fdctrl->fifo[5]) *
1111 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1112 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1113 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1114 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1115 (direction == FD_DIR_READ && dma_mode == 1)) {
1116 /* No access is allowed until DMA transfer has completed */
1117 fdctrl->msr &= ~FD_MSR_RQM;
1118 /* Now, we just have to wait for the DMA controller to
1119 * recall us...
1120 */
1121 DMA_hold_DREQ(fdctrl->dma_chann);
1122 DMA_schedule(fdctrl->dma_chann);
1123 return;
1124 } else {
1125 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1126 }
1127 }
1128 FLOPPY_DPRINTF("start non-DMA transfer\n");
1129 fdctrl->msr |= FD_MSR_NONDMA;
1130 if (direction != FD_DIR_WRITE)
1131 fdctrl->msr |= FD_MSR_DIO;
1132 /* IO based transfer: calculate len */
1133 fdctrl_raise_irq(fdctrl, 0x00);
1134
1135 return;
1136 }
1137
1138 /* Prepare a transfer of deleted data */
1139 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1140 {
1141 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1142
1143 /* We don't handle deleted data,
1144 * so we don't return *ANYTHING*
1145 */
1146 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1147 }
1148
1149 /* handlers for DMA transfers */
1150 static int fdctrl_transfer_handler (void *opaque, int nchan,
1151 int dma_pos, int dma_len)
1152 {
1153 FDCtrl *fdctrl;
1154 FDrive *cur_drv;
1155 int len, start_pos, rel_pos;
1156 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1157
1158 fdctrl = opaque;
1159 if (fdctrl->msr & FD_MSR_RQM) {
1160 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1161 return 0;
1162 }
1163 cur_drv = get_cur_drv(fdctrl);
1164 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1165 fdctrl->data_dir == FD_DIR_SCANH)
1166 status2 = FD_SR2_SNS;
1167 if (dma_len > fdctrl->data_len)
1168 dma_len = fdctrl->data_len;
1169 if (cur_drv->bs == NULL) {
1170 if (fdctrl->data_dir == FD_DIR_WRITE)
1171 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1172 else
1173 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1174 len = 0;
1175 goto transfer_error;
1176 }
1177 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1178 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1179 len = dma_len - fdctrl->data_pos;
1180 if (len + rel_pos > FD_SECTOR_LEN)
1181 len = FD_SECTOR_LEN - rel_pos;
1182 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1183 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1184 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1185 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1186 fd_sector(cur_drv) * FD_SECTOR_LEN);
1187 if (fdctrl->data_dir != FD_DIR_WRITE ||
1188 len < FD_SECTOR_LEN || rel_pos != 0) {
1189 /* READ & SCAN commands and realign to a sector for WRITE */
1190 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1191 fdctrl->fifo, 1) < 0) {
1192 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1193 fd_sector(cur_drv));
1194 /* Sure, image size is too small... */
1195 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1196 }
1197 }
1198 switch (fdctrl->data_dir) {
1199 case FD_DIR_READ:
1200 /* READ commands */
1201 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1202 fdctrl->data_pos, len);
1203 break;
1204 case FD_DIR_WRITE:
1205 /* WRITE commands */
1206 if (cur_drv->ro) {
1207 /* Handle readonly medium early, no need to do DMA, touch the
1208 * LED or attempt any writes. A real floppy doesn't attempt
1209 * to write to readonly media either. */
1210 fdctrl_stop_transfer(fdctrl,
1211 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1212 0x00);
1213 goto transfer_error;
1214 }
1215
1216 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1217 fdctrl->data_pos, len);
1218 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1219 fdctrl->fifo, 1) < 0) {
1220 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1221 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1222 goto transfer_error;
1223 }
1224 break;
1225 default:
1226 /* SCAN commands */
1227 {
1228 uint8_t tmpbuf[FD_SECTOR_LEN];
1229 int ret;
1230 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1231 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1232 if (ret == 0) {
1233 status2 = FD_SR2_SEH;
1234 goto end_transfer;
1235 }
1236 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1237 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1238 status2 = 0x00;
1239 goto end_transfer;
1240 }
1241 }
1242 break;
1243 }
1244 fdctrl->data_pos += len;
1245 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1246 if (rel_pos == 0) {
1247 /* Seek to next sector */
1248 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1249 break;
1250 }
1251 }
1252 end_transfer:
1253 len = fdctrl->data_pos - start_pos;
1254 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1255 fdctrl->data_pos, len, fdctrl->data_len);
1256 if (fdctrl->data_dir == FD_DIR_SCANE ||
1257 fdctrl->data_dir == FD_DIR_SCANL ||
1258 fdctrl->data_dir == FD_DIR_SCANH)
1259 status2 = FD_SR2_SEH;
1260 if (FD_DID_SEEK(fdctrl->data_state))
1261 status0 |= FD_SR0_SEEK;
1262 fdctrl->data_len -= len;
1263 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1264 transfer_error:
1265
1266 return len;
1267 }
1268
1269 /* Data register : 0x05 */
1270 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1271 {
1272 FDrive *cur_drv;
1273 uint32_t retval = 0;
1274 int pos;
1275
1276 cur_drv = get_cur_drv(fdctrl);
1277 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1278 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1279 FLOPPY_ERROR("controller not ready for reading\n");
1280 return 0;
1281 }
1282 pos = fdctrl->data_pos;
1283 if (fdctrl->msr & FD_MSR_NONDMA) {
1284 pos %= FD_SECTOR_LEN;
1285 if (pos == 0) {
1286 if (fdctrl->data_pos != 0)
1287 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1288 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1289 fd_sector(cur_drv));
1290 return 0;
1291 }
1292 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1293 FLOPPY_DPRINTF("error getting sector %d\n",
1294 fd_sector(cur_drv));
1295 /* Sure, image size is too small... */
1296 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1297 }
1298 }
1299 }
1300 retval = fdctrl->fifo[pos];
1301 if (++fdctrl->data_pos == fdctrl->data_len) {
1302 fdctrl->data_pos = 0;
1303 /* Switch from transfer mode to status mode
1304 * then from status mode to command mode
1305 */
1306 if (fdctrl->msr & FD_MSR_NONDMA) {
1307 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1308 } else {
1309 fdctrl_reset_fifo(fdctrl);
1310 fdctrl_reset_irq(fdctrl);
1311 }
1312 }
1313 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1314
1315 return retval;
1316 }
1317
1318 static void fdctrl_format_sector(FDCtrl *fdctrl)
1319 {
1320 FDrive *cur_drv;
1321 uint8_t kh, kt, ks;
1322
1323 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1324 cur_drv = get_cur_drv(fdctrl);
1325 kt = fdctrl->fifo[6];
1326 kh = fdctrl->fifo[7];
1327 ks = fdctrl->fifo[8];
1328 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1329 GET_CUR_DRV(fdctrl), kh, kt, ks,
1330 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1331 NUM_SIDES(cur_drv)));
1332 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1333 case 2:
1334 /* sect too big */
1335 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1336 fdctrl->fifo[3] = kt;
1337 fdctrl->fifo[4] = kh;
1338 fdctrl->fifo[5] = ks;
1339 return;
1340 case 3:
1341 /* track too big */
1342 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1343 fdctrl->fifo[3] = kt;
1344 fdctrl->fifo[4] = kh;
1345 fdctrl->fifo[5] = ks;
1346 return;
1347 case 4:
1348 /* No seek enabled */
1349 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1350 fdctrl->fifo[3] = kt;
1351 fdctrl->fifo[4] = kh;
1352 fdctrl->fifo[5] = ks;
1353 return;
1354 case 1:
1355 fdctrl->data_state |= FD_STATE_SEEK;
1356 break;
1357 default:
1358 break;
1359 }
1360 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1361 if (cur_drv->bs == NULL ||
1362 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1363 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1364 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1365 } else {
1366 if (cur_drv->sect == cur_drv->last_sect) {
1367 fdctrl->data_state &= ~FD_STATE_FORMAT;
1368 /* Last sector done */
1369 if (FD_DID_SEEK(fdctrl->data_state))
1370 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1371 else
1372 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1373 } else {
1374 /* More to do */
1375 fdctrl->data_pos = 0;
1376 fdctrl->data_len = 4;
1377 }
1378 }
1379 }
1380
1381 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1382 {
1383 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1384 fdctrl->fifo[0] = fdctrl->lock << 4;
1385 fdctrl_set_fifo(fdctrl, 1, 0);
1386 }
1387
1388 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1389 {
1390 FDrive *cur_drv = get_cur_drv(fdctrl);
1391
1392 /* Drives position */
1393 fdctrl->fifo[0] = drv0(fdctrl)->track;
1394 fdctrl->fifo[1] = drv1(fdctrl)->track;
1395 #if MAX_FD == 4
1396 fdctrl->fifo[2] = drv2(fdctrl)->track;
1397 fdctrl->fifo[3] = drv3(fdctrl)->track;
1398 #else
1399 fdctrl->fifo[2] = 0;
1400 fdctrl->fifo[3] = 0;
1401 #endif
1402 /* timers */
1403 fdctrl->fifo[4] = fdctrl->timer0;
1404 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1405 fdctrl->fifo[6] = cur_drv->last_sect;
1406 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1407 (cur_drv->perpendicular << 2);
1408 fdctrl->fifo[8] = fdctrl->config;
1409 fdctrl->fifo[9] = fdctrl->precomp_trk;
1410 fdctrl_set_fifo(fdctrl, 10, 0);
1411 }
1412
1413 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1414 {
1415 /* Controller's version */
1416 fdctrl->fifo[0] = fdctrl->version;
1417 fdctrl_set_fifo(fdctrl, 1, 0);
1418 }
1419
1420 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1421 {
1422 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1423 fdctrl_set_fifo(fdctrl, 1, 0);
1424 }
1425
1426 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1427 {
1428 FDrive *cur_drv = get_cur_drv(fdctrl);
1429
1430 /* Drives position */
1431 drv0(fdctrl)->track = fdctrl->fifo[3];
1432 drv1(fdctrl)->track = fdctrl->fifo[4];
1433 #if MAX_FD == 4
1434 drv2(fdctrl)->track = fdctrl->fifo[5];
1435 drv3(fdctrl)->track = fdctrl->fifo[6];
1436 #endif
1437 /* timers */
1438 fdctrl->timer0 = fdctrl->fifo[7];
1439 fdctrl->timer1 = fdctrl->fifo[8];
1440 cur_drv->last_sect = fdctrl->fifo[9];
1441 fdctrl->lock = fdctrl->fifo[10] >> 7;
1442 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1443 fdctrl->config = fdctrl->fifo[11];
1444 fdctrl->precomp_trk = fdctrl->fifo[12];
1445 fdctrl->pwrd = fdctrl->fifo[13];
1446 fdctrl_reset_fifo(fdctrl);
1447 }
1448
1449 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1450 {
1451 FDrive *cur_drv = get_cur_drv(fdctrl);
1452
1453 fdctrl->fifo[0] = 0;
1454 fdctrl->fifo[1] = 0;
1455 /* Drives position */
1456 fdctrl->fifo[2] = drv0(fdctrl)->track;
1457 fdctrl->fifo[3] = drv1(fdctrl)->track;
1458 #if MAX_FD == 4
1459 fdctrl->fifo[4] = drv2(fdctrl)->track;
1460 fdctrl->fifo[5] = drv3(fdctrl)->track;
1461 #else
1462 fdctrl->fifo[4] = 0;
1463 fdctrl->fifo[5] = 0;
1464 #endif
1465 /* timers */
1466 fdctrl->fifo[6] = fdctrl->timer0;
1467 fdctrl->fifo[7] = fdctrl->timer1;
1468 fdctrl->fifo[8] = cur_drv->last_sect;
1469 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1470 (cur_drv->perpendicular << 2);
1471 fdctrl->fifo[10] = fdctrl->config;
1472 fdctrl->fifo[11] = fdctrl->precomp_trk;
1473 fdctrl->fifo[12] = fdctrl->pwrd;
1474 fdctrl->fifo[13] = 0;
1475 fdctrl->fifo[14] = 0;
1476 fdctrl_set_fifo(fdctrl, 15, 0);
1477 }
1478
1479 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1480 {
1481 FDrive *cur_drv = get_cur_drv(fdctrl);
1482
1483 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1484 qemu_mod_timer(fdctrl->result_timer,
1485 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1486 }
1487
1488 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1489 {
1490 FDrive *cur_drv;
1491
1492 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1493 cur_drv = get_cur_drv(fdctrl);
1494 fdctrl->data_state |= FD_STATE_FORMAT;
1495 if (fdctrl->fifo[0] & 0x80)
1496 fdctrl->data_state |= FD_STATE_MULTI;
1497 else
1498 fdctrl->data_state &= ~FD_STATE_MULTI;
1499 fdctrl->data_state &= ~FD_STATE_SEEK;
1500 cur_drv->bps =
1501 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1502 #if 0
1503 cur_drv->last_sect =
1504 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1505 fdctrl->fifo[3] / 2;
1506 #else
1507 cur_drv->last_sect = fdctrl->fifo[3];
1508 #endif
1509 /* TODO: implement format using DMA expected by the Bochs BIOS
1510 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1511 * the sector with the specified fill byte
1512 */
1513 fdctrl->data_state &= ~FD_STATE_FORMAT;
1514 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1515 }
1516
1517 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1518 {
1519 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1520 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1521 if (fdctrl->fifo[2] & 1)
1522 fdctrl->dor &= ~FD_DOR_DMAEN;
1523 else
1524 fdctrl->dor |= FD_DOR_DMAEN;
1525 /* No result back */
1526 fdctrl_reset_fifo(fdctrl);
1527 }
1528
1529 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1530 {
1531 FDrive *cur_drv;
1532
1533 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1534 cur_drv = get_cur_drv(fdctrl);
1535 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1536 /* 1 Byte status back */
1537 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1538 (cur_drv->track == 0 ? 0x10 : 0x00) |
1539 (cur_drv->head << 2) |
1540 GET_CUR_DRV(fdctrl) |
1541 0x28;
1542 fdctrl_set_fifo(fdctrl, 1, 0);
1543 }
1544
1545 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1546 {
1547 FDrive *cur_drv;
1548
1549 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1550 cur_drv = get_cur_drv(fdctrl);
1551 fd_recalibrate(cur_drv);
1552 fdctrl_reset_fifo(fdctrl);
1553 /* Raise Interrupt */
1554 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1555 }
1556
1557 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1558 {
1559 FDrive *cur_drv = get_cur_drv(fdctrl);
1560
1561 if(fdctrl->reset_sensei > 0) {
1562 fdctrl->fifo[0] =
1563 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1564 fdctrl->reset_sensei--;
1565 } else {
1566 /* XXX: status0 handling is broken for read/write
1567 commands, so we do this hack. It should be suppressed
1568 ASAP */
1569 fdctrl->fifo[0] =
1570 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1571 }
1572
1573 fdctrl->fifo[1] = cur_drv->track;
1574 fdctrl_set_fifo(fdctrl, 2, 0);
1575 fdctrl_reset_irq(fdctrl);
1576 fdctrl->status0 = FD_SR0_RDYCHG;
1577 }
1578
1579 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1580 {
1581 FDrive *cur_drv;
1582
1583 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1584 cur_drv = get_cur_drv(fdctrl);
1585 fdctrl_reset_fifo(fdctrl);
1586 if (fdctrl->fifo[2] > cur_drv->max_track) {
1587 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1588 } else {
1589 cur_drv->track = fdctrl->fifo[2];
1590 /* Raise Interrupt */
1591 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1592 }
1593 }
1594
1595 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1596 {
1597 FDrive *cur_drv = get_cur_drv(fdctrl);
1598
1599 if (fdctrl->fifo[1] & 0x80)
1600 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1601 /* No result back */
1602 fdctrl_reset_fifo(fdctrl);
1603 }
1604
1605 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1606 {
1607 fdctrl->config = fdctrl->fifo[2];
1608 fdctrl->precomp_trk = fdctrl->fifo[3];
1609 /* No result back */
1610 fdctrl_reset_fifo(fdctrl);
1611 }
1612
1613 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1614 {
1615 fdctrl->pwrd = fdctrl->fifo[1];
1616 fdctrl->fifo[0] = fdctrl->fifo[1];
1617 fdctrl_set_fifo(fdctrl, 1, 0);
1618 }
1619
1620 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1621 {
1622 /* No result back */
1623 fdctrl_reset_fifo(fdctrl);
1624 }
1625
1626 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1627 {
1628 FDrive *cur_drv = get_cur_drv(fdctrl);
1629
1630 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1631 /* Command parameters done */
1632 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1633 fdctrl->fifo[0] = fdctrl->fifo[1];
1634 fdctrl->fifo[2] = 0;
1635 fdctrl->fifo[3] = 0;
1636 fdctrl_set_fifo(fdctrl, 4, 0);
1637 } else {
1638 fdctrl_reset_fifo(fdctrl);
1639 }
1640 } else if (fdctrl->data_len > 7) {
1641 /* ERROR */
1642 fdctrl->fifo[0] = 0x80 |
1643 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1644 fdctrl_set_fifo(fdctrl, 1, 0);
1645 }
1646 }
1647
1648 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1649 {
1650 FDrive *cur_drv;
1651
1652 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1653 cur_drv = get_cur_drv(fdctrl);
1654 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1655 cur_drv->track = cur_drv->max_track - 1;
1656 } else {
1657 cur_drv->track += fdctrl->fifo[2];
1658 }
1659 fdctrl_reset_fifo(fdctrl);
1660 /* Raise Interrupt */
1661 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1662 }
1663
1664 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1665 {
1666 FDrive *cur_drv;
1667
1668 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1669 cur_drv = get_cur_drv(fdctrl);
1670 if (fdctrl->fifo[2] > cur_drv->track) {
1671 cur_drv->track = 0;
1672 } else {
1673 cur_drv->track -= fdctrl->fifo[2];
1674 }
1675 fdctrl_reset_fifo(fdctrl);
1676 /* Raise Interrupt */
1677 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1678 }
1679
1680 static const struct {
1681 uint8_t value;
1682 uint8_t mask;
1683 const char* name;
1684 int parameters;
1685 void (*handler)(FDCtrl *fdctrl, int direction);
1686 int direction;
1687 } handlers[] = {
1688 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1689 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1690 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1691 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1692 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1693 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1694 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1695 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1696 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1697 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1698 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1699 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1700 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1701 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1702 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1703 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1704 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1705 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1706 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1707 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1708 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1709 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1710 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1711 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1712 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1713 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1714 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1715 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1716 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1717 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1718 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1719 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1720 };
1721 /* Associate command to an index in the 'handlers' array */
1722 static uint8_t command_to_handler[256];
1723
1724 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1725 {
1726 FDrive *cur_drv;
1727 int pos;
1728
1729 /* Reset mode */
1730 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1731 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1732 return;
1733 }
1734 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1735 FLOPPY_ERROR("controller not ready for writing\n");
1736 return;
1737 }
1738 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1739 /* Is it write command time ? */
1740 if (fdctrl->msr & FD_MSR_NONDMA) {
1741 /* FIFO data write */
1742 pos = fdctrl->data_pos++;
1743 pos %= FD_SECTOR_LEN;
1744 fdctrl->fifo[pos] = value;
1745 if (pos == FD_SECTOR_LEN - 1 ||
1746 fdctrl->data_pos == fdctrl->data_len) {
1747 cur_drv = get_cur_drv(fdctrl);
1748 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1749 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1750 return;
1751 }
1752 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1753 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1754 fd_sector(cur_drv));
1755 return;
1756 }
1757 }
1758 /* Switch from transfer mode to status mode
1759 * then from status mode to command mode
1760 */
1761 if (fdctrl->data_pos == fdctrl->data_len)
1762 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1763 return;
1764 }
1765 if (fdctrl->data_pos == 0) {
1766 /* Command */
1767 pos = command_to_handler[value & 0xff];
1768 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1769 fdctrl->data_len = handlers[pos].parameters + 1;
1770 fdctrl->msr |= FD_MSR_CMDBUSY;
1771 }
1772
1773 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1774 fdctrl->fifo[fdctrl->data_pos++] = value;
1775 if (fdctrl->data_pos == fdctrl->data_len) {
1776 /* We now have all parameters
1777 * and will be able to treat the command
1778 */
1779 if (fdctrl->data_state & FD_STATE_FORMAT) {
1780 fdctrl_format_sector(fdctrl);
1781 return;
1782 }
1783
1784 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1785 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1786 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1787 }
1788 }
1789
1790 static void fdctrl_result_timer(void *opaque)
1791 {
1792 FDCtrl *fdctrl = opaque;
1793 FDrive *cur_drv = get_cur_drv(fdctrl);
1794
1795 /* Pretend we are spinning.
1796 * This is needed for Coherent, which uses READ ID to check for
1797 * sector interleaving.
1798 */
1799 if (cur_drv->last_sect != 0) {
1800 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1801 }
1802 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1803 }
1804
1805 static void fdctrl_change_cb(void *opaque, bool load)
1806 {
1807 FDrive *drive = opaque;
1808
1809 drive->media_changed = 1;
1810 }
1811
1812 static const BlockDevOps fdctrl_block_ops = {
1813 .change_media_cb = fdctrl_change_cb,
1814 };
1815
1816 /* Init functions */
1817 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1818 {
1819 unsigned int i;
1820 FDrive *drive;
1821
1822 for (i = 0; i < MAX_FD; i++) {
1823 drive = &fdctrl->drives[i];
1824
1825 if (drive->bs) {
1826 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1827 error_report("fdc doesn't support drive option werror");
1828 return -1;
1829 }
1830 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1831 error_report("fdc doesn't support drive option rerror");
1832 return -1;
1833 }
1834 }
1835
1836 fd_init(drive);
1837 fd_revalidate(drive);
1838 if (drive->bs) {
1839 drive->media_changed = 1;
1840 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
1841 }
1842 }
1843 return 0;
1844 }
1845
1846 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1847 target_phys_addr_t mmio_base, DriveInfo **fds)
1848 {
1849 FDCtrl *fdctrl;
1850 DeviceState *dev;
1851 FDCtrlSysBus *sys;
1852
1853 dev = qdev_create(NULL, "sysbus-fdc");
1854 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1855 fdctrl = &sys->state;
1856 fdctrl->dma_chann = dma_chann; /* FIXME */
1857 if (fds[0]) {
1858 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1859 }
1860 if (fds[1]) {
1861 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1862 }
1863 qdev_init_nofail(dev);
1864 sysbus_connect_irq(&sys->busdev, 0, irq);
1865 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1866 }
1867
1868 void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1869 DriveInfo **fds, qemu_irq *fdc_tc)
1870 {
1871 DeviceState *dev;
1872 FDCtrlSysBus *sys;
1873
1874 dev = qdev_create(NULL, "SUNW,fdtwo");
1875 if (fds[0]) {
1876 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1877 }
1878 qdev_init_nofail(dev);
1879 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1880 sysbus_connect_irq(&sys->busdev, 0, irq);
1881 sysbus_mmio_map(&sys->busdev, 0, io_base);
1882 *fdc_tc = qdev_get_gpio_in(dev, 0);
1883 }
1884
1885 static int fdctrl_init_common(FDCtrl *fdctrl)
1886 {
1887 int i, j;
1888 static int command_tables_inited = 0;
1889
1890 /* Fill 'command_to_handler' lookup table */
1891 if (!command_tables_inited) {
1892 command_tables_inited = 1;
1893 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1894 for (j = 0; j < sizeof(command_to_handler); j++) {
1895 if ((j & handlers[i].mask) == handlers[i].value) {
1896 command_to_handler[j] = i;
1897 }
1898 }
1899 }
1900 }
1901
1902 FLOPPY_DPRINTF("init controller\n");
1903 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1904 fdctrl->fifo_size = 512;
1905 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
1906 fdctrl_result_timer, fdctrl);
1907
1908 fdctrl->version = 0x90; /* Intel 82078 controller */
1909 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1910 fdctrl->num_floppies = MAX_FD;
1911
1912 if (fdctrl->dma_chann != -1)
1913 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1914 return fdctrl_connect_drives(fdctrl);
1915 }
1916
1917 static const MemoryRegionPortio fdc_portio_list[] = {
1918 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
1919 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
1920 PORTIO_END_OF_LIST(),
1921 };
1922
1923 static int isabus_fdc_init1(ISADevice *dev)
1924 {
1925 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1926 FDCtrl *fdctrl = &isa->state;
1927 int iobase = 0x3f0;
1928 int isairq = 6;
1929 int dma_chann = 2;
1930 int ret;
1931
1932 isa_register_portio_list(dev, iobase, fdc_portio_list, fdctrl, "fdc");
1933
1934 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1935 fdctrl->dma_chann = dma_chann;
1936
1937 qdev_set_legacy_instance_id(&dev->qdev, iobase, 2);
1938 ret = fdctrl_init_common(fdctrl);
1939
1940 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
1941 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
1942
1943 return ret;
1944 }
1945
1946 static int sysbus_fdc_init1(SysBusDevice *dev)
1947 {
1948 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
1949 FDCtrl *fdctrl = &sys->state;
1950 int ret;
1951
1952 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
1953 sysbus_init_mmio(dev, &fdctrl->iomem);
1954 sysbus_init_irq(dev, &fdctrl->irq);
1955 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1956 fdctrl->dma_chann = -1;
1957
1958 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
1959 ret = fdctrl_init_common(fdctrl);
1960
1961 return ret;
1962 }
1963
1964 static int sun4m_fdc_init1(SysBusDevice *dev)
1965 {
1966 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
1967
1968 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
1969 "fdctrl", 0x08);
1970 sysbus_init_mmio(dev, &fdctrl->iomem);
1971 sysbus_init_irq(dev, &fdctrl->irq);
1972 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1973
1974 fdctrl->sun4m = 1;
1975 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
1976 return fdctrl_init_common(fdctrl);
1977 }
1978
1979 void fdc_get_bs(BlockDriverState *bs[], ISADevice *dev)
1980 {
1981 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1982 FDCtrl *fdctrl = &isa->state;
1983 int i;
1984
1985 for (i = 0; i < MAX_FD; i++) {
1986 bs[i] = fdctrl->drives[i].bs;
1987 }
1988 }
1989
1990
1991 static const VMStateDescription vmstate_isa_fdc ={
1992 .name = "fdc",
1993 .version_id = 2,
1994 .minimum_version_id = 2,
1995 .fields = (VMStateField []) {
1996 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
1997 VMSTATE_END_OF_LIST()
1998 }
1999 };
2000
2001 static Property isa_fdc_properties[] = {
2002 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2003 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2004 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2005 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
2006 DEFINE_PROP_END_OF_LIST(),
2007 };
2008
2009 static void isabus_fdc_class_init1(ObjectClass *klass, void *data)
2010 {
2011 DeviceClass *dc = DEVICE_CLASS(klass);
2012 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
2013 ic->init = isabus_fdc_init1;
2014 dc->fw_name = "fdc";
2015 dc->no_user = 1;
2016 dc->reset = fdctrl_external_reset_isa;
2017 dc->vmsd = &vmstate_isa_fdc;
2018 dc->props = isa_fdc_properties;
2019 }
2020
2021 static TypeInfo isa_fdc_info = {
2022 .name = "isa-fdc",
2023 .parent = TYPE_ISA_DEVICE,
2024 .instance_size = sizeof(FDCtrlISABus),
2025 .class_init = isabus_fdc_class_init1,
2026 };
2027
2028 static const VMStateDescription vmstate_sysbus_fdc ={
2029 .name = "fdc",
2030 .version_id = 2,
2031 .minimum_version_id = 2,
2032 .fields = (VMStateField []) {
2033 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2034 VMSTATE_END_OF_LIST()
2035 }
2036 };
2037
2038 static Property sysbus_fdc_properties[] = {
2039 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2040 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2041 DEFINE_PROP_END_OF_LIST(),
2042 };
2043
2044 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2045 {
2046 DeviceClass *dc = DEVICE_CLASS(klass);
2047 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2048
2049 k->init = sysbus_fdc_init1;
2050 dc->reset = fdctrl_external_reset_sysbus;
2051 dc->vmsd = &vmstate_sysbus_fdc;
2052 dc->props = sysbus_fdc_properties;
2053 }
2054
2055 static TypeInfo sysbus_fdc_info = {
2056 .name = "sysbus-fdc",
2057 .parent = TYPE_SYS_BUS_DEVICE,
2058 .instance_size = sizeof(FDCtrlSysBus),
2059 .class_init = sysbus_fdc_class_init,
2060 };
2061
2062 static Property sun4m_fdc_properties[] = {
2063 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2064 DEFINE_PROP_END_OF_LIST(),
2065 };
2066
2067 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2068 {
2069 DeviceClass *dc = DEVICE_CLASS(klass);
2070 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2071
2072 k->init = sun4m_fdc_init1;
2073 dc->reset = fdctrl_external_reset_sysbus;
2074 dc->vmsd = &vmstate_sysbus_fdc;
2075 dc->props = sun4m_fdc_properties;
2076 }
2077
2078 static TypeInfo sun4m_fdc_info = {
2079 .name = "SUNW,fdtwo",
2080 .parent = TYPE_SYS_BUS_DEVICE,
2081 .instance_size = sizeof(FDCtrlSysBus),
2082 .class_init = sun4m_fdc_class_init,
2083 };
2084
2085 static void fdc_register_types(void)
2086 {
2087 type_register_static(&isa_fdc_info);
2088 type_register_static(&sysbus_fdc_info);
2089 type_register_static(&sun4m_fdc_info);
2090 }
2091
2092 type_init(fdc_register_types)
Qemu copy for testing